The 8086 Microprocessor Architecture
The 8086 Microprocessor Architecture
The 8086 Microprocessor Architecture
Upward Compatibility
20 bit addr => 1M Byte of memory 16-bit data width Valid addr word on the bus Most significant byte enabled Memory or I/O Data direction Read/write bus cycle in progress Tell ext devices to put data On the bus To insert wait states into the bus cycles; for mem or I/O operations
Go to interrupt service NMI routine Go to reset service RESET routine External device req HOLD DMA interface Request granted