The 8086 Microprocessor Architecture

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The 8086 Microprocessor Architecture

Brief History of 8086

Brief History Continued

Upward Compatibility

8086 Pin Layout


GND AD14 Addr/data time multiplexing AD13 . . AD0 NMI INTR CLK GND TEST READY RESET 8086 CPU (16-bit microprocessor) (HMOS technology; ~29K transistors) VCC AD15 A16/S3 A17/S4 A18/S5 A19/S6 BHE/S7 MN/MX RD HOLD (RQ/GT0) HLDA (RQ/GT1) WR (LOCK) M/IO (S2) DT/R (S1) DEN (S0) ALE (QS0) INTA (QS1) Min (Max)

Minimum System Mode


8086 provides all control signals needed for memory and I/O Interface No need for other intermediate units
Interrupt req/ack Used to sync to external events

INTR INTA TEST

A0-A15, A16/S3-A19/S6 D0-D15 ALE BHE/S7 M/IO DT/R RD WR DEN READY

20 bit addr => 1M Byte of memory 16-bit data width Valid addr word on the bus Most significant byte enabled Memory or I/O Data direction Read/write bus cycle in progress Tell ext devices to put data On the bus To insert wait states into the bus cycles; for mem or I/O operations

Go to interrupt service NMI routine Go to reset service RESET routine External device req HOLD DMA interface Request granted

HLDA MN/MX CLK

Minimum System Mode Status Codes


S4 0 0 1 1 S3 0 1 0 1 Segment register Extra Stack Code/none Data
S6 = 0 always S5 = internal interrupt enable flag

Who generated physical address?

Maximum System Mode


Other microprocessors existing in the system Or a co-processor existing in the system Other blocks interact with 8086 to generate signals for memory, I/O access or interrupt interface 8289 bus arbiter (controls access to system bus) 8288 bus controller (generates signals for memory, I/O access) 8086 generates status signals that 8289 and 8288 use

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