Power Management Texas Instruments Incorporated

Designing DC/DC converters based on

SEPIC topology
By Jeff Falin
Senior Applications Engineer
Introduction coupling capacitor, CP; a power FET, Q1; and a diode, D1.
Figure 2 shows the SEPIC operating in continuous con­
The single-ended primary-inductance converter (SEPIC)
duc­tion mode (CCM). Q1 is on in the top circuit and off in
is a DC/DC-converter topology that provides a positive
the bottom circuit.
regulated output voltage from an input voltage that varies
To understand the voltages at the various circuit nodes,
from above to below the output voltage. This type of con-
it is important to analyze the circuit at DC when Q1 is off
version is handy when the designer uses voltages (e.g.,
and not switching. During steady-state CCM, pulse-width-
12 V) from an unregulated input power supply such as a
modulation (PWM) operation, and neglecting ripple voltage,
low-cost wall wart. Unfortunately, the SEPIC topology is
difficult to understand and requires two inductors, making
the power-supply footprint quite large. Recently, several Figure 1. Simple circuit diagram of
inductor manufacturers began selling off-the-shelf coupled SEPIC converter
inductors in a single package at a cost only slightly higher
than that of the comparable single inductor. The coupled
L1a CP D1
inductor not only provides a smaller footprint but also, to
get the same inductor ripple current, requires only half VIN VOUT
the inductance required for a SEPIC with two separate Q1
inductors. This article explains how to design a SEPIC
C IN L1b COUT
converter with a coupled inductor.
Basic operation
Figure 1 shows a simple circuit diagram of a SEPIC con-
verter, consisting of an input capacitor, CIN; an output
capacitor, COUT; coupled inductors L1a and L1b; an AC

Figure 2. SEPIC during CCM operation when Q1 is

on (top) and off (bottom)

+ –
VL1a

L1a CP
VIN + – VOUT
+
I L1a
+
C IN I L1b L1b VL1b COUT
–
–

+ –
VL1a
L1a CP D1
VIN + – VOUT

I L1a +
+
C IN I L1b L1b VL1b COUT
–
–

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Texas Instruments Incorporated Power Management

capacitor CP is charged to the input voltage,

Figure 3. SEPIC component voltages during CCM
VIN. Knowing this, we can easily determine
the voltages as shown in Figure 3.
When Q1 is off, the voltage across L1b VIN(max) + VOUT
must be VOUT. Since CIN is charged to VIN,
Q1 Q1
the voltage across Q1 when Q1 is off is VIN + VQ1
ON OFF
VOUT, so the voltage across L1a is VOUT. When
Q1 is on, capacitor CP, charged to VIN, is con- VOUT
nected in parallel with L1b, so the voltage VL1b
across L1b is –VIN.
The currents flowing through various cir- –VIN
VOUT
cuit components are shown in Figure 4. When VL1a
Q1 is on, energy is being stored in L1a from (VIN < VOUT) VIN
the input and in L1b from CP. When Q1 turns
off, L1a’s current continues to flow through VIN
CP and D1, and into COUT and the load. Both VL1a VOUT
COUT and CP get recharged so that they can (VIN > VOUT)
provide the load current and charge L1b,
respectively, when Q1 turns back on.
Duty cycle
Assuming 100% efficiency, the duty cycle, D,
for a SEPIC converter operating in CCM is Figure 4. SEPIC component currents during CCM
given by
VOUT + VFWD
D= , (1) TS
VIN + VOUT + VFWD
VIN + VOUT
where VFWD is the forward voltage drop of the
VQ1 D × TS (1 – D) × TS
Schottky diode. This can be rewritten as
D V + VFWD I
= OUT = IN . (2) I Q1(Peak)
1− D VIN IOUT
I IN + lOUT
l Q1
D(max) occurs at VIN(min), and D(min) occurs
at VIN(max).
Selecting passive components
I IN + lOUT
One of the first steps in designing any PWM l D1
switching regulator is to decide how much
inductor ripple current, ∆IL, to allow. Too
much increases EMI, while too little may I IN
result in unstable PWM operation. A rule of
thumb is to use 20 to 40% of the input cur- l CP
rent, as computed with the power-balance –I OUT
equation,
I I IN
∆I L = 30% × IN
η = 30% × IIN′. (3) l L1a

In this equation, IIN from Equation 2 is divided
by the estimated worst-case effi­ciency, η, at I OUT
VIN(min) and IOUT(max) for a more accurate I L1b
estimate of the input current, IIN′.
In an ideal, tightly coupled inductor, with
each inductor having the same number of
windings on a single core, the mutual induc-
tance forces the ripple current to be split
equally between the two coupled inductors.
In a real coupled inductor, the inductors do

19

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 Power Management Texas Instruments Incorporated

not have equal inductance and the ripple currents will not capacitance, but not too much ESR, to meet the applica-
be exactly equal. Regard­less, for a desired ripple-current tion’s requirement for output voltage ripple, ∆VRPL:
value, the inductance required in a coupled inductor is IOUT × D(max)
estimated to be half of what would be needed if there ∆VRPL ≤
COUT × fSW(min)
were two separate inductors, as shown in Equation 4: (6)
1 VIN(min) × D(max) + ESR × I L1a(Peak) + I L1b(Peak) 
L1a(min) = L1b(min) = × (4)
2 ∆I L × fSW(min) If very low-ESR (e.g., ceramic) output capacitors are used,

the ESR can be ignored and the equation reduces to
To account for load transients, the coupled inductor’s
saturation current rating needs to be at least 20% higher IOUT × D(max)
COUT ≥ , (7)
than the steady-state peak current in the high-side induc- ∆VRPL × fSW(min)

tor, as computed in Equation 5:
where fSW(min) is the minimum switching frequency. A
∆I L  
I L1a( Peak ) = I IN ′ + = I IN ′  1 + 30% (5) minimum capacitance limit may be necessary to meet the
2  2  application’s load-transient requirement.
Note that IL1b(Peak) = IOUT + ∆IL /2, which is less than The output capacitor must have an RMS current rating
IL1a(Peak). greater than the capacitor’s RMS current, as computed in
Figure 5 breaks down the capacitor ripple voltage as Equation 8:
related to the output-capacitor current. When Q1 is on, D(max)
the output capacitor must provide the load current. IC = IOUT × (8)
OUT( RMS) 1 − D(max)
Therefore, the output capacitor must have at least enough

Figure 5. Ripple voltage of output capacitor

TS

IIN

ICOUT
D × TS (1 – D) × TS

–IOUT
VESR × (IL1a + IL1b – IOUT)

∆VRPL_ESR

VESR × IOUT

∆VRPL_COUT

∆VRPL = ∆VRPL_ESR + ∆VRPL_COUT

∆VRPL
VOUT_AC

20

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Texas Instruments Incorporated Power Management

The input capacitor sees fairly low ripple currents due The output diode must be able to handle the same peak
to the input inductor. Like a boost converter, the input- current as Q1, IQ1(Peak). The diode must also be able to
current waveform is continuous and triangular; therefore, withstand a reverse voltage greater than Q1’s maximum
the input capacitor needs the RMS current rating, voltage (VIN[max] + VOUT + VFWD) to account for transients
∆I and ringing. Since the average diode current is the output
IC (RMS) = L . (9) current, the diode’s package must be capable of dissipat-
IN
12
ing up to PD_D1 = IOUT × VFWD .
The coupling capacitor, CP, sees large RMS current rela- Design example
tive to the output power:
A DC/DC converter is needed that can provide 12 V at
1 − D(max) 300 mA (maximum) with 90% efficiency from an input
IC = I IN ′ × (10)
P( RMS) D(max) voltage ranging from 9 to 15 V. We select the TPS61170,
which has a 38-V switch, a minimum switch-current limit of
From Figure 3, the maximum voltage across CP is 0.96 A, and a 1.2-MHz nominal (1.0-MHz minimum) switch­
VQ1(max) – VL1b(max) = VIN + VOUT – VOUT = VIN. ing frequency. The maximum output voltage ripple allowed
is 100 mVPP. The maximum ambient temperature is 70ºC,
The ripple across CP is
and we will use a high-K board. In Reference 1, Ray Ridley
IOUT × D(max) explains how to compensate the control loop at the link.
∆VC = . (11)
P CP × fSW Table 1 summarizes the computations using the equa-

tions given earlier. Equations 8 through 11 are not shown
Selecting active components because ceramic capacitors with low ESR, high RMS cur-
rent ratings, and the appropriate voltage ratings were
The power MOSFET, Q1, must be carefully selected so
used. Figure 6 shows the schematic. Figure 7 shows the
that it can handle the peak voltage and currents while
design’s effi­ciency with a Coiltronics DRQ73 inductor and
minimizing power-dissipation losses. The power FET’s
a Wurth 744877220. Figure 8 shows the device operation
current rating (or current limit for a converter with an
in deep CCM.
integrated FET) will determine the SEPIC converter’s
maximum output current. References
As shown in Figure 3, Q1 sees a maximum voltage of 1. Ray Ridley. (Nov. 2006). Analyzing the SEPIC
VIN(max) + VOUT. As shown in Figure 4, Q1 must have a converter. Power Systems Design Europe [Online].
peak-current rating of Available: http://www.powersystemsdesign.com/design_
IQ1( Peak ) = I L1a( Peak ) + I L1b( Peak ) = IIN ′ + IOUT + ∆I L . (12) tips_nov06.pdf
2. Robert W. Erickson and Dragan Maksimovic,
At the ambient temperature of interest, the FET’s power- Fundamentals of Power Electronics, 2nd ed. (New
dissipation rating must be greater than the sum of the York: Springer Science+Business Media LLC, 2001).
conductive losses (a function of the FET’s rDS[on]) and the 3. John Betten and Robert Kollman. (Jan. 25, 2006). No
switching losses (a function of the FET’s gate charge) as need to fear: SEPIC outperforms the flyback. Planet
given in Equation 13: Analog [Online]. Available: http://www.planetanalog.com/
2 showArticle.jhtml?articleID=177103753
PD _ Q1 = IQ 1(RMS) × rDS(on ) × D(max) + I Q1(Peak)
(13) Related Web sites
t Rise + tFall
×  VIN(min) + VOUT + VFWD  × × fSW , power.ti.com
2
www.ti.com/sc/device/TPS61170
where tRise is the rise time on the gate of Q1 and can be
computed as Q1’s gate-to-drain charge, QGD, divided by the
converter’s gate-drive current, IDRV. Q1’s RMS current is
I IN ′
IQ1( RMS ) = . (14)
D(max)

21

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 Power Management Texas Instruments Incorporated

Table 1. Computations for SEPIC design example

DESIGN EQUATION COMPUTATION SELECTED COMPONENT/RATING
Passive Components
12 V + 0 .5 V
(1) D(max) = = 0 .58 N/A
12 V + 9 V + 0 .5 V
0 .3 A × 12 V
(2) and (3) ∆I L = IIN′ × 30% = × 30% = 0 .44 A × 30% = 0 .13 A N/A
9 V × 90%
1 9 V ×0.58
(4) L1a = L1b = × = 20.1 µH
2 0.13 A ×1 MHz
Coiltronics DRQ73: 22 µH, 1.6 A, and 110 mΩ
 30% 
(5) I L1a(Peak) = 0 .44 A ×  1+ = 0 .51 A
 2 
0.3 A × 0.58
(7) COUT ≥ = 1.74 µF 4.7-µF, 25-V X5R ceramic
0.1 V × 1 MHz
Active Components
(12) IQ1(Peak) =0 .44 A+ 0 .3 A+ 0 .13 A = +0 .87 A

0 .44 A
(14) I Q1(RMS) = =0 .58 A TPS61170 with 0.96-A-rated switch. Capable
0 .58
of dissipating 825 mW at 70ºC.
PD_Q1 =(0 .58 A) 2 × 0 .3 Ω × 0 .58 +0 .87 A
(13)
× (9 V +12 V + 0 .5 V) × 10 ns × 1 MHz = 246 mW

— PD_D1 = 0 .3 A × 0 .5 V = 150 mW MBA140: 1 A, 40 V

Figure 6. SEPIC design with 9- to 15-V VIN and 12-V VOUT at 300 mA

VIN = L1a C4 VOUT =

9 to 15 V 22 µH 1 µF D1 12 V at 300 mA

CIN L1b COUT

4.7 µF 22 µH 4.7 µF
TPS61170 R1
87.6 kΩ
VIN SW

CTRL FB

4.99 kΩ
COMP GND R2
10 kΩ
C3
22 nF

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High-Performance Analog Products www.ti.com/aaj 4Q 2008 Analog Applications Journal

Texas Instruments Incorporated Power Management

Figure 7. Efficiency of example SEPIC design

100
Wurth, VIN = 9 V
95
Wurth, VIN = 15 V
90

85
Coiltronics, VIN = 9 V
Efficiency (%)
80
Coiltronics, VIN = 15 V
75

70

65

60

55

50
0 100 200 300 400
Output Current , IOUT (mA)

Figure 8. Operation at VIN = 9 V and IOUT = 200 mA

SW
(20 V/div)

IL High
(200 mA/div)

IL Low
(200 mA/div)

VOUT _AC
(50 mV/div)

Time, t (1 µs/div)

23

Analog Applications Journal 4Q 2008 www.ti.com/aaj High-Performance Analog Products

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
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