ST2106 & ST2107

Data Formatting & Carrier Modulation
Transmitter Trainer and Carrier

Demodulation & Data Reformatting
Receiver Trainer ST2106 & ST2107
Operating Manual
Ver 1.1
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ST2106 & ST2107
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ST2106 & ST2107
Data Formatting & Carrier Modulation Transmitter Trainer and Carrier

Demodulation & Data Reformatting Receiver Trainer
ST2106 & ST2107
Table of Contents
1. ST2106 Features 4
2. ST2106 Technical Specifications 5
3. ST2107 Features 6
4. ST2107 Technical Specifications 7
5. Theory of Data Formatting 8
a. Experiment 1 11
b. Experiment 2 15
c. Experiment 3 18
6. Introduction to Biphase Codes. 20
d. Experiment 4 22
e. Experiment 5 25
7. Introduction to 3 Level Codes 27
f. Experiment 6 30
g. Experiment 7 35
8. Carrier Modulation Introduction 37
h. Experiment 8 41
i. Experiment 9 47
j. Experiment 10 53
k. Experiment 11 62
l. Experiment 12 65
9. Warranty 66
10. List of Accessories 66

ST2106 & ST2107
Features
• On-board Carrier Generation Circuit (Sine waves synchronized to
transmitter data).
• On-board In Phase and Quadrate Phase Carrier for QPSK Modulation.
• Different Data Conditioning Formats NRZ (L), NRZ (M), RZ, Biphase.
(Manchester), Biphase (Mark), AMI, RB, Differentially Encoded Dibit
Pair.
• FSK, PSK, ASK & QPSK carrier modulation.
• Variable Carrier and Modulation Off-Set.
• Variable Carrier Gain.
• On-board Unipolar to Bipolar Conversion.
• On-board Data Inverter.
RoHS Compliance
Scientech Products are RoHS Complied.
RoHS Directive concerns with the restrictive of use of Hazardous substances (Pb, Cd, Cr,
Hg, Br compounds) in electric and electronic equipments.
Scientech products are “Lead Free” and “Environment Friendly”.
It is mandatory that service engineers use lead free solder wire and use the soldering irons
upto (25 W) that reach a temperature of 450°C at the tip as the melting temperature of the
unleaded solder is higher than the leaded solder.

ST2106 & ST2107
Technical Specifications
Input : Two channel time division multiplexed data.
Data formats : NRZ (L), NRZ (M), RZ, AMI, RB, Biphase
(Manchester), Biphase (Mark).
Carrier modulation : ASK, FSK, PSK, DPSK, QPSK
On-board carrier : Sine waves synchronized to transmitted data at
1.44 MHz, 960 KHz, (0 deg. phase) 960 KHz,
(90 degree phase)
Test Points : 49 Nos.
Power Supply : 230V ± 10%, 50Hz.
Power Consumption : 3VA (Approximately)
Interconnections : 4 mm sockets
Dimensions (mm) : W420 x H100 x D255
Weight : 2.5 Kgs. (Approximately)

ST2106 & ST2107
Features
• 7 different Data Reconditioning Formats NRZ (M), RZ, AMI, RB Biphase
(Manchester), Biphase (Mark), Differentially Encoded Dibit to NRZ data.
• ASK FSK, PSK, DPSK & QPSK Carrier Demodulation.
• Output gives 2 Channels TDM Multiplexed Data Output.
• On - Board Biphase Clock Recovery Circuit.
• On - Board Data Squaring Circuit and Differential Decoder.
• On - Board Butterworth Filters - 4th Order (2 Nos.)

ST2106 & ST2107
Technical Specifications
Input : From Model ST2106
Output : 2 Channel TDM Multiplexed data stream
Demodulation options : NRZ (M), RZ, AMI, RB, Biphase (Manchester),
Biphase (Mark), differentially encoded dibit to
NRZ (L)
Carrier Demodulation : ASK - Rectifier Diode
FSK - PLL Detector
PSK / DPSK- Square Loop Detector
QPSK - Fourth Power Loop Detector
Biphase Clock Recover : By PLL
Power Consumption : 6VA (approximately)
Test Points : 54 Nos.
Interconnections : 4mm Sockets
Power Supply : 230V +/- 10%, 50Hz
Dimensions (mm) : W 420 x H100 x D255
Weight : 2.5 Kgs. (approximately)

ST2106 & ST2107
Theory of Data Formatting

The symbols ‘0’ and ‘1’ in digital systems can be represented in various formats with
different levels & waveforms. The selection of particular format for communication
depends on the system bandwidth, system’s ability to pass DC level information, error
checking facility, ease of clock regeneration & synchronizations at receiver, system
complexity & cost etc.
The most widely used formats of data representation are given below. These are also
available on ST2106 trainer. Every data format has specific advantages &
disadvantages associated with them. We will study one by one see figure 1.
Different NRZ Encoding

Figure 1

ST2106 & ST2107
Non - Return To Zero (Level) NRZ (L) :

It is the simplest form of data representation. The NRZ (L) waveform simply goes
low for one bit time to represent a data '0' & high for one bit time to represent a data
'1'. Thus the signal alternates only when there is a data change. See figure 2
NRZ (L) Encoding

Figure 2
Clock Regeneration :
Since the level transition takes place at a predetermined moment (e.g. at rising/falling
edge of the data clock), it is possible to extract clock information at the receiver.
However the synchronization & clock information is sparse & sometimes even lost
when a long stream of zero or ones are encountered. The clock regeneration is very
difficult in such cases. This makes the clock regeneration design more complex.
Bandwidth :
The maximum rate at which NRZ (L) waveform can change is half the data clock.
This happens when the data stream consists of an alternate 0's and 1's. As it is known,
it is the maximum signal frequency which determines the bandwidth occupied by the
NRZ (L) code. As you will study other data formats you will appreciate that the NRZ
(L) waveform requires comparatively narrow bandwidth.

ST2106 & ST2107
DC Levels :
Another problem with NRZ (L) code is that it contains DC Level hence cannot be
used for communication systems which cannot pass DC. e.g. transmission paths
involving transformers AC coupled amplifiers or series capacitors filters etc. This
happens particularly in telephone systems.
Let us see now an NRZ (L) code is rendered useless in such systems. Assume a
sequence of repetitive data sent is 0110001 with data 1 level at + 5V & data '0' at 0V.
If the DC Level is lost, the waveform balances at the mean level.
Mean level = total value of samples ÷ no of samples.
= (0+5+5+0+0+0+5) ÷ 7 = 15 ÷ 7 = 2.14V
Thus if the DC Level information is lost, the whole signal balances about 2.14V.
Thus the peak value of + 5V will shift to 5 - 2.14 = 2.86V
It may slip down to a level where the receiver cannot recognize as level '1' & thus the
data could be misread. In extreme case where the input is constant series of logic 0's
then the NRZ (L) output would be a constant level. Now if the input changed to a
stream of logic 0's, the output would still be a constant level. The only difference is
the DC Level. Therefore if the DC Level information is lost, we have no way of
knowing whether the original input will have all 0's or all 1's.
Recommended testing instruments needed for experiments in this work book
1. Scientech oscilloscope model 201 20MHz, Dual Trace, ALT Trigger or
equivalent
2. Oscilloscope Probes X1 – X 10 etc.

ST2106 & ST2107
Experiment 1
Objective :
Study of NRZ (L) Code
Procedure :
1. The experiment makes use of four trainers namely ST2103, ST2104, ST2106 &
ST2107. ST2103 TDM pulse code modulation transmitter trainer serves as a
data source while ST2104 TDM pulse code modulation receiver trainer serves
as analog signal recover. ST2106 serves as data formatting (conditioning)
device while ST2107 reformats (recondition) the data.
ST2103 & ST2106 Trainers serves as transmitter for our system & ST2107 &
ST2104 trainer serves as receiver.
2. Ensure that all trainers are switched off, until the complete connections are
made.
3. Check ST2104 Trainer's clock regeneration circuit Set up for correct operation
as given at the end of ST2103 / 4 work book
4. Set up the following conditions on ST2103 trainer
a. Mode switch set in FAST position.
b. Pseudo - random sync code generator switched on.
c. Error check code selector switches A & B in A=0 & B=0 positions.
d. All switched faults ‘Off’
5. Set ST2106 trainer's mode switch in position 1
6. Set up following conditions on ST2104 trainers:
a. Mode switch set in FAST position
b. Pseudo - random sync code detector in ‘On’ position.
c. Error check code selector switch A & B in A = 0 & B = 0 position.
d. All switched faults to be kept ‘Off’
7. Make the following connections between ST2103, ST2106 trainers.
ST2103 trainer ST2106 trainer
a. TX clock output (TP3) to TX clock input
b. PCM output (TP44) to TX data input
8. Connect the TX to output (TP4) on ST2103 trainer to external trigger input of
the oscilloscope. Set to negative edge triggered mode in oscilloscope. It may be
necessary to adjust the trigger level manually to obtain a stable waveform.

ST2106 & ST2107
Figure 3
9. n ST2103 trainer make following connections
a. DC 1 to CH 0 input
b. CH 0 input to CH 1 input
This is done to supply the same voltage level to each of the two time division
multiplexed channels. Thus we are able to get the same data stream for any time
frame.
10. Make the rest of the connections as shown in configuration figure 3.
11. Switch ‘on’ the power
12. On ST2103 trainer adjust the DC1 potentiometer until the 7 bit code displayed
at A/D converter LEDs is
D6 D5 D4 D3 D2 D1 D0
0 1 0 0 0 1 1
13. Observe the data clock output at TP4 on ST2106 trainer's data format block
with Oscilloscope. Adjust the oscilloscopes time base & position control until
each rising edge of data clock coincides with one of scope's vertical graticule
line as shown in figure 4. Each main division on scope's horizontal axis now

ST2106 & ST2107
represents one data bit time. Adjust the trigger level (manually, if necessary, to
obtain a stable trace.) This sets convenient reference against which to observe
the other wave forms.
Data Clock Output

Figure 4
14. Examine the NRZ (L) TP5 in data format block of ST2106 trainer on other
channel of the oscilloscope. The NRZ (L) waveform must be identical to as
shown in figure 1.
15. You may recall from your work on ST2103 trainer that the least significant bit
D0 is transmitted first and then D6. Thus D6 will be available at the right hand
side of the oscilloscope trace.
Also note that the since the pseudo random sync generator is ‘Off’, a logic '0' is
transmitted as first bit. So from left to right on oscilloscope, the logic level read
0, then 1 1 0 0 0 1 0.
Also, you may recall, that ST2103 trainer has two input channels. Channel 0
and Channel 1, which are time division multiplexed, these two channels are sent
as a group of 15 bits or timeslots. The sync bit comes first, followed by 7 bits of
channel 0 and finally 7 bits of channel 1. The whole group of 15 timeslots is
called a 'Timing Frame'.
16. To view a timing frame, adjust the oscilloscope's time base & X-controls until
remove the lead of input to channel 1. Switch off the power connect channel1
input to DC 2 supply. You have exactly two clock pulses within each graticule
lines.
17. Switch on the power. Observe the effect on timing frame as you vary DC1 and
DC2 controls.
18. Note that the signals in the two cases are identical to that of ST2103 trainer's
PCM data output but delayed by half data clock. The recovery & interpretation
of NRZ (L) waveform at the receiver is in ST2104 work book.
Refer the ST2104 work book for more information.
Non - Return - To Zero (Mark) : [NRZ (M)] :

ST2106 & ST2107
The NRZ (M) code is very much similar to the NRZ (L) code. Here if logic 1 is to be
transmitted. The new level is inverse of the previous level i.e. change in level occurs.
It a data '0' is to be transmitted the level remains unchanged. Thus in the case of NRZ
(M) waveform the present level is related to the previous levels. See figure 5.
Thus, no longer the absolute value of signal is necessary instead it is the change in the
level for which we look now.
Remember, ----- A change means a logic '1'
----- No change means logic '0'
NZR (M) Format

Figure 5
Clock Recovery :
The receiver can extract the timing information from the NRZ (M) waveform unless
there are long periods of no level changes corresponding to long streams of ‘0's. Here
long stream of 1's are not a problem as in NRZ (L) because now it causes a level
change continuously & the receiver can easily extract the clock information. This is a
slight improvement over NRZ (L) waveform.
Band Width A DC Level :
The NRZ (M) is similar to NRZ (L) waveform in respect of the bandwidth utilized &
the passing of DC Levels. A considerable advantage of NRZ (M) is that it is
independent of the absolute level of the incoming data. The receiver simply has to
know the level changes. This is an advantage in phase shift keying as will be
discusses later on, where the receiver looks for a change in phase of the incoming
signal.
Decoding :
The NRZ (M) can be converted to NRZ (L) code by a bit decoder. The bit decoder
samples the incoming data bit, holds it for a moment takes a new sample & compare
the two, to see whether the changes has occurred. If it has occurred it gives output
logic '1' & if not it gives outputs logic '0'. This is the required NRZ (L) code.

ST2106 & ST2107
Experiment 2
Objective :
Study of NRZ (M) Code and its Detection
Procedure :
Steps (1) to (13) : Follow the set up procedure for steps 1 to 13 as given in
experiment1. Also Set pulse generator delay adjust potentiometer fully clock
wise in step 6.
1. Monitor the NRZ (M) output in data formatting circuit block (TP6). The
waveform will be identical to what's shown in figure 1 before or it will be the
logical inverse of the other. The reason is that the present level does not depend
on the current data bit, but also of the previous level.
2. Switch off the instruments. Make the following additional connections as shown
in figure 6.
a. Between ST2106 and ST2107
ST2106 ST2107
NRZ (M) output (TP6) to Bit decoder input (TP39)
b. Between ST2107 and ST2104
ST2107 ST2104
Bit decoder (TP39) input Clock regeneration circuits input (TP3)
Bit decoder output (TP40) to PCM data input (TP1)
ST2104 ST2107
Clock regeneration circuit to Clock input (TP41) Output (TP8)
On ST2104 trainer connect clock regeneration circuit's output (TP8) to RX
clock input (TP46)
3. Switch on the power.
4. The bit decoder samples the NRZ (M) waveform at the centre of each data bit.
If the sampled level bit is same as the previous level, the decoder output a low
level or logic '0'. If however, the sampled data level differs from the previous
one, the decoder's output is logic '1'. Thus the decoders output is a NRZ (L)
signal which can be monitored at decoder's output (TP40). Observe that the
output is identical to ST2106 NRZ (L) output signal (TP5) but delayed one bit
time. Also observe the bit decoder output (TP40) with respect to clock input
(TP4)
5. Switch on the ST2103 trainer’s pseudo - random sync code generator.
6. Observe that now the receiver is frame synchronized to the transmitter. This is
indicated by the fact that ST2103 trainer's A/D converter LEDs and ST2104
trainer's D/A converter LEDs carry the same data.
7. Also observe that now the NRZ (M) waveform is non repeatable. This is
because the sync data bit is different for different frames.
8. Switch off the trainers. On ST2103 disconnect the two inputs to channel 0 &
channel 1. Instead connect CH 0 to 1 KHz signal & CH.1 to 2 KHz signal.
9. Switch on the power. Observe the two channel outputs on ST2104 trainer (TP33
& TP36) simultaneously. Use dual trace oscilloscope. Also observe that there is
no interference between the two waveforms and the output changes in
amplitude by varying the function generator potentiometer.

ST2106 & ST2107
Figure 6
Return To Zero (RZ) Format :
The RZ code provides a partial solution to overcome the receiver clock regeneration
problem with NRZ (L) code. It is similar to NRZ (L) code, except that the information
is contained in the first half of the bit, interval, while the level during the second half
of each period is always 0 volts. The comparison of the two waveforms for a given
data is shown in figure 7. The change may not see much, but it has two main effects
as will be discussed in following paragraphs.
RZ Format
Figure 7

ST2106 & ST2107
Receiver Clock :
One advantage of RZ signal is that now it has rising & falling transitions for every
data 'I' sent. This leads to a greater no. of transitions. These extra transitions tend to
make the receiver clock generation circuit more simpler than in case of NRZ (L) code.
Even if we utilize only the rising edge, RZ will produce two rising transitions for two
consecutive l's instead of one as in case of NRZ (L) code. But RZ code proves
helpless when it encounters long stream of zeros.
Bandwidth :
The maximum signal frequency of RZ signal occurs when a string of a data '1' is
transmitted. It is equivalent to sending two logic levels in each clock period i.e. in
most case; the maximum signal frequency is same as the data clock rate. This is twice
as many changes per second as for the NRZ (L) code. Therefore the bandwidth
required is twice as that required for the NRZ waveforms.
DC Level :
Another problem with RZ is that like NRZ (L) it has DC Component & hence it can
not be utilized for systems / links, which cannot pass DC & in NRZ (L) decoding the
level is read by the receiver halfway through each bit interval to let the data settle
down after transitions. Otherwise the level may be wrongly read.
In RZ code, to catch the mid-point of the data the receiver must be clocked at quarter
way through the bit interval. The data is read on the rising edge of the regenerated
clock in the receiver.
In spite of its deficiencies RZ is often used because it is simple to generate & yet
produces more transitions than NRZ, there by making the receiver clock regeneration
some what easier.

ST2106 & ST2107
Experiment 3
Objective :
Study of RZ Code and its Detection
Procedure :
experiment1. Also set pulse generator delay adjusts fully clockwise in step 6.
1. Examine the RZ output from the ST2106 trainer's data formatting circuit at TP7
with respect to data clock (TP4). Note that the waveform displayed is as shown
in figure 1.
2. Switch off the power. The procedure for recovering RZ (L) waveform is similar
to that of NRZ (L) waveform, the data is simply clocked in at correct instance of
time. The difference between the clocking a RZ signal & NRZ (L) signal is that
for RZ, the data is clocked a quarter way through each bit interval where as for
the NRZ (L) waveform, the data is clocked in half way through each bit time.
This can be seen from following figure 8.
Figure 8
3. Make following connections (Additionally).
ST2106 ST2104
RZ output (TP7) to PCM. data input (TP1)
4. Note if the distance is too large for a signal connector link, you can use unused
joint input sockets. This may damage the components
5. Make following connections on ST2104 trainer PCM data input (TP1) to clock
regeneration circuit input (TP3).
6. Clock regeneration circuit output (TP8) to RX clock input (TP46) See
connection in figure 9
7. Ensure that the RZ waveforms is clocked into the receiver at correct instance of
time by turning the pulse generator delay turning adjust pot on ST2104 trainer
fully anti clockwise. Turn ‘On’ the power. Verify the correct clocking of RZ

ST2106 & ST2107
data in to receiver by verifying that the rising edge of the correct

(approximately) centre of each 'RZ' pulse.
8. Monitor the regenerated data clock at TP8 of ST2104 and see that it runs
approximately a quarter cycles later than data clock on ST2106 TP4. If the
frequency is incorrect check the adjustment of the RX clock regeneration circuit.
9. Switch on the pseudo - random sync code generator & note that the transmitter
& receiver have 'Frame - Synchronized'. This can be verified by observing the
A/D counter LEDs ‘On’ ST2103 trainer & D/A counter LEDs on ST2104
trainer. They should carry same data.
10. Switch off the trainers. Disconnect the inputs CH0 & CH1 connect CH0 to 1
KHz signal & CH1 to 2 KHz signal.
11. Switch on the power. Switch the dual trace oscilloscope to internal triggering.
Monitor both channel outputs of ST2104 trainer (TP33 & TP36). Both channels
are completely independent. If some interference is found to be present it can be
eliminated by adjusting pulse generator delay adjust potentiometer.
12. Try the above experiment with pseudo random sync code generator in ST2103
trainer to ‘Off’? What is its effect?
Figure 9

ST2106 & ST2107
Introduction to Biphase Codes

The main disadvantage with all the previous formats is their inability to provide
reliable clock synchronized information to the receiver clock. biphase codes
overcome this problem by providing the transition in both 0's and ‘1’s.
The two most common biphase codes in practice are biphase (Manchester) & biphase
(Mark) codes. Also these codes are independent of the DC Levels i.e. they have zero
DC component.
Biphase (Manchester) Coding :
The encoding rules for biphase (Manchester) code are as follows. A data '0' is
encoded as a low level during first half of the bit time and a high level during the
second half.
A data '1' is encoded as a high level during first half of the bit time and a low level
during the second half. Thus string of l's or 0's as well as any mixture of them will not
pass any synchronization problem in receiver. Figure 10 shows the biphase
(Manchester) waveform for a given data stream.
Biphase (Manchester) Format

Figure 10
Bandwidth :
The Biphase (Manchester) code always contains at least one transition per bit time,
irrespective of the data being transmitted. Hence the maximum frequency of the
Biphase (Manchester) code is equal to the data clock rate when a stream of
consecutive data '1' & '0' is transmitted. Therefore the required bandwidth is same as
that of the RZ code & double as that of the NRZ (L) code.

ST2106 & ST2107
DC Level :
Since the biphase (Manchester) code has a high level for half of each data bit time &
low level for second half irrespective of the data. The effective DC level of the
biphase coded waveform is zero. This allows it to be used in AC coupled
communication systems.
Problem In Decoding :
This form of coding certainly provides plenty of rising edges for clock
synchronization but they do not all occur at same time e.g. we have a rising transition
at the start of code for data 'I' where as for data '0' we have it at the midway of the
data bit time. This causes confusion in the clock regeneration circuit.
To overcome this, we employ a special biphase clock recovery circuit which can be
synchronized by the rising edge occurring at either time.
Rest of the decoding is same as for the RZ code. Since the valid data is carried for in
first half of each clock period, we ensure that the regenerated receiver clock's rising
edge occurs at this time.

ST2106 & ST2107
Experiment 4
Objective :
Study of Biphase (Manchester) Code and its Detection
Procedure :
experiment 1. Also set pulse generator delay adjusts fully clockwise in step 6.
1. Use the other trace of your oscilloscope to observe the biphase (Manchester)
waveform at (TP8) of ST2106. This is identical to the waveform shown in figure
1.
2. To view the complete waveform adjust the time base & X- position controls
until you have exactly two clock pulse within each of the oscilloscope's vertical
graticule lines. Monitor biphase (Manchester) waveform again.
3. Readjust the time base & X-Position controls to original set-up again. Switch off
the power. As it has been stated earlier in the biphase (Manchester) theory
section, we need a biphase clock recovery circuit, on ST2107 trainer. The
function of biphase clock recovery circuit is that it accepts rising edges at both
the centre of a bit interval as well as at the start. Its output is a square wave
whose period is equal to one bit interval & where as rising edge occupies one
quarter (1/4) of the way through the bit interval.
4. Make the following additional connections. (see figure 11) Biphase
(Manchester) output (TP8) on ST2106 to biphase clock recovery circuit input
(TP31) on ST2107.
5. Make the following connections between ST2107 and ST2104 trainers.
6. Biphase clock recovery circuit input (TP31) ‘On’ ST2107 to PCM data input
(TP1) on ST2104.
7. Biphase clock recovery circuit output (TP32) on ST2107 to 'RX clock input
(TP46) on ST2104 see figure 11.
8. Switch on the trainers. On close observation of the regenerated data output. We
see that the frequency of the signal is same but is quarter cycle delayed as
compared to the data clock.
9. Switch off the trainers. Disconnect the CH0 & CH 1 inputs & connect 1 KHz
output to CH0 & 2 KHz output to CH 1.
10. Turn ‘On’ the power. Observe the two channel outputs on ST2104 trainer (TP33
& 36). Also observe they are independent is found, it can be removed by
adjusting the pulse generator delay adjust potentiometer control slightly.

ST2106 & ST2107
Figure 11
The Biphase (Mark) :
The biphase (Mark) is yet another form of biphase formats. In this coding also, the
data is coded as two levels in each bit time. Here, the sequence of transmitted levels
(low succeeded by high) or (high succeeded by low) depends on the order of sequence
in previous bit time and the present data. The encoding laws followed by biphase
(mark) format are :
a. If a data '0' is to be transmitted, the sequence of the transmitted levels will
remain same as for the previous bit interval.
b. If a data '1' is to be transmitted, the sequence of the transmitted levels will
reverse i.e. phase reversal will occur.
Thus, Logic '0' --------> Bit Pattern Stays the Same
Logic '1' --------> Phase Reversal
The figure 12 would make it very clear.

ST2106 & ST2107
Biphase (Mark) Format

Figure 12
Bandwidth :
The biphase (Mark) code being very similar to the biphase (Manchester) coding
requires same amount of bandwidth i.e. double as that of the NRZ (L) code. This is
the required bandwidth in worst case when a series of consecutive 'l's occur.
DC Level :
Similar, to the biphase (Manchester) code, this code too is independent of the DC
Level. This is so because for every bit time the level is high for a half period & low
for other half. This feature makes it useful in applications & systems supporting only
the AC coupling.
Receiver Clock Regeneration :

This coding provides plenty of rising edges for clock synchronization. But as with
biphase (Manchester) these do not all occur at the same time e.g. in one of the rising
edge may occur at the start of the bit interval where as in other bit it may occur mid-
way between the bit interval.
Again to over come this problem biphase clock recovery circuit is used which can be
synchronized by rising edge occurring at either time, as we have studied earlier.
Rest of decoding is same as that for biphase (Manchester). But since the output gives
the information other than the actual levels, it needs to be further processed in bit
decoder as has been studied in NRZ (M) decoding. In this circuit each sample is
compared with the previous one. If they are same, a logic '0' is produced if different, a
logic '1'.
The advantage of this system over biphase (Manchester) is that it is suitable for the
systems where it is easier to spot the changes in sequence than the actual level e.g. in
PSK modulation system.

ST2106 & ST2107
Experiment 5
Objective :
Study of Biphase (Mark) Code and its Detection
Procedure :
experiment1 . Also set pulse generator delay adjusts fully clockwise in step 6.
1. Observe the biphase (Mark) output from ST2106s data formatting circuit (TP9)
along with the data clock (TP4) on dual trace oscilloscope. The wave form may
be as shown in the figure 1 or it may be its logical inverse. The reason is that
biphase (Mark) wave form depends not only on the current data bit but also on
the previous one.
2. To see the other alternative, just try disconnecting the input to channel 1, by
pulling out the connector for a moment & then reinserting it. After few tries, you
will see the waveform change to the logical inverse of the previous one.
3. To monitor the whole frame, adjust the time base & X-position control so that
now two data clocks are visible in vertical graticule lines. Monitor the biphase
(Mark) waveform at (TP9) again.
4. To decode biphase (Mark) signal, the receiver clock must go 'High' one quarter
of the way through each bit interval as for the biphase (Manchester) signal.
Therefore biphase clock recovery circuit is used. Biphase (Mark) obeys the
same rule as NRZ (M) in case of bit level decision with respect to previous bit.
Therefore the NRZ (L) data can be recovered from the bit decoder by clocking
the biphase (Mark) data. Using the output signal from biphase clock recovery
circuit.
5. Reset the time base & X- position control to the original one. Switch off the
power. Make following connections between ST2106 & ST2107 trainers.
6. Connect the biphase (Mark) output (TP9) of ST2106 to biphase clock recovery
circuitry (TP31) of ST2107.
7. Make additional following connections on ST2107 and ST2104 trainer. See
figure 13.
a. Connect biphase clock recovery circuit input (TP31) to bit decoder input
(TP39) on ST2107.
b. Biphase clock recovery circuit output (TP32) to clock input on bit decoder
clock input (TP41) of ST2107 and also to ST2104 RX clock input TP46.
c. Bit decoder output (TP40) of ST2107 to ST2104 PCM data input (TP1)
8. Observe the regenerated data clock at (TP32) of ST2107 which should have the
same frequency as the data clock but is delayed by approximately quarter cycle.
Examine the input and output of biphase clock recovery circuit (TP31 & 32) and
also the output of bit decoder (TP40) on ST2107 trainer. The output is of the bit
decoder is required NRZ (L) waveform.

ST2106 & ST2107
9. To set up a complete system, switch on the pseudo random sync code generator
& note that the trainers are in frame synchronization. This can be verified by
checking the D/A converter LEDs ST2104 trainer. LED should light up same as
at the A/D converter LEDs on ST2103 trainer.
10. Observe the biphase (Mark) waveform at TP9 on ST2106 trainer. It is very
difficult to observe the waveform in this case. Because now the '15 - bit word' is
now changing due to pseudo - random sync code generator.
11. Switch off the power. ‘On’ ST2103 disconnect the inputs to channel 0 &
channel 1. Instead connect 0 channel to the 1 KHz signal & the '1' channel to the
2 KHz signal.
12. Switch the dual trace Oscilloscope to internal triggering and adjust the trigger
level.
13. Switch on the Trainer observe the two channel outputs of ST2104 trainer (TP33
& 36). Also notice that the two channels are independent & there should be no
interference between the two waveforms. However, the interference, if present,
can be eliminated by adjusting the pulse generator delay adjust potentiometer.
Check the amplitude of input sine waves to check whether the corresponding
check is reflected at the receiver.

ST2106 & ST2107
Figure 13
Introduction to Three Level Codes
The three level codes, as the name suggests have three levels. Generally, they are two
bipolar voltages & a 0Volt. The two important codes in this category are Return-to-
bias (RB) and Alternate Mark Inversion (A.M.I.). The return to bias coding method
provides easy clock synchronization & the alternate mark inversion coding is
particularly suitable for the AC coupled communication systems.
Return - To - Bias (R. B.) :
R. B. Code is a three level code. The levels used are positive voltage level negative
voltage level, and an intermediate (or bias) level (usually 0volts). There is no
restriction on the value of bias level. It can be above or below the logic 0 and 1
voltages or it can be between them.
During the first half period of each clock bit, a positive level is transmitted for data '1'
and a negative level for a data '0'. During the second half, the waveform just returns to
the bias level. Figure 14 shows the coded waveform for the given data.

ST2106 & ST2107
RB Format
Figure 14
Bandwidth Requirement :
Since the maximum signal frequency is equal to the data clock frequency, the
bandwidth requirements is same as that for RZ, biphase codes & double that for the
NRZ codes.
DC Level :
As it can be seen from the above figure the waveform at the output is not balanced
with respect to the mean level. The DC Level of the waveform depends on the strings
of l's & 0's. Therefore we cannot use it in an AC coupled communication link.
Clock Recovery :
The most significant advantage of RB coding is that the timing information is very
easily obtained. The magnitude of the transmitted waveform itself is the original data
clock signal. The system is even referred to as 'Self Clocking' system. The other
disadvantage of RB signal is that transmitter must generate three levels, a more
complex transmitter is required.

ST2106 & ST2107
Decoding :
A simple comparator decodes the RB signal into RZ waveform. The comparator
output is a logic 1(+5V), if the signal is greater than the bias voltage (threshold
voltage) applied to the other input and a logic 0 (0V) output if the input voltage is
less. The rest of decoding is same as that for the RZ code. See figure 15.
Signal Decoding
Figure 15
The clock can be simply extracted by a circuit that gives a positive output when RB
signal is not at 0volts (polarity doesn't matter) & provides a zero voltage whenever the
RB waveform is at bias level.

ST2106 & ST2107
Experiment 6
Objective:
Study of RB Code and its Detection
Procedure :
experiment 1, also set pulse generator delay adjust fully clockwise in step 6.
1. Before experimenting with RB code. It is necessary to know about functioning
of unipolar - bipolar converter. The unipolar - bipolar converter has two inputs.
a. The Input (TP19). A logic 0 applied to this socket produces a logic
0 at the output (TP21).
b. When the unipolar - Bipolar converter is not disabled (when a logic 1 is
applied to input or is kept open), the outputs (TP21) depends on
the input (TP20) applied in following manner.
Disabled = Output -----> 0 Volts

Enabled & Input Logic 1 = Output -----> + 4 Volts
Enabled & Input Logic 0 = Output -----> - 4 Volts
Table 1
If the data clock is applied to disable input, the output of unipolar - bipolar
converter automatically goes to the '0' level during second half. This ensures the
bias level for the RB wave during second half. In the first half when the
converter is enabled, the output is +4volts or -4volts depending upon the input
applied. To generate & decode RB wave. Configure additionally the trainers as
shown in figure 16.
2. Examine the output of converter (TP21) with respect to data clock (TP4) and
with respect to NRZ (L) waveform (TP5) on ST2106 to understand how RB
waveform is generated check whether the unipolar - bipolar converter's output is
the same RB waveform shown in figure 1.
3. Switch off the power. Check for the following connections between ST2106 &
ST2107 trainer
4. Unipolar - Bipolar converter output (TP21) of ST2106 connected to
comparator1 input (TP46) of ST2107 in data squaring circuit block. Also, note
that on board ST2107 trainer,
a. Comparator 1 input (TP46) to comparator 2 input (TP49)
b. Comparator l's bias pot turned fully clockwise.
c. Comparator 2's bias pot turned fully anticlockwise.
This sets the comparator's threshold level as shown in figure 17.

ST2106 & ST2107
Figure 16
5. Turn ‘On’ the trainers : Examine the outputs of comparator 1 (TP47).
Observe that RB signal has been turned to RZ signal. To decode this RZ signal
applied at PCM data input on ST2104, we require a regenerated clock
waveform delayed by quarter bit time. Also observe the output of comparator 2
(TP50).
6. The output of the two comparators go to Exclusive-NOR gate (also abbreviated
as EX-NOR, E NOR, X NOR gate). It is 'equivalence gate' i.e. its output is logic
‘l' when its inputs are equal.
7. Now take a look at EX-NOR gate output (TP51) of the data squaring circuit on
ST2107 trainer. Notice that the output waveform is the extracted data clock
signal. Thus the receiver is able to extract the timing information irrespective of
the transmitted data.
8. Before this regenerated clock can be used, it must be delayed by quarter bit
time. This is done by connecting the EX-NOR output (TP51) to ST2104's clock
regeneration circuit input (TP3). Turn the pulse generator delay adjust fully
anticlockwise. This introduces a delay of a quarter bit time.
9. You can compare the input & output (TP3 & 8 respectively) of the clock
regeneration circuit.

ST2106 & ST2107
10. Check that the clock regeneration circuits output (TP8) is connected to the RX
clock input (TP46) on ST2104 trainer.
11. Turn ‘On’ the pseudo random sync code generator. See that the transmitter &
receiver are frame synchronized This can be verified by checking that the A/D
converter LEDs on ST2103 trainer & D/A converter LEDs on ST2104 trainer
carry same data.
Threshold Level of Comparators

Figure 17
12. Switch off the supply. Disconnect the inputs to channel 0 & channel 1 instead
connects CH0 to 1 KHz signal & CH1 to 2 KHz signal.
13. Switch on the trainers. Switch the oscilloscope for internal triggering.
14. Use a dual trace oscilloscope to monitor the two channels (CH0 & CH1) outputs
(TP33 & 36) on ST2104 trainer. The output is similar to the input signals
applied. Also notice that they are independent & free of interference i.e.
variation of one's parameter doesn't affect other. If any interference is present, it
can be removed by adjusting the pulse generator delay adjust potentiometer.
Alternate - Mark Inversion (AMI) :
AMI being a three level code uses three levels namely, a positive voltage level a
negative voltage level and a bias level of 0 volts.
Like RB waveform, the AMI always returns to the bias level during second half of the
bit time interval during the first half the transmitted level can be a positive level a
negative level or a bias level, according to following coding rules.
a. A data '0' is always represented by the bias level.
b. A data '1' may be represented by either a positive level or negative level, the
level being chose opposite to what it was used to represent the previous data '1'.
Thus we have alternating positive level and negative level. This justifies its
name Alternate Mark Inversion Mark is a telegrapher's word for logic '1'. The
figure 18 shows the AMI waveform for the given data. The AMI waveform can
be thought of as a gradual development from NRZ (L) to RZ and then finally to
AMI.

ST2106 & ST2107
In NRZ (L) Code the pulse simply goes to the required level for one bit clock. In RZ,
the pulse goes to the required level for first half & then returns to zero during the
second half. In AMI, first logic '1' go to a positive voltage level & then the second 1
goes a negative level alternating and so on. The development can be seen from the
figure
Various Formats Representing Arbitrary Data

Figure 18
Bandwidth Requirement :
Since the maximum transition rate for AMI can only occur during a stream of all '1’s,
we have maximum number of two transitions per data bit time. Thus the bandwidth
required is twice that required for the NRZ codes & equal to the other codes
mentioned earlier
DC Level :
The main advantage of AMI code is that it is independent of DC level. This happens
because the '1's are represented by alternating positive levels & negative levels with 0
volts for data '0'. Therefore average DC Level is always zero volts for any
combination of '1's & '0's.
This renders it very useful in AC coupled communication systems / link e.g. in
telephony PCM. This makes it very popular for use in PCM telephone systems.

ST2106 & ST2107
Clock Regeneration :
The disadvantage of AMI that there are no transition of a long string of 0’s is
transmitted. Therefore the receiver may slip out of synchronization in such cases.
Since AMI is a three bit code, the transmitter is more complex.
An advantage associated with AMI is that if due to noise the voltage level of 1's is
reduced/enhanced so much that it acquires the polarity of the previous bit, the receiver
will take it as a violation of coding rule & may ask the transmitter to send the string
again. Thus the transmission reliability can be increased.

ST2106 & ST2107
Experiment 7
Objective :
Study of AMI Code and its Detection
Procedure :
experiment 1. Also set pulse generator delay adjusts fully anti clockwise in step
6. In step 10 make additional connections on ST2106.
a. RZ output (TP7) to unipolar-bipolar converter's disable input (TP19).
b. NRZ (M) output (TP6) to unipolar - bipolar converter input (TP20).
1. Now on ST2106 connect NRZ (M) output TP6 to unipolar to bipolar converter's
input TP20 & RZ output TP7 to its disable input TP19.
2. Examine the unipolar-bipolar converter's output (TP21) on ST2106 trainer with
reference to the data clock on a dual trace oscilloscope. Compare this with the
AMI waveform shown in figure 1. The output is identical to the AMI waveform
shown or is its logical inverse. The reason for this ambiguity is the fact the
present level for data '1' in AMI coding depends on the level for previous data
'1'. You may obtain the depicted waveform, if you temporarily disconnect the
unipolar - bipolar converter's input temporarily for a second. Insert it again.
After a few try, you will get the depicted waveform.
3. Also, observe the unipolar-bipolar converter's output (TP21) with respect to the
input (TP20) & disable input (TP19). This will help you understand the
technique behind the AMI generation.
4. Switch off the power. Make the following additional connections (See figure 19).
a. Between ST2106 & ST2107 trainers unipolar-bipolar converter output
(TP21) to comparator 1 input (TP46).
b. On ST2107 trainer comparator 1 input (TP49) to comparator 2 input (TP49)
c. Between ST2107 & ST2104 trainers EX-NOR output (TP51) to PCM data
input (TP1).
d. On ST2104 Trainer
i. PCM data input (TP1) to clock regeneration circuit input (TP3)
ii. Clock regeneration circuit output (TP8) to RX clock input (TP46).
5. Switch ‘On’ the power : In ST2107 data squaring circuit block, turn
comparator 1's bias pot fully clockwise & comparator 2's bias pot fully
anticlockwise. Examine the outputs of the two comparators (TP47 & 50)
6. The outputs of the two comparator's goes to the EX-NOR gate. Examine the
EX-NOR gate output (TP51). Notice that the AMI signal has been converted
into RZ wave form by data squaring circuit,

ST2106 & ST2107
Figure 19
7. Ensure that the ST2104 trainer's pulse generator delay adjusts is in fully
anticlockwise position. Examine the RX clock input & PCM data input signals
at (TP46 & TP1 respectively) on ST2104 trainer. Notice that the RZ is being
clocked into the ST2104 Receiver at correct instance of time.
8. Turn ‘On’ the pseudo random sync code generator on ST2103 trainer. Notice
that the transmitter & receiver are in frame synchronization with each other.
Therefore the A/D converter LEDs or ST2103 trainer & the D/A converter
LEDs or ST2103 trainer & the D/A converter LEDs or ST2104 trainer, now
carry the same data.
9. Turn ‘Off’ the trainers. Disconnect the CH 0 & CH 1 inputs on ST2103 to
trainer. Instead connect them to 1 KHz signal & 2 KHz signals respectively.
Turn the oscilloscope to internal triggering mode. Observe the two channel
outputs CH0 & CH l on ST2103 trainer. Notice that the two channels are
independent of each other & free from interference. This can be examined by
varying the amplitude of one signal on ST2103 board. This should not produce
change in the other output at the ST2104 board. If some interference is present,
it can be removed by turning the pulse generator delay adjust potentiometer.

ST2106 & ST2107
Carrier Modulation Introduction

Introduction :
To transmit the digital data from one place to another, we have to choose the
transmission media. The simplest possible method to connect the transmitter to the
receiver with a piece of wire. This works satisfactorily for short distances in some
cases. But for long distance communication & in situations like communication with
the aircraft, ship, and vehicle this is not feasible. Here we have to opt for the radio
transmission.
It is not possible to send the digital data directly over the antenna because the
antennae of practical size works on very high frequencies, much higher than our data
transmission rate.
To be able to transmit the data over antenna, we have to 'modulate' the signal's phase,
frequency or amplitude etc. is varied in accordance with the digital data.
At receiver we separate the signal from digital information by the process of
demodulation. After this process we are left with high frequency signal (called as
carrier signal) which we discard & the digital information, which we utilize.
Modulation also allows different data streams to be transmitted over the same channel
(transmission medium). This process is called as ‘multiplexing’ & results in a
considerable saving in no. of channels to be used. Also it increases the channel
efficiency. The variations of particular parameter variation of the carrier wave give
rise to various modulation techniques. Some of the basic modulation techniques are
described as under.
a. Amplitude Shift Keying (ASK) :

In this technique modulation involves the variation of the amplitude of the
carrier wave in accordance with the data stream.
b. Frequency Shift Keying (FSK) :
This technique involves the variation of carrier frequency with the data
information.
c. Phase Shift Keying (PSK) :
In this technique, the phase of the carrier frequency is varied in accordance with
the data stream.
The selection of particular modulation method used is determined by the application
intended as well as by the channel characteristic such as available bandwidth,
susceptibility of channel fading, antenna characteristics, ability to transmit DC or low
frequencies etc. The last criterion is necessary when data transmission using a
telephone channel is intended, because of transformer or series capacitors getting
included in the transmission path.
EX-FSK is very useful in a fading channel because it is relatively insensitive to
amplitude function. A fading channel is one in which the received signal amplitude
varies with the time because of variability’s in the transmission medium.

ST2106 & ST2107
Amplitude Shift Keying :

The simplest method of modulating a carrier with a data stream is to change the
amplitude of the carrier wave every time the data changes. This modulation technique
is known amplitude shift keying.
The simplest way of achieving amplitude shift keying is by switching ‘On’ the carrier
whenever the data bit is '1' & switching off. Whenever the data bit is '0' i.e. the
transmitter outputs the carrier for a' 1 ' & totally suppresses the carrier for a '0'. This
technique is known as ‘On-Off’ keying figure 20 illustrates the amplitude shift keying
for the given data stream.
Thus,
Data = 1 carrier transmitted
Data = 0 carrier suppressed
The ASK waveform is generated by a balanced modulator circuit, also known as a
linear multiplier. As the name suggests, the device multiplies the instantaneous signal
at its two inputs. The output voltage being product of the two input voltages at any
instance of time. One of the input is AC coupled 'carrier' wave of high frequency.
Generally, the carrier wave is a sine wave since any other waveform would increase
the bandwidth, without providing any advantages. The other input which is the
information signal to be transmitted, is DC coupled. It is known as modulating signal.
ASK modulation
Figure 20
In order to generate ASK waveform it is necessary to apply a sine wave at carrier
input & the digital data stream at modulation input. The double - balanced modulator
is shown in figure 21.

ST2106 & ST2107
Amplitude Shift Keying

Figure 21
The data stream applied is unipolar i.e. 0 volts at logic '0' & + 5 Volts at logic '1'. The
output of balanced modulator is a sine wave, unchanged in phase when a data bit ‘l' is
applied to it. In this case the carrier is multiplied with a positive constant voltage
when the data bit '0' is applied, the carrier is multiplied by 0 volts, giving rise to 0 volt
signal at modulator's output.
The ASK modulation result in a great simplicity at the receiver. The method to
demodulate the ASK modulation results in a great simplicity at the receiver. The
method to demodulate the ASK waveform is to rectify it, pass it through the filter &
'Square Up' the resulting waveform. The output is the original data stream. Figure 22
shows the functional blocks required in order to demodulate the ASK waveform at
receiver.
ASK Demodulator
Figure 22

ST2106 & ST2107
The various steps involved are summed below :

Step A : The ASK waveform is rectified by a diode rectifier, giving a positive going
signal. This signal is too rounded to be used as digital data. Also the carrier
component is still present & it is of unreliable amplitude due to the attenuation &
noise in transmission path. In fact it is a great drawback associated with ASK
modulation. The data level may be misinterpreted by the receiver if the amplitude
change is too much.
Step B : After rectification, the signal is passed through the low pass filter to remove
the carrier component. This result in slightly rounded pulses of unreliable amplitude.
Step C : These rounded pulsed are then 'Squared Up' (i.e. shaped in a square wave
fashion) by passing it through voltage comparator set at a threshold level. If the input
voltage exceeds the threshold level, the comparator output is a +5V signal and in
other case it is O\Z Thus at the end we have the true copy of the original input data
see figure 23.
ASK Modulation
Figure 23
Amplitude shift keying is fairly simple to implement in practice, but it is less efficient,
because the noise inherent in the transmission channel can deteriorate the signal so
much that the amplitude changes in the modulated carrier wave due to noise addition,
may lead to the incorrect decoding at the receiver. This is particularly true when the
noise added is comparable to the comparator threshold level. Hence, this technique is
not widely used is practice. Application wise, it is however used in diverse areas and
old as emergency radio transmissions and fiber-optic communications.

ST2106 & ST2107
Experiment 8
Objective :
Study of ASK Modulation and its Demodulation
Procedure :
experiment 1. Also Set pulse generator delay adjusts fully clockwise in step 6.
1. Switch off the power. Connect additional board as shown in figure 24 as follows
:
a. On ST2106 trainer :
i) NRZ (L) output (TP5) to carrier modulation circuit’s modulation input
(TP27).
ii) 1.44 MHz carrier output (TP16) to carrier input socket of modulator
circuit (TP26).
b. Between ST2106 and ST2107 :
i.) Modulator 1 output (TP28) to ASK demodulator input (TP21).
c. On ST2106 and ST2107 :
i.) ASK demodulator output (TP22) to Low Pass Filter 1 input (TP23).
ii.) Low Pass Filter 1 output (TP24) to comparator 1 input (TP46)
d. On ST2104 trainer :
i.) PCM. data input (TP1) to clock regent circuit input (TP3)
ii.) Clock regent circuit output TP8 to RX clock input (TP46)
e. Connect :
i.) Comparator 1 output (TP47) on ST2107 to PCM data input (TP1) on
ST2104.
2. Turn ‘On’ the trainers : Monitor NRZ (L) output (TP5) from ST2106 trainer
on one channel of the oscilloscope Use the other channel to monitor the output
of modulator 1 (TP28) in ST2106 trainer.
3. Three variables have been provided in the modulators block. Their use may be
necessary to obtain a required ASK waveform. These variables are
a. Gain : This pot adjusts the amplification of the modulator's output. Adjust
this pot till the output is not a 2Vpp signal in ‘On’ state.
b. Modulation Offset : This control is used to adjust the amplitude of the
‘Off’ signal. Adjust this control till the amplitude of the ‘Off’ signal is an
close to zero as possible.
c. Carrier Offset : This control adjusts the ‘Off’ bias level of the ASK
waveform. Adjust this control till the ‘Off’ level occurs midway between the
‘On’ signal peaks.
4. To see the demodulation process, observe the output at the ASK demodulator
(TP22) & low pass filter (TP24) on ST2107 trainer.

ST2106 & ST2107
5. The last stage of demodulation is 'squaring up' of filter output. In order to

achieve this it is necessary to adjust the bias level for comparator 1 so that the
output has the correct pulse width.
6. Adjust it till the output signal pulse width is not similar to the NRZ (L) data
pulse width. You can observe these two simultaneously on the dual trace
oscilloscope. The two will be identical once the bias level is adjusted except for
short delay between them.
7. Turn ‘On’ the pseudo-random sync code generator on ST2103 trainer. This pulls
the transmitter & receiver in 'Frame - Synchronization'. Observe the A/D
Converter LEDs on ST2103 trainer & D/A Converter LEDs on ST2104 trainer.
Now they will be carrying the same data. Change the position of the DC l
potentiometer Observe that the same change is reflected at the receiver.
8. Turn ‘Off’ the power : Disconnect CH0 & CH1. Instead connect them to 1
KHz & 2KHz signal respectively. Turn ‘On’ the trainers. & check the
reconstructed analog output on ST2104 CH 0 & CH 1 (TP33 & 36).
9. You can use any data format available on ST2106 trainer to modulate the
carrier. Remember to demodulate the carrier as described above & convert the
date format back to NRZ (L) format by means of reformatting techniques
described in the earlier sections.
10. The same experiment can be performed by using 960 KHz (1) signal instead of
1.44 MHz signal.

ST2106 & ST2107
Figure 24
Frequency Shift Keying :
In frequency shift keying, the carrier frequency is shifted in steps (i.e. from one
frequency to another) corresponding to the digital modulation signal. If the higher
frequency is used to represent a data '1' & lower frequency a data '0', the resulting
Frequency shift keying waveform appears as shown in figure 25.
Thus Data = 1 high frequency
Data = 0 low frequency
FSK Waveform
Figure 25

ST2106 & ST2107
On a closer look at the FSK waveform, it can be seen that it can be represented as the
sum of two ASK waveforms. This is illustrated in figure 26.
Generation of FSK Waveform from ASK Waveforms

Figure 26
Let us assume that we apply the above data stream to an ASK modulator using the
higher frequency carrier. The resulting output is shown in figure 27
Let us now invert the original data stream.
Original 0 1 1 0 0 0 1 0 1 1
Data Steam
Inverted 1 0 0 1 1 1 0 1 0 0
Data Steam :
Figure 27
We now apply the inverted data stream to the ASK modulator using a lower stream
frequency carrier. The result is the original data '0' filled with the lower frequency
carrier shown in figure 28

ST2106 & ST2107
ASK Wave form using Lower Frequency Carrier with Inverted Data Stream
Figure 28
Lastly, we have to sum the two ASK waveforms, to get a FSK wave.
The functional blocks required in order to generate the FSK signal is as shown in
figure 29. The two carriers have different frequencies & the digital data is inverted in
one case.
FSK Modulator
Figure 29

ST2106 & ST2107
The demodulation of FSK waveform can be carried out by a phase locked loop. As
known, the phase locked loop tries to 'lock' to the input frequency. It achieves this by
generating corresponding output voltage to be fed to the voltage controlled oscillator,
if any frequency deviation at its input is encountered. Thus the PLL detector follows
the frequency changes & generates proportional output voltage. The output voltage
from PLL contains the carrier components. Therefore the signal is passed through the
low pass filter to remove them. The resulting wave is too rounded to be used for
digital data processing. Also, the amplitude level may be very low due to channel
attenuation. The signal is 'Squared Up' by feeding it to the voltage comparator. Figure
30 shows the functional blocks involved in FSK demodulation.
FSK Demodulator
Figure 30
Since the amplitude change in FSK waveform does not matter, this modulation
technique is very reliable even in noisy & fading channels. But there is always a price
to be paid to gain that advantage.
The price in this case is widening of the required bandwidth. The bandwidth increase
depends upon the two carrier frequencies used & the digital data rate. Also, for a
given data, the higher the frequencies & the more they differ from each other, the
wider the required bandwidth. The bandwidth required is at least doubled than that in
the ASK modulation. This means that lesser number of communication channels for
given band of frequencies.

ST2106 & ST2107
Experiment 9
Objective :
Study of FSK Modulation and Demodulation
Procedure :
experiment 1, also set pulse generator delay adjust fully clockwise in step 6.
1. Switch off the power. Make the additional connections as shown in figure 31 as
follows
a. On ST2106 Trainer :
i) NRZ (L) output (TP5) to modulation input of unipolar-bipolar
converter (TP27)
ii) Modulation input (TP27) to data inverter input (TP32)
iii) Modulator output (TP28) to summing amplifier input A (TP34)
iv) Data inverter output (TP33) to modulation input of modulator 2 (TP30)
v) 1.44 MHz carrier (TP16) to Modulator 1 carrier input (TP26)
vi) 960KHz (1) carrier (TP17) to modulator 2 carrier input (TP29)
vii) Modulator 2 output (TP31) to summing amplifier input (TP35)
b. Between ST2106 & ST2107 trainer :
i) Summing amplifier output (TP36) to PLL detector input (TP16)
c. On ST2107 trainer :
i) PLL detector output (TP17) to low pass filter 1 input (TP23)
ii) Low pass filter 1 Output (TP24) comparator 1 input (TP46)
d. Between ST2107 & ST2104 trainer :
i) Comparator 1 output (TP24) to PCM. data input (TP1)
e. On ST2104 trainer :
i) PCM. data input (TP1) to clock regeneration circuit input (TP3)
ii) Clock regeneration circuit output (TP8) to RX clock input (TP46)
2. Monitor the output of modulator 1 (TP28) on ST2106 trainer. Make the
adjustments of the given controls in the modulator block as follows
a. Gain : Adjust this pot until the amplitude of the ‘On’ signal is 2Vpp.
b. Modulation off set : It is used to control the amplitude of ‘Off’ signal.
Adjust it till the ‘Off’ signal level doesn't approach as close to zero as
possible.
c. Carrier Offset : This adjusts the ‘Off’ bias level of the ASK waveform.
Adjust this control until the ‘Off’ level occurs midway between the peaks of
the ‘On’ level of the signal

ST2106 & ST2107
Figure 31
3. Repeat step no 15 with modulator 2 by observing its output at TP31.
4. Observe the output of the summing amplifier on the ST2106 trainer at (TP36)
Note that it is the FSK waveform for the given data.
5. Adjust the ‘Gain’ control of modulator 2, if necessary to make the amplitude the
two frequency components equal.
6. Display the FSK waveform simultaneously with NRZ (L) output. Observe that
for data bit '0' the FSK signal is at lower frequency (960KHz) & for data bit '1’
the FSK signal is at higher frequency (1.44 MHz).
7. Now, to study about demodulation, examine the input (TP16) and the output
(TP17) of ST2107 FSK demodulator. The PLL detector has been used as the
FSK demodulator on this trainer.
8. Observe that the output voltage of the PLL detector is greater for higher
incoming frequency. Also, observe that for both incoming carrier frequencies,
the demodulator's output also contains a component at that frequency.
9. The unwanted frequency component is removed by passing it through the low
pass filter. On a dual trace oscilloscope examine the input (TP23) & output

ST2106 & ST2107
(TP24) of ST2107 low pass filter 1 simultaneously. Observe that the output
contains no carrier frequency components.
10. The rounded output of the low pass filter is removed by passing it through the
data squaring circuit. But prior to it, the BIAS level of the comparator I is to be
adjusted to a value until the output pulse width (TP47) is same as the NRZ (L)
input (TP5) on ST2106. For this purpose, display them simultaneously. Observe
that the comparator output is slightly delayed then NRZ (L) input.
11. Turn ‘On’ the pseudo-random sync generator. This locks the transmitter &
receiver in 'frame synchronization. Therefore the data on A/D converter LEDs
on ST2103 trainer is same as that present on D/A converter LEDs on ST2104
trainer. You can examine this fact by varying the data on transmitter trainer
ST2103 by the DC1 pot variation.
12. To examine FSK modulation & demodulation for a time variant data/wave,
connect CH0 and CH1 input to ~1 KHz & ~2 KHz function generator outputs
instead of DC1/DC2 input.
13. Remember to connect/disconnect the links only with the trainers in switched off
position. Switch the oscilloscope for internal triggering. Check the
reconstructed waveform CH0 & CH1 outputs on ST2104 trainer. They should
be identical to the input waveforms. Remember, the two outputs are
independent of each other & thus interference free. Any interference if present
can be removed by adjusting phase generator delay adjusts control.
14. You can try experimenting FSK modulation / demodulation by using any other
data format. Equally, any of the other binary outputs from the Data Formatting
Circuits can be used. But remember to reformat it to NRZ (L) waveform on
ST2107 board, after demodulation, before feeding it to the ST2104 trainer.
PSK and DPSK :
Phase shift keying involves the phase change of the carrier sine wave between ‘0° and
180° in accordance with the data stream to be transmitted. Phase shift keying is also
known as phase reversal keying (PRK). The PSK waveform for a given data is as
shown in figure 32
PSK Waveform

ST2106 & ST2107
DPSK Waveform
Figure 32
Functionally, the PSK modulator is very similar to the ASK modulator. Both uses
balanced modulator to multiply the carrier with the modulating signal. But in contrast
to ASK technique, the digital signal applied to the modulation input for PSK
generation is bipolar i.e. have equal positive and negative voltage levels. When the
modulating input is positive the output of modulator is a sine wave in phase with the
carrier input. Where as for the negative voltage levels, the output of modulator is a
sine wave which is shifted out of phase by 180° from the carrier input. This happens
because the carrier input is now multiplied by the negative constant level. Thus the
output in phase when a change in polarity of the modulating signal results figure 33
shows the functional blocks of the PSK modulator.
PSK Modulator
Figure 33
The unipolar-Bipolar converter converts the unipolar data stream to bipolar data. At
receiver, the square loop detector circuit is used to demodulate the transmitted PSK
signal. Functionally, the demodulator is as shown in figure 34.
PSK Demodulator
Figure 34

ST2106 & ST2107
The incoming PSK signal with 0° & 180° phase changes is first fed to the signal
squarer, which multiplies the input signal by itself. The output of this block is a signal
of twice the frequency with the frequency of the output doubled, the 0° & 180° phase
changes are reflect as 0° & 360° phase changes. Since phase change of 360° is same
as 0° phase change, it can be said that the signal squarer simply removes the phase
transitions from the original PSK waveform.
The PLL block locks to the frequency of the signal square output & produces a clean
square wave output of same frequency. To derive the square wave of same frequency
as the incoming PSK signal, the PLL's output is divided by two in frequency domain
is the divided by 2 circuit.
The following phase adjust circuit allows the phase of the digital signal to be adjusted
with respect to the input PSK signal. Also its output controls the closing of an analog
switch. When the output is high the switch closes & the original PSK signal is
switched through the detector. When the phases adjust block's output is low, the
switch opens & the detector's output falls to 0 Volts. The demodulator output contains
positive half cycles when the PSK input has one phase & only negative half cycles
when the PSK input has another phase. The phase adjust potentiometer is adjusted
properly. The average level information of the demodulator output which contains the
digital data information is extracted by the following low pass filter. The low pass
filter output is too rounded to be used for digital processing. Therefore it is 'Squared
Up' by a voltage comparator.
Since the sine wave is symmetrical, the receiver has no way of detecting whether the
incoming phase of the signal is 0° or 180° This phase ambiguity create two different
possibilities for the receiver output i.e. the final data stream can be either the original
data stream or its inverse.
This phase ambiguity can be corrected by applying some data conditioning to the
incoming stream to convert it to a form which recognizes the logic levels by changes
that occur & not by the absolute value. One such code is NRZ (M) where a change or
the absence of change conveys the information. A change in level represents data '1'
& no change represents data '0'. This NRZ (M) waveform is used to change the phase
at the modulator. The comparator output at receiver can again be of two forms, one
being the logical inverse of the other. But now it is not the absolute value in which we
are interested. Now the receiver simply locks for changes in levels, a level change
representing a '1' and no level changes representing a '0' thus the phase ambiguity
problem does not makes difference any more. This is known as differential phase shift
keying.
From the differential bit decoder output is a data '1' when it encounters a level change
& a '0' when no change occurs. Thus the output from the differential bit decoder is a
NRZ (L) waveform. Figure 35 shows the functional block diagram of the PSK
transmitter & receiver.

ST2106 & ST2107
PSK Transmitter System
PSK Receiver System

Figure 35

ST2106 & ST2107
Experiment 10
Objective :
Study of PSK and DPSK
Procedure :
experiment 1, Also set pulse generator delay adjust fully clockwise in step 6. In
step 5. Set the switch in ST2107 trainer PSK demodulator block to 960 KHz
position.
1. Switch off the power. Make the additional connections as shown in figure 36 as
follows:
i) Carrier input of modulator 1 (TP26) to 960KHz (1) carrier (TP17)
ii) NRZ (M) output (TP6) to unipolar-bipolar converter input (TP20)
iii) Unipolar-bipolar converter output (TP21) to modulator 1 input (TP27)
b. Between ST2106 & ST2107 trainers :
i.) Modulator 1 output (TP28) to PSK demodulator input (TP10)
i.) PSK demodulator output (TP15 to low pass filter 1 input (TP23)
ii.) Low pass filter 1 output (TP24) to comparator 1 input (TP46)
iii.) Comparator 1 output (TP47) bit decoder input (TP39)
d. Between ST2107 and ST2104 trainers :
i.) Bit decoder output (TP40) to PCM data input (TP1)
ii.) Bit decoder input (TP39) to clock regeneration circuit input (TP3)
iii.) Bit decoder clock input (TP41) to clock regeneration circuit output
(TP8)
e. On ST2104 trainers :
i.) Clock regeneration circuit output (TP8) to clock input (TP46)
2. Switch on the trainers.
3. Monitor the modulator 1 output (TP28) in ST2106 trainer with reference to its
input (TP27) by using a dual trace oscilloscope. The three controls in modulator
block may require some setting.

ST2106 & ST2107
Figure 36
a. Gain : This controls the amplitude of the modulator output signal. Vary it
until the amplitude of the output is 2Vpp.
b. Modulation offset : This controls the peak to peak amplitudes of 0° & 180°
phases relative to each other. Vary it till the amplitudes for both faces
become equal.
c. Carrier offset : This control the DC offsets of two phases namely 0° &
180° phases, relative to each other. Vary the control till the DC off set for
them is reduced to as close as zero volts.
Displaying the NRZ (M) input with the PSK modulated waveform helps to
understand the PSK modulation concept. Notice that every time the NRZ (M)
waveform level changes, PSK modulated waveform undergoes a 180° phase
change.
4. To see the PSK demodulation process, examine the input of PSK demodulator
(TP10) on ST2107 trainer with the demodulator's output (TP15). Adjust the
phase adjust control & see its effect on the demodulator's output.

ST2106 & ST2107
Check the various test points provided at the output of the functional blocks of
the PSK demodulator. This will help you fully grasp the PSK demodulation
technique.
5. The output of the demodulator goes to the low pass filter 1's input. Monitor the
filter's output (TP24) with reference to its input (TP28). Notice that the filter has
extracted the average information from the demodulator output. Adjust the PSK
demodulator's phase adjust control until the amplitude of filter's output is
maximum.
6. The low pass filter's output rounded & cannot be used for digital processing. In
order to 'square up' the waveform comparators are used (data squaring circuit).
The bias control is adjusted so that the comparator's output pulse width at TP47
is same as the NRZ (M) pulse width.
7. Switch on the pseudo-random sync code generator. Notice that the data on A/D
converter LEDs is same as that of the D/A converter LEDs. You can verify this
by varying the DC l pot on ST2103 trainer. The data on ST2104 trainer always
copy the ST2103 trainer's data output. This proves that the transmitter &
receiver are now in frame synchronization.
8. Switch off the trainers. Select internal triggering mode for the oscilloscope
disconnect the CH 0 & CH 1 inputs on ST2103 trainer Instead connect CH 0 to
~1 KHz signal & CH l to ~2KHz signal.
9. Switch on the power. Notice the outputs CH0 & CH1 on ST2104 trainers. They
are replica of the input signals from ST2103 trainers. Also notice that they are
independent of each other (i.e. free from interference) & variation in one does
not affect the other. If some interference is present, it can be removed adjust on
ST2104 trainer.
10. Perform the same experiment with NRZ (L) data and observe the phase
ambiguity of the detector.
11. The same experiment can be done by using biphase (Mark) code. Just remember
to reformat the signal as described in biphase (Mark) chapter.
12. The carrier frequency used in the above experiment was 960KHz. 1.44 MHz
carrier can well be used. The only change to be made is to put the PSK
demodulator switch in 1.44 MHz position.
Quadrature Phase Shift Keying (QPSK) :
In quardrature Phase Shift keying each pair of consecutive data bit is treated as a two
bit (or dibit) code which is used to switch the phase of the carrier sinewave between
one of four phases 90° apart. The four possible combination of dibit code are 00, 01,
10 and 11. Each code represents either a phase of 45°, 135°, 225°, and 315° lagging,
relative to the phase of the original un-modulated carrier. The choice of these phases
is arbitrary as it is convenient to produce them. Quadrature phase shift keying offers
an advantage over PSK, in a manner that now each phase represents a two bit code
rather than a single bit. This means now either we can change phase per second or the

ST2106 & ST2107
same amount of data can be transmitted with half as many phase changes per second.
The second choice results in a lowering of bandwidth requirement.
The four phases are produced by adding two carrier waves of same frequency but 90°
out of phases. The 0° phase carrier is called In-phase carrier and is labeled 1. The
other is 90° (lagging) phase carrier termed as the quadrature carrier and is labeled Q.
The carrier is controlled by the MSB (most significant bit) of the dibit code. When the
MSB is a level ‘0' the phase is 0 degrees when the MSB goes to level 1 the phase
reverses to 180°.
The Q-carrier starts with 90° out of phase (with respect to reference 1 carrier). This
carrier is controlled by the LSB (least significant bit) of the digit code when the LSB
is a level 0; the phase is 90° degrees with reference to 1-carrier). When the LSB goes
to a level 1, the phase reverses to 270°. See figure 37
Phasor Diagram
Figure 37
Assume the digit code be 0. This would give a 0° phase to the in phase carrier and 0°
phase to quadrature carrier (90° out of phase with respect to I-carrier). If we add these
two waves we would get a 45° resultant. See figure 38.
Phasor Diagram
Figure 38

ST2106 & ST2107
Similarly, the phase shifts for other three possible combinations would be as summed
in the table below :
NRX (L) Dibit Code Phase
0 0 45°
0 1 315°
1 0 135°
1 1 225°
Table 2
At any instance of time, there is always a +/- 90° phase difference between the two
modulation outputs. As a result, the amplitude of the resultant phasor will always be
√2 times the amplitude of input phase or if they are equal. The creation of four phases
by vector addition is as shown in figure 39
Phasor Diagram
Figure 39
It can be appreciated from the above phasor diagram that each phasor switches its
phase depending on the data level exactly in the same way as the same way as the
PSK modulator does. The only difference is that QPSK is sum of two such PSK
modulators.
The QPSK modulator can be configured as shown in the figure 40

ST2106 & ST2107
QPSK Modulator
Figure 40
The two carriers namely I & Q as has been stated, have same frequency but differ in
phase by 90°. Also the I data refer to the dibit MSB & Q data refers to the dibit LSB.
Each modulator performs phase-shift keying on its respective carrier input in
accordance with respective data input such that,
a. The output of modulator 1 is a PSK signal with phase shift of 0° and 180°
respectively, relative to the I-carrier, and
b. The output of modulator 2 is a PSK signal with phase shift of 90° and 270°
respectively, relative to the I-carrier.
The output of the two modulators is summed by a summing amplifier. As it is clear
from the earlier phasor diagram, the phase of the summing amplifier's output signal
relative to I-carrier, at any instance of time takes one of the four phases 45° 135°,
225°, and 315° depending on the applied debit code. When these dibit codes alter, the
phase of the QPSK output changes by 0°, 90°, 180° or 270° from its previous phase
position. Thus the output of the summing amplifier is a QPSK waveform. The
demodulation of QPSK signal is performed by the fourth power loop detector. The
demodulator is quite similar to the one used in PSK system as can be seen from figure
41
QPSK Demodulator
Figure 41

ST2106 & ST2107
The incoming QPSK signal is first squared in the signal squarer 1. The functioning of
the signal squarer has already been discussed in the PSK Modulator section. The
output of the signal squarer 1 is a signal at twice the original frequency with phase
changes reduced to 0° & 180°. This is because all the phase changes are also doubled.
The 0° & 180° phase changes becomes 0° (as 2 x 180° = 360° = 0° phase shift.) and
the 90° and 270° phases both become 180° (since 270° + 270° = 540° = 180° phase
shift)
The output of the signal squarer 1 is fed to signal 1. The output of the signal squarer 1
is fed to signal squarer 2. This circuit is identical to signal squarer with frequency
double that of the signal at its input (Quadrupled with respect to the original QPSK
input signal frequency). The 0° and 180° phases changes are also reduced to a 0°
phase changes are also reduced to 0° phases shift, since the phases are also doubled
(Also 2 x 180° = 360° = 0° phase shift).
Therefore, the output from signal squarer 2 is a sinewave at four times the frequency
of the original QPSK carrier signal with no phase changes.
The output of signal squarer 2 is fed to the phase locked loop (PLL) which locks on
the incoming signal & produces a square wave of same frequency as that of the input.
The output of PLL is divided in frequency by a factor of 4 by a ÷ 4 circuit. Now the
frequency is same as that of the QPSK carrier signal.
The next stage in demodulation is a phase adjusts Circuit. The output of the phase
adjust circuit are two square waves of same frequency as the input signal applied and
with 90° phase shift between them. Also the phase of the two output signals can also
be adjusted relative to the original QPSK signal. Note that the 90° phase difference
between the two outputs is maintained.
The output of the phase circuit controls the two analog switches. The switch is closed
when the corresponding output goes high. The original QPSK signal is then switched
through to one of the QPSK demodulator. How output can be input with a low level,
the switches are open & the output is pulled down to 0V.
The two outputs from the demodulator are labeled I & Q. Once the correct phase
relation between QPSK signal & phase adjust output have been set, the I & Q outputs
will contain information about original two bit code. This is illustrated in phase or
diagram. See figure 42.

ST2106 & ST2107
All Angles represent phase LAG with respect to 0°

Phasor Diagram
Figure 42
The average level of the I & Q outputs contains information about the dibit code. The
average level of the two outputs is extracted by passing them through the low pass
filter. The output of the filters is rounded & cannot be used for digital processing. The
wave 'Squared Up' by a voltage a comparator circuit.
A problem arises at this point. Since the phase information is lost in demodulator, the
receiver does not know which phase is which as a result it might interpret any of the
four phases e.g. 45° QPSK wave. Since there are four possible combinations our
chances of recovering correct code is mere 25% e.g. if the receiver treats one of the
three QPSK Phases to be at 45° phase, then the possibilities which arise are :
a. 'Q' data at 'I' data output 'I' data at 'Q' data output & inverted.
b. 'I' data at 'Q' data output 'Q' data at 'I' data output & inverted.
c. 'I' data at 'Q' data at correct outputs but both data streams inverted.
This leads to phase ambiguity. To overcome this problem, the NRZ (L) data is first
encoded into differentially encoded dibit format at transmitter. In this format, each
dibit pair is encoded as a change in the code. This means that we make the phase
change depend on the two bit code at the input instead of making the phase dependent
on two bit code. i.e. still make use of dibit code but now they mean changes in phase
rather than actual phase

ST2106 & ST2107
Code Old Meaning New Meaning

NRZ (L) Code The Phase The Phase Change
0 0 45° No Change
0 1 315° 90°
1 0 135° 180°
1 1 225° 270°
Table 3
At the receiver, once again there are four possibilities the two outputs may be
interchanged or inverted as mentioned above. But now the absolute levels of the
received data are no longer important. The receiver simply has to tell the two bit code
change. As a result phase ambiguity is no longer a problem. To derive NRZ (L)
waveform from the encoded pair a differential dibit decoder is used at receiver. Its
output is serially transmitted. The figure 43 shows the functional block diagrams of
the QPSK system.
QPSK Transmitter
QPSK Receiver
Figure 43

ST2106 & ST2107
Experiment 11
Objective :
Study of QPSK Modulation and Demodulation
Procedure :
experiment 1, Also Set pulse generator delay adjust fully clock wise in step 6.
1. Make the additional connections as shown in figure 44 as shown in following
steps.
i) Differentially encoded dibit MSB (TP10) to unipolar bipolar converter
1 input (TP20)
ii) Unipolar-Bipolar converter 1 output (TP21) to modulator 1 input
(TP27).
iii) Differentially encoded dibit LSB (TP11) to unipolar -bipolar 2 input
(TP23).
iv) Unipolar-Bipolar converter 2 output (TP24 to modulator 2 input
(TP30).
v) 960KHz (1) output (TP17) to modulator 1 carrier input (TP26).
vi) 960KHz (Q) output (TP18) to modulator 2 carrier input (TP29)
vii) Modulator 1 output (TP28) to summing amplifier's input A (TP34).
viii) Modulator 2 output (TP31) to summing amplifier's input B (TP35).
b. Between ST2106 & ST2107 :
i) Summing amplifier's output (TP36) to QPSK demodulator input (TP1).
i) QPSK demodulator output 1 (TP8) to low pass filter 1 input (TP23).
ii) QPSK demodulator's Q output (TP9) to low pass filter 2 input (TP23).
iii) Low pass filter 1 output (TP24) to comparator 1 input (TP46).
iv) Low pass filter 2 output (TP28) to comparator 2 input (TP49).
v) Data squaring circuit comparator 1 output (TP47) to differential
decoder MSB input (TP42).
vi) Data squaring circuit comparator 2 output (TP50) to differential
decoder LSB input (TP43).
d. Between ST2107 & ST2104 Trainers :
i) Comparator 1 output (TP47) to clock regeneration circuit input (TP3).
ii) Dibit decoder output (TP47) to PCM data input (TP3)
iii) Dibit decoder clock input (TP41) to clock regeneration circuit output
(TP8).

ST2106 & ST2107
e. On ST2104 trainer :
i) Clock regeneration circuit output (TP8) to RX clock input (TP46).
2. Monitor the output of modulator 1 (TP28) in ST2106 trainer. Adjust the scope's
trigger level manually to obtain a stable display Use the controls provided in the
modulator as shown in followings steps.
a. Gain : This controls the overall amplitude of the modulated waveform.
Adjust it till you obtain a 2VPP signal.
b. Modulation off set : This controls the peak to peak amplitude of the 0° & 180°
phases, relative to each other. Adjust this pot such that the amplitudes of the two
phases are equal.
3. Make the same adjustments for modulator 2's output (TP31) by monitoring its
outputs on the oscilloscope.
4. Monitor the output of the summing amplifier (TP36). The output is a QPSK
Signal with 0°, 90°, 180° & 270° phase shifts clearly visible.
5. To observe the QPSK demodulation process, monitor each output (TP8 & 9) of
the QPSK demodulator with reference to input signal (TP1) on ST2107. Also
monitor the test points provided at various block outputs, to understand the
process of demodulation clearly.
6. Observe the two low pass filter's outputs (TP24 & 28). Adjust the phase adjust
control provided on QPSK demodulator block until you obtain two levels only
at low pass filter's outputs. The incorrect placement of phase adjust control
produces multilevel output at filter output.
7. Monitor both the comparator's output (TP47 & 50). Adjust the bias level control
of both comparators till their output doesn’t have the correct pulse width.
a. Now that the filter's output is balanced around 0Volts. Adjustment of bias
level to produce 0V terminal of the comparator help achieving 'Squared up'
version of the filter's output signal. This can be compared by
simultaneously displaying the filter's output & the comparator's output on
the oscilloscope.
8. Temporarily disconnect & then reconnect the QPSK input to the QPSK
demodulator. Observe that after some trial you will obtain four different
combinations at comparator's outputs (TP47 & 50). This explains the phase
ambiguity in QPSK system.
9. To resolve the phase ambiguity problem the outputs from the comparators
(TP47 & 50) are fed to the two inputs (TP42 & 43) of the differential dibit
decoder which is driven by the regenerated clock from the ST2104 trainer. It is
synchronized to the rising edge of the signal at output of ST2107 trainers
comparator 1.
a. On observing the differential dibit decoder's output (TP44) along with the
NRZ (L) waveform (TP5) on the other channel you will notice that the
output is nothing but the delayed NRZ (L) waveform.
b. Try disconnecting & reconnecting the QPSK modulation output for a short
period. Notice that this time the decoders output is unchanged. This is

ST2106 & ST2107
become the Differential decoder looks for the change in tap bit code rather
than the absolute value. Thus the phase ambiguity problem is solved.
10. Turn ‘On’ the ST2103 pseudo-random sync code generator. The transmitter &
receiver one locked in 'frame synchronization'. This can be checked by
verifying that A/D converter LEDs on ST2104 & trainer now carry the same
data. Try varying the DC input to the ST2103 trainer. The ST2104 trainer
should follow the changes.
11. Turn ‘Off’ the trainers. Discount the CH0 & CH1 inputs of ST2103 trainer.
Connect CH0 input to ~2 KHz signal.
12. Turn ‘On’ the trainers. Observe the CH0 & CH1 outputs (TP33 & 36) at
ST2104 trainers. The output should be identical to the input signal fed to each
channel. The notice that the two signals are independent of each other &
verification of one do not affect the other. If some interference is present it can
be removed by varying the phase generator delay adjust control on ST2104
trainer.
Figure 44

ST2106 & ST2107
Experiment 12
Objective :
Observation of Eye Diagrams
Procedure :
1. Perform the experiment 9 FSK modulator experiment.
2. Observe the output of the summing amplifier on the ST2106 trainer at (TP36).
3. Press XY switch on oscilloscope.
4. You will observe an eye pattern as shown below; this is known as eye diagram.
Eye Pattern
Figure 45

ST2106 & ST2107
Warranty
1) We guarantee the product against all manufacturing defects for 24 months from
the date of sale by us or through our dealers. Consumables like dry cell etc. are
not covered under warranty.
2) The guarantee will become void, if
a) The product is not operated as per the instruction given in the operating
manual.
b) The agreed payment terms and other conditions of sale are not followed.
c) The customer resells the instrument to another party.
d) Any attempt is made to service and modify the instrument.
3) The non-working of the product is to be communicated to us immediately giving
full details of the complaints and defects noticed specifically mentioning the
type, serial number of the product and date of purchase etc.
4) The repair work will be carried out, provided the product is dispatched securely
packed and insured. The transportation charges shall be borne by the customer.
List of Accessories
Accessories for ST2106 :
1. Patch Cord 8" ..........................................................................................6 Nos.
2. Patch Cord 16" ........................................................................................2 Nos.
3. Patch Cord 20" ........................................................................................2 Nos.
4. Mains Cord..............................................................................................1 No.
5. Operating Manual....................................................................................1 No.
Accessories for ST2107 :
1. Patch Cord 8"..........................................................................................6 Nos.
2. Patch Cord 16"........................................................................................2 Nos.
3. Patch Cord 20"........................................................................................2 Nos.
4. Mains Cord.............................................................................................1 No.
5. e- Manual CD .........................................................................................1 No.
Updated 04-08-2008

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Data Formatting & Carrier Modulation

Transmitter Trainer and Carrier

An ISO 9001 : 2000 company

94-101, Electronic Complex Pardeshipura,

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Data Formatting & Carrier Modulation Transmitter Trainer and Carrier

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Scientech Products are RoHS Complied.

Scientech products are “Lead Free” and “Environment Friendly”.

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Theory of Data Formatting

Different NRZ Encoding

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Non - Return To Zero (Level) NRZ (L) :

NRZ (L) Encoding

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Data Clock Output

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NZR (M) Format

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data in to receiver by verifying that the rising edge of the correct

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Introduction to Biphase Codes

Biphase (Manchester) Format

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Biphase (Mark) Format

Receiver Clock Regeneration :

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Disabled = Output -----> 0 Volts

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Threshold Level of Comparators

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Various Formats Representing Arbitrary Data

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Carrier Modulation Introduction

a. Amplitude Shift Keying (ASK) :

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Amplitude Shift Keying :