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    The document discusses a MIPS-based computer system with 2GB of main memory on a single circuit board. It has a single control signal between the CPU and memory to indicate read or write operations. It asks (a) how wide the memory data bus is (b) how wide the memory address bus is using 4-bank memory interleaving (c) how long it takes to fetch 8 words using this configuration (d) the memory bandwidth compared to no interleaving. The answer determines that (a) the data bus is 8 bits wide, (b) the address bus is 31 bits wide with interleaving, (c) it will take 28 cycles to fetch 8 words, and (d) interle

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    The document discusses a MIPS-based computer system with 2GB of main memory on a single circuit board. It has a single control signal between the CPU and memory to indicate read or write operations. It asks (a) how wide the memory data bus is (b) how wide the memory address bus is using 4-bank memory interleaving (c) how long it takes to fetch 8 words using this configuration (d) the memory bandwidth compared to no interleaving. The answer determines that (a) the data bus is 8 bits wide, (b) the address bus is 31 bits wide with interleaving, (c) it will take 28 cycles to fetch 8 words, and (d) interle

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    The document discusses a MIPS-based computer system with 2GB of main memory on a single circuit board. It has a single control signal between the CPU and memory to indicate read or write operations. It asks (a) how wide the memory data bus is (b) how wide the memory address bus is using 4-bank memory interleaving (c) how long it takes to fetch 8 words using this configuration (d) the memory bandwidth compared to no interleaving. The answer determines that (a) the data bus is 8 bits wide, (b) the address bus is 31 bits wide with interleaving, (c) it will take 28 cycles to fetch 8 words, and (d) interle

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    19 views3 pages

    Answer

    Uploaded by

    Anonymous 0MQ3zR
    The document discusses a MIPS-based computer system with 2GB of main memory on a single circuit board. It has a single control signal between the CPU and memory to indicate read or write operations. It asks (a) how wide the memory data bus is (b) how wide the memory address bus is using 4-bank memory interleaving (c) how long it takes to fetch 8 words using this configuration (d) the memory bandwidth compared to no interleaving. The answer determines that (a) the data bus is 8 bits wide, (b) the address bus is 31 bits wide with interleaving, (c) it will take 28 cycles to fetch 8 words, and (d) interle

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    © All Rights Reserved
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    of 3

    Given: A MIPS-based computer system with 2 GB of main memory that is built on a single

    circuit board. It is designed with a single control signal between the CPU chip and main memory,
    i.e. one bit of control that is set to one for Read operations and zero for Write operations.

    a) How many bits wide is the main memory data bus?


    b) How many bits wide is the main memory address bus when 4-banks memory interleaved is
    used?

    c) How long does it takes to fetch 8 words from the memory to MIPS registers using the memory
    configuration in (b)? Assume that one cycle is required to place the address and one cycle to
    transfer one word and 15 cycles for memory access.

    d) Find the memory bandwidth and compare it to memory bandwidth when no memory
    interleaved is used
    Answer:

    Coming to the concept of time taken by the system to access the data, read the data and write it
    back to the system, we need to consider all the required parameters such as, the time required to
    read a block of word, to write the block of word and the interleaving used.
    The interleaving is used to minimise the read and write access. In this process the memory is
    divided into the individually different chunks to process out the operation of its own word.
    According to the problem given, we assume that each read and write operation takes one cycle.
    And in addition we have used 4 banks of memory for interleaving.
    Initially, without interleaving, time required was (1+1+15) =17 cycles/word.
    i.e One cycle to place the address, one cycle to transfer one word and 15 cycles for memory
    access.

    Now, y the concept of interelaving the time required would be:1 + 15 + 2 x (4 x 1) = 24 cycles.
    As per the question asked, 4 banks of memory interleaving is used, and altogether we hav to
    transfer 8 word of data, therefore the formula has been modified above.
    Thus, the total time required to fetch 8 words would be 24 cycles

    a) data bus was 8bits wide


    b)31 bits wide
    c)it will take 28 sec to fetch 8words from the memory
    d) the difference is 21 bits when compared no memory is interealved

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