MESFET Ece Project
MESFET Ece Project
MESFET Ece Project
Ping Chen
Yuba R Shrestha
Hui Shen
Electrical Engineering
University of Cincinnati
Zinc Blende
Group of symmetry
Td2-F43m
4.421022
240 A
Debye temperature
360 K
Density
5.32 g cm-3
12.9
10.89
0.063mo
0.51mo
0.082mo
Electron affinity
4.07 eV
Lattice constant
5.65325 A
0.035 eV
Energy gap
1.424 eV
Intrinsic resistivity
3.3108cm
2.1106 cm-3
Mobility electrons
Mobility holes
Breakdown field
4105 V/cm
200 cm2/s
10 cm2/s
GaAs is a direct band gap semiconductor, which means that the minimum
of the conduction band is directly over the maximum of the valence band (Fig.
1.2). Transitions between the valence band and the conduction band require
only a change in energy, and no change in momentum, unlike the indirect bandgap semiconductor such as silicon. This property makes GaAs a very useful
material for the manufacture of light-emitting diodes and semiconductor lasers,
since a photon is emitted when an electron changes energy level from the
conduction band to valence band.
And the crystal structure and energy band structure of GaAs are shown in
the following figures,
High electron mobility in GaAs channel also gives short transit time and
high speed because channel transit time
The following two figures show the advantages of GaAs MESFET over Si
NMOS in current-drive capability and cutoff frequency.
barrier increases. The more the electrons that is able to tunnel through the
barrier, the more current flows from semiconductor to the metal, creating an
ohmic contact. The condition for the source and drain regions is that the more
heavily doping the region the better the ohmic contact the junction makes. The
system just described is called a tunneling barrier contact, which is
shown on Fig. 1.4
There are also ideal non-rectifying barrier contacts, which are realized
when the metal work function is smaller than the semiconductor work function.
In this case electrons flow from the metal into the semiconductor to achieve
thermal equilibrium, bending the Ec and Ev bands down into the junction,
therefore allowing current to flow in both directions.
1.6
Schottky Barrier
The Schottky barrier gate is one of the two most important elements of many
GaAs devices; the other is an ohmic contact. The size and placement of the gate
is critical to FET performance in both power and low noise FETs and in FETs
The schottky junction can be operated in the forward bias mode, and in reverse
bias mode. In reverse bias mode, the junction barrier is increased from the
semiconductor to the metal. In forward bias mode, the barrier from the
semiconductor is reduced, allowing the majority carriers to shoot across from
the semiconductor to the metal. The amount of increase and decrease in the
barrier depends on the amount of bias voltage applied.
Two important characteristics are the depletion with W, given by :
Where:
2.1
11
12
capacitances and for device isolation. To prepare the substrate, the GaAs wafer is slightly
etched to remove about 100 nm to remove surface oxide, contamination and damage from
packaging and handling. A silicon nitride insulating layer is then deposited by reactive
sputtering to a thickness of 100 nm. This capping layer protects the GaAs surface during
the entire processing operation and helps to prevent loss of As from the surface by
decomposition of the GaAs during high temperature processing.
The first masking step (mask #1) in the fabrication is the formation of the channel
regions between the source and drain regions using a silicon ion implantation process.
Since the GaAs substrate is semi-insulating, implantation of silicon ions is used to form a
lightly doped but conducting, n-type region. The energy and dose for the silicon
implantation is determined from the pinchoff voltage required for the MESFET. Positive
resist is used to define the channel location (area of the wafer surface to be implanted)
and implantation is done through the silicon nitride cap layer. After implantation, the
silicon nitride is slightly etched (about 30 nm deep) in order to mark the wafer surface
before the resist is removed for subsequent alignment of masks for the source and drain
and gate regions. The resist is then stripped off the wafer leaving the nitride intact.
Formation of the source and drain regions for the MESFET is done in the next
masking step (mask #2) in a similar fashion. Positive resist is again used to define the
area of the implant and implantation is done through openings in the resist and through
the silicon nitride cap layer. The energy and dose for the silicon implantation is now
determined by the need for low resistance, ohmic source/drain regions contacting the
ends of the channel. Higher doping levels are required (> 1018 /cm3) to provide low
resistance contacts and to form low resistance, ohmic metal-semiconductor contacts for
contacting metal to the MESFET's source and drain regions. The resist is then removed
(stripped) after the implant.
Since implantation produces severe damage to the semiconductor lattice, a thermal
annealing step is needed after the implant to repair the damage and to activate the
implanted species. After removal of the resist from the source/drain implant, the wafer is
rapid thermally annealed at an elevated temperature for a brief period (seconds). The
silicon nitride cap on the wafer during this process helps to control the decomposition of
the GaAs surface which can occur by the preferential loss of As. This completes the
formation of the active regions of the device.
Next, to make electrical contacts to the device's source and drain regions, resist is
applied and patterned (mask # 3) and openings in the silicon nitride are etched down to
the semiconductor surface over the source and drain regions. After patterning, the resist
is treated in chlorobenzene to swell its top surface and produce an overhanging ledge at
the top of the resist in the windows. The underlying silicon nitride is etched away in the
windows to expose the underlying GaAs surface. The contact metal Au/Ge/Ni is then
deposited, patterned and the excess metal removed (lifted off) by dissolving the resist in a
solvent. This same lithography process and liftoff technique is also used to pattern the
aluminum Schottky metal (mask #4) to form the gate electrode for the MESFET.
The MESFET's fabrication is now complete and the device is ready for testing and
electrical characterization. The fabrication process outlined above is a basic one with a
minimum of mask levels and processing. More sophisticated fabrication processes may
14
contain more mask levels, for example to define a second layer of metal for
interconnection of devices. Over the course of this quarter, we will proceed
systematically through this fabrication process by performing a set of process steps each
week. The aim is to complete the device fabrication by the end of the eighth week so that
electrical characterization of the devices and test structures can be done in the last two
weeks.
Fig. 2.2
15
( x RP )2
2 RP2
(2.1)
where
N p = peak concentration
R p = projected range
R p =projected range straggle
RP is called the projected range and is equal to the average distance an ion travel
before it stops. The peak concentration NP occurs at x = RP. Because of the statistical
nature of the process, some ions will be lucky and will penetrate beyond the projected
range RP, and some will be unlucky and will not make it as far as RP. The spread of the
distribution is characterizes by the standard deviation R p , called the straggle.
The total number of ion implantation per unit area is the implanted dose Q, which can
be calculated from the integration of impurity concentration under the curve, given by
Q = 2 N P RP
(2.2)
Implantation doses can range from 1010 /cm2 to 1018 /cm2, and ion implantation is
often used to replace the pre-deposition step in a two-step diffusion process. Doses in the
range of 1010 /cm2 to 1013 /cm2 are required for threshold adjustment in MOS
technologies and are almost impossible to achieve using diffusion.
Ion energy
Implant
dose
Resist
thickness
SiN
thickness
Channel implant
Si+
180 keV
5x1012
/cm2
1.6 m
100 nm
Source/Drain implant
Si+
200 keV
2x1013
/cm2
0.7 m
100 nm
16
Because ions enter resist first and lose most energy in resist, we can simplify multilayer situation by treating it as consisted of one outermost layer and get pretty good
approximation. Then projection range RP and projection range straggle R p in
photoresist or silicon nitride layer can be found from chart for given implant ion energy.
The RP and R p for Si ion in photoresist, SiN and GaAs for given implant energy is
Photoresist
Rp
R p
0.8170
0.9082
Silicon Nitride
Rp
R p
0.1248
0.1339
0.1548
0.1724
Gallium Arsenide
Rp
R p
0.0432
0.0465
0.1559
0.1739
0.0697
0.0753
Table 2.2 RP and R p parameters for Si ion in Photo resist, SiN and GaAs (m)
a) Silicon implant profile for the channel implant (resist-masked region)
The implant parameters from the table (Si in Photo resist) are
R p = 0.8170 microns
R p = 0.1248 microns
xr = 1.6m
xn = 100 nm
Peak concentration
NP =
Q
2 RP
5 1012 / cm 2
= 1.6 1017 / cm3
4
2 (0.1248 10 cm)
N ( x) = N P e
2 RP2
( x 0.817 ) 2
= 5.6 10 / cm e
16
2(0.1248 )2
The value of the doping concentration at the GaAs surface can be calculated from the
above expression with the value of x =1.6 m +100 nm = 1.7 m as follows.
N ( x = 1.7 m) = 5.6 10 / cm e
16
17
(1.7 0.817 ) 2
2(0.1248 ) 2
16
x 10
Resist
SiN GaAs
Xn
Xr
Np=5.6x1016 cm-3
5
4
3
2
7.5x105 cm-3
1
0
0.2
0.4
0.6
Figure 2.3
0.8
1
1.2
Depth, x
1.4
1.6
1.8
{ x ' RP }2
N ( x) = N P e
2 RP2
{ x + t RP }2
2 RP2
= N Pe
( x 0.0548 )2
= 1.62 10 / cm e
17
2(0.0432 )2
(0 0.0548 ) 2
2(0.1248 ) 2
1.62 1017
x j = 0.0548 + (0.0432 ) 2 ln
= 0.221
1.0 1014
x 10
1.8
SiN
t = 0.1 m
1.6
GaAs
Substrate
Np=1.62x1017 cm-3
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-0.1
-0.05
Figure 2.4
0.05
0.1
0.15
Depth, x
0.2
0.25
0.3
0.35
0.4
The Implant parameters for Si ion in photo resist (200 keV, Si in Photo resist) are
R p = 0.9082 microns ,
R p = 0.1339 microns
t1 = 0.8m
t2 = 100 nm
19
2 1013 / cm 2
= 5.96 1017 / cm3
2 (0.1339 104 cm)
N ( x) = N P e
2 RP2
{ x + t1 + t2 RP }2
2 RP2
= NPe
( x 0.0082 )2
2(0.1339 )2
N ( x = 0) = 2.09 10 / cm e
17
x 10
SiN
Resist
Xr
2.5
GaAs
Xn
Np=2.09x1017 cm-3
1.5
0.5
-0.8
-0.6
-0.4
-0.2
0
0.2
Depth, x
0.4
0.6
0.8
20
For the source/drain implant with a dose of 2x1013 /cm3 through the SiN, the implant
parameters (200 keV, Si in SiN) are
R p = 0.1724 microns ,
R p = 0.0465 microns
Silicon nitride: 65 nm
Peak concentration location
xP = 172.4 65 = 107.4 nm
The peak concentration is given by
Q
NP =
2 RP
=
2 1013 / cm 2
= 1.716 1018 / cm3
4
2 (0.0465 10 cm)
N ( x) = N P e
2 RP2
{ x + t RP }2
2 RP2
= NPe
( x 0.1074 )2
= 6.0 10 / cm e
17
2(0.0465 )2
2(0.0465 )
( x 0.0548 ) 2
2(0.0432 ) 2
The plot is shown in figure 2.6. We can read the total peak concentration from the figure
N peak = 6.863 1017 cm3
Determination of total concentration at GaAs surface (x=0)
(0 0.1074 ) 2
N ( x = 0 ) = 6.0 10 / cm e
17
2(0.0465 ) 2
Determination of junction depth xj where N(x) = NB. For NB = 1x1014 /cm3, the figure in
log scale is shown in figure 2.7, and we can read the junction depth from the figure as
x j = 0.3
Comparing these results with those for the channel implant, we can see the peak
concentration and junction depth of source/drain implant is bigger because of higher dose
and implant energy.
21
17
x 10
6
Si Impurity concentration, N(x)
S/D implant
Channel implant
Total
GaAs
Substrate
0.05
Figure 2.6
0.1
0.15
0.2
Depth, x
0.25
0.3
0.35
0.4
18
10
S/D implant
Channel implant
Total
16
10
14
10
12
10
GaAs
Substrate
10
10
10
10
10
10
0.05
Figure 2.7
0.1
0.15
0.2
Depth, x
0.25
0.3
0.35
0.4
22
23
Figure 2.8 Surface concentration vs. average conductivity for different X/Xj. The two
lines show the values read for average conductivity
E g k BT N D
Vbi = m +
ln
q
2q
ni
where
m = Gate metal (Al) work function = 4.4 V
= Electron Affinity of GaAs = 4.04 V
Eg = Energy bandgap of GaAs = 1.42 eV
ni = Intrinsic carrier concentration of GaAs = 8.7x105/cm3
ND = channel doping (use Ns = 7.2 x 1016 /cm3 )
q = 1.6x10-19 C
kB = 1.38x10-23 J/K
and
T = 300oK
Substituting these values in the expression for Vbi, we get
Vbi = 0.3 V.
Also,
24
(2.3)
Using the values for peak channel doping and implant energy as follows
Implant energy, Ei = 180 kev
Peak concentration,
Np = 1.62 x 1017 /cm3
We can read the value for pinchoff voltage form the figure 2.9
Vp 2.5 V.
The figure 2.8 shows the method of calculating the pincoff voltage.
Now, the threshold voltage is given by
VT = Vbi Vp = 0.13024 2.5 = -2.2 V
Figure 2.9
2.5 Conclusion
Some simulation results from Silvacos Athena fab. simulator for the Channel and
Source/Drain implant profiles using the same parameters as those used in the theoretical
calculations above are presented here for the comparison purposes.
For channel implant through SiN (Si in GaAs) we have
Ei = 180 keV
Q = 5 x 1012 /cm2
SiN cap layer = 100 nm
35 % activation
Simulation results:
NP = 6.15 x 1016 /cm3
25
Figure 2.9
26
Figure 2.11
As seen above, the simulation results are in agreement with those calculated. Some
values such as junction depth are not consistent which is due to the use of different
masking materials and the different thickness. So our theoretical calculations are
consistent to those values obtained from the Silvacos Athena fab simulator.
27
Introduction
This chapter describes in brief the fabrication process summary. The exact
equipment settings for each process are given. The results of different tests and the
sample calculations are also shown given in this chapter. The problems encountered
during the experiment and the possible solutions are also described here when ever
possible. The chapter will conclude with comparisons of experimental results with the
theoretical calculations.
3.2
Photo
resist
S1818
S1807
S1807
S1818
5 sec.
Spread
Cycle (rpm)
500
500
500
500
28
30 sec.
Spin Cycle
(rpm)
5000
4000
4000
5000
Target
thickness
(m)
1.6
0.7
0.7
1.6
Dose (cm-2)
5x1012
2x1013
10. Shallow etching of silicon nitride ( 50nm) for alignment registration purposes in
buffered HF solution and plasma etching (SOP # 210):
Plasma etching parameters:
Gas: 9.6 sccm of CF4 + 0.4 sccm of O2
RF power: 100W
Frequency: 30 KHz
Time: 30 seconds
29
channel implant process is described in detail by the figure 3.2. This figure also shows
the cross-section of the wafer at each step. The processes starting from the resist
application to the Silicon Nitride etching are described in this figure. The Source / Drain
implant processes are summarized in the figure 3.3. This figure also shows the detail
cross-section and the top view of the wafer at each step of the process.
An important process of the MESFET fabrication process is the Mask and wafer
alignment and the exposure. A special technique used to make sure of the alignment of all
of the dies on the wafer is the Split-Field alignment. This technique allows us to view two
different sites at a time and align them. This technique is shown in the figure 3.5. This
figure also shows the Optical Mask Aligner in our laboratory.
Figure 3.1
31
Figure 3.2
Figure 3.3
33
Figure 3.4
3.3
In order to evaluate the device variation due to the effects resulting from the design or
process phases, it is necessary to make sheet resistance measurements using the Van Der
Pauw structures (device #1 for Channel region device #2 for Source/Drain region)
fabricated on the wafer. The quality of the MESFET depends heavily on the quality of the
contacts. Using the four-point method, the sheet resistance of the implanted layer can be
calculated using the expression given below:
V4 V3
(3.1)
RS
ln(2) I12
Where I12 is the current forced through the probe 1 and 2 and V4 and the V3 are the
voltage sensed between probes 3 and 4.
34
I
I (uA): V (V): AA(uA): V (V): U-W
I (uA): U-W V (V): AA-Y
W-Y
U
AA-Y
-100
-0.0188
-100
-0.0192
-100
-0.01895
-90
-0.0169
-90
-0.0173
-90
-0.017
-80
-0.0151
-80
-0.01538
-80
-0.01516
-60
-0.0113
-60
-0.01159
-60
-0.01137
-40
-0.0075
-40
-0.00768
-40
-0.00757
-20 -0.00376
-20
-0.00383
-20
-0.00378
-10 -0.00187
-10
-0.0019
-10
-0.00186
-1 -0.000164
-1
-0.00016
-1
-0.00016
1
0.00021
1
0.00022
1
0.000165
10
0.0019
10
0.00195
10
0.00199
20
0.0038
20
0.00388
20
0.00382
40
0.0076
40
0.00774
40
0.00761
60
0.0114
60
0.01159
60
0.01141
80
0.0152
80
0.0154
80
0.0152
100
0.0189
100
0.0193
100
0.0189
Table 3.1
35
AA-Y; V: U-W
W-Y; V: AA-U
U-W; V: AA-Y
100
I (A)
50
-50
-100
-20
-15
-10
-5
10
15
20
V (V)
Figure 3.5
The data for the current - voltage characteristics for the Source / Drain are listed in
the table 3.1 and the plots are shown in Figure 3.1.
Similarly the data and the plots for the current voltage characteristics for the
channel Van Der Pauw are shown in the table 3.2 and figure 3.2 respectively.
36
I
V (V): AA- I (uA):
(uA):
Y
U-W
U-W
-12
-0.5
-12
-5
-0.167
-5
-3
-0.199
-3
-2
-0.146
-2
-1
-0.068
-1
1
0.0473
1
2
0.0672
2
3
0.0865
3
5
0.0921
5
10
0.21
10
12
0.25
12
Table 3.2
V (Y-W)
I (uA): U-W
V (W-U)
-12
-5
-3
-2
-1
-0.5
0
0.5
1
1.5
-0.102
-0.075
-0.057
-0.023
0.025
0.035
0.043
0.065
0.115
0.23
-0.09
-0.045
-0.03
-0.02
-0.036
0.012
0.032
0.038
0.003
15
I: U-W; V: AA-Y
I: AA-U; V: W-Y
I: AA-Y; V: U-W
10
I (A)
-5
-10
-15
-60
-50
-40
-30
-20
-10
10
20
V (mV)
Figure 3.6
30
The IV plots for both of the Source / Drain and the Channel Van Der Pauw are
clearly showing a linear nature. This shows that the contact for the Source / Drain Van
Der Pauw are Ohmic-like where as those for channel Van Der Pauw are slightly different.
The standard deviations for both Van Der Pauws are also shown on the tables. The
resistances calculated from the I-V curves are shown in the table 3.3 and table 3.4 for
Source / Drain and Channel Van Der Pauw respectively.
I: AA-Y; V: U-W
I: W-Y; V: AA-U
I: U-W; V: AA-Y
Table 3.3
Site
#
1
2
3
4
5
Input
I(A)
0.1
1
0.1
1
0.1
1
0.1
1
0.1
1
0.27415
0.1729
0.21074
R ( k )
0.189
0.193
0.189
Resistance calculation for source-drain Van Der Pauw from I-V curve
I: U-W; V: AA-Y
I: AA-U; V: W-Y
I: AA-Y; V: U-W
Table 3.4
dI/dV ( A / mV )
5.29883
5.19376
5.27837
dI/dV ( A / mV )
0.29178
0.568
0.48066
2.52054
1.46061
0.85148
R ( k )
3.43
1.76
2.08
Resistance calculation for channel Van Der Pauw from I-V curve
In: W-Y
In: W-U
Out: AA-U
Out: AA-Y
V
V
Rs ( )
Rs ( )
(V)
(V)
9.5
430.5
10
453.2
130
589.2
130
589.2
10
453.2
63
2855.2
187
847.5
176
797.6
4.2
190.3
5.7
258.3
132
598.2
130
589.2
8
362.6
13
589.2
180
815.8 177.6 804.9
46
2084.8
12
543.8
240 1087.7 239 1083.2
Table 3.5
In: AA-U
Out: W-Y
V
Rs ( )
(V)
5.7
258.3
140
634.5
54
2447.3
176
797.6
4.7
213.0
131
593.7
11
498.5
178
806.7
11
498.5
246 1114.9
In: AA-Y
Out: W-U
R s ()
V
Rs ( )
(V)
7
317.2 364.8
141
639.0 613.0
60
2719.2 2118.7
187
847.5 822.6
6
271.9 233.4
132
598.2 594.8
10
453.2 475.9
180
815.8 810.8
10
453.2 895.1
234 1060.5 1086.6
Rs ()
92.6
27.5
1123.2
28.8
38.2
4.3
94.3
5.8
794.0
22.3
The sheet resistances calculated for the two Van Der Pauw are shown on the table 3.5
and table 3.6. Clearly the Source / Drain Van Der Pauw has low sheet resistance which is
38
in the order of few hundreds where as those calculated for the Channel Van Der Pauw are
in the order of few thousands.
Site Input
# I(A)
1
2
3
4
5
10
1
1
1
1
In: W-Y
In: W-U
In: AA-U
In: AA-Y
Out: AA-U
Out: AA-Y
Out: W-Y
Out: W-U
V
V
V
V
Rs ( )
Rs ( )
Rs ( )
Rs ( )
(V)
(V)
(V)
(V)
25.45 1.15E+01 25.85 1.17E+01 27.03 1.23E+01 26.7 1.21E+01
7.81 3.54E+01 6.97 3.16E+01 8.83 4.00E+01 9.72 4.41E+01
1.13 5.12E+06
1.3 5.89E+06 2.19 9.93E+06
2.1 9.52E+06
131.4 5.96E+08 101.7 4.61E+08 115.3 5.23E+08 129.5 5.87E+08
19.36 8.77E+07 18.46 8.37E+07 24.38 1.10E+08 29.7 1.35E+08
Table 3.6
3.4
R s ( )
Rs ()
1.19E+04
3.78E+04
7.61E+03
5.41E+05
1.04E+05
3.32E+02
5.43E+03
2.46E+03
6.28E+04
2.35E+04
The TLM measurements data at five test sites with the calculated resistances are
shown in the table 3.7. The average values for the resistance at five different sites are
shown in the table 3.8. From dimensions measurements, we get the exact length of the
spacing d (also shown in table 3.8).
Width of the contact region W = 0.0020 inch = 0.00508 cm,
Width of the metal contacts L = 0.0006~0.0007 inch = 0.001524 ~ 0.001778 cm
The plot for the average resistance at each contact spacing versus the contact spacing
is shown in the figure 3.3. The slope and standard deviation is marked in the plot. We can
see that we have smaller deviation for the case not considering L.
So we can calculate the sheet resistance (not considering L)
W R
Rs R
W 383.58854 0.0020 0.767 k / square 767 / square
d d
39
Site #
#1
#2
#3
#4
#5
Spacing
Voltage (V)
Current (mA)
Resistance ( k )
1X
2X
3X
4X
5X
7X
1X
2X
3X
4X
5X
7X
1X
2X
3X
4X
5X
7X
1X
2X
3X
4X
5X
7X
1X
2X
3X
4X
5X
7X
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.14970
0.07987
0.05268
0.03470
0.02848
0.02109
0.17915
0.09000
0.06070
0.04630
0.03730
0.02650
0.11670
0.05690
0.03862
0.03070
0.02450
0.01700
0.12470
0.06540
0.04347
0.02878
0.02356
0.01747
0.14320
0.06993
0.04758
0.03724
0.02991
0.02105
0.6680
1.2520
1.8983
2.8818
3.5112
4.7416
0.5582
1.1111
1.6474
2.1598
2.6810
3.7736
0.8569
1.7575
2.5893
3.2573
4.0816
5.8824
0.8019
1.5291
2.3004
3.4746
4.2445
5.7241
0.6983
1.4300
2.1017
2.6853
3.3434
4.7506
Table 3.7
1X
2X
3X
4X
5X
7X
TLM measurements
Resistance (k)
0
0.000
0.002
0.004
0.006
0.008
0.010
0.012
0.014
Spacing (inch)
Figure 3.7
41
0.016
3.5
A lot of information comes from the I-V measurements of the diode structures
fabricated on the wafer. From the I-V measurement we can verify the devices behavior
in the forward and reverse bias conditions. The reverse breakdown voltage, reverse
saturation current, the barrier height and the ideality factor n and be calculated from this
measurement.
For diode #4 and #18, the results of I-V measurements are shown in figure 3.8 and
figure 3.9. From these figures we can directly determine the reverse saturation currents as
given below.
For #4I = 3.810-6 A,
and for #18,
I = 5.610-7A.
From these curves we can verify that the Schottky diodes #4, #18 show very good
diode like behavior. All the sites show the similar results and it is a good identification
that the quality of diodes is uniform and good repeatability. This can tell the parameter of
the channel making and Al deposition is good.
0.0008
0.0007
site 1
site 2
site 3
site 4
site 5
0.0006
Current (A)
0.0005
0.0004
0.0003
0.0002
0.0001
0.0000
-0.0001
-6
-4
-2
Voltage (V)
Figure 3.8
42
0.0004
Current (A)
0.0003
site 1
site 2
site 3
site 4
site 5
0.0002
0.0001
0.0000
-6
-4
-2
Voltage (V)
Figure 3.9
From the measurement at different sites of the wafer, the breakdown characteristics of
the devices are predicted. From the result, which is shown in the figure 3.10, the
breakdown voltage is around 28 V and is the same for other devices.
Current (A)
0 .0 1 0
0 .0 0 5
0 .0 0 0
-3 5
-3 0
-2 5
-2 0
-1 5
-1 0
V o lta g e ( V )
-5
-0 .0 0 5
-0 .0 1 0
-0 .0 1 5
43
1 0
Figure 3.10
The current-voltage characteristics for Schottky diode is given by the familiar diode
expression as follows,
nkqVT
J J s e B 1
(3.2)
Where
Js A T e
**
qBn
k BT
Figure 3.11 Optical measurement of dimensions for device #4 and device #18
(Unit: 0.0001 inch)
Then we can plot log J-V plots as follows from the obtained I-V curves. The figure
3.12 shows this plot.
44
0.5
0.0
-0.5
-1.0
-1.5
ln (J)
-2.0
-2.5
-3.0
-3.5
-4.0
site
site
site
site
site
-4.5
-5.0
-5.5
-6.0
1
2
3
4
5
Y=
Y=
Y=
Y=
Y=
4.4
4.6
-6.60665 + 1.34391 * X
-15.95997 + 3.23921 * X
-6.47556 + 1.38161 * X
-14.12939 + 2.84298 * X
-13.59726 + 2.73942 * X
-6.5
3.0
3.2
3.4
3.6
3.8
4.0
4.2
4.8
5.0
5.2
Voltage (V)
Figure 3.12
From the slop of the curves above we can calculate the ideality factor n as follows.
q
V
(3.3)
n
k BT ln J
n
q
V
1
k BT ln J slope (0.0259)
Device #4
site 1
site 2
site 3
site 4
site 5
Average
ln J / V
1.34391
3.23921
1.38161
2.84298
2.73942
2.3 0.9
28.72963
11.91958
27.94569
13.58083
14.09424
16.71846
site 1
site 2
site 3
site 4
site 5
Average
Device #18
ln J / V
3.77354
1.3343
0.57811
3.27287
3.19152
2.4 1.4
10.23178
28.93655
66.78666
11.797
12.0977
15.88846
45
Table 3.9
site 2
site 3
site 4
site 5
Average
Y-intercept
-6.60665
-15.96
-6.47556
-14.1294
-13.5973
11 4
JS (A/cm2)
0.001351
1.17E-07
0.001541
7.31E-07
1.24E-06
1.17E-05
site 1
site 2
site 3
site 4
site 5
Average
Y-intercept
-20.4712
-8.44625
-2.99516
-18.8849
-17.1166
14 7
JS (A/cm2)
1.29E-09
0.000215
0.050029
6.29E-09
3.68E-08
1.26E-06
Device #18
Table 3.10
Calculations of JS
k BT A**T 2
ln
q
JS
(3.4)
For Device #4
8.16 3002
k BT A**T 2
ln
0.0259
ln
-05
q
1.17 10
JS
0.644V
8.16 3002
k BT A**T 2
ln
0.0259
ln
-6
q
1.26 10
JS
0.702V
For GaAs,
46
Then we can calculate built-in potential Vbi for device #4 and #18 as follows.
For Device #4
Vbi B Vn 0.625V
For Device #18
Vbi B Vn 0.683V
These results are very close to the theoretic value for Vbi, which is 0.3V.
3.6
Capacitance-Voltage Measurement
From the Capacitance-Voltage measurement, the built-in potential Vbi and channel doping
carrier concentration ND can be obtained. The plots of C-V measurement for #20 are
shown in Figure 3.13. The expression for the space charge capacitance is given by
q S N D
C SC S
W
2(Vbi V )
From this equation we can get
2(Vbi V )
1
(3.5)
2
CSC (V ) q s N D A2
8.00E-011
Capacitance (F)
7.00E-011
6.00E-011
5.00E-011
4.00E-011
3.00E-011
-2.0
-1.5
-1.0
-0.5
0.0
0.5
Voltage (V)
Figure 3.13
C vs. V Curve
Where,
A is the capacitor area or the Schottky contact area, for #19 capacitance,
A 4.9 10-4 cm-2
s 0 r (8.85 1014 Farad / cm) 13.1 1.16 1012 Farad / cm
47
1
versus the reverse bias is shown in figure 3.14.
2
CSC
8.00E+020
7.00E+020
5.00E+020
1/C SC
6.00E+020
4.00E+020
3.00E+020
2.00E+020
1.00E+020
-2.0
-1.5
-1.0
-0.5
0.0
0.5
Voltage (V)
Figure 3.14
1
versus the reverse bias
2
CSC
2 .0 0 E + 0 2 0
1 .8 0 E + 0 2 0
1 .6 0 E + 0 2 0
1 .4 0 E + 0 2 0
1/C
1 .2 0 E + 0 2 0
1 .0 0 E + 0 2 0
8 .0 0 E + 0 1 9
6 .0 0 E + 0 1 9
4 .0 0 E + 0 1 9
2 .0 0 E + 0 1 9
L in e a r F it o f 1 /C
2
SC
-V p lo t:
Y = 1 .6 1 0 9 7 E 2 0 -1 .1 6 9 1 8 E 2 0 *X
X -in te rc e p t: 1 .3 7 V
0 .0 0 E + 0 0 0
-0 .2
0 .0
0 .2
0 .4
0 .6
0 .8
1 .0
V o lta g e (V )
Figure 3.15
48
1 .2
1 .4
An extrapolation of the linear line is performed to get the voltage intercept and the builtin potential.
Vbi = 1.37 V
k BT N D
ln
2q
q
ni
1.42
7.2 E16
Vbi
V (0.0259V ) ln
Vbi 0.06V
2
8.7 E 5
So the barrier height is 1.43V
bn M Vbi S Vbi
Eg
The Channel Doping Profile (ND vs. W) can now be obtained form the following
expressions. The plot for the resulting channel doping is shown in the figure 3.15.
2
d (1/ CSC )
dV
s A
W (V )
CSC (V )
2
N D (W )
q s A2
49
(3.6)
(3.7)
8.00E+017
7.00E+017
6.00E+017
5.00E+017
4.00E+017
3.00E+017
2.00E+017
1.00E+017
0.00E+000
0.00 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 0.11 0.12 0.13 0.14 0.15
Depth (m)
Figure 3.15
3.7
Conclusion
Most of the measurements and calculations shown in this chapter are consistent with
the theoretical values. The experimentally measured values shown in this chapter show,
in general close agreement with those calculated theoretically in the previous chapter.
There are few exceptions where we had to do minor adjustments to get the consistent
results. For example the channel C V data from the first time measurement was
completely unexpected. This might be due to improper channel doping. To obtain abovementioned results we took the readings in a fresh wafer. The fabrication of the device in
the lab was successful.
One thing we clearly see that the channel implantation might have some problem.
This is because the measurement data for channel sheet resistance and also the C-V data
are not consistent to the theoretical expectation. But the Source / Drain implantation
seems to be pretty good. This can be verified from the sheet resistance measurement data
given above.
50
Introduction
(4.1)
which represents the net potential required to deplete a channel of thickness h under
the gate. The theshold voltage is then defined as
VT = Vbi VPo
(4.2)
E g k BT N D
ln
Vbi = m s = m +
2q
q
ni
(4.3)
where m is the Gate metal (Al) work function (4.4 V), is Electron Affinity of
GaAs (4.04 V) and Eg, ni are Energy bandgap and Intrinsic carrier concentration
(1.42 eV, 8.7x105/cm3 for GaAs)
Figure 4.1
51
The dashed parabola in Figure 4.1 is the locus of saturation voltage. The saturation
voltage VDsat is the drain-source voltage at which the drain current saturates for a given
VGS., given by
VDsat = VPo Vbi + VGS
(4.4)
The region to the left of this parabola is known as the linear region because, for a
given gate voltage, the drain current is linear with VDS until saturation effects become
dominant as VDsat is approached. The region between the parabola and avalanche
breakdown is known as the saturation region.
We can calculate the ID (VGS, VDS) equations for two regions from saturated
velocity model, given by
Linear region, VD < VDsat
1/ 2
q n N DWh (Vbi VG )
ID =
1
VD
L
VPo
(4.5)
4.1.2
3/ 2
3(V V )
Vbi VG
q n N DWh
bi
G
VPo 1
=
+ 2
3L
VPo
VPo
(4.6)
The I-V characteristics of 2- m channel (device 10) and 5- m channel (device 12)
GaAs MESFET are shown in Fig. 4.2 and Fig. 4.3. The drain current is plotted against
the drain voltage for various gate voltages.
52
0.8
VGS = 0 V
VGS = -0.1 V
VGS = -0.2 V
VGS = -0.3 V
VGS = -0.4 V
VGS = -0.5 V
VGS = -0.6 V
VDS = -0.7 V
0.7
0.6
IDS ()
0.5
0.4
0.3
0.2
0.1
0.0
0
VDS (volts)
Figure 4.2
1.0
VGS = 0 V
VGS = -0.1 V
VGS = -0.2 V
VGS = -0.3 V
VGS = -0.4 V
VGS = -0.5 V
VGS = -0.6 V
VDS = -0.7 V
0.8
IDS ()
0.6
0.4
0.2
0.0
VDS (volts)
Figure 4.3
53
4.1.3
As shown in the IDS-VDS characteristics for different gate voltage, we see that the
drain current becomes almost zero at about VGS = -0.7 V for both device 10 and
device 12. Reading were taken only up to this point, as if we had gone further into
negative VGS, we would have reached a point of zero drain current at a negligible
value. Therefore by these figures we get a rough estimate of the threshold voltage,
which will be greater than -0.7 V, but not too greater.
Measurement of threshold voltage from linear region ID - VG curve
ID
nW
(4.7)
(VG VT )VD
Lh
So we can plot ID vs. VG in the linear region, the x-intercept will be the threshold
voltage VT, the plot for device #12 is shown in figure 4.4, and the threshold voltage is
shown in table 4.1.
0.4
VDS = 0.3 V
IDS (A)
0.3
Linear fit:
Y=0.38133+0.5581*X
0.2
0.1
0.0
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
VGS (volts)
Figure 4.4
54
0.1
Table 4.1
Device No
VD (V)
VT (V)
10
0.4
-0.7
12
0.3
-0.7
I D - VG curve
nW
Lh
(VG VT ) 2
(4.8)
from the x-intercept. The plot for device #12 is shown in figure 4.5 and the calculated
threshold voltage is shown in table 4.2.
1.0
0.9
VDS = 3.9 V
VDS = 5.9 V
0.8
sqrt (IDS)
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
VGS (volts)
Fig 4.5
I DS -VGS plot for Device #12 , VDS = 3.9, 5.9 V, (VDS > VDsat)
55
Table 4.2
Device No
VD (V)
VT (V)
10
3, 5
-0.9
12
3.9, 5.9
-0.9
From (4.2), the threshold voltage can be calculated from pinchoff voltage VPo and
gate-channel builtin potential Vbi. The gate-channel builtin potential can be calculated
from (4.3)
1.42
7.2 E16
Vbi = 4.4V 4.04V +
V (0.0259V ) ln
= 0.3V
2
8.7 E 5
It can be seen in the IDS-VDS plot (Figure 4.6) that the breakdown voltage for 2 m
56
Figure 4.6
n =
I D
Lh
1
W (VG VT ) VD V
G
where
(4.9)
VD VG
I D
(S )
VD
(cm2 / V sec)
3.70E-05
409.2823
-0.1
2.80E-05
361.34834
57
-0.2
2.30E-05
356.18622
-0.3
1.75E-05
338.76407
-0.4
1.30E-05
335.53775
-0.5
9.00E-06
348.44304
AVERAGE
Table 4.3
358.26029
I D
(S )
VD
(cm2 / V sec)
0.0007625
405.11691
-0.1
0.0006625
410.65129
-0.2
0.0005875
436.99496
-0.3
0.0003875
360.2884
AVERAGE
403.26289
Table 4.4
L = 5 m
h = 0.221 m
W = 104.1 m
VG (V )
I D
(S )
VD
(cm2 / V sec)
0.001333333
1771.0029
-0.1
0.001066667
1652.936
-0.2
0.000886667
1648.8037
-0.3
0.000686667
1596.1163
AVERAGE
Table 4.5
1667.2147
58
From the theoretical calculation for the channel, we know the peak concentration NP
is
Figure 4.7
The mobility is about 4400 cm2/V-s. Here the discrepancy is very big. Maybe this is
caused by poor channel implant.
4.3 Transconductance measurements
The transconductance can be calculated from the above MESFET transistor I-V
characteristics, given by
gm =
I D (VGS ,VDS )
VGS
(4.10)
Vg (V)
-0.2
-0.3
-0.2
-0.3
Table 4.6
Id (A)
0.426
0.322
0.415
0.28
Transconductance values
59
gm (S)
1.04
1.35
go =
I DS
VDS
1
RDS
=
VGS
(4.11)
The output conductance g0 of our device is for 0.9x10-6 S for 2 m device and almost
contant for all VGS, corresponding output resistance (RDS) is of the order of 106 ohm.
For 5m, g0 and RDS are 10-6 S and 106 ohm respectively.
The output capacitance is important since it also affects the transit time. The output
capacitance is a parasitic capacitance on the devices output, which degrades its high
frequency performance. We can calculate the output (drain-source) capacitance from
the average output conductance by
CDS = g 0
Leff
vS
(4.12)
where
Leff : the effective channel length (approximate as the gate metal length)
vS : the electron velocity in the channel (approximated as 1.2x107 cm/sec)
For 2 m MESFET, CDS = 1.5 105 pF and for 5 m MESFET,
With the drain open (floating), we can measure the I-V characteristic for the gate to
source. We also can obtain the corresponding resistance by
I
Ri = GS
VGS
(4.13)
The calculation results are Ri = 4.4 107 and 1.3 108 for 2 m MESFET and 5
m MESFET respectively.
4.5 Gate - Source capacitance
We can also estimate the gate-source capacitance () by GSC
CGS ( pF ) = CSCWL
60
(4.14)
where
RS =
AuW
dL
(4.15)
where
Au : the resistivity of Au
W: the width of gate
L: the length of gate
d: the thickness of metal on gate
For 2 m MESFET, Rs= 2.28 ohm and for 5 m MESFET Rs= 0.912 ohm.
This series resistance contributes the reduction of transconductance. The extrinsic
transconductance is reduced by this extrinsic series resistance. The relationship
between and is given by
gm =
g mi
1 + g mi RS
(4.16)
where the calculated intrinsic transconductance is 5.057 (mS) for 2m MESFET and
4.0146 (mS) for 5m MESFET.
The gate and drain capacitance can be calculated by
CDG =
o
dGD
W tm
(4.17)
where
dGD = separation of the gate and drain metal on GaAs surface
W = gate width perpendicular to current flow
tm = thickness of pad metal
The small signal equivalent circuit for the MESFET can be assembled from the above
measurements and calculations as shown in figure 4.8. The data is shown table 4.7
61
and 4.8.
Figure 4.8
From the above measurement and calculations, we can assemble the small signal
equivalent circuit for MESFET. We choose the DC point at VDS=3 V for device #10
VDS=1.9 V for device #12, VGS= -0.3V.
For 2 m MESFET,
Intrinsic Element
Extrinsic Elements
Gm=1.04 (S)
CGS=0.5654(pF)
Rd=10000( )
Rg=2.28( )
Rd=1.43( )
Ri = 4.4 107
Rs=1.43( .)
CDG=0.0381 (pF)
Table 4.7
For 5 m MESFET,
62
Intrinsic Element
Extrinsic Elements
Gm=1.35 (S)
CGS=1.363(pF)
Rd=20000( )
Rg=0.912( )
Rd=1.43( )
Ri = 1.3 108
Rs=1.43( )
CDG=0.0381 (pF)
The small equivalent circuit for 2 m is shown in Fig. 3.32
4.8 Cutoff Frequency
The cutoff frequency fT is maximum frequency at which the transistor can operate
with gain and is given by
fT =
gm
2 (CGS + CGD )
(4.18)
The cutoff frequencies obtained in our devices are fT = 1.32MHz for 2 m MESFET
and 3.96MHz for 5 m MESFET. In general, the maximum cutoff frequency is
related to the transit time effect. Therefore, in order to obtain a more desirable and
higher cutoff frequency, the output resistance and the parasitic source to drain
resistance must be minimized to achieve a higher transconductance. The output
capacitance should also been reduced. Furthermore, improvement of the fabrication
and measuring techniques in our lab should be made.
63
Chapter 5 Conclusion
In this Fabrication Lab course, we fabricated the GaAs MESFETs using a
simple four-mask, double ion implantation process. This process includes the standard
process of photolithography, ion implantation, and metal deposition.
After fabrication, we did the sheet resistance measurements, channel and
source/drain I-V measurements, TLM measurements, IV characteristic of Schottky
diode measurements, breakdown measurements, C-V measurements, MESFET I-V
measurements, threshold voltage measurements, trans-conductance measurements,
Electron mobility measurements, Output conductance measurements, gate source
leakage measurements, and optical measurements for some devices.
After dealing with the experimental data, we found most of the obtained data
from experiments are consistent to the theoretical results. This testifies the theories to
describe the fabrication process and the characteristics of these devices are correct.
Also the results verified that we did the correct fabrication process and obtained the
devices with good quality and did the correct measurements.
From this class, we learn the comprehensive knowledge in fabrication and in the
various characteristics for MESFET devices. This gave us a much deeper
comprehension in this field and will surely help us in the future learning and working.
We would like to appreciate Prof. Kenneth P. Roenker for his perfect lectures.
And we also want to give our thanks to the engineer and the TA for this class for their
good help.