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    Vlsi Resume

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    linhanuma
    Naga Sitaram is a final year M.Tech student in VLSI and Embedded Systems from IIIT Hyderabad seeking a position as a Design Engineer. He has a B.E. in Electronics and Communications from Sir C R Reddy College of Engineering and is pursuing an M.Tech from IIIT Hyderabad with a 6.2 CGPA. His areas of focus include analog, mixed signal and low-power VLSI design and he has experience with EDA tools like Tanner and Quartus II.

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    Vlsi Resume

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    linhanuma
    7K views4 pages
    Naga Sitaram is a final year M.Tech student in VLSI and Embedded Systems from IIIT Hyderabad seeking a position as a Design Engineer. He has a B.E. in Electronics and Communications from Sir C R Reddy College of Engineering and is pursuing an M.Tech from IIIT Hyderabad with a 6.2 CGPA. His areas of focus include analog, mixed signal and low-power VLSI design and he has experience with EDA tools like Tanner and Quartus II.

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    Naga Sitaram is a final year M.Tech student in VLSI and Embedded Systems from IIIT Hyderabad seeking a position as a Design Engineer. He has a B.E. in Electronics and Communications from Sir C R Reddy College of Engineering and is pursuing an M.Tech from IIIT Hyderabad with a 6.2 CGPA. His areas of focus include analog, mixed signal and low-power VLSI design and he has experience with EDA tools like Tanner and Quartus II.

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    7K views4 pages

    Vlsi Resume

    Uploaded by

    linhanuma
    Naga Sitaram is a final year M.Tech student in VLSI and Embedded Systems from IIIT Hyderabad seeking a position as a Design Engineer. He has a B.E. in Electronics and Communications from Sir C R Reddy College of Engineering and is pursuing an M.Tech from IIIT Hyderabad with a 6.2 CGPA. His areas of focus include analog, mixed signal and low-power VLSI design and he has experience with EDA tools like Tanner and Quartus II.

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    of 4

    NAGA SITARAM.

    Srinilayam • 25-10-12 • Fire Station Street • NR Pet • Eluru -534006


    Phone: +91 9885838554 • E-mail: [email protected]

    OBJECTIVE
    Being a final year post graduation student in the VLSI stream, I am seeking for
    the position of a Design Engineer that requires applying my analytical skills in
    the field of VLSI.

    EDUCATION
    • Now pursuing M.Tech program specialized in VLSI &Embedded Systems
    in IIIT, Hyderabad &obtained 6.2 CGPA till now.

    • In 2006 received B.E degree in the field of Electronics &Communications


    Engineering from Sir C R Reddy COE, Eluru (Affiliated to Andhra
    University) with 69%.

    • In 2002 completed Intermediate (MPC) in Siddartha Vidyalaya, Eluru with


    93%.

    • In 2000 finished SSC in Sri Helapuri High School, Eluru with 79%.

    SUBJECTS LEARNED
    Analog, Mixed Signal and Low -Power Design, VLSI Algorithms, Advanced
    Digital Design with HDLs, Formal Foundations of VLSI Design, and
    Introduction to VLSI Design.

    COMPUTER COURSES
    Certified as EXCELLENT in “Honors diploma in Web Applications”, in
    which Linux, SQL, Software Engineering etc. are the part of its curriculum at
    NIIT, ELURU in March 2006.
    PROJECT WORKS
    Data Compression using LZW algorithm with C: Our project implements the
    LZ algorithm in an efficient way and uses Gzip, Deflate standards for
    compressed data. So, any commercial software like WinZip can decompress the
    file, which is compressed using these standards.

    Data Security with Steganography using MATLAB: Our project consists of


    two phases: The first phase is data encryption and the second phase is hiding
    encrypted data in the picture. As an application to this project Digital
    watermarking was implemented.

    Hardware implementation of AES in Puzzle Algorithm: In this project we


    Implemented a novel video encryption algorithm, called Puzzle, to encrypt video
    data. It is fast enough to meet real-time demands and provides a sufficient
    security. The algorithm can readily be incorporated into existing multimedia
    systems.

    ACHIEVEMENTS
    Runner-up in the Poster Presentation contest at NIT Warangal in TechnoZion
    06, a National Level Technical Symposium.

    Won Second Prize in paper presentation contest in National level Technical


    Symposium –Knew 06, Channabasaveswara Institute of Technology, Tumkur,
    Karnataka.

    Stood in Third Position in National Level Paper Presentation Contest at JNTU,


    Kakinada in AEON 05.

    Got Consolation Prize in National Level Paper Presentation Contest at


    Audisankara College of Engineering & Technology, Gudur in FLAIR 05.

    EDA TOOLS (DIGITAL DESIGN)


    Simulation: Active HDL

    Synthesis : QUARTUS II (Altera)

    FPGA implementation tools : Quartus-II (Altera)


    EDA TOOLS (ANLOG DESIGN)
    Tanner EDA tools

    schematic Capture: S-Edit

    Simulation: T-Spice, W-Edit

    Physical Layout: L-Edit

    Verification: L-Edit Standard DRC, L-Edit LVS

    TECHNICAL SKILLS
    Programming languages: C, shell, perl, SQL, HTML, PhP, XML, C++, java

    HDLs : Verilog

    Operating Systems : Linux, Windows

    STRENGTHS
    Good Knowledge in the VLSI Design flow.

    Strong analytical Ability Skills.

    Excellent English Communication skills both written and verbal.

    Basic Knowledge of Networking and Hardware.

    INTERESTS AND ACTIVITIES


    Class representative &Lab in-charge for PG2k6 VLSI batch in IIIT.

    Active member of Student Parliament in IIIT –H.

    Led the IETE Student Forum in Sir CRR Engineering College, Eluru as the
    President in B.E final year.

    COMMUNITY ACTIVITIES
    Member of Ashakiran health wing in IIIT –H

    Active Member of NSS in Sir CRR Engineering college, Eluru

    REFERENCES:
    Available on request.

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