Scribd Logo
Upload

Welcome to Scribd!

  • 2K views

    VHDL Cheat Sheet PDF

    Uploaded by

    Eng Cina Hassan Cina
    This document provides a cheat sheet for VHDL concepts including concurrent and sequential statements. Concurrent statements like concurrent signal assignment use the dataflow model to assign signals simultaneously, while sequential statements like processes use the behavioral model to assign signals in sequence. Conditional structures like if/else statements and case statements allow conditional signal assignments based on conditions or expressions.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    VHDL Cheat Sheet PDF

    Uploaded by

    Eng Cina Hassan Cina
    2K views1 page
    This document provides a cheat sheet for VHDL concepts including concurrent and sequential statements. Concurrent statements like concurrent signal assignment use the dataflow model to assign signals simultaneously, while sequential statements like processes use the behavioral model to assign signals in sequence. Conditional structures like if/else statements and case statements allow conditional signal assignments based on conditions or expressions.

    Original Title

    VHDL Cheat Sheet.pdf

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    This document provides a cheat sheet for VHDL concepts including concurrent and sequential statements. Concurrent statements like concurrent signal assignment use the dataflow model to assign signals simultaneously, while sequential statements like processes use the behavioral model to assign signals in sequence. Conditional structures like if/else statements and case statements allow conditional signal assignments based on conditions or expressions.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    2K views1 page

    VHDL Cheat Sheet PDF

    Uploaded by

    Eng Cina Hassan Cina
    This document provides a cheat sheet for VHDL concepts including concurrent and sequential statements. Concurrent statements like concurrent signal assignment use the dataflow model to assign signals simultaneously, while sequential statements like processes use the behavioral model to assign signals in sequence. Conditional structures like if/else statements and case statements allow conditional signal assignments based on conditions or expressions.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 1

    VHDL Cheat-Sheet

    Copyright: 2007 Bryan J. Mealy

    Concurrent Statements

    Sequential Statements

    Concurrent Signal Assignment

    Signal Assignment

    (dataflow model)

    target <= expression;

    target <= expression;

    A <= B AND C;
    DAT <= (D AND E) OR (F AND G);

    A <= B AND C;
    DAT <= (D AND E) OR (F AND G);

    Conditional Signal Assignment

    if (condition) then
    { sequence of statements }
    elsif (condition) then
    { sequence of statements }
    else --(the else is optional)
    { sequence of statements }
    end if;

    target <= expressn when condition else


    expressn when condition else
    expressn;

    F3 <= 1 when (L=0 AND M=0)


    1 when (L=1 AND M=1)
    0;

    (dataflow model)

    with chooser_expression select


    target <= expression when choices,
    expression when choices;

    11,
    10,
    01,
    00,
    others;

    Process
    (behavioral model)

    opt_label: process(sensitivity_list)
    begin
    {sequential_statements}
    end process opt_label;
    proc1: process(A,B,C)
    begin
    if (A = 1 and B = 0) then
    F_OUT <= 1;
    elsif (B = 1 and C = 1) then
    F_OUT <= 1;
    else
    F_OUT <= 0;
    end if;
    end process proc1;

    if
    (SEL =
    elsif (SEL =
    elsif (SEL =
    elsif (SEL =
    else F_CTRL
    end if;

    else
    else

    Selective Signal Assignment

    with SEL select


    MX_OUT <= D3 when
    D2 when
    D1 when
    D0 when
    0 when

    if statements

    (dataflow model)

    111) then
    110) then
    101) then
    000) then
    <= 0;

    F_CTRL
    F_CTRL
    F_CTRL
    F_CTRL

    case statements

    <=
    <=
    <=
    <=

    case (expression) is
    when choices =>
    {sequential statements}
    when choices =>
    {sequential statements}
    when others => -- (optional)
    {sequential statements}
    end case;
    case ABC is
    when 100 =>
    when 011 =>
    when 111 =>
    when others =>
    end case;

    F_OUT
    F_OUT
    F_OUT
    F_OUT

    <=
    <=
    <=
    <=

    1;
    1;
    1;
    0;

    D(7);
    D(6);
    D(1);
    D(0);

    You might also like