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    CO (Elective) June10

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    shahpatel19
    This document appears to be an exam for a computer architecture course. It contains 7 questions testing knowledge of various computer architecture topics like: 1) Booth's multiplication algorithm and performing a multiplication using it. 2) Instruction pipelining and branch prediction methods. 3) Memory read operation timing diagrams. 4) Memory segmentation and optical memory. The questions cover additional topics such as cache memory organization and replacement algorithms, microprogrammed control and microinstruction format, parallel and serial port structure and access methods, pipeline hazards, hardwired control implementation, virtual memory and address translation using TLB, IA-32 register organization and addressing modes, I/O device access methods and interrupts, cache mapping

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    CO (Elective) June10

    Uploaded by

    shahpatel19
    59 views1 page
    This document appears to be an exam for a computer architecture course. It contains 7 questions testing knowledge of various computer architecture topics like: 1) Booth's multiplication algorithm and performing a multiplication using it. 2) Instruction pipelining and branch prediction methods. 3) Memory read operation timing diagrams. 4) Memory segmentation and optical memory. The questions cover additional topics such as cache memory organization and replacement algorithms, microprogrammed control and microinstruction format, parallel and serial port structure and access methods, pipeline hazards, hardwired control implementation, virtual memory and address translation using TLB, IA-32 register organization and addressing modes, I/O device access methods and interrupts, cache mapping

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    CO(Elective) June10 (2)

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    This document appears to be an exam for a computer architecture course. It contains 7 questions testing knowledge of various computer architecture topics like: 1) Booth's multiplication algorithm and performing a multiplication using it. 2) Instruction pipelining and branch prediction methods. 3) Memory read operation timing diagrams. 4) Memory segmentation and optical memory. The questions cover additional topics such as cache memory organization and replacement algorithms, microprogrammed control and microinstruction format, parallel and serial port structure and access methods, pipeline hazards, hardwired control implementation, virtual memory and address translation using TLB, IA-32 register organization and addressing modes, I/O device access methods and interrupts, cache mapping

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    59 views1 page

    CO (Elective) June10

    Uploaded by

    shahpatel19
    This document appears to be an exam for a computer architecture course. It contains 7 questions testing knowledge of various computer architecture topics like: 1) Booth's multiplication algorithm and performing a multiplication using it. 2) Instruction pipelining and branch prediction methods. 3) Memory read operation timing diagrams. 4) Memory segmentation and optical memory. The questions cover additional topics such as cache memory organization and replacement algorithms, microprogrammed control and microinstruction format, parallel and serial port structure and access methods, pipeline hazards, hardwired control implementation, virtual memory and address translation using TLB, IA-32 register organization and addressing modes, I/O device access methods and interrupts, cache mapping

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
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    - Con. 3957-10. (REVISED COURSE) AN-4462
    (3 Hours) [Total Marks: 100
    N.B. : (1) Question No, 1 is compulsory.
    (2) Attempt any four out of remaining six question.
    (3) Figures to the right indicate full marks.
    1. Solve any 'Four' of the following:
    a) Discuss Booth's algorithm for multiplication. Perform 1001 x 0011 using booth's 05
    algorithm.
    b) What is instruction pipelining? Write different branch prediction methods. 05
    c) Explain Memory read operation with timing diagram 05
    d) What is Memory Segmentation? Explain in Brief. 05
    e) Explain In Brief Optical memory. 05
    2. a) Explain in details organization of cache memory. Explain different replacement 10
    algorithms.
    b) What is micro programmed control? Explain in details. Write format of 10
    r"'\ " Microinstruction.
    ,
    3. a) Explain structure of serial and Parallel ports. Write methods to access it. 10
    ;; b) Explain Different Hazards in pipelining in details. 10
    4. a) Explain in details Hardwired control. Discuss different methods to implement it. 10
    b) Explain concept of Virtual memory. What is address translation? Explain use of 10
    TLB.
    ,
    5. a) Explain register organization for IA-32 family. Hence explain different 10
    addressing modes for IA-32 architecture.
    b) Explain different I/O device access methods. Hence explain use of interrupts to 10
    access I/O Device.
    6. a) Explain different Mapping functions for Cache memory. 10
    ---
    b) Explain data transfer in Synchronous Bus with timing diagram. Hence explain 10
    bus arbitration schemes.
    7. Write short notes on (Any nYQ) : 20
    . i) RISC Vs CISC Characteristics
    : ii) Paging
    iii) The ARM family Architecture(RISC)
    iv) Superscalar Architecture.
    :L',i;

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