Electronics Projects

K55.
SUCTION CUP PHONE PICKUP

It is often very convenient for other people in the room to The output of the second preamp is fed to the power
listen to both sides of a phone conversation. The amplifier amplifier stage via C7 & P1. C7 removes any DC
in this it has been designed for this use. A specially component from the amplified signal while P1 acts as a
designed magnetic pickup with a suction cup attaches volume control. The LM386 is very easy to use and
onto the earpiece of your phone at one end and into the requires a minimum of external components. C8 provides
amplifier at the other. The design is low cost and there filternig & bypassing for the internal bias network. C9
is no direct electrical connection to the phone system. removes any DC component from the output signal. The
gain of the LM386 may be set according to the
The kit is constructed on single-sided printed circuit combination of resistors & capacitors across pins 1 & 8.
boards. Protel Autotrax & Schematic were used. With no components the gain is 20. Finally use some wire
to connect the speaker to the terminal block output.
ASSEMBLY INSTRUCTIONS
Check off the components against the component listing. Place the suction cup near the receiver on the handset.
Make sure you identify every component. It is generally Keep the speaker away from the handset to stop any
easiest if you solder the lowest height components first, feedback. The pickup will be affected by strong magnetic
the resistors then the capacitors & IC sockets. Make sure fields - mains wiring, a computer monitor and TV set. Low
to get the electrolytic capacitors around the correct way. roll-off filters (to reduce the 50Hz hum) could have been
Note there is one link to make on the board next to the included in the circuit just as the high roll-off filters have
power supply pads. Use an offcut from a resistor to make been. However, since the pickup responds to low
the link. frequency this allows the unit to be used to trace mains
wiring behind your walls or under the floor.
CIRCUIT DESCRIPTION
The telephone pickup is really a magnetic field fluctuation WHAT TO DO IF IT DOES NOT WORK
detector. It picks up the oscillating magnetic field from the Poor soldering is the most likely reason. Check all solder
receiver of your telephone when someone is speaking to joints carefully under a good light. Next check that all
you. But it will also collect any other oscillating magnetic components are in their correct position on the PCB. Did
fields which happen to be floating you add the single link. Are the IC's in their correct places.
around in the air. For example, low & high frequency noise Are the electrolytic capacitors around the correct way.
from your TV set or computer monitor or the characteristic
mains humm from power lines. High frequency filters have Visit our web site http://kitsrus.com
been built into the circuit to reduce some of this unwanted
noise.
The telephone pickup circuit consists of two high gain COMPONENTS

preamplifier stages in the LM358 followed by a power
amplifier to drive the speaker. The IC's are low cost and Resistors 1/4w, 5%:
easily available. 10K R2 R4 R5 R6 brown black orange 4
270K R1 R7 red violet yellow 2
Both preamps in the LM358 are biased to half the supply 100K R3 brown black yellow 1
voltage by R4 & R5. This allows maximum voltage swing Koa Trimpot 10K 103 1
at the outputs before hitting either supply rail. C6 Monoblock capacitors:
bypasses any AC signal to ground, stabalizing the DC
bias voltage. R3 is necessary to couple the DC bias 100nF 104 C4 C5 C7 3
voltage to IC1:B while also providing a high impedence to Electrolytic capacitors:
the input signal. 10uF mini C6 C8 2
100uF mini C1 C9 2
The RC feedback circuit on both preamps will, like any RC 220pF ceramic capacitors C3 C10 2
circuit, have a cutoff frequency. Or to think of it another 4n7 MPE box capacitor C2 1
way, the capacitance starts to act as a short circuit as the LM358 IC1 1
frequency increases and the gain decreases. The cutoff LM386 IC2 1
frequency is given by the formula: 8 pin IC socket 2
K55 PCB 1
f = 1 / (6.28 x RC) Audio jack 1
6V battery snap 1
8 ohm speaker 1
This gives a cutoff frequency of 2.7KHz which has the
Magnetic pickup with suction cap 1
effect of limiting the amount of high frequency noise, or
2 pole terminal block 1
'hiss'. This high frequency roll-off does not greatly affect
voice frequency signals since voice frequency is
nominally in the range 300Hz to 3.0KHz.
K55. SUCTION CUP PHONE PICKUP
KIT 56. DTMF DECODING & DISPLAY
This kit connects to the telephone line and records the time is the elapsed time from the first digit dialed to
number dialled (assuming tone dialling) and the the phone being hung up.
duration of the call. The kit can also be used to record
any DTMF tones detected via the built in microphone Operation via microphone input
input. The kit will not detect numbers dialled using The microphone input can take a variety of different
pulse dialling. The source code for the K1 micro- devices; a dynamic or ceramic microphone as well as
controller is provided on the floppy disk for study. a suction cup pickup coil. Be sure to insert the link
next to the microphone jack if using a ceramic type
Assembly microphone, otherwise leave open.
Check the components supplied in the kit against the
Component Listing. There are several points to note: Disconnect the decoder from the telephone line, plug
in a microphone or pickup coil and move switches
• make sure Q3 does not poke up too high. SW2 and SW3 to the "MIC" position. The "MIC"
• pins 15 & 16 on the LCD display are not used they position disables line monitoring and the decoder is
are for backlighting (which this model of LCD does unable to power down. Therefore the unit should be
not have.) So the male 14-pin single in-line header switched off when not in use.
goes in from pins 1 to 14.
Position the microphone close to the DTMF source. If
Solder the lowest height components first; the using a pickup coil as input, attach the suction cup to
resistors and capacitors. Solder the two crystals the telephone handset next to the earpiece. Switch on
quickly as they are easily damaged by excess heat. the power. The last number detected will be blank and
The tuning fork crystal can be soldered down by the the call duration set to "00:00:00".
two pads provided. Put the 9V battery snap through
the hole next to the pads to provide strain relief. As each DTMF digit is detected it is displayed. If the
decoder fails to respond to any DTMF tones, try
Operation via telephone line positioning the microphone closer to the source or
Ensure that switches SW2 and SW3 are in the "TEL" increasing the volume of the tones. Excessive volume
position. Connect the decoder to the telephone line may distort the signal presented to the DTMF decoder
and switch on the power. When connected to the and cause the tones to be ignored. If using the pickup
telephone line the decoder should be left switched on. coil, try moving the coil to a different position relative to
The decoder monitors the line condition and turns itself the earpiece (front, back or side). To reset the call
off when the line is not looped (phone is hung up!). duration time and clear the last number dialed, turn the
Current consumption is less than 50uA when off. power off then on again.
The decoder is activated whenever the phone is picked Power Consumption

up (‘the line is looped’ in telephone jargon.) The LCD The amount of current consumption varies depending
display is turned on and the last number dialed, on the mode of operation and the time elapsed since
together with the call duration, is displayed. When the decoder was activated.
using the decoder for the first time (or after switching
off), the number dialed is blank and the call duration is TEL Mode: With the phone hung up, the decoder
set to "00:00:00". Hanging up without dialing any digits draws approximately 50uA from the
will not affect the current information. battery. The current jumps to
approximately 12mA for the first 60
Dialing any digit will clear the last number dialed and seconds after picking up the handset.
re-start the call duration timer. The first digit dialed and After 60 seconds the DTMF decoder
any subsequent digits will be saved automatically. The chip and microphone circuitry are
decoder will save up to a maximum of 16 digits. Any disabled and the current consumption
further digits will be ignored. drops to approximately 6mA. It will
remain at 6mA until the unit is
In order to prolong battery life, the DTMF decoder chip switched off or the phone is hung up.
is disabled sixty seconds after the phone is picked up.
All dialing must be completed within sixty seconds of MIC Mode: The decoder draws approximately
picking up the phone. Any digits dialed after sixty 12mA from the battery while switched
seconds are not detected and therefore ignored. on.
Call progress detection is not implemented on this --------------------

unit. This means that the decoder cannot detect when
the called party answers. Therefore the call duration
Components - Kit 56 The source code for this Kit and a a general include file can
be downloaded from the software download page of our
220K 1/2W resistors ..... R1 R2............................. 2 website at
Resistors 1/4W, 5%
1K ............................... R11 ................................ 1 http://kitsrus.com/soft.html
10K ............................. R7 12 13 14 15 18 22....... 7
22K ............................. R24 ................................ 1
56K ............................. R3.................................. 1 For our full range of kits see our website at
68K ............................. R4 R20 ........................... 2
100K ........................... R10 R16 R19 R21............ 4 http://kitsrus.com
180K ........................... R9.................................. 1
220K ........................... R5.................................. 1
270K ........................... R6.................................. 1 You may email the designer of this kit at
390K ........................... R17 R23 ......................... 2
3M3............................. R8.................................. 1
10K 103 Koa trimpot ..... VR1................................ 1
[email protected]
1N4148........................ D2.................................. 1
WO2 bridge rectifier ...... D1.................................. 1
2-pin header ................. LK1................................ 1
Jumper ........................ ...................................... 1
3.579MHz crystal ......... Y1.................................. 1
4.096mhz crystal.......... Y2.................................. 1
10nF/63V box capacitor C1 C2............................. 2
10uF mini electrolytic.... C8 C9............................. 2
100nF 104 monoblok..... C3 C4 C5 C10 C11 .......... 5
0.47uF 474 monoblok.... C12 ................................ 1
27pF ceramic ............... C6 C7............................. 2
BC557 transistor........... Q1 Q3 ............................ 2
BC547 ......................... Q2.................................. 1
SPDT switch................ SW1 SW2 ...................... 2
DPDT switch................ SW3............................... 1
2.5mm audio jack ......... J1................................... 1
Telephone jack ............. X1 .................................. 1
LCD 2x16..................... ...................................... 1
14-pin male single-in-line header ........................... 1
14-pin female single-in-line header......................... 1
LM358 IC ..................... U5.................................. 1
MAX666 IC................... U4.................................. 1
Programmed 68HC705K1P........U2....................... 1
8870 decoder IC ........... U1.................................. 1
8 pin IC socket ............. ...................................... 2
16 pin IC socket ........... ...................................... 1
18 pin IC socket ........... ...................................... 1
9V battery snap............ ...................................... 1
Plastic box & 4 screws . ...................................... 1
K56 PCB ..................... ...................................... 1
DIY Electronics
Southern Cross II
8031 Single Board Computer
Hardware Manual
DIY Electronics (HK) Ltd

PO Box 88458
Sham Shui Po
Hong Kong
Fax: (852) 2725-0610

Voice: (852) 2720-0255
Email: [email protected]
http://kitsrus.com
November, 1998.
0
Introduction
The Southern Cross II single board computer is based around the 8032/52 8-bit microcontroller. Adding a
power supply and connecting to any PC capable of running an 8051 cross-assembler enables the user to
implement an 8031 software development system. Programming in BASIC is also possible using one of the
8052-BASIC chips currently available. If your board is fitted with one of these BASIC chips then switching
from one software environment to the other is simply a matter of inserting or removing a link.
The Southern Cross II, when used in conjunction with the MVS-31 debugging monitor, implements a
complete 8031-based assembly language software development system. The extra resources provided by an
8032/52 over an 8031,(extra timer and an additional 128 bytes of internal RAM memory), together with an
independent external UART allows the user complete access to all the 8031's internal ports and timers.
Software debugging tools such as breakpoints, watchpoints and single stepping are provided by the MVS-31
monitor program. Refer to the "MVS-31 User's manual" for further details.
Getting Started
Running in 8031 mode
Insert the MVS-31 monitor EPROM into socket IC4 and ensure that jumper JP2 is set to the correct EPROM
type. An 8032/52 microcontroller chip must be used in position IC1.
1. Insert a link on jumper JP1.

2. Move switch SW2 to the OFF position.
3. Connect a 9 - 12 volt DC plug pack via power connector J7.
4. Connect the supplied serial cable to connector J5 ("HOST" port). Connect a terminal or PC (running
terminal emulation software) to the D25 connector on the cable. Configure the terminal or PC serial port
to 8 data bits, 1 stop bit and no parity. The baud rate should be set to 1200, 2400, 4800, 9600 or 19200
bps.
5. Turn on the power via switch SW3. LED D2 should light.
6. Press the Carriage Return ( Enter↵ ) key to trigger the MVS-31 automatic baud rate detection. A sign on
banner will appear followed by a " > " prompt. Commands may now be entered.
Running in BASIC mode
This mode requires an 8052-BASIC microcontroller chip in position IC1. A 27256 EPROM is also necessary
in position IC4 if BASIC programs are to be saved into EPROM. Ensure that jumper JP2 is set to the correct
EPROM type.
1. Remove the link from jumper JP1.

2. Move switch SW2 to the OFF position.
3. Connect a 9 - 12 volt DC plug pack via power connector J7.
4. Connect the supplied serial cable to connector J6 ("USER" port). Connect a terminal or PC (running
terminal emulation software) to the D25 connector on the cable. Configure the terminal or PC serial port
to 8 data bits, 1 stop bit and no parity. The baud rate should be set to 1200, 2400, 4800, 9600 or 19200
bps.
5. Turn on the power via switch SW3. LED D2 should light.
6. Press the space bar to trigger the BASIC-52 automatic baud rate detection. A sign on message will
appear followed by a "READY" prompt. Commands may now be entered.
Please read the section on "BASIC-52 Programming" before attempting to save any programs into EPROM.
EPROM types
The Southern Cross II can use three different EPROM types, 8K (2764), 16K (27128) and 32K (27256). The
EPROM type is selected by setting jumper JP2 to the correct position as marked on the circuit board.
Note that in order to save BASIC programs in EPROM, a 27256 EPROM must be used.
Southern Cross II Memory Map

This manual does not aim to provide a detailed explanation of the architecture of the 8051 family of
microcontrollers. However a short description is necessary so that the memory decoding scheme can be
explained and understood.
The 8051 family of microcontrollers implement the Harvard memory architecture. This means that these
devices have separate address spaces for Program and Data memory, each up to 64K in size. Internal
circuitry in the microcontroller accesses the correct memory based on the instruction being executed.
As well as having separate Program and Data spaces, these microcontrollers also have internal and external
Program and Data memory. The 8051/52 series of microcontrollers can have up to 8K of internal program
memory. Thus any program address in the range 0000h to 1FFFh is directed to internal Program memory.
Any other program address is directed externally. It is possible to direct all program access externally by
disabling internal program memory. This is done by connecting the /EA pin to ground. The 8031/32 series
have no internal program memory so all program access must be directed externally. The microcontrollers
running BASIC are 8052 series chips with the BASIC interpreter stored in internal program memory.
Program memory can only be read, not written to, The /PSEN signal is used as a read strobe for any external
program memory. Data memory occupies a separate address space from Program memory. The /RD and /WR
signals are used to access external Data memory as needed. Only Data memory can be written to and
programs can only run from Program memory!
It is possible to combine all or part of the Program and Data memory into one address space. This is done by
logically ORing the /PSEN and /RD signals with the decoded memory range required and using the resultant
output as a read strobe. Combining Program and Data memory is necessary on the Southern Cross II so that
users can download and run programs.
The Southern Cross II provides 16K of RAM memory that is accessible as both Program and Data memory.
This is the area of memory where user programs are downloaded into and executed from. The other 16K of
RAM is accessible as Data memory only.
The EPROM can be an 8K, 16K or 32K type. The EPROM address space is split, with 16K located at 0000h
and the other 16K located at 8000h. The 16K block at 8000h is used to store BASIC programs when the
Southern Cross II is used as a BASIC computer! Refer to the "BASIC-52 Programming" reference manuals
for more information.
All external I/O devices such as the SPI and PPI chips are located in external data memory. Remember that
only data memory can be written to!
Figure 1 gives an overall picture of the Southern Cross II memory map.
Memory and I/O decoding is provided via two programmable logic devices (GALs). Using GALs for address
mapping adds great flexibility to the circuit design as well as significantly reducing chip count. Other memory
and I/O address mapping schemes are possible by re-programming the GALs.
Contact DIY Electronics for further information.
External External
Program Data
Memory Memory
0000h EPROM 0000h
( MVS-31 ) RAM
2000h EPROM
4000h
Common RAM
program and ⇒
data space OPTIONAL CLOCK/CALENDAR( See text ) 7FFFh
8000h 8000h
EPROM
C000h
SPI F000h
VACANT PPI F400h
I/O EXPANSION F800h
BIT PORT 1 FC00h
BIT PORT 2 FD00h
BIT PORT 3 FE00h
BIT PORT 4 FF00h
Fig 1
Serial Ports
These are implemented as simple "3-wire" interfaces, using just TxD, RxD and GND. The modem control
lines "CTS, DSR and DCD" are held at the RS-232 "ON" level and do not provide any hardware
handshaking. No software handshaking protocol is used either.
The Southern Cross II has two serial ports.
1. Uses the internal serial port of the 8032/52 chip and is referred to as the "USER" port. Connection is via
the 10-pin header labelled J6.
2. Uses an external SC2691 UART chip from Philips Components and is referred to as the "HOST" port.
Connection is via the 10-pin header labelled J5
The RS-232 signals are brought out to standard D9 connectors by using a 10-way flat ribbon cable. One end
is terminated with a 10-pin IDC plug and the other end with a crimp-style female D9 connector. By
connecting pin 1 on the 10-pin plug with pin 1 on the D9 connectors, the signals will be in the correct
positions to allow a "straight-through" connection to a D9-type PC COM port.
RS-232 Interface - J5, J6

Signal J5, J6 pin D9 pin
TxD 3 2
RxD 5 3
CTS 6 8
DSR 2 6
GND 9 5
DCD 1 1
Parallel I/O Ports
A number of parallel I/O ports are provided. Some are "static" in operation, meaning that any data written to
the port is latched. The other ports are "dynamic" in nature. These ports do not latch data written to them.
Output data is only valid while the port is being addressed. These ports are referred to as "bit ports".
8031 I/O ports - J1

The 8051 family of microcontrollers have four inbuilt 8-bit parallel ports, labelled P0-3. Two of these ports,
P0 and P2, are used as address/data busses when external program and data memory access is required. This
is the mode in which the Southern Cross II operates. Port bits P3.6 and P3.7 are used as /RD and /WR signals
and therefore are not available for use as I/O lines. This leaves 13 I/O lines available for use, all of port 1 and
bits 0-5 of port 3. Note that port bits P3.0 - P3.5 all have secondary functions eg. P3.0 and P3.1 are the Rx
and Tx lines for the 8031 serial port.
These 13 I/O lines are brought out to a 16-pin header labelled J1.
J1 pin Signal J1 pin Signal

1 P1.0 2 P1.1
3 P1.2 4 P1.3
5 P1.4 6 P1.5
7 P1.6 8 P1.7
9 P3.0 / RxD 10 P3.1 / TxD
11 P3.2 / INT0 12 P3.3 / INT1
13 P3.4 / T0 14 P3.5 / T1
15 GND 16 GND
Port bits P1.3, P1.4 ans P1.5 also have a secondary function. They are connected via switch SW2 to the
memory decoder GAL, IC9, and used by the 8052-BASIC chips as EPROM programming control pins. These
pins are only needed by BASIC-52 when programs are to be saved into EPROM. Refer to the section on
"BASIC-52 Programming" for further details.
8255 I/O Ports - J2

Three 8-bit parallel ports are implemented using the 8255 Programmable Peripheral Interface (PPI) chip
(IC6). This chip is mapped in external data memory at address F400h. These 24 I/O lines are brought out to a
26-pin header labelled J2.

1 PA0 2 PA1
3 PA2 4 PA3
5 PA4 6 PA5
7 PA6 8 PA7
9 PB0 10 PB1
11 PB2 12 PB3
13 PB4 14 PB5
15 PB6 16 PB7
17 PC0 18 PC1
19 PC2 20 PC3
21 PC4 22 PC5
23 PC6 24 PC7
25 GND 26 GND
Bit Ports - J4
As mentioned previously, these are "dynamic" not static ports. With referrence to sheet 2 of the schematic
diagram, the 8 I/O lines are actually driven by the data bus (BAD0 - 7). The ports are formed by decoding a
256 byte memory block and using the resulting output as an active low strobe, similar to the chip enable
signals for the EPROM and RAM chips. These 4 bit ports are mapped in external data memory at the
following address locations:
Bit port 1 FC00h

Bit port 2 FD00h
Bit port 3 FE00h
Bit port 4 FF00h
Although each port is mapped into a 256 byte block, it is only one address "wide". Therefore bit port 1 can
be accessed at address FC00h, FC01h, FC02h ... etc right through to FCFFh. These ports are both input and
output ports, depending on the instruction used to access them.
These ports are pin for pin compatible to the CN1 port on the Z80 based "Southern Cross" computer, also
available from DIY Electronics. It is provided on the Southern Cross II to take advantage of a number of add-
on boards already available for the "Southern Cross" computer.
The bit ports are brought out to a 16-pin header labelled J4.

1 +5V 2 /RESET
3 /BIT PORT 1 4 /BIT PORT 2
5 /BIT PORT 3 6 /BIT PORT 4
7 GND 8 GND
9 BAD4 10 BAD3
11 BAD5 12 BAD2
13 BAD6 14 BAD1
15 BAD7 16 BAD0
I/O Expansion Interface - J3

A maximum of 256 bytes of I/O expansion is available via connector J3. This interface allows for further
devices to be connected to the microcontroller. The interface is mapped in external data memory beginning at
address location F800h.

1 A0 2 A1
3 A2 4 A3
5 A4 6 A5
7 A6 8 A7
9 AD0 10 AD1
11 AD2 12 AD3
13 AD4 14 AD5
15 AD6 16 AD7
17 /RD 18 /WR
19 RESET 20 ALE
21 /IOEXP 22
23 +5V 24 +5V
25 GND 26 GND
Signals preceeded by " / " are active low, all other signals are active high.
The signal " /IOEXP " is the block decode signal for the expansion interface and should be used in
conjunction with address lines A0-A7 to provide further address decoding.
Address lines A0-A7 have already been de-mulitplexed on the Southern Cross II board ie. they are actually
address lines. This allows devices with separate address and data lines to be connected to the expansion
interface directly. For those devices with a multiplexed address/data bus use signals AD0-AD7 and ALE.
Clock/Calendar
An optional clock/calendar device is available for the Southern Cross II, a Dallas Semiconductor DS1216C
Intelligent Socket. Access to this clock/calendar is provided in the MVS-31 debugging monitor.
The DS1216C contains an internal lithium battery. This keeps the clock going during power down and also
makes the CMOS RAM non-volatile ie. no loss of data when power to the Southern Cross II is removed.
Battery life is over 10 years. No circuit modifications are necessary to use the DS1216C, just plug it in
between the RAM chip and the IC socket (or solder directly to the PCB if purchased with the Southern Cross
II kit).
BASIC-52 Programming
As mentioned, the Southern Cross II board is capable of being programmed in BASIC. A number of
suppliers, such as Intel and Micromint Inc., have available an 8052 microcontroller with a BASIC interpreter
programmed into the chip's internal EPROM. The Southern Cross II needs one of these chips installed as IC1
in order run the BASIC-52 language.
BASIC-52 has the ability to store its programs into an external memory device such as EPROM.
Programming EPROMs requires a voltage level of between 12.5 and 25 volts ( depending on the EPROM ).
The Southern Cross II generates this programming voltage using a DC-DC converter chip, IC12.
The Southern Cross II is designed to use a 27256 EPROM for storing BASIC programs. These EPROMs
require a programming voltage of 12.5 volts. Before attempting to save any programs in EPROM, the
programming voltage must be set to this level. This is done by measuring the voltage on test pin TP1 and
adjusting trimpot VR1 for 12.5 volts. This procedure is only required once. However it is worth checking this
voltage periodically or whenever any problems occur with saving programs to EPROM.
The Southern Cross II only uses 27256 EPROMs for saving BASIC programs. Remove the MVS-31 monitor
EPROM and install a 27256 type in its place. The MVS-31 monitor can reside on the same 27256 EPROM
used to save BASIC programs. The monitor would reside in the bottom 8K starting at address 0000h whereas
BASIC programs are saved at address locations 8000h upwards, which is in the upper 16K of the EPROM.
The memory decoder GAL, IC9, splits the EPROM into two halves, with one half starting at 0000h and the
other half starting at 8000h. Remember to set jumper JP2 to the correct EPROM type. A number of BASIC-
52 programming and startup options are also available. Refer to the BASIC-52 reference manual for further
details.
BASIC-52 uses port bits P1.3, P1,4 and P1.5 as EPROM programming control lines. The function of these
lines is:
P1.3 ALE Disable
P1.4 Program pulse width
P1.5 Enable program voltage
These signals are not connected directly to the EPROM or associated programming circuitry. Instead they are
connected via switch SW2 and the memory decoder GAL, IC9. When the GAL detects a low on its pin 5, it
uses these port bits to control the output signals " /ROM_CE, SYS_ALE and /VPP_CONT ". Moving SW2 to
the " ON " position connects the port bits to the GAL and pulls pin 5 low, ready for EPROM programming.
These port bits can also be used as general purpose I/O lines and are brought out on connector J1. These pins
MUST be isolated from any external voltage levels. This would be the case if any of these pins were inputs
being "driven" from a device connected to J1. Therefore, it is advisable before saving programs to EPROM to
disconnect any device from J1.
To summarize, the following steps must be carried out before issuing a BASIC-52 programming command.
1. Disconnect any device attached to connector J1.

2. Move switch SW2 to the " ON " position.
Whilst the MVS-31 monitor program and BASIC programs can be stored on the same 27256 EPROM it is
advisable to use two separate EPROMs. If you wish to keep them together then make a copy of the MVS-31
EPROM and use the copy instead. The MVS-31 binary file is on the disk supplied with the Southern Cross II
computer.
References
The hardware & software for the Southern Cross 2 were developed by Frank Crivelli for DIY Electronics.
Frank can be contacted at [email protected]
The following web sites contain 80xx code & material

http://www.lvr.com
http://livewire.ee.latrobe.edu/~sjm
http://cera2.com/gatox805.htm
http://www.atmel.com
Southern Cross II - REGISTRATION
Question: Why Register?

Answer: So that you can be notified when new hardware and software becomes
available. The Southern Cross II will be supported in the future with new
hardware, software and documentation.
Please fill in the form below and return to:
DIY ELECTRONICS (HK) LTD

PO BOX 88458
SHAM SHUI PO
HONG KONG
or fax to (852) 2725-0610.
Your comments about the Southern Cross II are most welcome.
Name
Address
Zip Country
MVS-31 Disk size for 360K 1.2M 720K 1.44M

Version & Date software updates?
Comments:
CIRCUIT IDEAS
MULTI-SWITCH DOORBELL
WITH INDICATORS S.C.
DWI
VED
I
T.K. HAREENDRAN also pulled down by resistor R5. Clock in-

put (pin 5) of the quad D-latch is wired in
H
ere’s the circuit of a multi-switch normally low mode and hence all the four
input musical doorbell (shown in outputs (Q0 through Q3) have the same
Fig.1). The circuit is built around states as their corresponding data inputs.
the popular and less expensive quad As a result, LED1 through LED4 are in off Fig. 2: Suggested panel layout of musical
D-latch CD4042B (IC1). When switch S6 condition. doorbell
is pushed to ‘on’ condition, the circuit gets There are four switches fitted at four
+9V and the four data inputs (D1 through different doors/gates outside the home and switch S1 at door 1), pins 2 and 4 of IC1
D4) of ICI are in low state because these a monitoring panel (as shown in Fig. 2) in go high.
are tied to ground via resistors R1 through the common room of the home. If any Simultaneously, pin 3 to IC1 (Q0 out-
R4. Polarity input (POL) pin 6 of IC1 is switch is pressed by a visitor (for example, put) goes low and LED1 starts glowing to
indicate that switch
S1 is pressed by
someone.
Next, output pin
13 of the dual 4-in-
put NOR gate (IC2,
here wired as a
single 4-input OR
gate) goes high to
forward bias buzzer-
driver transistor T1
via resistor R10.
The final result is
a soft and pleasing
musical bell, which
lasts until reset
switch S5 is pressed
by the owner. For
this latching arrange-
ment , output pin 13
of IC2 from the NOR
gate is fed back to
the clock input of
IC1.
The circuit costs
Fig. 1: Multi-switch doorbell with indicators around Rs 100.
ELECTRONICS FOR YOU APRIL 2003

CIRCUIT IDEAS
SONG NUMBER
DISPLAY SAN
I THE
O
PRABHASH K.P.
H
ere’s a circuit to display the song number in an audio
system for quick reference to songs. It also serves the
purpose of an extra visual indicator in modern audio
systems.
When the power is switched on, the power-on-reset cir-
cuit comprising 3.3k resistor R20 and 1µF, 25V capacitor C6
resets the counters, showing ‘00’ in the display. One can also
reset the display to zero at any time by pressing reset switch
S1.
When the first song starts playing, the output pins of IC1
(KA2281) go low and capacitor C5 starts charging. This for-
ward biases transistor T1 and hence the input to IC3 at pin 1
goes to high state. As a result, the output of the counter goes
to the next state, showing 01 on the display. The counter
remains in this state until the song is completed.
During the time gap before the next song starts playing,
capacitor C5 discharges. After discharging of capacitor C5,
the input to IC3 becomes low again. When the song starts,
the process described above is repeated and the display shows
02. You can adjust VR3 to change the time gap setting. This
must be set such that the circuit doesn’t respond to short
gaps, if any, within a song and responds only to long gaps
between different songs.
Transistor T2 helps in gap-delay adjustment. The inten-
sity of LED11 diminishes when a song is completed and the
counter is ready to accept the next pulse.
Connect the input to the preamp output or equaliser out-
put of the audio system. Adjust VR1 and VR2 to get the
correct audio-level indication. If you are already using KA2281
for audio-level indication, just connect diodes D1 and D2 as
shown in this circuit.
Note that the counter counts the songs by detecting the
gaps. Therefore any long gap within a song may cause false
triggering and the display will also be incremented. However,
as this is very unlikely to happen, the circuit shows the
correct song number almost all the time.
The circuit costs around Rs 100.
APRIL 2003 ELECTRONICS FOR YOU

CIRCUIT IDEAS
FLASHING BEACON S.C.

DWI
VED
I
ASHOK K. DOCTOR the figure. The IC is pro-

vided with an aluminium
A
flashing beacon has many uses. It heat-sink to dissipate the
can be employed as a distress sig- heat generated while deliv-
nal on highways or as a direction ering full current. Since the
pointer for parking lots, hospitals, hotels, IC has an inbuilt switch-on
etc. Here we present a flashing beacon current limiter, it extends
that uses well-known regulator IC LM317T. the bulb life.
As LM317T regulator can deliver more than For the shown values
1 amp. A small 12V, 10W bulb with a of resistors and capacitors,
high-quality reflector can serve as a good the bulb flashes at approxi-
visible blinker. mately 4 cycles per second.
A 12-15V, 1A DC supply is connected The number of flashes de-
to the input pin of the IC. A 12V, 10W pends on the charge-dis-
bulb and a combination of resistors and charge time of the capaci-
capacitors are connected between the out- tors. Different values of resistors and ca- crease the number of flashes.
put pin and ADJ pin of the IC as shown in pacitors can be used to increase or de- This circuit costs around Rs 50.
NOVEMBER 2002 ELECTRONICS FOR YOU

CIRCUIT IDEAS
INTRUDER RADIO ALERT SYSTEM SUN

IL KU
MAR
DAVID NASH PIOUS
C
onsider a situation where a burglar
has entered your house and snapped
the telephone wires, leaving you
with no means of communication with the
outside world. In such an emergency, you
will find this intruder alarm to be very
handy. It transmits a prerecorded emer-
gency message repeatedly for reception by
an FM receiver.
The message containing address, geo-
graphical location, name, etc is recorded
onto a chip. The prerecorded message can
then be transmitted repeatedly with the
help of an FM transmitter, in the hope
that some noble soul will hear it and in-
form the police about the incident.
The circuit comprises a sound record-
ing-and-playback chip (UM5506BH). This
chip consists of a 96kbit SRAM and can
record up to six seconds of audio. (For
details, refer ‘Mini Voice Processor’ circuit
published in April 2000 issue of EFY.) Af-
ter the required message has been re-
corded, it is passed to a low-power, VHF
FM transmitter wired around BC547 and
2N2369 transistors. The range of this trans- Fig. 2: Circuit diagram of intruder radio alert system
mitter is 60 to 100 The transmitted message can be heard over

metres using a 40-70cm the FM receiver.
long wire as an antenna. A possible modification, though it has
The major advantage legal complications, is to vary the coil in-
of this circuit is its low ductance such that the transmission is on
power consumption. The police band, thus alerting the police for
author operated it on 3V quick help. Even the need of repeatedly
button cells (Maxell CR pressing play button can be obviated by
2032, CR 2025, etc used configuring an astable multiviberator (us-
in digital diaries). To ing IC 555 timer) to trigger IC UM5506BH
transmit the prerecorded every six seconds so that the message is
message, the play but- played repeatedly.
Fig. 1: Block diagram of the intruder radio alert system ton is pressed repeatedly. This circuit costs around Rs 200.
DECEMBER 2002 ELECTRONICS FOR YOU

CIRCUIT IDEAS
AUTOMATED TRAFFIC SIGNAL RUP

ANJA
NA
CONTROLLER
VIKRAM BANERJEE sity is high. This controller allows the pe- of 8 seconds each. For the left- and right-
MRINAL KANTI MANDAL destrians to safely cross the road during turning traffic and pedestrians crossing
DR ANIRUDHA GHOSAL certain periods. from north to south, south to north, east
3. The controller uses digital logic, to west, and west to east, only green and
T
his automated traffic signal control- which can be easily implemented by us- red signals are used.
ler can be made by suitably pro- ing logic gates. Table I shows the simultaneous states
gramming a GAL device. (For GAL 4. The controller is a generalised one of the signals for all the traffic. Each row
programming you may refer to the con- and can be used for different roads with represents the status of a signal for 8
Fig. 1: Flow of traffic in all possible directions
TABLE I
Simultaneous States of Signals for All the Traffic
X Y Z B-C/B-G B-E D-E/D-A D-G F-G/F-C F-A H-A/H-E HC WALK WALK
Lt/Rt St Lt/Rt St Lt/Rt St Lt/Rt St (N-S)/(S-N) (E-W)/(W-E)
0 0 0 R R R R G G R R R R
0 0 1 R G R R R G R R G R
0 1 0 R G R R R Y R R G R
0 1 1 G Y R R R R R R R R
1 0 0 R R R R R R G G R R
1 0 1 R R R G R R R G R G
1 1 0 R R R G R R R Y R G
1 1 1 R R G Y R R R R R R
struction project published on page 52 in slight modification. seconds. As can be observed from the
EFY’s September issue.) Its main features 5. The control can also be exercised table, the ratio of green, yellow, and red
are: manually when desired. signals is 16:8:40 (=2:1:5) for the straight
1. The controller assumes equal traffic The time period for which green, yel- moving traffic. For the turning traffic the
density on all the roads. low, and red traffic signals remain ‘on’ ratio of green and red signals is 8:56
2. In most automated traffic signals the (and then repeat) for the straight moving (=1:7), while for pedestrians crossing the
free left-turn condition is provided through- traffic is divided into eight units of 8 road the ratio of green and red signals is
out the entire signal period, which poses seconds (or multiples thereof) each. Fig. 16:48 (=2:6).
difficulties to the pedestrians in crossing 1 shows the flow of traffic in all permis- In Table II (as well as Table I) X, Y,
the road, especially when the traffic den- sible directions during the eight time units and Z are used as binary variables to

CIRCUIT IDEAS
TABLE II depict the eight states of 8 trol output.

Boolean Functions for All the Signal Conditions seconds each. Letters A The circuit diagram for realising these
Signal Reference Boolean functions through H indicate the left Boolean functions is shown in Fig. 2.
and right halves of the roads Timer 555 (IC1) is wired as an astable
Green B-C(Lt)/B-G (Rt) X’YZ
in four directions as shown multivibrator to generate clock signal for
Green B-E (St) XYZ’+X’Y’Z
in Fig. 1. Two letters with a the 4-bit counter 74160 (IC2). The time
Red B-E (St) X+Y’Y’Z’ dash in between indicate the duration of IC1 can be adjusted by vary-
Yellow B-E (St) X’YZ direction of permissible ing the value of resistor R1, resistor R2,
Green D-E (Lt)/D-A (Rt) XYZ
movement from a road. or capacitor C2 of the clock circuit. The
Green D-G (St) XYZ’+XY’Z
Straight direction is indicated ‘on’ time duration T is given by the fol-
Red D-G (St) X’+XY’Z’
by St, while left and right lowing relationship:
Yellow D-G (St) XYZ
turns are indicated by Lt and T = 0.695C2(R1+R2)
Green F-G(Lt)/F-C (Rt) X’Y’Z’ Rt, respectively. IC2 is wired as a 3-bit binary counter
Green F-A (St) X’Y’ The Boolean functions by connecting its Q3 output to reset pin 1
Red F-A (St) X+X’YZ
for all the signal conditions via inverter N1. Binary outputs Q2, Q1,
Yellow F-A (St) X’YZ’
are shown in Table II. and Q0 form variables X, Y, and Z, re-
Green H-A (Lt)/H-E (Rt) XY’Z’
The left- and the right-turn spectively. These outputs, along with their
Green H-C (St) XY’
signals for the traffic have complimentary outputs X’, Y’, and Z’,
Red H-C (St) X’+XYZ the same state, i.e. both are respectively, are used as inputs to the rest
Yellow H-C (St) XYZ’ red or green for the same of the logic circuit to realise various out-
Green Walk (N-S/S-N) X’YZ’+X’Y’Z
duration, so their Boolean puts satisfying Table I.
Green Walk (E-W/W-E) XYZ’+XY’Z
functions are identical and You can simulate various traffic lights
Note. X’, Y’, and Z’ denote complements of variables X, Y,
they should be using green, yellow, and red LEDs and
and Z, respectively.
connected to the same con- feed the outputs of the circuit to respec-
tive LEDs via
current-limit-
ing resistors of
470 ohms each
to check the
working of the
circuit. Here,
for turning traf-
fic and pedes-
trians crossing
the road, only
green signal is
made avail-
able. It means
that for the re-
maining period
these signals
have to be
treated as ‘red’.
In practice,
the outputs of
Fig. 2 should
be connected
to solidstate re-
lays to operate
high-power
bulbs. Further,
if a particular
signal condi-
tion (such as
turning signal)
is not appli-
cable to a
given road, the
output of that
signal condi-
Fig. 2: The circuit diagram for traffic light signalling tion should be
ELECTRONICS FOR YOU NOVEMBER 2002

CIRCUIT IDEAS
Table III connected by entering the binary value correspond-

Execution Results of Software Program to green ing to that particular state into the parallel
signal of input pins of the 3-bit counter. Similarly,
SIG-B SIG-D SIF-F SIG-H WALK(N-S) WALK(E-W)
the next the signal can be reset at any time by
GGRY GGRY GGRY GGRY GR GR state (refer providing logic 0 at the reset pin (pin 1)
0010 0100 1100 0010 01 01 Table I). of the counter using an external switch.
0100 0100 0100 0010 10 01 T h e A software program to verify the
0100 0100 0001 0010 10 01 traffic sig- functioning of the circuit using a PC
1001 0100 0010 0010 01 01 nals can is given below. (Source code and execut-
0010 0100 0010 1100 01 01 also be able file will be provided in the next
0010 1000 0010 0100 01 10 controlled month’s EFY-CD.) When executing the pro-
0010 1000 0010 0001 01 10 manually, gram, keep pressing Enter key to get the
0010 0011 0010 0010 01 01 if desired. next row of results. The test results on
Note. The first column under G (green) in each group of four signals indicates the Any signal execution of the program is shown in Table
turn signal, while the next three columns under GRY indicate signal for the straight state can be III.
traffic. established This circuit costs around Rs 125.
TRAFFIC.C
#include<stdio.h> c=(seq&1);b=(seq&2)>>1;a=(seq&4)>>2; walk_ns,stop_ns,

#include<conio.h> green_bl=and3(not(a),b,c); walk_ew,stop_ew);
#define TRUE 1 green_bs=or2(and3(not(a),b,not(c)),and3(not(a),not(b),c)); getch();
#define False 0 red_bs=or2(a,and3(not(a),not(b),not(c))); }
yellow_bs=and3(not(a),b,c); return;
int not(int x); green_dl=and3(a,b,c); }
int or2(int x,int y); green_ds=or2(and3(a,b,not(c)),and3(a,not(b),c)); int and2(int x,int y)
int or3(int x,int y,int z); red_ds=or2(not(a),and3(a,not(b),not(c))); {
int and2(int x,int y); yellow_ds=and3(a,b,c); return(x && y);
int and3(int x,int y,int z); green_fl=and3(not(a),not(b),not(c)); }
int main(void) green_fs=and2(not(a),not(b)); int and3(int x,int y,int z)
{ red_fs=or2(a,and3(not(a),b,c)); {
int a,b,c; yellow_fs=and3(not(a),b,not(c)); return(x && y && z);
int seq,green_bl,green_bs,red_bs,yellow_bs; green_hl=and3(a,not(b),not(c)); }
int green_dl,green_ds,red_ds,yellow_ds; green_hs=and2(a,not(b)); int or2(int x,int y)
int green_fl,green_fs,red_fs,yellow_fs; red_hs=or2(not(a),and3(a,b,c)); {
int green_hl,green_hs,red_hs,yellow_hs; yellow_hs=and3(a,b,not(c)); return(x || y);
int walk_ns,stop_ns; walk_ns=green_bs; }
int walk_ew,stop_ew; stop_ns=or3(and3(not(a),not(b),not(c)),and3(not(a),b,c),a); int or3(int x,int y,int z)
walk_ew=green_ds; {
clrscr(); stop_ew=or3(not(a),and3(a,b,c),and3(a,not(b),not(c))); return(x || y || z);
printf(“ SIG-B SIG-D SIF-F SIG-H printf(“%d %d %d %d %d %d %d %d }
WALK(N-S) WALK(E-W)\n”); %d %d %d %d %d %d %d %d %d %d int not(int x)
printf(“G G R Y G G R Y G G R Y G G R Y %d %d\n”, {
GR G R\n”); green_bl,green_bs,red_bs,yellow_bs, return(!x);
green_dl,green_ds,red_ds,yellow_ds, }
for(seq=0;seq<8;seq++) green_fl,green_fs,red_fs,yellow_fs,
{ green_hl,green_hs,red_hs,yellow_hs,

CIRCUIT IDEAS
INFRARED TOY CAR SAN

I THE
O
MOTOR CONTROLLER
T.K. HAREENDRAN
T
his add-on circuit enables remote depressed again, the monostable is example, behind the front glass, and con-
switching on/off of battery-operated retriggered to reset decade counter IC2 and nect its wires to the circuit board using a
toy cars with the help of a TV/ the motor is switched off. Standby LED1 short 3-core ribbon cable/shielded wire.
video remote control handset operating at glows again. Note. Since the circuit uses modu-
30–40 kHz.
When the circuit is energised
from a 6V battery, the decade
counter CD4017 (IC2), which is
configured as a toggle flip-flop, is
immediately reset by the power-on-
reset combination of capacitor C3
and resistor R6. LED1 connected
to pin 3 (Q0) of IC2 via resistor R5
glows to indicate the standby con-
dition. In standby condition, data
output pin of the integrated infra-
red receiver/demodulator
(SFH505A or TSOP1738) is at a
high level (about 5 volts) and tran-
sistor T1 is ‘off’ (reverse biased).
The monostable wired around IC1
is inactive in this condition.
When any key on the remote
control handset is depressed, the
output of the IR receiver momen-
tarily transits through low state and
transistor T1 conducts. As a result,
the monostable is triggered and a
short pulse is applied to the clock
input (pin 14) of IC2, which takes Q1 out- This circuit can be easily fabricated on lated infrared beam for control function,
put (pin 2) of IC2 high to switch on motor a general-purpose printed board. After con- ambient light reflections will not affect the
driver transistor T2 via base bias resistor struction, enclose it inside the toy car and circuit operation. However, fluorescent
R7 and the motor starts rotating connect the supply wires to the battery of tubelights with electronic ballasts and CFL
continously (car starts running). Resistor the toy car with right polarity. Rewire the lamps may cause malfunctioning of the
R8 limits the starting current. DC motor connections and fix the IR re- circuit.
When any key on the handset is ceiver module in a suitable location, for
JULY 2002 ELECTRONICS FOR YOU

CIRCUIT IDEAS
ANTI-THEFT SECURITY mately 5 seconds as ‘on’ and 5 seconds as

‘off’ time.
Gate N4, with its associated compo-
FOR CAR AUDIOS S.C.

DWIV
EDI nents, forms a self-testing circuit. Nor-
mally, both of its inputs are in ‘high’ state.
However, when one switches off the igni-
tion key, the supply to the car audio is
T.K. HAREENDRAN also disconnected. Thus the output of gate
N4 jumps to a ‘high’ state and it provides
T
his small circuit, based on popu- Whenever an attempt is made to re- a differentiated short pulse to forward bias
lar CMOS NAND chip CD4093, move the car audio from its mounting by transistor T1 for a short duration. (The
can be effectively used for protect- cutting its connecting wires, the combination of capacitor C1 and resistor
ing your expensive car audio system optocoupler immediately turns off, as its R5 acts as the differentiating circuit.)
against theft. LED cathode terminal is hanging. As a As a result, buzzer in the collector
When 12V DC from the car battery is result, the oscillator circuit built around terminal of T1 beeps for a short duration
to announce that
the security cir-
cuit is intact.
This ‘on’ period
of buzzer can be
varied by chang-
ing the values of
capacitor C1
and/or resistor
R5.
After con-
struction, fix the
LED and buzzer
in dashboard as
per your re-
quirement and
hide switch S1
applied to the gadget (as indicated by gates N2 and N3 is enabled and it con- in a suitable location. Then connect lead
LED1) through switch S1, the circuit goes trols the ‘on’/‘off’ timings of the relay via A to the body of car stereo (not to the
into standby mode. LED inside transistor T2. (Relay contacts can be used body of vehicle) and lead B to its positive
optocoupler IC1 is lit as its cathode ter- to energise an emergency beeper, indica- lead terminal. Take power supply for the
minal is grounded via the car audio (am- tor, car horns, etc, as desired.) circuit from the car battery directly.
plifier) body. As a result, the output at Different values of capacitor C2 give Caution. This design is meant for car
pin 3 of gate N1 goes low and disables different ‘on’/‘off’ timings for relay RL1 to audios with negative ground only.
the rest of the circuit. be ‘on’/‘off’. With 100µF we get approxi-
ELECTRONICS FOR YOU ❚ JULY 2001

CIRCUIT IDEAS
SIMPLE TELEPHONE IL KU
MAR
caded in such a way that the positive volt-
age available at the emitter of transistor
RING TONE GENERATOR

SUN
T1 is extended to the collector of transis-
tor T3 when the outputs of all the three
stages are low. As a result, transistors
K. UDHAYA KUMARAN, VU3GTH T1 through T3 are forward biased for 0.4,
1.6, and 0.025 seconds, respectively and
H
ere is a simple telephone ring tor (CMOS IC CD4060B) is used to gen- reverse biased for similar durations.
tone generator circuit designed erate three types of pulses, which are Using a built-in oscillator-type piezo-
using only a few components. It available from pin 1 (O11), pin 3 (O13), and buzzer produces around 1kHz tone. In this
produces simulated telephone ring tone pin 14 (O7), respectively. Preset VR1 is circuit, the piezo-buzzer is turned ‘on’ and
and needs only DC voltage (4.5V DC to adjusted to obtain 0.3125Hz pulses (1.6- ‘off’ at 20 Hz for ring tone sound by tran-
12V DC). One may use this circuit in or- second ‘low’ followed by 1.6-second ‘high’) sistor T3. 20Hz pulses are available at
dinary intercom or phone-type intercom. at pin 3 of IC1. At the same time, pulses the collector of transistor T3 for 0.4-sec-
available from pin 1 will be of 1.25 Hz ond duration. After a time interval of 0.4
second, 20Hz
pulses become
again avail-
able for an-
other 0.4-sec-
ond duration.
This is fol-
lowed by two
seconds of no-
sound inter-
val. Thereaf-
ter the pulse
pattern re-
The sound is quite loud when this circuit (0.4-second ‘low’, 0.4-second ‘high’) and 20 peats itself.
is operated on +12V DC power supply. Hz at pin 14. The three output pins of Refer the figure that indicates wave-
However, the volume of ring sound is ad- IC1 are connected to base terminals of forms available at various points includ-
justable. transistors T1, T2, and T3 through resis- ing the collector of transistor T3. Preset
The commonly available 14-stage bi- tors R1, R2, and R3, respectively. VR2 can be used for adjusting the ampli-
nary ripple counter with built-in oscilla- Transistors T1 through T3 are cas- tude of the ring tone.
ELECTRONICS FOR YOU ❚ JULY 2001

CIRCUIT IDEAS
DTMF PROXIMITY DETECTOR

NA from an object, falls on photodetector di-
K.S. SANKAR ANJA
RUP ode D1. (The photodetector is to be
shielded from direct IR light transmis-
sion path of IR LED1 by using any opaque
A
DTMF-based IR transmitter and column 1 (pin 12) get connected together partition so that it receives only the re-
receiver pair can be used to realise via transistor T2 after a power-on delay flected IR light.) On detection of the sig-
a proximity detector. The circuit (determined by capacitor C1 and resis- nal by photodetector, it is coupled to
presented here enables you to detect any tors R1 and R16 in the base circuit of the DTMF decoder IC2 through emitter-fol-
object capable of reflecting the IR beam transistor) to generate DTMF tone (com- lower transistor T1.
and moving in front of the IR LED photo- bination of 697 Hz and 1209 Hz) corre- When the valid tone pair is detected
detector pair up to a distance of about 12 sponding to keypad digit “1” continuously. by the decoder, its StD pin 15 (shorted to
cm from it. LED 2 is used to indicate the tone TOE pin 10) goes ‘high’. The detection of
The circuit uses the commonly avail- output from IC3. This tone output is am- the object in proximity of IR transmitter-
able telephony ICs such as dial-tone gen- plified by Darlington transistor pair of T3 receiver combination is indicated by
erator 91214B/91215B (IC1) and DTMF and T4 to drive IR LED1 via variable re- LED1. The active-high logic output pulse
decoder CM8870 (IC2) in conjunction with sistor VR1 in series with fixed 10-ohm (terminated at connector CON1, in the
infrared LED (IR LED1), photodiode D1, resistor R14. Thus IR LED1 produces figure) can be used to switch on/off any
and other components as shown in the tone-modulated IR light. Variable resis- device (such as a siren via a latch and
figure. A properly regulated 5V DC power tor VR1 controls the emission level to vary relay driver) or it can be used to clock a
supply is required for operation of the cir- the transmission range. LED 3 indicates counter, etc.
cuit. that transmission is taking place. This DTMF proximity detector finds
The transmitter part is configured A part of modulated IR light signal applications in burglar alarms, object
around dialer IC1. Its row 1 (pin 15) and transmitted by IR LED1, after reflection counter and tachometers, etc.
ELECTRONICS FOR YOU ❚ JUNE 2001

CIRCUIT IDEAS
UNDER-/OVER-VOLTAGE BEEP used to sense high or low voltage in this

circuit.
FOR MANUAL STABILISER IL KU

MAR
Transistor T1 in conjunction with ze-
ner diode ZD1 and preset VR1 is used to
sense and adjust the high-voltage level
SUN for beep indication. Similarly, transistor
K. UDHAYA KUMARAN
T2 along with zener ZD2 and preset VR2
is used to sense and adjust low voltage
M
anual stabilisers are still popu- eration is very irritating and inconvenient level for beep indication.
lar because of their simple con- for the user. When the DC voltage across capaci-
struction, low cost, and high re- This under-/over-voltage audio alarm tor C1 rises above the preset high-level
liability due to the absence of any relays circuit designed as an add-on circuit for voltage or falls below the preset low-level
while covering a wide range of mains AC the existing manual stabilisers overcomes voltage, the collector of transistor T2 be-
voltages compared to that handled by au- the above problem. Whenever the comes high due to non-conduction of tran-
tomatic voltage stabilisers. These are used stabiliser’s output voltage falls below a sistor T2, in either case. However, if the
mostly in homes and in business centres preset low-level voltage or rises above a DC voltage sampled across C1 is within
for loads such as lighting, TV, and fridge, preset high-level voltage, it produces dif- the preset high- and low-level voltage,
and in certain areas where the mains AC ferent beep sounds for ‘high’ and ‘low’ volt- transistor T2 conducts and its collector
voltage fluctuates between very low (dur- age levels—short-duration beeps with voltage gets pulled to the ground level.
ing peak hours) and abnormally high (dur- short intervals between successive beeps These changes in the collector voltage of
ing non-peak hours). for ‘high’ voltage level and slightly longer- transistor T2 are used to start or stop
Some manual stabilisers available in duration beeps with longer interval be- oscillations in the astable multivibrator
the market incorporate the high-voltage tween successive beeps for ‘low’ voltage circuit that is built around transistors T3
and T4. The collector
of transistor T4 is con-
nected to the base of
buzzer driver transis-
tor T5 through resis-
tor R8. Thus when the
collector voltage of
transistor T4 goes
high, the buzzer
sounds. Preset VR3 is
used to control the
volume of buzzer
sound.
In normal condi-
auto-cut-off facility to turn off the load level. By using these two different types tion, the DC voltage sampled across ca-
when the output voltage of manual of beep sounds one can readily readjust pacitor C1 is within the permissible win-
stabiliser exceeds a certain preset high the stabiliser’s AC voltage output with the dow voltage zone. The base of transistor
voltage limit. The output voltage may be- help of the rotary switch. There is no need T3 is pulled low due to conduction of di-
come high due to the rise in AC mains of frequently checking voltmeter reading. ode D2 and transistor T2. As a result,
voltage or due to improper selection by It is advisable to preset the high-level capacitor C2 is discharged. The astable
the rotary switch on manual stabiliser. voltage 10V to 20V less than the required multivibrator stops oscillating and tran-
One of the major disadvantage of us- high-voltage limit for auto-cut-off opera- sistor T4 starts conducting because tran-
ing a manual stabiliser in areas with a tion. Similarly, for low level one may pre- sistor T3 is in cut-off state. No beep sound
wide range of voltage fluctuations is that set low-level AC voltage 20V to 30V above is heard in the buzzer due to conduction
one has to keep a watch on the manual minimum operating voltage for a given of transistor T4 and non-conduction of
stabiliser’s output voltage that is displayed load. transistor T5.
on a voltmeter and keep changing the The primary winding terminals of When the DC voltage across capaci-
same using its rotary switch. Or else, the step-down transformer X1 are connected tor C1 goes above or below the window
output voltage may reach the preset auto- to the output terminals of the manual voltage level, transistor T2 is cut off. Its
cut-off limit to switch off the load without stabiliser. Thus, 9V DC available across collector voltage goes high and diode D2
the user’s knowledge. To turn on the load capacitor C1 will vary in accordance with stops conducting. Thus there is no dis-
again, one has to readjust the stabiliser the voltage available at the output termi- charge path for capacitor C2 through di-
voltage using its rotary switch. Such op- nals of the manual stabiliser, which is ode D2. The astable multivibrator starts
ELECTRONICS FOR YOU ❚ MAY 2001

CIRCUIT IDEAS
oscillating. The time period for which the sampling. The time taken for charging longer duration with longer interval be-
beep is heard and the time interval be- capacitors C2 and C3 is less when the DC tween successive beeps compared to that
tween two successive beeps are achieved voltage is high and slightly greater when during high-voltage level sensing.
with the help of the DC supply voltage, the DC voltage is low for astable This circuit can be added to any ex-
which is low during low-level voltage sam- multivibrator operation. Thus during low- isting stabiliser (automatic or manual) or
pling and high during high-level voltage level voltage sensing the buzzer beeps for UPS to monitor its performance.

CIRCUIT IDEAS
15-STEP DIGITAL POWER SUPPLY

ing resistor across the relay contacts gets
connected to the circuit.
The table shows the theoretical out-
put for various digital input combinations.
NAVEEN THARIYAN NA The measured output is nearly equal to
ANJA
RUP the theoretically calculated output across
regulator IC3 (LM317). The output volt-
H
ere is a simple circuit to obtain down by closing switch S2. age is governed by the following relation-
variable DC voltage from 1.25V The output of counter IC2 is used to ship as long as the input-to-output differ-
to 15.19V in reasonably small realise a digitally variable resistor. This ential is greater than or equal to 2.5V:
steps as shown in the table. The input section consists of four N/O reed relays Vout = 1.25(1+R2'/R1')
voltage may lie anywhere between 20V that need just about 5mA current for their Where, R1' = R15 = 270 ohms (fixed)
and 35V.
The first section of the circuit com-
prises a digital up-down counter built
around IC1— a quad 2-input NAND
schmitt trigger (4093), followed by
IC2— a binary up-down counter (4029).
Two gates of IC 4093 are used to gen-
erate up-down logic using push but-
tons S1 and S2, respectively, while the
other two gates form an oscillator to
provide clock pulses to IC2 (4029). The
frequency of oscillations can be varied
by changing the value of capacitor C1
or preset VR1.
IC2 receives clock pulses from the os- operation. (EFY lab note. The original and R2' = R11 + R12 + R13 + R14
cillator and produces a sequential binary circuit containing quad bilateral switch = 220 + 470 + 820 +1500 ohms
output. As long as its pin 5 is low, the IC 4066 has been replaced by reed relays = 3,010 ohms (with all relays
counter continues to count at the rising operated by transistorised switches be- energised)
edge of each clock pulse, but stops count- cause of unreliable operation of the One can use either the binary
ing as soon as its pin 5 is brought to logic former.) The switching action is performed weighted LED display as indicated by
1. using BC548 transistors. External resis- LED1 through LED4 in the circuit or a
Logic 1 at pin 10 makes the counter tors are connected in parallel with the 74LS154 IC in conjunction with LED5
to count upwards, while logic 0 makes it reed relay contacts. If particular relay con- through LED20 to indicate one of the 16
count downwards. Therefore the counter tacts are opened by the control input at selected voltage steps of Table I. The in-
counts up by closing switch S1 and counts the base of a transistor, the correspond- put for IC4 is to be tapped from points

CIRCUIT IDEAS
TABLE sets itself, and hence the output at pins

Binary Equivalent LED4 LED3 LED2 LED1
6, 11, 14, and 12 is equivalent to binary
output dec no. R14 (W) R13 (W) R12 (W) R11 (W) R2' (W) Vout (V) zero, i.e. ‘0000’. The corresponding DC
0000 0 Shorted Shorted Shorted Shorted 0 1.25 output of the circuit is minimum (1.25V).
0001 1 Shorted Shorted Shorted 220 220 2.27 As count-up switch S1 is pressed, the
0010 2 Shorted Shorted 470 Shorted 470 3.43 binary count of IC2 increases and the
0011 3 Shorted Shorted 470 220 690 4.44 output starts increasing too. At the high-
0100 4 Shorted 820 Shorted Shorted 820 5.05
0101 5 Shorted 820 Shorted 220 1040 6.06 est count output of 1111, the output volt-
0110 6 Shorted 820 470 Shorted 1290 7.22 age is 15.19V (assuming the in-circuit re-
0111 7 Shorted 820 470 220 1510 8.24 sistance of preset VR2 as zero). Preset
1000 8 1500 Shorted Shorted Shorted 1500 8.19 VR2 can be used for trimming the output
1001 9 1500 Shorted Shorted 220 1720 9.21
1010 10 1500 Shorted 470 Shorted 1970 10.37
voltage as desired. To decrease the out-
1011 11 1500 Shorted 470 220 2190 11.39 put voltage within the range of 1.25V to
1100 12 1500 820 Shorted Shorted 2390 11.99 15.2V, count-down switch S2 is to be de-
1101 13 1500 820 Shorted 220 2540 13.01 pressed.
1110 14 1500 820 470 Shorted 2790 14.17
Notes. 1. When relay contacts across
1111 15 1500 820 470 220 3010 15.19
a particular resistor are opened, the cor-
marked ‘A’ through ‘D’ in the figure. This count value. LEDs at the output of this responding LED glows.
arrangement can be used to replace the IC can be arranged in a circular way along 2. The output voltages are shown as-
LED arrangement at points A, B, C, and side the corresponding voltages. suming the in-circuit resistance of preset
D. This 74LS154 IC is a decoder/ VR2 as zero. Thus when the in-circuit re-
demultiplexer that senses the output of sistance of preset VR2 is not zero, the
IC2 and accordingly activates only one of
Working output voltage will be higher than that
its 16 outputs in accordance with the When the power is switched on, IC2 re- indicated here.

CIRCUIT IDEAS
GENERATION OF 1-SEC. PULSES

ming of the 5-second and 1-second pulse
width of respective sections.
When switch S2 is in position ‘a’ and
switch S1 is pressed momentarily, the out-
SPACED 5-SEC. APART RUP

ANJA
NA
put at pin 5 goes high for about 5 sec-
onds. The trailing (falling) edge of this 5-
second pulse is used to trigger the second
timer via 0.1µF capacitor C6. This action
PRAVEEN SHANKER
results in momentarily pulling down of
pin 8 towards the ground potential, i.e.
T
his circuit using a dual-timer ing switch S1 momentarily ‘low’. (Otherwise pin 8 is at 1/2 Vcc and
NE556 can produce 1Hz pulses you can generate a single pulse of 5- triggers at/below 1/3 Vcc level.) When the
spaced 5 seconds apart, either second duration. When switch S2 is second timer is triggered at the trailing
manually or automatically. IC NE556 kept in ‘b’ position, i.e. pins 6 and 2 are edge of 5-second pulse, it generates a 1-
comprises two independent NE555 tim- shorted, timer 1 in NE556 triggers by second wide pulse.
ers in a single package. It is used to itself. When switch S2 is on position ‘b’,
produce two separate pulses of differ- The output of the first timer is con- switch S1 is disconnected, while pin 6 is
ent pulse widths, where one pulse nected to trigger pin 8 of second timer, connected to pin 2. When capacitor C is
initiates the activation of the second which, in turn, is connected to a poten- charged, it is discharged through pin 2
pulse. tial divider comprising resistors R4 and until it reaches 1/3Vcc potential, at which
The first half of the NE556 is wired R5. Resistor R1, preset VR1, resistor R2, it is retriggered since trigger pin 6 is
for 5-second pulse output. When slide preset VR2, and capacitors C2 and C5 also connected here. Thus timer 1 is
switch S2 is in position ‘a’, the first timer are the components determining time pe- retriggered after every 5-second period
is set for manual operation, i.e. by press- riod. Presets VR1 and VR2 permit trim- (corresponding to 0.2Hz frequency). The
second timer is triggered as before to
produce a 1-second pulse in synchro-
nism with the trailing edge of 5-sec-
ond pulse.
This circuit is important wherever
a pulse is needed at regular intervals;
for instance, in ‘Versatile Digital Fre-
quency Counter Cum Clock’ construc-
tion project published in EFY Oct. ’97,
one may use this circuit in place of
CD4060-based circuit. For the digital
clock function, however, pin 8 and 12
are to be shorted after removal of
0.1µF capacitor and 10-kilo-ohm resis-
tors R4 and R5.
ELECTRONICS FOR YOU ❚ FEBRUARY 2001

CIRCUIT IDEAS
AUTOMATIC HEAT DETECTOR IVEDI

lay is in energised state. LED1, con-
nected in series with 68-ohm resistor
R1 across resistor R4, glows when the
DW
SUKANT KUMAR BEHARA S.C. siren is on.
To test the working of the cir-
T
his circuit uses a complementary Pin Designation Sound Effect cuit, bring a burning matchstick
pair comprising npn metallic SEL1 SEL2 close to transistor T1 (BC109),
transistor T1 (BC109) and pnp No Connection No Connection Police Siren which causes the resistance of its
germanium transistor T2 (AC188) to de- +3V No Connection Fire Engine Siren emitter-collector junction to go low
tect heat (due to outbreak of fire, etc) Ground No Connection Ambulance Siren due to a rise in temperature and it
in the vicinity and energise a siren. The Do not care +3V Machine Gun starts conducting. Simultaneously,
collector of transistor T1 is connected transistor T2
to the base of transistor T2, while the also conducts be-
collector of transistor T2 is connected cause its base is
to relay RL1. connected to the
The second part of the circuit com- collector of tran-
prises popular IC UM3561 (a siren and sistor T1. As a
machine-gun sound generator IC), which result, relay RL1
can produce the sound of a fire-brigade energises and
siren. Pin numbers 5 and 6 of the IC switches on the
are connected to the +3V supply when siren circuit to
the relay is in energised state, whereas produce loud
pin 2 is grounded. A resistor (R2) con- sound of a fire-
nected across pins 7 and 8 is used to fix brigade siren.
the frequency of the inbuilt oscillator. Lab note.
The output is available from pin 3. We have added a
Two transistors BC147 (T3) and sound from UM3561. Resistor R4 in setable to enable readers to obtain all pos-
BEL187 (T4) are connected in ries with a 3V zener is used to provide sible sound effects by returning pins 1
Darlington configuration to amplify the the 3V supply to UM3561 when the re- and 2 as suggested in the table.
ELECTRONICS FOR YOU ❚ MARCH 2001

CIRCUIT IDEAS
MUSICAL TOUCH BELL S.C.

DWIV
EDI
ing. Simultaneously, the emitter-baser
junction of transistor BC558 also starts
conducting. As a result, the collector of
SUKANT KUMAR BEHARA transistor BC558 is pulled towards the
positive rail, which thus activates melody
H
ere is a musical call bell that The collector of BC558 is connected to generator IC1 (UM66). The output of
can be operated by just bridg- pin 2 of musical IC UM66, and pin 3 of IC1 is amplified by transistor BEL187
ing the gap between the touch- IC UM66 is shorted to the ground. The and fed to the speaker. So we hear a
plates with one’s fingertips. Thus there output from pin 1 is connected to a tran- musical note just by touching the touch
is no need for a mechanical ‘on’/‘off’ sistor amplifier comprising BEL187 points.
switch because the touch-plates act as transistor for feeding the loudspeaker. The washer’s inner diameter should
a switch. Other features include low cost One end of 2.2-mega-ohm resistor R1 be 1 to 2 mm greater than that of the
and low power consumption. The bell is connected to the positive rail and the screwhead. The washer could be fixed in
can work on 1.5V or 3V, using one or
two pencil cells, and can be used in
homes and offices.
Two transistors are used for sens-
ing the finger touch and switching
on a melody IC. Transistor BC148 is
npn type while transistor BC558 is pnp
type.
The emitter of transistor BC148 is
shorted to the ground, while that of other to a screw (as shown in the fig- the position by using an adhesive, while
transistor BC558 is connected to the ure). The complete circuit is connected the screw can be easily driven in a
positive terminal. The collector of tran- to a single pencil cell of 1.5V. wooden piece used for mounting the
sistor BC148 is connected to the base of When the touch-plate gap is bridged touch-plate. The use of brass washer and
BC558. The base of BC148 is connected with a finger, the emitter-collector junc- screw is recommended for easy solder-
to the washer (as shown in the figure). tion of transistor BC148 starts conduct- ability.
ELECTRONICS FOR YOU ❚ MARCH 2001

C I R C U I T I D E A S
PRECISION AMPLIFIER DWIV

EDI
Gains greater than 100 may not be
practical because even at gain value of
WITH DIGITAL CONTROL

S.C. 100 itself, a 100µV offset will work out
to be around 10 mV at the output (100µV
x 100). This can be trimmed using the
offset null option in the OP07, connect-
ANANTHA NARAYAN ing a trimpot between pins 1 and 8, and
connecting wiper to +5V supply rails.
T
his circuit is similar to the pre- puts are not loaded on measurement. For better performance, use ICL7650
ceding circuit of the attenuator. The user can terminate the inputs with (not pin-compatible) in place of OP07
Gain of up to 100 can be resistance of his choice (such as 10 meg- and use ±7.5V instead of ±5V supply.
achieved in this configuration, which is ohm or 1 meg-ohm) to avoid floating of Eight steps for gain or attenuation
useful for signal conditioning of low out- the inputs when no measurement is be- can be added by using two CD4051 and
put of transducers in millivolt range. ing made. pin 6 inhibit on CD4051/52. More steps
The gain selection resistors R3 to IC5 is used as an inverting buffer to can be added by cascading many
R6 can be selected by the user and restore polarity of the input while IC4 CD4051, or CD4052, or CD4053 ICs, as
can be anywhere from 1 kilo-ohm to 1 is used as buffer at the output of pin 6 works like a chip select.
meg-ohm. Trimpots can be used for ob- CD4052, because loading it by resistance Some extended applications of this
taining any value of gain required by of value less than 1 meg-ohm will cause circuit are given below.
the user. The resistor values shown in an error. An alternative is to make 1. Error correction in transducer
the circuit are for decade gains suitable R7=R8=1 meg-ohm and do away with amplifiers by correcting gain.
for an autoranging DPM. IC4, though this may not be an ideal 2. Autoranging in DMM.
Resistor R1 and capacitor C1 reduce method. 3. Sensor selection or input type se-
ripple in the input and also snub tran- lection in process control.
sients. Zeners Z1 and Z2 limit the input Truth Table (Control Input vs Gain) 4. Digitally preset power supplies or
to ±4.7V, while the input current is lim- X,Y (On-switch (2) (1) Gain electronic loads.
ited by resistor R1. Capacitors C2 and Pair) B A (Av.) 5. Programmable precision mV or
C3 are the power supply decoupling ca- X0,Y0 0 0 1/10 mA sources.
pacitors. X1,Y1 0 1 1 6. PC or microcontroller or micro-
Op-amp IC1 is used to increase the X2,Y2 1 0 10 processor based instruments.
X3,Y3 1 1 100
input impedance so that very low in- 7. Data loggers and scanners.
ELECTRONICS FOR YOU ❚ JANUARY 2001

C I RC ICR CUUII T
T I D E A S
IDEAS
counter IC. Since only one of its out-
puts is high at any instant, only one
ADD-ON STEREO CHANNEL

switch will be closed at a time. IC
CD4017 is configured as a 4-bit ring
counter by connecting the fifth output
SELECTOR
Q4 (pin 10) to the reset pin. Capacitor
RUPANJANA
C5 in conjunction with resistor R6 forms
a power-on-reset circuit for IC2, so that
on initial switching ‘on’ of the power
supply, output Q0 (pin 3) is always
PRABHASH K.P.
‘high’. The clock signal to CD4017 is pro-
vided by IC1 (NE555) which acts as an
T
he add-on circuit presented here channel A is selected, the audio from astable multivibrator when transistor
is useful for stereo systems. This the tape recorder will be present at the T1 is in cut-off state.
circuit has provision for connect- output. After the tape is played com- IC5 (KA2281) is used here for not
ing stereo outputs from four different pletely, or if there is sufficient pause only indicating the audio levels of the
sources/channels as inputs and only one between consecutive recordings, the cir- selected stereo channel, but also for for-
of them is selected/ connected to the cuit automatically switches over to the ward biasing transistor T1. As soon as
output at any one time. output from the radio receiver. To a specific threshold audio level is de-
When power supply is turned ‘on’, manually skip over from one (selected) tected in a selected channel, pin 7 and/
channel A (A2 and A1) is selected. If no active channel, simply push the skip or pin 10 of IC5 goes ‘low’. This low
audio is present in channel A, the cir- switch (S1) momentarily once or more, level is coupled to the base of transistor
cuit waits for some time and then se- until the desired channel inputs gets T1, through diode-resistor combination
lects the next channel (channel B), This selected. The selected channel (A, B, C, of D2-R1/D3-R22. As a result, transis-
search operation continues until it de- or D) is indicated by the glowing of cor- tor T1 conducts and causes output of
tects audio signal in one of the chan- responding LED (LED11, LED12, IC1 to remain ‘low’ (disabled) as long as
nels. The inter-channel wait or delay LED13, or LED14 respectively). the selected channel output exceeds the
time can be adjusted with the help of IC CD4066 contains four analogue preset audio threshold level.
preset VR1. If still longer time is switches. These switches are connected Presets VR2 and VR3 have been in-
needed, one may replace capacitor C1 to four separate channels. For stereo cluded for adjustment of individual au-
with a capacitor of higher value. operation, two similar CD4066 ICs are dio threshold levels of left stereo chan-
Suppose channel A is connected to used as shown in the circuit. These ana- nels, as desired. Once the multivibrator
a tape recorder and channel B is con- logue switches are controlled by IC action of IC1 is disabled, output of IC2
nected to a radio receiver. If initially CD4017 outputs. CD4017 is a 10-bit ring does not change further. Hence, search-
97
ing through the channels continues un- switch S1 is used to skip a channel even ily extended up to ten, by using addi-
til it receives an audio signal exceeding if audio is present in the selected chan- tional 4066 ICs.
the preset threshold value. The skip nel. The number of channels can be eas-
98
CIRCUIT IDEAS
Telephone Number R. R
AINA
Display
BHASKAR BANERJEE
T
he given circuit, when connected
in parallel to a telephone, dis-
plays the number dialled from
the telephone set using the DTMF mode.
This circuit can also show the number
dialled from the phone of the called
party. This is particularly helpful for
receiving any number over the phone
lines.
The DTMF signal—generated by the
phone on dialling a number—is decoded
by DTMF decoder CM8870P1 (IC1),
which converts the received DTMF sig-
nal into its equivalent BCD number that
corresponds to the dialled number. This
binary number is stored sequentially in
10 latches each time a number is dialled
from the phone. The first number is
stored in IC5A (1/2 of CD4508) while
the second number is stored in IC5B
and so on. The binary output from IC1
for digit ‘0’ as decoded by IC1 is 10102
(=1010), and this cannot be displayed by
the seven-segment decoder, IC10. There-
fore the binary output of IC1 is passed
through a logic-circuit which converts
an input of ‘10102’ into ‘00002’ without
affecting the inputs ‘1’ through ‘9’. This
is accomplished by gates N13 through
N15 (IC11) and N1 (IC12).
The storing of numbers in respec-
tive latches is done by IC2 (4017). The
data valid output from pin 15 of IC1 is
used to clock IC2. The ten outputs of
IC2 are sequentially connected to the
store and clear inputs of all the latches,
except the last one, where the clear in-
put is tied to ground. When an output
pin of IC2 is high, the corresponding
latch is cleared of previous data and
kept ready for storing new data. Then,
on clocking IC2, the same pin becomes
low and the data present at the inputs
of that latch at that instant gets stored
and the next latch is cleared and kept
ready. The similar input and output pins
of all latches are connected together to
ELECTRONICS FOR YOU n MAY '99

CIRCUIT IDEAS
form two separate input and output coding by IC10, gets displayed in the mum of ten digits, one can reduce the
buses. corresponding display. For instance, con- display digits as required. For doing
There is only one 7-segment decoder/ tents of IC5A are displayed on display this, connect the reset pin of IC2, say,
driver IC10 for all the ten displays. This ‘DIS1,’ that of IC5B on ‘DIS2’ and so for a 7-digit display, with S6 output at
not only reduces size and cost but re- on. The system should be connected to pin 5.
duces power requirement too. The out- the telephone lines via a DPDT switch The present circuit can be built on a
put from a latch is available only when (not shown) for manual switching, oth- veroboard and housed in a suitable box.
its disable pins (3 and 15) are brought erwise any circuit capable of sensing The displays are common-cathode type.
low. This is done by IC3, IC12 and IC13. handset’s off-hook condition and thereby To make the system compact, small, 7-
IC3 is clocked by an astable switching relays, etc. can be used for segment displays can be used but with
multivibrator IC4 (555). IC3 also drives automatic switching. The power-supply some extra cost. Also, different colour
the displays by switching correspond- switch can also be replaced then. Such displays can be used for the first three
ing transistors. When a latch is enabled, circuits, under different captions, can or four digits to separate the exchange
its corresponding display is turned on be found in EFY’s back issues. Though code/STD code, etc. The circuit can be
and the content of that latch, after de- this circuit is capable of showing a maxi- suitably adopted for calling-line display.
ELECTRONICS FOR YOU n MAY '99

CIRCUIT IDEAS
LUGGAGE SECURITY SYSTEM

DHURJATI SINHA EDI alarm sounds, connections to pin 1 and 6
DWIV
S.C. may be made as per the table.
Select 1 Select 2 Sound effect
W
hile travelling by a train or bus, sistor T1 gets forward biased to extend (Pin6) (Pin1)
we generally lock our luggage the positive supply to the alarm circuit. X X Police siren
using a chain-and-lock arrange- In idle mode, the power consumption of VDD X Fire-engine siren
ment. But, still we are under tension, ap- the circuit is minimum and thus it can be VSS X Ambulance siren
prehending that somebody may cut the used for hundreds of travel hours. “-” VDD Machine-gun sound
chain and steal our luggage. Here is a To enable generation of different Note: X = no connection; “-” = do not care
simple circuit to alarm you when
somebody tries to cut the chain.
Transistor T1 enables supply to
the sound generator chip when the
base current starts flowing through
it. When the wire (thin enameled
copper wire of 30 to 40 SWG, used
for winding transformers) loop
around the chain is broken by some-
body, the base of transistor T1,
which was earlier tied to positive
rail, gets opened. As a result, tran-
86
TABLE I
UNIVERSAL HIGH-RESISTANCE Position 1 of Function Switch

Edc input Meter Current
VOLTMETER
5.00V 44 µA
4.00V 34 µA
I 3.00V 24 µA
VED
DWI 2.00V 14 µA
S.C. 1.00V 4 µA
YOGESH KATARIA
TABLE II
T
he full-scale deflection of the uni- Calculate RI according to the applica-
versal high-input-resistance volt- tion from one of the following equations: Position 2 of Function Switch
meter circuit shown in the figure Erms input Meter Current
(a) DC voltmeter: RIA = full-scale EDC/IFS
5V 46 µA
(b) RMS AC voltmeter (sine 4V 36 µA
wave only): RIB = 0.9 full-scale 3V 26 µA
ERMS/ IFS 2V 18 µA
(c) Peak reading voltmeter 1V 10 µA
(sine wave only): RIC = 0.636 full-
scale EPK/IFS TABLE III
(d) Peak-to-peak AC voltme- Position 3 of Function Switch
ter (sine wave only): RID = 0.318 EPk input Meter Current
full-scale EPK-TO-PK / IFS 5V peak 46 µA
The term IFS in the above 4V peak 36 µA
equations refers to meter’s full- 3V peak 26 µA
2V peak 16 µA
scale deflection current rating in 1V peak 6 µA
amperes.
It must be noted that neither TABLE IV
meter resistance nor diode volt-
Position 4 of Function Switch
age drops affects meter current.
EPk-To-Pk Meter Current
Note: The results obtained
5V peak to peak 46 µA
during practical testing of the cir- 4V peak to peak 36 µA
depends on the function switch position cuit in EFY lab are tabulated in Tables I 3V peak to peak 26 µA
as follows: through IV. 2V peak to peak 16 µA
(a) 5V DC on position 1 A high-input-resistance op-amp, a 1V peak to peak 7 µA
(b) 5V AC rms in position 2 bridge rectifier, a microammeter, and a
(c) 5V peak AC in position 3 few other discrete components are all that ing the value of the resistor connected be-
(d) 5V AC peak-to-peak in position 4 are required to realise this versatile cir- tween the inverting input terminal of the
The circuit is basically a voltage-to- cuit. This circuit can be used for mea- op-amp and ground. The voltage to be
current converter. The design procedure surement of DC, AC RMS, AC peak, or measured is connected to non-inverting in-
is as follows: AC peak-to-peak voltage by simply chang- put of the op-amp.

CIRCUIT IDEAS
Time Switch Y. K
ATA
RIA
the position of mode switch. At the time
of alarm, when point A connected to col-
lector of transistor T1 passes through
logic 0 state, the output logic state of
AVNISH PUNDIR both the gates will toggle.
Assuming that mode switch is
T
his circuit is especially designed out having to flip the mode switch (i.e. flipped to ‘Mode Off’ position at power-
for those who often need to wake mode switch can be omitted). on-reset (when point D is at logic 1),
up early in the morning. Ordi- Please refer to the back panel dia- initially diode D1 would be in blocking
nary alarms in electronic watches are gram of a typical analogue clock and state and transistor T2 would be for-
not loud enough and the audio jack, to see how the existing ward biased via resistor R5 and
very often they fail to buzzer of diodes D2 and D3. As a result, the
wake up. The switch the clock is relay is in energised state, which makes
circuit described here required to output power available at output socket-
will come handy; it can be wired to 1 and cuts it off from socket-2. At alarm
be used to switch on a the audio time, the audio signal toggles logic
TV, radio or tape re- output output states of both gates N1 and N2.
corder etc, which will from the As a result, point D goes to logic 0
not allow even the la- clock. This state. Diode D1 conducts, taking the
ziest amongst us to ig- will ensure that when plug is inserted voltage at junction of diodes D1 and
nore their sound for too long. Besides, in the audio jack, the clock’s buzzer will D2 to near about 1 volt. Diode D3
this time switch can also be used to remain off and not consume any power ensures that its series combination with
switch on/off any other electric or elec- unnecessarily. diode D2 puts them in blocking mode.
tronic gadget at any time. What you The audio alarm output from the Capacitor C3 meanwhile discharges
need is a simple analogue electronic clock is coupled to the AF detector built via resistor R6 and the voltage at base
clock with alarm facility and a small around low-power switching transistor of transistor T2 approaches towards
circuit to implement the time switch. T1. During alarm, the collector of tran- ground level, cutting off transistor
This time switch has two modes. sistor T1 will fluctuate around ground T2 and de-energising relay RL1. Now
One is ‘time-on’ mode and the other is level and Vcc. During absence of audio the power at output socket-1 would be
‘time-off ’ mode. In time-on mode, you alarm input, the collector of transistor cut off while it becomes available in
set up the alarm in your clock as per T1 is held at Vcc potential. socket-2.
normal procedure and at the set time The next stage consists of an S-R If the above operation is repeated
this switch turns on the gadget con- latch built around NAND gates N1 and with switch S1 in ‘Mode On,’ the power
nected at the output socket-1. In time- N2. Capacitor C2 and resistor R4 are would initially not be available in
off mode, it turns your gadget off at the used for power-on-reset. On switching socket-1 (but available in socket-2). But
set time. The optional output socket-2 the power supply, gate N2 output will after the alarm, the power would be-
is wired in such a way that when you acquire logic 1 and that of gate N1 logic come available in socket-1 and not in
use this socket, the mode changes with- 0. This is the initial state, irrespective of socket-2.
ELECTRONICS FOR YOU n MARCH '99

CIRCUIT IDEAS
Infrared Cordless gauge or thicker wires) are used for con-

nection to TV side while high-imped-
ance windings are connected to IR trans-
Headphone G.S.
SAG
OO
mitter. This IR transmitter can be pow-
ered from a 9-volt mains adapter or bat-
tery. Red LED1 in transmitter circuit
functions as a zener diode (0.65V) as
PRADEEP G. well as supply-on indicator.
IR receiver uses 3-stage transistor
amplifier. The first two transistors (T4
U
sing this low-cost project one possible. Range can be extended by and T5) form audio signal amplifier
can reproduce audio from TV using lenses and reflectors with IR sen- while the third transistor T6 is used to
without disturbing others. It sors comprising transmitters and re- drive a headphone. Adjust potmeter VR2
does not use any wire connection be- ceivers. for max. clarity.
tween TV and headphones. In place of IR transmitter uses two-stage tran- Direct photo-transistor towards IR
a pair of wires, it uses invisible infra- sistor amplifier to drive two series-con- LEDs of transmitter for max. range. A
red light to transmit audio signals from nected IR LEDs. An
audio out-
put trans-
former is
used (in re-
verse) to
couple audio
output from
TV to the IR
transmitter.
Transistors
T1 and T2
amplify the
audio sig-
nals re-
ceived from
TV to headphones. Without using any TV through the audio transformer. Low- 9-volt battery can be used with receiver
lens, a range of up to 6 metres is impedance output windings (lower for portable operation.
ELECTRONICS FOR YOU n AUGUST '99

CIRCUIT IDEAS
Dual-Channel Digital mum count being 15 (all outputs logic

1) and minimum count being 0 (all out-
puts logic 0), it results in maximum and
Volume Control . DH
ILLO
N
minimum volume respectively.
The active high outputs A, B, C and
D of the counter are used for control-
ling two quad bi-polar analogue switches
A.P.S in each of the two CD4066 ICs (IC3 and
SHEENA K. IC4). Each of the output bits, when high,
short a part of the resistor network com-
T
his circuit could be used for re- quency pulses to up/down clock input prising series resistors R6 through R9
placing your manual volume con- pins of pre-setable up/down counter for one channel and R10 through R13
trol in a stereo amplifier. In this 74LS193 (IC2) via push-to-on switches for the other channel,
circuit, push-to-on switch S1 controls the S1 and S2. To vary the pulse width of and thereby control the output of the
forward (volume increase) operation of pulses from IC1, one may replace tim- audio signals being fed to the inputs of
both channels while a similar switch ing resistor R1 with a variable resistor. stereo amplifier. Push-to-on switch S3
S2 controls reverse (volume decrease) Operation of switch S1 (up) causes is used for resetting the output of
operation of both channels. the binary output to increment while counter to 0000, and thereby turning
Here IC1 timer 555 is configured as operation of S2 (down) causes the bi- the volume of both channels to the mini-
an astable flip-flop to provide low-fre- nary output to decrement. The maximum level.
ELECTRONICS FOR YOU n AUGUST '99

CIRCUIT IDEAS
Simple Low-Cost R4, and on releasing these two switches,

capacitor C3 starts discharging through
resistor R4. Capacitor C3 and resistor
R4 are so selected that it takes about
Digital Code Lock five seconds to fully discharge C3.

Depressing switches S1 and S8 in
unison, within five seconds of releasing
the switches SA and SC, pulls pin 2 to
NA ground and IC 555 is triggered. The ca-
A. JEYABAL ANJA
RUP pacitor C1 starts charging through re-
sistor R1. As a result, the output (pin
3) goes high for five seconds (i.e. the
M
any digital code lock circuits An essential property of this elec- charging time T of the capacitor C1 to
have been published in this tronic code lock is that it works in the threshold voltage, which is calcu-
magazine. In those circuits a monostable mode, i.e. once triggered, lated by the relation T=1.1 R1 x C1 sec-
set of switches (conforming to code) are the output becomes high and remains onds).
pressed one by one within the specified so for a period of time, governed by the Within these five seconds, switches
time to open the lock. In some other timing components, before returing to SA and SC are to be pressed momen-
circuits, custom-built ICs are used and the quiescent low state. In this circuit, tarily once again, followed by the de-
positive and negative logic pulses are timer IC 555 with 8 pins is used. The pression of last code-switch pair S3-S4.
keyed in sequence as per the code by IC is inexpensive and easily available. These switches connect the relay to out-
two switches to open the lock. Its pin 2 is the triggering input pin put pin 3 and the relay is energised.
A low-cost digital code lock circuit which, when held below 1/3 of the sup- The contacts of the relay close and the
is presented in this article. Here the ply voltage, drives the output to high solenoid pulls in the latch (forming part
keying-in code is rather unique. Six state. The threshold pin 6, when held of a lock) and the lock opens. The re-
switches are to be pressed to open the higher than 2/3 of the supply voltage, maining switches are connected between
lock, but only two switches at a time. drives the output to low state. By ap- reset pin 4 and ground. If any one of
Thus a total of three sets of switches plying a low-going pulse to the reset these switches is pressed, the IC is re-
have to be pressed in a particular se- pin 4, the output at pin 3 can be set and the output goes to its quiescent
quence. (Of these three sets, one set is brought to the quiescent low level. Thus low state. Possibilities of pressing these
repeated.) The salient features of this the reset pin 4 should be held high for reset switches are more when a code
circuit are: normal operation of the IC. breaker tries to open the lock.
1. Use of 16 switches, which sug- Three sets of switches SA-SC, S1- LED D5 indicates the presence of
gests that there is a microprocessor in- S8 and S3-S4 are pressed, in that or- power supply while resistor R5 is a cur-
side. der, to open the lock. On pressing the rent limiting resistor.
2. Elimination of power amplifier switches SA and SC simultaneously, ca- The given circuit can be recoded eas-
transistor to energise the relay. pacitor C3 charges through the poten- ily by rearranging connections to the
3. Low cost and small PCB size. tial divider comprising resistors R3 and switches as desired by the user.
ELECTRONICS FOR YOU n JULY '99

CIRCUIT IDEAS
Electronic Jam A.P.S

. DH
ILLO
N
output pin 8 of IC3 becomes high, which
causes outputs of both gates N1 and
N2 to go to logic 0 state. Logic 0 output
of gate N2 inhibits IC1, and thus press-
RAJESH K.P. ing of any other switch S1 through S8
has no effect. Thus, the contestant who
T
his jam circuit can be used in through R8. All eight outputs of IC1 presses his switch first, jams the dis-
quiz contests wherein any par- are connected to inputs of priority en- play to show only his number. In the
ticipant who presses his button coder 74LS147 (IC2) as well as 8-input unlikely event of simultaneous press-
(switch) before the other contestants, NAND gate 74LS30 (IC3). The output ing (within few nano-seconds difference)
gets the first chance to answer a ques- of IC3 thus becomes logic 0 which, after of more than one switch, the higher
tion. The circuit given here permits up inversion by NAND gate N2, is applied priority number (switch no.) will be
to eight contestants with each one al- to latch-enable pin 11 of IC1. With all displayed. Simultaneously, the logic 0
lotted a distinct number (1 to 8). The input pins of IC2 being logic 1, its BCD output of gate N1 drives the buzzer via
display will show the number of the con- output is 0000, which is applied to 7- pnp transistor BC158 (T1). The buzzer
testant pressing his button before the segment decoder/driver 74LS47 (IC6) af- as well the display can be reset (to
others. Simultaneously, a buzzer will ter inversion by hex inverter gates in- show 0) by momentary pressing of re-
also sound. Both, the display as well as side 74LS04 (IC5). Thus, on reset the set switch S9 so that next round may
the buzzer have to be reset manually display shows 0. start.
using a common reset switch. When any one of the push-to-on Lab Note: The original circuit sent
Initially, when reset switch S9 is mo- switches—S1 through S8—is pressed, by the author has been modified as it
mentarily pressed and released, all out- the corresponding output line of IC1 is did not jam the display, and a higher
puts of 74LS373 (IC1) transparent latch latched at logic 0 level and the display number switch (higher priority), even
go ‘high’ since all the input data lines indicates the number associated with when pressed later, was able to change
are returned to Vcc via resistors R1 the specific switch. At the same time, the displayed number.
ELECTRONICS FOR YOU n JUNE '99

CIRCUIT IDEAS
figure. The 1kHz signal can be further
CRYSTAL-CONTROLLED DWI
VED
I
divided using decade counters to gener-
ate the required time period.
EFY lab note. To generate required
TIME-BASE GENERATOR S.C. gate for use in a frequency counter circuit,

the final oscillator output needs to be fol-
lowed by a toggle flip-flop. For example, a
PRATAP CHANDRA SAHU 1kHz clock, when applied to a toggle flip-
A
digital frequency counter needs a
time-base generator to count the
frequency with high resolution.
Normally, a crystal-based oscillator with
divider IC chain or a similar circuit in the
form of an ASIC (application-specific IC)
is used for time-base generation. Here
we’ve presented a simple circuit for accu-
rate time-base generation using the readily
available 3.5795MHz crystal commonly
used in telecommunication equipment.
The 3.5795MHz crystal is used in con-
junction with a CD4060-based crystal os- Thus the crystal frequency is divided
cillator-cum-divider (IC1). The crystal fre- by 3584, giving the final output frequency flop, will generate gates with 1-sec ‘on’
quency is divided by 512 by IC1, which is of around 998.8 Hz. This frequency can period and 1-sec ‘off’ period.
further divided by 7 by CD4017 (IC2). IC2 be trimmed to exactly 1 kHz with the help This circuit is estimated to cost below
is reset as soon as its Q7 output goes high. of trimmer capacitor VC1 as shown in the Rs 50.
ELECTRONICS FOR YOU MAY 2002

CIRCUIT IDEAS
MAINS-OPERATED SAN
I THE
O
CHRISTMAS STAR
PRINCE PHILLIPS
capacitors C1, C2, and C3, diodes D1 and
D2, and zener ZD1 are used to develop a
fairly steady 5V DC supply voltage that
H
ere is a low-cost circuit of Christ- advantage of this circuit is that it doesn’t provides the required current to operate
mas star that can be easily con- require any step-down transformer or ICs. the multivibrator circuit and trigger triac
structed even by a novice. The main Components like resistors R1 and R2, BT136 via LED1.
The multivibrator circuit is constructed
using two BC548 transistors (T1 and T2)
and some passive components. The fre-
quency of the multivibrator circuit is con-
trolled by capacitors C4 and C5 and resis-
tors R3 through R7. The output of the
multivibrator circuit is connected to tran-
sistor T3, which, in turn, drives the triac
via LED1. During positive half cycles of
the multivibrator’s output, transistor T3
energises triac BT136 and the lamp glows.
This circuit is estimated to cost Rs 75.
MAY 2002 ELECTRONICS FOR YOU

CCIIRRC UCIUT IITD EIADS E A S
MAINS MANAGER SUN

IL KU
MAR
SHIBASHISH PATEL
V
ery often we forget to switch off volts via diode D3. This voltage is suffi- possible, plug the unit into the mains via
the peripherals like monitor, scan- cient to hold transistor T2 in forward bi- an earth leakage circuit breaker. The mains
ner, and printer while switching off ased condition for about 200 ms even af- LED1 should glow and the slave LED2
our PC. The problem is that there are sepa- ter the controlling load on the master should remain off. Now connect a table
rate power switches to turn the peripher- socket is switched off. lamp to the master socket and switch it
als off. Normally, the peripherals are con- When transistor T2 is ‘on’, transistor ‘on’. The lamp should operate as usual.
nected to a single of those four-way trail- T1 gets forward biased and is switched The slave LED should turn ‘on’ whenever
ing sockets that are plugged into a single on. This, in turn, triggers Triac 1, which the lamp plugged into slave socket is
wall socket. If that socket is accessible, all then powers the slave loads. Capacitor C4 switched on. Both lamps should be at full
the devices could be switched off from and resistor R9 form a snubber network to brightness without any flicker. If so, the
there and none of the equipment used will ensure that the triac turns off cleanly with unit is working correctly and can be put
require any modification. an inductive load. into use.
Here is a mains manager
circuit that allows you to turn
all the equipment on or off by
just operating the switch on
any one of the devices; for
example, when you switch off
your PC, the monitor as well
as other equipment will get
powered down automatically.
You may choose the main
equipment to control other
gadgets. The main equipment
is to be directly plugged into
the master socket, while all
other equipment are to be con-
nected via the slave socket.
The mains supply from the
wall socket is to be connected
to the input of the mains man-
ager circuit.
The unit operates by
sensing the current drawn by
the control equipment/load
from the master socket. On
sensing that the control
equipment is on, it powers up the other LED1 indicates that the unit is operat- Note. 1. The device connected to the
(slave) sockets. The load on the master ing. Capacitor C1 and zener ZD1 are effec- master socket must have its power switch
socket can be anywhere between 20 VA tively in series across the mains. The result- on the primary side of the internal trans-
and 500 VA, while the load on the slave ing 15V pulses across ZD1 are rectified by former. Some electronic equipment have
sockets can be 60 VA to 1200 VA. diode D2 and smoothened by capacitor C2 the power switch on the secondary side
During the positive half cycle of the to provide the necessary DC supply for the and hence these devices continue to draw
mains AC supply, diodes D4, D5, and D6 circuit around transistors T1 and T2. Resis- a small current from the mains even when
have a voltage drop of about 1.8 volts tor R3 is used to limit the switching-on switched off. Thus such devices, if con-
when current is drawn from the master surge current, while resistor R1 serves as a nected as the master, will not control the
socket. Diode D7 carries the current dur- bleeder for rapidly discharging capacitor C1 slave units correctly.
ing negative half cycles. Capacitor C3, in when the unit is unplugged. LED1 glows 2. Though this unit removes the power
series with diode D3, is connected across whenever the unit is plugged into the mains. from the equipment being controlled, it
the diode combination of D4 through D6, Diode D1, in anti-parallel to LED1, carries doesn’t provide isolation from the mains.
in addition to diode D7 as well as resistor the current during the opposite half cycles. So, before working inside any equipment
R10. Thus current pulses during positive Don’t plug anything into the master or connected to this unit, it must be un-
half-cycles, charge up the capacitor to 1.8 slave sockets without testing the unit. If plugged from the socket.
ELECTRONICS FOR YOU JULY 2002

CIRCUIT IDEAS
AUTO SHUT-OFF FOR CASSETTE tween the noise and the signal. Resistor
R4 offers feedback resistance to control
the gain of the opamp. By increasing or
PLAYERS AND AMPLIFIERS

decreasing the value of resistor R4, the
MAR gain can be increased or decreased, re-
IL KU
SUN spectively. The preset time delay of timer
NE555 (which is about one minute) can
ARTHUR LOUIS be increased by increasing the value
of C4.
H
ere are two simple, low-cost cir- interrupt the power supply. Initial energisation of relay RL2 and
cuits that can be used to shut The other circuit, shown in Fig. 2, charging of capacitor C4 take place on
off the mains supply to any au- functions on the basis of the signal re- depression of switch S3 in the same man-
dio or video equipment (such as tape received from preamp of the appliance used. ner as charging of capacitor C1 (refer Fig.
corder, CD player, and amplifier). These In this circuit, opamp µA741 is wired in 1) on depression of switch S1. As a re-
circuits are helpful to those in the habit inverting opamp configuration. It ampli- sult, pins 2 and 6 of NE555 go high and
of falling asleep with their music system fies the signal received from the preamp. the output of timer goes low to switch off
on. Timer NE555 is used to provide the nec- mains supply from the relay to step-down
The circuits will also protect the equip- essary time delay of about one minute. transformer X2 of the appliance. Bleeder
ment from getting damaged due to high- Preset VR1 is used to control the sen- resistor R6 is used to discharge capacitor
voltage spikes whenever there is a re- sitivity of the circuit to differentiate be- C4. Now if signals are received from the
sumption of power after a break. This is
possible because the equipment will get
switched off automatically under such con-
ditions but will not get switched on auto-
matically on resumption of mains supply.
The circuit in Fig. 1 can be used to
shut off any cassette player that has a
reliable auto-stop mechanism. Whenever
switch S1 is pressed momentarily, it ex-
tends the supply to the step-down trans-
former of the tape recorder and charges
capacitor C1 through diode D1. This, in
turn, makes transistor T1 conduct and
energise relay RL1 to provide a parallel
path to switch S1, so that supply to the
step-down transformer continues even
when switch S1 is released.
When any button on the cassette
player is pressed, the capacitor charges
through diode D2. This ensures conduc-
tion of transistor T1 and thus the conti-
nuity of operation of cassette player. How-
ever, whenever the auto-stop mechanism
functions at the end of a tape, the leaf
switch gets opened. This cuts the charg-
ing path for the capacitor and it starts
discharging slowly. After about one
minute, the relay opens and interrupts
main power to the transformer. The time
delay can be increased by increasing the
value of capacitor C1.
If the appliance used is a two-in-one
type (e.g. cassette player-cum-radio), just
connect another diode in parallel with di-
odes D1 and D2 to provide an additional
path for charging capacitor C1 via the
tape-to-radio changeover switch, so that
when radio is played the relay does not
ELECTRONICS FOR YOU ❚ APRIL 2001

CIRCUIT IDEAS
preamplifier, these are amplified by 741 the mains supply to transformer X2. driven from the preamplifier of the gad-
and fed to the base of transistor T2, which Switch S2 can be depressed momentarily get used, and not from its power ampli-
keeps capacitor C4 charged through re- if the device needs to be manually fier output. Switches S1 and S2 are 2-
sistor R5. When there is no signal, T2 switched off. pole push-to-on switches. These can also
will not conduct and the capacitor slowly Note. The 12V supply should be probe fabricated from 2-pole on-off switches,
discharges through R6. The output of 555 vided to the circuit from the equipment’s which are widely used in cassette play-
goes high to switch off the relay and thus power supply. Opamp 741 should be ers, by removing the latch pin from them.

CIRCUIT IDEAS
CONDENSER MIC SUN

IL KU
MAR
varying its gain. In order to increase the
audio power, the low-level audio output
from the preamplifier stage is coupled via
AUDIO AMPLIFIER coupling capacitor C7 to the audio power

amplifier built around BEL1895 IC.
BEL1895 is a monolithic audio power
D. PRABAKARAN amplifier IC designed specifically for sen-
sitive AM radio applications that delivers
T
he compact, low-cost condenser transmitters, and packet radio receivers. 1 watt into 4 ohms at 6V power supply
mic audio amplifier described here Transistors T1 and T2 form the mic voltage. It exhibits low distortion and
provides good-quality audio of 0.5 preamplifier. Resistor R1 provides the nec- noise and operates over 3V-9V supply volt-
watts at 4.5 volts. It can be used as part essary bias for the condenser mic while age, which makes it ideal for battery op-
of intercoms, walkie-talkies, low-power preset VR1 functions as gain control for eration. A turn-on pop reduction circuit
prevents thud when the power
supply is switched on.
Coupling capacitor C7 deter-
mines low-frequency response of
the amplifier. Capacitor C9 acts
as the ripple-rejection filter. Ca-
pacitor C13 couples the output
available at pin 1 to the loud-
speaker. R15-C13 combination
acts as the damping circuit for
output oscillations. Capacitor C12
provides the boot strapping func-
tion.
This circuit is suitable for low-
power HAM radio transmitters to
supply the necessary audio power
for modulation. With simple modi-
fications it can also be used in
intercom circuits.
ELECTRONICS FOR YOU ❚ DECEMBER 2001

CIRCUIT IDEAS
EDI
CONTACTLESS RINGER FOR TELEPHONES S.C.
DWIV
PRADEEP G.
S
everal circuits of a telephone
extension ringer have earlier been
published in EFY. The circuit pre-
sented here is distinct from these circuits
in that it has no electrical contact with
the telephone lines. It senses the induced
fluctuating electric field of telephone lines
when the phone rings.
The input is sensed by a 5-8cm long
plastic insulated flexible wire that is wound
3-4 times on telephone cable. When the
telephone rings, about 20Hz AC voltage is
available on the telephone line, which
causes field fluctuation up to a few centimetres
outside the telephone cable also.
The 20Hz AC signal induced in the
pick-up sensor is coupled to the clock pin
of decade counter IC CD4017. The CD4017
is wired as a divide-by-two counter by
connecting its pin 4 to reset pin 15.
As the input impedance of CMOS IC transistor BC547 in class-C mode of op- ing duration. As a result, the alarm is
is extremely high, the induced electric field eration. The transistor conducts during the activated when the telephone rings.
is sufficient to clock it. The output ob- positive half cycle of square wave. The When the handset is picked up or the
tained at pin 3 of CD4017 is a 10Hz square positive voltage (high) available at the telephone stops ringing, the transistor
wave (half of input 20Hz signals). This emitter of the transistor pulls reset pin 4 stops conduction. Then reset pin of IC2
square wave signal is used to bias npn of 555 timer IC high for the correspond- goes low and the alarm is disabled.
JUNE 2002 ELECTRONICS FOR YOU

CIRCUIT IDEAS
EXCLUSIVE-OR GATE APPLICATIONS S.C.

DWIV
EDI
ANAND TAMBOLI therefore be used as

control input for XOR
gates to behave as
X
OR gate is a derived logic gate that inverters or buffers. Here
finds many applications in digital one of the inputs of each
circuits. Here we have described XOR gate are connected
use of XOR gate as controlled inverter,
TRUTH TABLE I
9’s BCD subtractor and up-/down-counter. XOR Gate
It can be seen from Fig. 1 and the A B Y
accompanying truth table that XOR gate
0 0 0
works as NOT (inverter) gate when its
0 1 1
one input is held high, and as a buffer
1 0 1
when the same input is pulled low. The
1 1 0
common input (as shown in Fig. 2) can Fig. 1: XOR gate as inverter and buffer
subtraction circuits using 1’s and

2’s complements.
In another configuration of XOR
gate shown in Fig. 3, the circuit
works as a 9’s BCD subtractor. Its
output=9 – input.
The circuit in Fig. 3 can be used
as a down-counter when employed
with 4-bit BCD counter IC 7490 as
shown in Fig. 4. Truth table of this
configuration is given alongside. As
seen from the figure, this circuit can
Fig. 2: XOR gate as controlled inverter Fig. 4: Up-/down-counter be built using a single XOR-IC (TTL-
together to serve as TRUTH TABLE II

the control signal, Down-Counter
while the DiCiBiAi DEC. EQ. D0C0B0A0 DEC. EQ.
remaining inputs 0000 0 1001 9
serve as input bits. 0001 1 1000 8
When control 0010 2 0111 7
signal is zero, the 0011 3 0110 6
output is same as 0100 4 0101 5
the input (buffer 0101 5 0100 4
mode). However, 0110 6 0011 3
when control signal 0111 7 0010 2
is held high, all bits 1000 8 0001 1
are inverted. Thus 1001 9 0000 0
the output is
complement of the 7486). The NOR gate used in the circuit
input. This is inevitable, but it can be replaced by a
complementing resistance-transistor logic (RTL) circuit or
function is useful in any other equivalent circuit.
Fig. 3: XOR gate as 9’s BCD subtractor
ELECTRONICS FOR YOU JUNE 2002

CIRCUIT IDEAS
FASTEST FINGER DWIV

EDI
anode 7-segment LED display (DIS.1,
FND507 or LT543).
S.C.
FIRST INDICATOR
The audio alarm generator comprises
clock oscillator IC7 (555), whose output
drives a loudspeaker. The oscillator fre-
P. RAJESH BHAT quency can be varied with the help of
preset VR1. Logic 0 state at one of the
Q
uiz-type game shows are increas- When a contestant presses his switch, outputs of IC2 produces logic 1 input con-
ingly becoming popular on tele- the corresponding output of latch IC2 dition at pin 4 of IC7, thereby enabling
vision these days. In such games, (7475) changes its logic state from 1 to 0. the audio oscillator.
fastest finger first indicators (FFFIs) are The combinational circuitry comprising IC7 needs +12V DC supply for suffi-
used to test the player’s reaction time. dual 4-input NAND gates of IC3 (7420) cient alarm level. The remaining circuit
The player’s designated number is dis- locks out subsequent entries by produc- operates on regulated +5V DC supply,
played with an audio alarm when the ing the appropriate latch-disable signal. which is obtained using IC1 (7805).
player presses his entry button. Priority encoder IC4 (74147) encodes Once the organiser identifies the con-
The circuit presented here determines the active-low input condition into the cor- testant who pressed the switch first, he
as to which of the four contestants first responding binary coded decimal (BCD) disables the audio alarm and at the same
pressed the button and locks out the re- number output. The outputs of IC4 after time forces the digital display to ‘0’ by
maining three entries. Simultaneously, an inversion by inverter gates inside hex in- pressing reset pushbutton S5.
audio alarm and the correct decimal num- verter 74LS04 (IC5) are coupled to BCD- With a slight modification, this cir-
ber display of the corresponding contes- to-7-segment decoder/display driver IC6 cuit can accommodate more than four con-
tant are activated. (7447). The output of IC6 drives common- testants.
ELECTRONICS FOR YOU ❚ DECEMBER 2001

CIRCUIT IDEAS
FM BOOSTER SUN
IL KU
MAR
PRADEEP G.
H
ere is a low-cost circuit of an FM stations clearly. The circuit comprises a 2SC2570. (Only C2570 is annotated on the
booster that can be used to listen common-emitter tuned RF preamplifier transistor body.)
to programmes from distant FM wired around VHF/UHF transistor Assemble the circuit on a good-quality
PCB (preferably, glass-epoxy). Adjust in-
put/output trimmers (VC1/VC2) for maxi-
mum gain.
Input coil L1 consists of four turns of
20SWG enamelled copper wire (slightly
space wound) over 5mm diameter former.
It is tapped at the first turn from ground
lead side. Coil L2 is similar to L1, but has
only three turns. Pin configuration of tran-
sistor 2SC2570 is shown in the figure.
ELECTRONICS FOR YOU FEBRUARY 2002

CCIIRRC UC IUT IITD EIADS E A S
minals of pnp transistor T1) develops
MUSIC-ON-HOLD FOR enough voltage to forward bias transistor

T1 and it starts conducting.
TELEPHONES S.C.
DWIV
EDI As a consequence, output voltage at
the collector of transistor T1 sustains for-
ward biasing of transistor T2, even if switch
S1 is released. This latching action keeps
SIBIN K. ZACHARIAH
both transistors T1 and T2 in conduction
as long as the output of the bridge rectifier
H
ere is a simple circuit for music- line voltage is more than 15 volts, i.e. is greater than 15 volts.
on-hold with automatic shut off fa- when the handset is placed on the cradle. If the handset is now lifted off-hook,
cility. During telephone conversa- Once the transistor pair of TI and T2 the rectifier output drops to about 9 volts
tion if you are reminded of some urgent starts conducting, melody generator IC1 and hence latching action ceases and the
work, momentarily push switch S1 until
red LED1 glows, keep the telephone hand-
set on the cradle, and attend to the work
on hand. A soft music is generated and
passed into the telephone lines while the
other-end subscriber holds. When you re-
turn, you can simply pick up the handset
again and continue with the conversation.
The glowing of LED1, while the music
is generated, indicates that the telephone
is in hold position. As soon as the handset
is picked up, LED1 is turned off and the
music stops.
Normally, the voltage across telephone
lines is about 50 volts. When we pick up gets the supply and is activated. The mu- circuit automatically switches off.
the receiver (handset), it drops to about 9 sic is coupled to the telephone lines via (EFY lab note. The value of resistor
volts. The minimum voltage required to capacitor C2, resistor R1, and the bridge R2 determines the current through resistor
activate this circuit is about 15 volts. If the rectifier. R1 to develop adequate voltage (greater
voltage is less than 15 volts, the circuit With the handset off-hook after a ring, than 0.65 volts) for conduction of transis-
automatically switches off. However, ini- momentary depression of switch S1 causes tor T1. Hence it may be test selected be-
tially both transistors T1 and T2 are cut off. forward biasing of transistor T2. Mean- tween 33 kilo-ohms and 100 kilo-ohms to
The transistor pair of T1 and T2 performs while, if the handset is placed on the obtain instant latching.)
switching and latching action when switch cradle, the current passing through R1 The total cost of this circuit is around
S1 is momentarily pressed, provided the (connected across the emitter and base ter- Rs 50.
ELECTRONICS FOR YOU APRIL 2002

CIRCUIT IDEAS
INVISIBLE BROKEN For audio-visual indication, one may

use a small buzzer (usually built inside
WIRE DETECTOR
quartz alarm time pieces) in parallel with
EDI one small (3mm) LCD in place of LED1
DWIV
S.C. and resistor R5. In such a case, the cur-
rent consumption of the circuit will be
K. UDHAYA KUMARAN, VU3GTH around 7 mA. Alternatively, one may use
two 1.5V R6- or AA-type batteries. Using
P
ortable loads such as video cam- The frequency is determined by timing this gadget, one can also quickly detect
eras, halogen flood lights, elec- components comprising resistors R3 and fused small filament bulbs in serial loops
trical irons, hand drillers, grind- R4, and capacitor C1. Gates N1 and N2 powered by 230V AC mains.
ers, and cutters are powered by connect- are used to sense the presence of 230V AC The whole circuit can be accommo-
ing long 2- or 3-core cables to the mains field around the live wire and buffer weak dated in a small PVC pipe and used as a
plug. Due to prolonged usage, the power AC voltage picked from the test probe. handy broken-wire detector. Before detect-
cord wires are subjected to mechanical The voltage at output pin 10 of gate N2 ing broken faulty wires, take out any con-
strain and stress, which can lead to in- can enable or inhibit the oscillator circuit. nected load and find out the faulty wire
ternal snapping of wires at any point. In When the test probe is away from any first by continuity method using any mul-
such a case most people go for replacing high-voltage AC field, output pin 10 of timeter or continuity tester. Then connect
the core/cable, as finding the exact loca- gate N2 remains low. As a result, diode 230V AC mains live wire at one end of
D3 conducts and inhibits the faulty wire, leaving the other end free.
the oscillator circuit from Connect neutral terminal of the mains
oscillating. Simulta- AC to the remaining wires at one end.
neously, the output of gate However, if any of the remaining wires is
N3 at pin 6 goes ‘low’ to also found to be faulty, then both ends of
cut off transistor T1. As a these wires are connected to neutral. For
result, LED1 goes off. single-wire testing, connecting neutral
When the test probe is only to the live wire at one end is suffi-
moved closer to 230V AC, cient to detect the breakage point.
50Hz mains live wire, dur- In this circuit, a 5cm (2-inch) long,
ing every positive half- thick, single-strand wire is used as the
cycle, output pin 10 of gate test probe. To detect the breakage point,
N2 goes high. turn on switch S1 and slowly move the
Thus during every test probe closer to the faulty wire, begin-
positive half-cycle of the ning with the input point of the live wire
mains frequency, the os- and proceeding towards its other end.
cillator circuit is allowed LED1 starts glowing during the presence
tion of a broken wire is difficult. In 3-core to oscillate at around 1 kHz, making red of AC voltage in faulty wire. When the
cables, it appears almost impossible to de- LED (LED1) to blink. (Due to the persis- breakage point is reached, LED1 immedi-
tect a broken wire and the point of break tence of vision, the LED appears to be ately extinguishes due to the non-avail-
without physically disturbing all the three glowing continuously.) This type of blink- ability of mains AC voltage. The point
wires that are concealed in a PVC jacket. ing reduces consumption of the current where LED1 is turned off is the exact
The circuit presented here can easily from button cells used for power supply. broken-wire point.
and quickly detect a broken/faulty wire A 3V DC supply is sufficient for pow- While testing a broken 3-core rounded
and its breakage point in 1-core, 2-core, ering the whole circuit. AG13 or LR44 cable wire, bend the probe’s edge in the
and 3-core cables without physically dis- type button cells, which are also used in- form of ‘J’ to increase its sensitivity and
turbing wires. It is built using hex inside laser pointers or in LED-based conti- move the bent edge of the test probe closer
verter CMOS CD4069. Gates N3 and N4 nuity testers, can be used for the circuit. over the cable. During testing avoid any
are used as a pulse generator that oscil- The circuit consumes 3 mA during the strong electric field close to the circuit to
lates at around 1000 Hz in audio range. sensing of AC mains voltage. avoid false detection.
ELECTRONICS FOR YOU ❚ AUGUST 2001

C I R CC UI RICTU I IT DI ED EAASS
when it detects IR light, triggering the

IR REMOTE SWITCH DWIV
EDI
monostable (1-second) built around timer
NE555. The output of the mono toggles
K.S. SANKAR S.C. the J-K flip flop, whose Q output drives
the relay through SL100 npn transistor (T1).
LED2, LED3, and LED4 are used to
I
magine the convenience of selecting works up to a distance of about 10 metres. display the status of each output stage dur-
TV channels using your remote and The circuit is built around a 3-pin IR ing circuit operation. Back-EMF diode D5
then pointing the same remote to your IC receiver (Siemens SFH-506-38 or equiva- is used for protection. Transistor T1 is con-
switchboard to switch on/off the fan or lent) that can detect 38kHz burst frequency figured as an open-collector output device
the tubelight. Here is a simple circuit to generated by a TV remote. (This IR re- to drive the relay rated at 12V DC.
remotely switch on/off any electrical de- ceiver module has been covered earlier in The circuit draws the power from volt-
vice through a relay using the normal TV/ many projects published in EFY.) age regulator 7805. Capacitor C5 is sol-
VCR/VCP/VCD remote control unit. It The output pin of IR sensor goes low dered close to the IR sensor’s pins to avoid
noise and false
triggering. Ca-
pacitor C3 and
resistor R3 also
avoid false trig-
gering of
monostable
NE555. The
monostable acts
as a 1-second
hysterisis unit to
restrict the flip-
flop from getting
retriggered
within one sec-
ond. To activate
any other 12V
logic device, use
the output across
the relay coil ter-
minals.
MARCH 2002 ELECTRONICS FOR YOU

CIRCUIT IDEAS
LASER TORCH-BASED VOICE

TRANSMITTER AND RECEIVER
PRADEEP G.
SAN
I THE
O
U
sing this circuit you can communi-
cate with your neighbours
wirelessly. Instead of RF signals,
light from a laser torch is used as the
carrier in the circuit. The laser torch can
transmit light up to a distance of about 500
metres. The phototransistor of the receiver
must be accurately oriented towards the
laser beam from the torch. If there is any
obstruction in the path of the laser beam,
no sound will be heard from the receiver.
The transmitter circuit (Fig. 1) com-
prises condenser microphone transistor
amplifier BC548 (T1) followed by an op-
amp stage built around µA741 (IC1). The
gain of the op-amp can be controlled with
the help of 1-mega-ohm potmeter VR1.
The AF output from IC1 is coupled to the
base of transistor BD139 (T2), which, in
turn, modulates the laser beam.
The transmitter uses 9V power sup-
ply. However, the 3-volt laser torch (after
removal of its battery) can be directly con-
nected to the circuit—with the body of
the torch connected to the emitter of
BD139 and the spring-loaded lead protrud-
ing from inside the torch to circuit ground.
The receiver circuit (Fig. 2) uses an
npn phototransistor as the light sensor that
is followed by a two-stage transistor
preamplifier and LM386-based audio
power amplifier. The receiver does not
need any complicated alignment. Just keep
the phototransistor oriented towards the
remote transmitter’s laser point and ad-
just the volume control for a clear sound.
To avoid 50Hz hum noise in the from AC light sources such as bulbs. cause any problem. But the sensor should
speaker, keep the phototransistor away The reflected sunlight, however, does not not directly face the sun.
JANUARY 2002 ELECTRONICS FOR YOU

CIRCUIT IDEAS
MOBILE PHONE I THE

O
configuration and the positive DC supply
is directly connected to the charger’s out-
BATTERY CHARGER SAN

put contact, while the negative terminal
is connected through current limiting re-
sistor R2.
T.K. HAREENDRAN LED2 works as a power indicator with
resistor R1 serving as the current limiter
M
obile phone chargers available in 7.2 volts, such as Nokia 6110/6150. and LED3 indicates the charging status.
the market are quite expensive. The 220-240V AC mains supply is During the charging period, about 3 volts
The circuit presented here comes downconverted to 9V AC by transformer drop occurs across resistor R2, which turns
as a low-cost alternative to charge mobile X1. The transformer output is rectified by on LED3 through resistor R3.
telephones/battery packs with a rating of diodes D1 through D4 wired in bridge An external DC supply source (for in-
stance, from a vehicle battery) can also be
used to energise the charger, where resis-
tor R4, after polarity protection diode D5,
limits the input current to a safe value.
The 3-terminal positive voltage regulator
LM7806 (IC1) provides a constant voltage
output of 7.8V DC since LED1 connected
between the common terminal (pin 2) and
ground rail of IC1 raises the output volt-
age to 7.8V DC. LED1 also serves as a
power indicator for the external DC sup-
ply.
After constructing the circuit on a
veroboard, enclose it in a suitable cabinet.
A small heat sink is recommended for IC1.
ELECTRONICS FOR YOU JANUARY 2002

CIRCUIT IDEAS
KNOCK ALARM SUN

IL KU
MAR
PRADEEP G. circuit. When someone knocks on the

door, the piezoelectric sensor gener-
T
his circuit (Fig. 1), used in conjunc- ates an electrical signal, which is am-
tion with a thin piezoelectric plate, plified by transistors T1 through T3.
senses the vibration generated on The amplified signal is rectified
knocking a surface (such as a door or a and filtered to produce a low-level
table) to activate the alarm. It uses readily- DC voltage, which is further ampli-
available, low-cost components and can fied by the remaining transistors. The
also be used to safeguard motor vehicles. final output from the collector of pnp
The piezoelectric plate is used as the sen- transistor T6 is applied to reset pin 4
sor. It is the same as used in ordinary of 555 (IC1) that is wired as an Fig. 2: Proposed installation of knock alarm
Fig. 1: The circuit of knock alarm

piezobuzzers and is easily available in the astable multivibrator. Whenever the col- time that capacitor C5 connected between
market. lector of transistor T6 goes high, the astable the emitter of transistor T4 and ground
The piezoelectric plate can convert any multivibrator activates to sound an alarm takes to discharge after a knock. The time
mechanical vibration into electrical varia- through the speaker. The value of resistor delay can be changed by changing the
tion. As it doesn’t sense sound from a dis- R12 is chosen between 220 and 680 ohms value of capacitor C5. After about 10 sec-
tance like a microphone, it avoids false such that IC1 remains inactive in the ab- onds, the alarm is automatically reset.
triggering. The plate can be fixed on a door, sence of any perceptible knock. The circuit operates off a 9V or a 12V
cash box, cupboard, etc using adhesive. A 1- When the circuit receives an input sig- battery eliminator. The proposed installa-
1.5m long, shielded wire is connected be- nal due to knocking, the alarm gets acti- tion of the knock alarm is shown in Fig. 2.
tween the sensor plate and the input of the vated for about 10 seconds. This is the This circuit costs around Rs 75.
ELECTRONICS FOR YOU NOVEMBER 2002

CIRCUIT IDEAS
DING-DONG BELL SAN

I TH
EO
tary-pair, two-transistor amplifier is used
to amplify the sound to a fair level of
PRAVEEN SHANKER audiblity. You may either use a piezo
tweeter or an 8-ohm, 500mW speaker at
T
his simple and cost-effective door (Website address: fortech@mantramail. the output.
bell circuit is based on IC 8021-2 com). It is an 8-pin DIP IC whose only During the standby period, the IC con-
from Formox Semiconductors four pins, as shown in the circuit, have sumes nominal current of a few microam-
been used. peres only. Therefore switch S1 may be
The IC has an in-built kept closed. Each time switch S2 is
circuitry to produce ding- pressed, ding dong sound is produced
dong sound each time its twice. If you try to press switch S2 a sec-
pin 3 is pulled low. The ond time when the first ding dong sound
sound is stored in the IC is still being produed, it has no effect what-
as bits, as in a ROM. The ever and the two ding-dong bell sounds
sound output from the IC will be invariably produced.
can’t however drive a The circuit costs no more than Rs 35
speaker directly, as this and the IC 8021-2 used in the circuit is
puts strain on the device. readily available for around Rs 15 in the
Therefore a complemen- market.
ELECTRONICS FOR YOU MARCH 2002

CCI IR R
C UCI U
T II TD E IAD
S EAS
PC-BASED OSCILLOSCOPE SAN

I THE
O
M.M. VIJAI ANAND
T
his circuit conditions different sig- put signal such that the negative half cycle The final output voltage (Vo) at pin 7
nals of frequency below 1 kHz and of the input signal is available in the posi- of op-amp A2 is given by the following
displays their waveforms on the PC’s tive side itself, so both the half cycles are relationship:
screen. The hardware is used to condition read as positive when it is given as input Vo=(1+R/2R)(-2Vi/3)= -Vi
the input waveform and convert it to the to the ADC. During positive half cycle, As Vi is negative, the output voltage is
digital format for interfacing to the PC. The diode D3 is on and diode D4 is off, and positive.
software for acquiring the data into the PC op-amps A1 and A2 act as inverters. Thus The zero-crossing detector detects
and displaying the same on its screen is the output is a replica of the input. During whether the cycle is positive or negative.
written in Turbo C. the negative half cycle, diode D3 is off It is the most critical part of the circuit
The input waveform (limited to 5V and diode D4 is on. With and if it operates improperly, the symme-
peak-to-peak) is first applied to a full-wave R2=R3=R4=R5=R6=R=330 ohms, the try of the analogue signal displayed in the
rectifier comprising op-amps A1 and A2 of voltage (V) at inverting pin 2 of op-amp PC monitor gets affected. At the zero-cross-
quad op-amp LM324 (IC4) and a zero- A1 is related to the input voltage (Vi) as ing instant when the input signal transits
crossing detector built around LM3914 dot/ follows: to negative side, the zero-crossing detec-
bar display driver (IC8) simultaneously. Vi/R +V/(2R)+V/R=0 tor informs the PC by taking pin 15 of 25-
The full-wave rectifier rectifies the in- V= -(2/3)Vi pin ‘D’ connector of the parallel port high.
ELECTRONICS FOR YOU DECEMBER 2002

CIRCUIT IDEAS
The input at pin 15 of ‘D’ connector goes R1=10 kilo-ohms and C4=150 pF, which tus port address is 0x0379 and the
low when the input signal transits to posi- are the externally connected timing com- control port address is 0x037a. The port
tive side. The zero-crossing detector components. The conversion time obtained is addresses for parallel ports are summarised
municates with the PC through bit D3 of approximately 100 µs. The functions of below:
the status port 379Hex. other pins are given below: Printer Data port Status port Control port
The zero-crossing detector has been Pin 1 (CS): This is active- LPT1 0x0378 0x0379 0x037a
realised using LM3914 IC. You may adjust low chip-select pin. LPT2 0x0278 0x0279 0x027a
VR1 such that the last LED (LED10) goes Pin 2 (RD): This active-low LPT3 0x03bc 0x03bd 0x03be
off when the input signal transits negative pin enables the digital output
side of the input waveform. The LM3914 buffers. When high, the 8-bit bus will be (EFY Lab note. For details of the par-
itself rectifies the input signal and allows in Hi-Z state. allel port pins, refer ‘PC-based Dial Clock
only positive half of the cycle. Pin 3 (WR): This active-low pin is used with Timer’ project published in June 2002
The output from the full-wave rectifier to start the conversion. issue of EFY.)
is applied to the input of a sample-and-hold Pin 9 (Vref/2): This is optional input The software, written in C program-
circuit comprising op-amps A3 and A4 of pin. It is used only when the input signal ming language, is user-friendly and easy-
the LM324 (IC5), capacitor C3, transistor range is small. When pin 9 is at 2V, the to-understand. It gets data from the devel-
T1 (SL100), and analogue switch IC6 range is 0-4V, i.e. twice the voltage at pin 9. oped hardware circuit and displays it in
(CD4016). This circuit samples the input Pin 6 (V+), Pin 7(V-): The actual in- the graphical screen with some changes.
signal, i.e. it divides the waveform into a put is the difference in voltages applied to The C program includes two user-de-
number of voltages or points and inputs these pins. The analogue input can range fined functions with the main function:
each voltage level (with a delay) to the from 0 to 5V. graphics( ) and settings( ). The settings( )
ADC for conversion into the digital format. In this circuit, pins 1 and 2 are always function is used to adjust the voltage and
Op-amps A3 and A4, along with a switch made low, so the IC and the buses are time scale. The graphics( ) function is used
from IC CD4016 and a 1500pF capacitor always enabled. Pin 9 is made open, as to display the waveform on the screen. The
with sampling time of 20 µs, are used as we use analogue input with 0-5V range. sample control signal is used to close the
voltage followers/buffers. Pin 7 is grounded. switch in the sample-and-hold circuit, so the
When the base of transistor T1 is made Pin 5 (INTR): This active-low pin indi- capacitor charges towards the analogue in-
low via strobe pin 1 (bit Do of I/O port cates the end of conversion. It is connected put voltage. After the sampling is over, the
37A) of 25-pin D connector of the parallel to pin 17 (bit D3 of I/O port 37A) of ‘D’ switch is opened using the same signal.
port, the transistor stops conducting and connector. (Note that this bit is inverted.) Then the start-of-conversion control signal
the voltage at its collector goes high. The The start-of-conversion command via is given to start the conversion. The sam-
high voltage at the collector of transistor pin 16 of ‘D’ connector is applied to pin 3 pling time is approximately 20 µs and the
T1 closes the switch inside CD4016. As a of the ADC0804. Since we cannot read 8- conversion time is approximately 100 µs.
consequence, the analogue input signal is bit digital data output from ADC through After the conversion is over, the 8-bit
applied to the capacitor, which charges to- the 4-bit status port at a time, we divide it binary data for the specific voltage sample
wards the signal voltage. in two 4-bit parts and read. Hence the is available in the data bus of the ADC.
When the switch is subsequently ADC data output is multiplexed through Since the PC accepts only 4-bit data through
opened by applying a logic-high voltage two 4-bit sections of octal buffers of IC1 the status port (379H), the 8-bit data must
from pin 1 of ‘D’ connector to the base of (74244) with the help of output-enable sig- be split into two 4-bit data, which are ac-
transistor T1, the capacitor retains the volt- nals from pins 2 and 9 of ‘D’ connector to cepted one after another. This is done by IC
age with a loss of about 20 mV/sec and pins 1 and 19 (OE1 and OE2, respectively) 74244, which is controlled by D0 and D7
this voltage is given to input pin 6 of the of IC1. The digital data output from IC1 is bits of the data port. Then the two 4-bit
ADC0804 (IC3) via buffer A4 for conver- interfaced to the PC via pins 13 (D4), 12 data are packed to get the final 8-bit data.
sion to the digital format. When the num- (D5), 10 (D6), and 11 (D7) of status input The default BGI directory path is set
ber of sampling points in the input signal port 379H of ‘D’ connector. as ‘c:\tc\bgi’. The sampling time is de-
waveform is increased, the reconstructed The circuit uses 9V and 5V regulated cided by the ‘for’ loop that uses the samp
waveform becomes more accurate. DC supply voltages as shown in the cir- value. The maximum delay produced
The ADC0804 is compatible with mi- cuit diagram. should be greater than 20 µs, which is the
croprocessors. It is a 20-pin IC that works A PC printer port is an inexpensive maximum acquisition time of the capaci-
with 5V supply. It converts the analogue platform for implementing low-frequency tor. When the sample value is increased,
input voltage to 8-bit digital output. The data acquisition projects. Each printer port the number of points on the input signal
data bus is tristate buffered. With eight consists of data, status, and control port decreases and therefore the accuracy de-
bits, the resolution is 5V/255 = 19.6 mV. addresses. These addresses are in sequen- creases. The time scale may be calibrated
The inbuilt clock generator circuit pro- tial order; for example, if the data port with 50Hz sine wave as reference.
duces a frequency of about 640 kHz with address is 0x0378, the corresponding sta- This circuit costs around Rs 400.
PROGRAM IN ‘C’ FOR PC OSCILLOSCOPE

/* PROGRAM FOR PC OSCILLOSCOPE */ #include<stdio.h> #define data 0x0378
/*by M.M.VIJAI ANAND B.E (E.E.E) C.I.T */ #include <graphics.h> #define stat 0x0379
#include<dos.h> #include<string.h> #define cont 0x037a
#include<time.h> #include<stdlib.h>
DECEMBER 2002 ELECTRONICS FOR YOU

CIRCUIT IDEAS
void graphics(int[],int[]); //FUNCTION TO DIS- setcolor(BROWN); {

PLAY GRAPH AND WAVEFORM outtextxy(max-200,may+10,”press any key to exit”); outtextxy(10,200,”TYPE 1 for 1 unit = 2 volt”);
setcolor(GREEN); outtextxy(10,240,”TYPE 2 for 1 unit = 4 volt”);
void settings(); //FUNCTION TO CHANGE settextstyle(0,0,0); outtextxy(10,300,”TYPE 3 for user defined”);
THE SETTINGS(TIME AND VOLT- for(a=0;a<=may;a+=get) switch(getch())
AGE) {line(0,a,800,a); {
} case ‘1’ :
long int samp=7000; //PLEASE CHECK THESE VAL- for(a=0;a<=max;a+=get) { scale=2;
UES WHEN CONVERSION IS { break;
// NOT PROPER(+- line(a,0,a,may); }
3000) } case ‘2’ :
setcolor(BROWN); {scale = 4;
float scale=1; setlinestyle(0,3,0); break;
float times=1; line(max/2,0,max/2,may); }
char again=’a’; line(0,may/2,max,may/2); case ‘3’ :
int number=800; setcolor(RED); {
for(a=0,c=0;a<=max;a+=50,c++) outtextxy(10,340,”TYPE VALUES FROM 1 TO 9
void main() { (minimize) or m to (magnify)”);
{ putpixel(a,may/2,BLUE); d=getch();
int i,j,k,a[1700],b[1700],c[1700],e[1700]; //This value itoa((a-c*30)*times/2,str,10); if(d==’m’)
1700 is given when we want to compress the waveform outtextxy(a+3,may/2+3,str); {
} outtextxy(10,360,”TYPE a (1 unit = 0.5 volt) or b
//done when we compress the time scale for(b=(may/2)-45,c=1;b>=0;b-=45,c++) (1 unit = 0.25 volt)”);
long int b1; { switch(getch())
clrscr(); itoa((c*scale),str,10); {
settings(); putpixel((max/2),b,BLUE); case ‘a’:
while(again==’a’) outtextxy((max/2)+3,b+3,str); {
{ } scale=0.5;
for(i=0;i<number;i++) for(b=(may/2)+45,c=1;b<=800;b+=45,c++) break;
{ { }
outportb(cont,0x05^0x0b); itoa((c*scale),str,10); case ‘b’:
outportb(cont,0x04^0x0b); strcat(st,str); {
e[i]=(inportb(stat)^0x80)&0x08; putpixel((max/2),b,BLUE); scale=0.25;
for(b1=0;b1<=samp;b1++) //sampling outtextxy((max/2)+2,b+2,st); break;
time is approximately 50 µsec strcpy(st,”-”); }
{} } }
setcolor(MAGENTA); }
outportb(cont,0x05^0x0b); else
outportb(cont,0x01^0x0b); outtextxy(max-80,may/2+30,”time(msec)”); { e[0]=’0';
outportb(cont,0x05^0x0b); settextstyle(0,1,0); e[1]= ‘0’;
while((inportb(cont)&0x08)==0x00) //converstion outtextxy((max/2)-10,0,”volt(s)”); e[2]=d;
time is approximately 100 µsec scale=atoi(e);
{ setlinestyle(0,0,0); break;
} setcolor(RED); }
moveto(0,may/2); }
outportb(data,0xf0); for(b=0,c=0;b<=number;c+=1, b++) }
a[i]=(inportb(stat)^0x80)&0xf0; { }
outportb(data,0x01); if(e1[b]!=0x08) setcolor(BROWN);
b[i]=(inportb(stat)^0x80)&0xf0; { outtextxy(10,380,”TYPE C TO CHANGE TIME SET-
outportb(data,0xff); lineto(c*times,((may/2)-a1[b])); TINGS”);
} } m=getch();
for(i=0;i<number;i++) else if( m==’c’)
{ { {
a[i]=a[i]>>4; lineto(c*times,((may/2)+a1[b])); cleardevice();
c[i]=a[i]+b[i]; } outtextxy(10,20,”X AXIS 1 unit= 10msec CHANGE
c[i]=c[i]*0.0196*45/scale; } TO x(10msec)”);
} again = getch(); outtextxy(10,40,”TYPE ‘a’ IF x IS (2 to 9) ,’b’ IF x IS
graphics(c,e); closegraph(); (10 to 99) AND ‘c’ IF x IS (.5 TO .9)”);
} restorecrtmode(); switch(getch())
{
} } case ‘a’:
outtextxy(10,60,”x value is ....”);
void graphics(int a1[],int e1[]) void settings() n[0]=getch();
{ { times=atoi(n);
int gd=DETECT,gm,max,may,a,b,c,im,error,get=5; int gd=DETECT,gm,error,max,may,b; itoa(times,n,10);
char c,d,e[2],m,*n; outtextxy(10,70,n);
char str[10],*st=”-”,d; times=1; break;
initgraph(&gd,&gm,”c:\\tc\\bgi”); //default bgi case ‘b’:
clrscr(); directory path outtextxy(10,60,”x value is ....”);
initgraph(&gd,&gm,”c:\\tc\\bgi”); //use error=graphresult(); n[0]=getch();
default bgi path if(error != grOk) n[1]=getch();
error=graphresult(); { times=atoi(n);
if(error != grOk) printf(“Graphics error %s /n”,grapherrormsg(error)); itoa(times,n,10);
{ printf(“PRESS ANY KEY TO EXIT”); outtextxy(10,70,n);
printf(“Graphics error %s /n”,grapherrormsg(error)); getch(); break;
//reports error when exit(1);
} case ‘c’:
//graphics is not set max=getmaxx(); outtextxy(10,60,”x value is...”);
printf(“PRESS ANY KEY TO EXIT”); setbkcolor(LIGHTBLUE); getch();
getch(); settextstyle(1,0,0); n[0]=getch();
exit(1); setcolor(BROWN); times=atoi(n)*0.1;
} outtextxy(max/2-60,20,”SETTINGS”); outtextxy(10,70,”scale decremented”);
setbkcolor(LIGHTCYAN); line(0,60,800,60); break;
setcolor(MAGENTA); setcolor(MAGENTA);
settextstyle(1,0,1); }
settextstyle(0,0,2); outtextxy((max/4)-70,80,”Voltage Scale”); number=800;
max=getmaxx(); settextstyle(0,0,0); if(times<1)
may=getmaxy(); setcolor(BROWN); {number=number/times;
may=may-20; outtextxy(10,120,”DEFAULT :”); }
outtextxy(0,may,”OSCILLOSCOPE”); outtextxy(10,120,” 1 unit = 1 volt”); getch();
settextstyle(0,0,1); setcolor(RED); }
setcolor(BLUE); outtextxy(10,170,”TYPE ‘C’ TO CHANGE AND ‘D’ TO closegraph();
outtextxy(max-200,may+2,”press ‘a’ for next DEFAULT”); restorecrtmode();
sample”); c=getch(); }
if(c==’c’)
ELECTRONICS FOR YOU DECEMBER 2002

CIRCUIT IDEAS
9-LINE TELEPHONE SHARER DWIV

EDI
called subscriber. When the call is estab-
lished, no ring-back tone is heard by the
S.C. calling party. The calling subscriber has
DHURJATI SINHA then to press the asterik (*) button on
the telephone to activate the tone mode
T
his circuit is able to handle nine heard in all the nine telephones (it is (if the phone normally works in dial mode)
independent telephones (using a also possible that the phones will not and dial extension number, say, ‘1’, within
single telephone line pair) lo- work due to higher load), and out of 10 seconds. (In case the calling subscriber
cated at nine different locations, say, nine persons eight will find that the call fails to dial the required extension num-
up to a distance of 100m from each is not for them. Further, one can over- ber within 10 seconds, the line will be
other, for receiving and making outgo- hear others’ conversation, which is not disconnected automatically.) Also, if the
ing calls, while maintaining conversa- desirable. To overcome these problems, dialed extension phone is not lifted within
tion secrecy. This circuit is useful when the circuit given here proves beneficial, 10 seconds, the ring-back tone will cease.
a single telephone line is to be shared as the ring is heard only in the desired The ring signal on the main phone
by more members residing in different extension, say, extension number ‘1’. line is detected by opto-coupler MCT-
rooms/apartments. For making use of this facility, the 2E (IC1), which in turn activates the
Normally, if one connects nine calling subscriber is required to initially 10-second ‘on timer’, formed by IC2
phones in parallel, ring signals are dial the normal phone number of the (555), and energises relay RL10 (6V, 100-
ohm, 2 C/O). One of the ‘N/O’
contacts of the relay has been
used to connect +6V rail to the
processing circuitry and the
other has been used to provide
220-ohm loop resistance to de-
energise the ringer relay in
telephone exchange, to cut off
the ring.
When the caller dials the
extension number (say, ‘1’) in
tone mode, tone receiver
CM8870 (IC3) outputs code
‘0001’, which is fed to the 4-
bit BCD-to-10 line decimal de-
coder IC4 (CD4028). The out-
put of IC4 at its output pin
14 (Q1) goes high and
switches on the SCR (TH-1)
and associated relay RL1. Re-
lay RL1, in turn, connects, via
its N/O contacts, the 50Hz ex-
tension ring signal, derived
from the 230V AC mains, to
the line of telephone ‘1’. This
ring signal is available to tele-
phone ‘1’ only, because half
of the signal is blocked by di-
ode D1 and DIAC1 (which do
not conduct below 35 volts).
As soon as phone ‘1’ is
lifted, the ring current in-
creases and voltage drop
across R28 (220-ohm, 1/2W re-
sistor) increases and operates
opto-coupler IC5 (MCT-2E).
This in turn resets timer IC2
causing:
(a) interruption of the
power supply for processing
circuitry as well as the ring

CIRCUIT IDEAS
SOLIDSTATE SWITCH FOR Hence transistor T2 (pnp) also conducts.

The positive voltage available at the col-
DC-OPERATED GADGETS S.C. DWIV

EDI
lector of transistor T2 is fed back to the
base of transistor T1 via resistor R3. Hence
a latch is formed and transistor T2 (as
PRAVEEN SHANKER also transistor T1) continues to conduct,
which activates gadget 1 and LED1 glows.
Conduction of transistor T2 causes its
T
his solidstate DC switch can be as- from transistor T2 to transistor T1 to keep collector to be pulled towards positive rail.
sembled using just three transistors this transistor pair in latched state (on/ Since the collector of T2 is connected to
and some passive components. It off), while the state of the third transistor the base of pnp transistor T3, it causes
can be used to switch on one gadget while stage is the complement of transistor T2’s transistor T3 to cut off, switching off the
switching off the second gadget with mo- conduction state. supply to gadget 2) as well as extinguish-
mentary operation of switch. To reverse Initially when switch S3 is closed, both ing LED2. This status is maintained until
the operation, you just have to momen- transistors T1 and T2 are off, as no for- switch S2 is momentarily pressed. Depres-
tarily depress another switch. ward bias is available to these, while the sion of switch S2 effectively grounds the
The circuit operates over 6V-15V DC base of transistor T3 is effectively grounded base of transistor T1, which cuts off and
supply voltage. It uses positive feedback via resistors R8 and R6 (shunted by the thus virtually opens the base-emitter cir-
load of the first cuit of transistor T2 and thus cutting it
gadget). As a re- off. This is the same condition as was ob-
sult, transistor T3 tained initially. This condition can be re-
is forward biased versed by momentarily pressing switch S1
and gadget 2 gets as explained earlier.
the supply. This EFY lab note. During testing, it was
is indicated by noticed that for proper operation of the
glowing of LED2. circuit, gadget 1 must draw a current of
When switch more than 100 mA (i.e. the resistance of
S1 is momentarily gadget 1 must be less than 220 ohms) to
depressed, T1 sustain the latched ‘on’ state. But this stipu-
gets the base lation is not applicable for gadget 2. A
drive and it maximum current of 275 mA could be
grounds the base drawn by any gadget.
of transistor T2 The total cost of this circuit is around
via resistor R4. Rs 30.

CIRCUIT IDEAS
ELECTRONIC SECURITY SYSTEM S.C. DWI

VED
I
K. BHARATHAN output of
t h e
T
his reliable and easy-to-operate elec- Darlington
tronic security system can be used pair drives
in banks, factories, commercial es- the loud-
tablishments, houses, etc. speaker
The system comprises a monitoring sys- whose out-
tem and several sensing zones. Each sens- put volume
ing zone is provided with a closed-loop can be con-
switch known as sense switch. Sense trolled by
switches are fixed on the doors of premises potentiom-
under security and connected to the moni- eter VR1.
toring system. As long as the doors are Capacitor
closed, sense switches are also closed. The C1 serves
monitoring system can be installed at a as a filter
convenient central place for easy operation. capacitor.
Fig. 1 shows the monitoring circuit Y o u
only for zone 1 along with the common can alter
alarm circuit. For other zones, the the alarm
monitoring circuit is identical, with only sound as
the prefixes of components changing desired by
as per zone number. Encircled points A, changing
B, and C of each zone monitoring circuit the con-
need to be joined to the corresponding nections of
points of the alarm circuit (upper half IC1 as
of Fig. 1). shown in
When zone 1 sensing switch S11, zone the table.
on/off slide switch S12, and system on/off T h e
switch S1 are all on, pnp transistor T12 circuit con-
reverse biases to go in cut-off condition, tinues to
with its collector at around 0 volt. When sound the
the door fitted with sensor switch S11 is alarm until
opened, transistor T12 gets forward biased zone door Fig. 1: Monitoring circuit along with the alarm circuit
and it conducts. Its collector voltage goes
high, which forward biases transistor T10
via resistor R10 to turn it on. (Capacitor
C10 serves as a filter capacitor.) As a re-
sult, the collector voltage of transistor T10
falls to forward bias transistor T11, which
conducts and its collector voltage is sus-
tained at a high level. Under this latched
condition, sensor switch S11 and the state
of transistor T12 have no effect. In this
state, red LED11 of the zone remains lit.
Simultaneously, the high-level voltage
from the collector of transistor T11 via di-
ode D10 is applied to VDD pin 5 of siren
sound generator IC1 (UM3561) whose pin
2 is grounded. Resistor R3 connected across
pins 7 and 8 of IC1 determines the fre-
Fig. 2: Physical layout of sensors and monitoring/alarm system
quency of the in-built oscillator. As a re-
sult, IC1 starts generating the audio signal is closed (to close switch S11) and the The system operates off a 3V DC bat-
output at pin 3. The output voltage from reset switch is pressed momentarily (which tery or recharging battery with charging
IC1 is further amplified by Darlington pair causes transistor T10 to cut off, returning circuit or battery eliminator. If desired,
of transistors T1 and T2. The amplified the circuit to its initial state). more operating zones can be added.

CIRCUIT IDEAS
Alarm sound Circuit connections for respective ing to the zone glows to indicate that the
zones in closed door of the zone is open. The alarm and
IC pin 1 connected to IC pin 6 connected to position. Also the LED indication will continue even af-
Police siren NC NC keep zone slide ter that particular door with the sensing
Ambulance siren NC VDD switches S12, S22, switch is immediately closed, or even if
Fire engine Sound NC VSS S32, S42, etc in that switch is removed/damaged or con-
Machinegun sound VSS NC ‘on’ position. This necting wire is cut open.
puts the system in Any particular zone in the monitoring
Note. NC indicates no connection
operation, guard- system can be put to operation or out of
ing all the zone operation by switching on or switching off
Initially keep the monitoring system doors. the corresponding slide switch in the moni-
switch S1 off. Keep all the zone doors fixed Now, if the door of a particular zone toring system.
with sensing switches S11, S21, S31, S41, is opened, the monitoring system sounds The circuit for monitoring four zones
etc closed. This keeps the sensing switches an audible alarm and the LED correspond- costs around Rs 400.

CIRCUIT IDEAS
HOUSE SECURITY SYSTEM IL KU

MAR nected at the output.
SUN The receiver unit comprises two iden-
MALAY BANERJEE tical step-down transformers (X1 and X2),
two 6V relays (RL1 and RL2), an LDR, a
transistor, and a few other passive com-
H
ere is a low-cost, invisible laser for generating a laser beam.
circuit to protect your house A combination of plain mir-
from thieves or trespassers. A rors M1 through M6 is used
laser pointer torch, which is easily avail- to direct the laser beam
able in the market, can be used to oper- around the house to form a
ate this device. net. The laser beam is di-
The block diagram of the unit shown rected to finally fall on an
in Fig. 1 depicts the overall arrangement LDR that forms part of the
for providing security to a house. A laser receiver unit as shown in Fig.
torch powered by 3V power-supply is used 2. Any interruption of the
beam by a thief/ ponents. When switches S1 and S2 are
trespasser will re- activated, transformer X1, followed by a
sult into full-wave rectifier and smoothing capaci-
energisation of tor C1, drives relay RL1 through the la-
the alarm. The ser switch.
3V power-supply The laser beam should be aimed con-
circuit is a continuously on LDR. As long as the laser
ventional full- beam falls on LDR, transistor T1 remains
wave rectifier-fil- forward biased and relay RL1 is thus in
ter circuit. Any energised condition. When a person
alarm unit that crosses the line of laser beam, relay RL1
operates on 230V turns off and transformer X2 gets
AC can be con- energised to provide a parallel path across
N/C contact and the pole of relay RL1.
In this condition, the laser beam will have
no effect on LDR and the alarm will con-
tinue to operate as long as switch S2 is
on.
When the torch is switched on, the
pointed laser beam is reflected from a defi-
nite point/place on the periphery of the
house. Making use of a set of properly
oriented mirrors one can form an invis-
ible net of laser rays as shown in the
block diagram. The final ray should fall
on LDR of the circuit.
Note. LDR should be kept in a long
pipe to protect it from other sources of
light, and its total distance from the
source may be kept limited to 500 metres.
The total cost of the circuit, including the
laser torch, is Rs 400 or less.

CIRCUIT IDEAS
SONG NUMBER
DISPLAY SAN
I THE
O
PRABHASH K.P.
H
ere’s a circuit to display the song number in an audio
system for quick reference to songs. It also serves the
purpose of an extra visual indicator in modern audio
systems.
When the power is switched on, the power-on-reset cir-
cuit comprising 3.3k resistor R20 and 1µF, 25V capacitor C6
resets the counters, showing ‘00’ in the display. One can also
reset the display to zero at any time by pressing reset switch
S1.
When the first song starts playing, the output pins of IC1
(KA2281) go low and capacitor C5 starts charging. This for-
ward biases transistor T1 and hence the input to IC3 at pin 1
goes to high state. As a result, the output of the counter goes
to the next state, showing 01 on the display. The counter
remains in this state until the song is completed.
During the time gap before the next song starts playing,
capacitor C5 discharges. After discharging of capacitor C5,
the input to IC3 becomes low again. When the song starts,
the process described above is repeated and the display shows
02. You can adjust VR3 to change the time gap setting. This
must be set such that the circuit doesn’t respond to short
gaps, if any, within a song and responds only to long gaps
between different songs.
Transistor T2 helps in gap-delay adjustment. The inten-
sity of LED11 diminishes when a song is completed and the
counter is ready to accept the next pulse.
Connect the input to the preamp output or equaliser out-
put of the audio system. Adjust VR1 and VR2 to get the
correct audio-level indication. If you are already using KA2281
for audio-level indication, just connect diodes D1 and D2 as
shown in this circuit.
Note that the counter counts the songs by detecting the
gaps. Therefore any long gap within a song may cause false
triggering and the display will also be incremented. However,
as this is very unlikely to happen, the circuit shows the
correct song number almost all the time.
The circuit costs around Rs 100.

CIRCUIT IDEAS
SPELLER EFFECT
high, transistor T1 goes off and its out-
put at the collector goes low. Since the
EDI emitter of transistor T2 is connected to
DWIV
SIGN DISPLAY
S.C. the collector of transistor T1, and collec-
tor and emitter terminals of transistors
T1 through T9 are connected in series,
all transistors next to transistor T1, i.e.
VIJAYA KUMAR P. transistors T2 through T9, do not get sup-
ply and hence all their outputs go low.
T
he circuit described here uses low- CD4017 is a decade counter having Next, when Q1 output goes high, tran-
cost and easily available IC ten outputs, of which one output is high sistor T2 goes off. Thus outputs of tran-
CD4017 to produce a speller type for each clock pulse. However, this pro- sistors T2 through T9 remain low. Since
light display. In such displays, each let- duces running lights effect. To change this Q0 output at this instant is low, transis-
ter of the sign sequentially lights up, one sequence to get the speller effect, pnp tor T1 is forward biased and its output
after the other, until all letters are glow- transistors T1 through T9 are wired as goes high to light up the first character.
ing. After a few seconds, the letters switch shown in the figure. Nine triacs (triac 1 Similarly, when Q2 output goes high,
off and the cycle repeats. This circuit pro- through triac 9) are used to drive 230V Q0 and Q1 outputs are low and therefore
vides a maximum of nine channels and bulbs. (In place of 230V bulbs, miniature outputs of transistors T1 and T2 go high
therefore can be used to spell a word or lamps connected in series in the form of to light up the first and second characters.
sign having up to nine characters. characters or letters can also be used, pro- This process continues until all tran-
Timer IC1 (555) is configured in vided the voltage drop across the series sistors turn on, making all the characters
astable mode to produce clock signal for combination is 230 volts.) to light up. The cycle repeats endlessly,
triggering IC2 (CD4017). Speed of switch- When any of the outputs of IC2 goes producing the speller type light effect.
ing on the display can be controlled by high, the corresponding transistor con-
varying preset VR1. nected to the output goes off. When Q0 is
ELECTRONICS FOR YOU ❚ NOVEMBER 2001

CIRCUIT IDEAS
STEREO TAPE HEAD PREAMPLIFIER other audio device as well.

When the preamplifier is in ‘off’ state,
switching relay RL1 is off and it allows
FOR PC SOUND CARD SUN

IL KU
MAR
connection of external signals to the sound
card. When the preamplifier is turned ‘on’,
the relay is energised by transistor T3
after a short delay determined by the val-
T.K. HAREENDRAN ues of resistor R21 and capacitor C23. On
energisation, the relay contacts
H
ere is a stereo tape head pream- The amplified and equalised signals changeover the signals to internal source,
plifier circuit for your PC sound available at output pins 3 and 6 of IC1 i.e. the head preamplifier.
card that can playback your are coupled to the inputs of line amplifier After constructing the whole circuit
favourite audio cassette through the PC. circuit built around transistors T1 (via ca- on a veroboard, enclose it in a mini me-
Audio signals from this circuit can be di- pacitor C5, potmeter VR1, resistor R8, and tallic cabinet with level controls and sock-
rectly connected to the stereo-input (line- capacitor C12) and T2 (via capacitor C10, ets at suitable points. Use a regulated
input) socket of the PC sound card for potmeter VR2, resistor R19, and capaci- 1A, 12V DC power supply for powering
further processing. tor C16), respectively. Left and right play- the whole circuit including the tape deck
The circuit is built around a popular back levels can be adjusted by variable mechanism. (A 1A, 18V AC secondary
stereo head preamp IC LA3161. Weak resistors VR1 and VR2. The audio signals transformer with 4700µF, 40V electrolytic
electrical signals from the playback heads are finally available at the negative ends capacitor and 78M12 regulator is suffi-
are fed to pins 1 and 8 of IC1 via DC of capacitors C13 and C17. cient.)
decoupling capacitors C1 and C6, respec- The circuit wired around relay driver You can use any kind of tape deck
tively. Components between pins 2 and 3 transistor T3 serves as a simple source mechanism with this circuit. Use of good-
and pins 6 and 7 provide adequate selector. This is added deliberately to help quality playback head and well-screened
equalisation to the signals for a normal the user share the common PC sound card wires are recommended.
tape playback. line-input terminal for operating some
ELECTRONICS FOR YOU ❚ OCTOBER 2001

CIRCUIT IDEAS
LEAD-ACID BATTERY CHARGER WITH SAN

I THE
O
VOLTAGE ANALYSER
D. MOHAN KUMAR The charger circuit consists of a stan- comprising resistors R1 through R5. Thus
dard step-down 12V AC (2-amp) trans- the voltage applied to any non-inverting
N
owadays maintenance-free lead-acid former and a bridge rectifier comprising input is the ratio of the resistance between
batteries are common in vehicles, diodes D1 through D4. Capacitor C1 that non-inverting terminal and ground to
inverters, and UPS systems. If the smoothes the AC ripples to provide a clean the total resistance (R1+R2+R3+R4+R5).
battery is left in a poor state of charge, its DC for charging the battery. The resistor chain provides a positive volt-
useful life is shortened. It also reduces the The battery voltage analyser circuit is age of above 5V to the non-inverting inputs
capacity and rechargeability of the battery. built around the popular quad op-amp of all op-amps when battery voltage is 12.5V
For older types of batteries, a hygrometer LM324 that has four separate op-amps (A or more. A reference voltage of 5V is ap-
can be used to check the specific gravity through D) with differential inputs. Op- plied to the inverting inputs of op-amps via
of the acid, which, in turn, indicates the amps have been used here as compara- 5V zener diode ZD1.
charge condition of the battery. However, tors. Switch S2 is a pushswitch, which is When the circuit is connected to the
you cannot use a hygrometer for sealed- pressed momentarily to check the battery battery and pushswitch S2 is pressed (with
type maintenance-free batteries. The only voltage level before charging the battery. S1 open), the battery voltage is sampled
way to know their charge level is by check- The non-inverting terminals of op-amps by the analyser circuit. If the supply volt-
ing their terminal voltage. A through D are connected to the positive age sample applied to the non-inverting
The circuit presented here can replen- supply rail via a potential divider chain input of an op-amp exceeds the reference
ish the charge in a battery within 6-8 hours. voltage applied
It also has a voltage analysing circuit for Battery voltage Status of LEDs Comments to the invert-
quick checking of voltage before start of Red Green Yellow Orange ing inputs, the
charging, since overcharging may damage output of the
the battery. The voltage analyser gives an <9.8V Off Off Off Off Buzzer off
op-amp goes
audio-visual indication of the battery volt- >9.8V On Off Off Off Danger level
high and the
age level and also warns about the critical 11.5V On On Off Off Low level
LED connected
voltage level at which the battery requires 12.0V On On On Off Normal level
at its output
immediate charging. 12.5V On On On On High level
lights up.

CIRCUIT IDEAS
The different levels of battery voltages 9.8V. If the voltage level goes below 9.8V, wire and crocodile clips to connect the
are indicated by LED1 through LED4. All the buzzer goes off, which indicates that charger to the battery. A 2.5-amp fuse con-
the LEDs remain lit when the battery is it’s time to replace the battery. The status nected to the output of the charger pro-
fully charged (above 12.5V). The buzzer of LEDs for different battery voltages is tects the analyser circuit against acciden-
connected to the output of IC1 also sounds shown in the table. tal polarity reversal.
(when S2 is pressed with S1 kept open) as The circuit can be assembled on a gen- The circuit costs around Rs 120 with
long as the voltage of battery is above eral-purpose PCB or a veroboard. Use 4mm all accessories.

CIRCUIT IDEAS
THREE-COLOUR DISPLAY USING S.C.

DWI
VED
I
BICOLOUR LEDs
PRIYANK MUDGAL
T
he circuit presented here uses
bicolour LEDs to generate a dis-
play in three colours, namely, red,
green, and yellowish green.
Transistors T1 through T20 form a grid
to which common-cathode bicolour LEDs
(LED1 through LED10) are connected.
Transistors T1 through T10 have their col-
lector terminals connected to the emitter
of transistor T21. Similarly, transistors T11
through T20 have their collector terminals
connected to the emitter of transistor T22.
The bases of each pair of transistors (i.e.
T1 and T11, T2 and T12,…, T10 and T20)
are tied to outputs Q0, Q1,…, Q9, respec-
tively, of IC1 (CD4017) through 10-kilo-
ohm resistors as shown in the figure. Posi-
tive supply to collectors of transistors T1
through T10 is controlled by transistor T21.
Similarly, positive supply to collectors of
transistors T11 through T20 is controlled
by transistor T22.
IC1 and IC2 are decade counters. Clock
pulse to IC1 is provided by the oscillator
circuit comprising NOR gates N1 and N2.
The outputs of IC1 advance sequentially
with each clock. (Any other source of
squarewave pulses also serves the pur-
pose.) IC2 is used to select the mode of
display. Clock input pin 14 of IC2 is con-
nected to Q9 output of IC1. Thus IC2 re-
ceives one pulse after every ten pulses re-
ceived by IC1.
When the circuit is switched on, Q0
output of IC2 is active high. Thus transis-
tor T21 gets forward biased via diode D3
and it conducts to extend positive supply
to transistors T1 through T10. Transistors
T1 through T10 are forward biased sequen-
tially by Q0 through Q9 outputs of IC1,
i.e. at a time only one of these ten transis-
tors is forward biased (on). Thus only red
LED parts of bicolour LEDs light up se- After completion of the third glowing Now both transistors T21 and T22 con-
quentially. (Transistor T22 is not conduct- sequence of red LEDs, when Q3 output of duct due to diodes D1 and D2. Thus both
ing at this moment.) IC2 goes high, transistor T21 stops con- red and green LEDs in bicolour LEDs (LED1
When red LED part of LED10 glows, ducting and T22 starts conducting with the through LED10) glow sequentially. The ef-
IC2 receives a clock pulse and its Q1 output next three sequences of green LEDs of fect of red and green LEDs glowing to-
goes high. Transistor T21 still conducts, as bicolour LEDs (LED1 through LED10) gether is a distinct yellowish orange colour.
it is forward biased through diode D6, and glowing sequentially. This sequence repeats four times.
next again via diode D5. Thus red LEDs After completion of three sequences of Thereafter, the whole sequence repeats,
complete two more glowing sequences. green LEDs, output Q6 of IC2 goes high. starting with red LEDs. Thus the bicolour-
ELECTRONICS FOR YOU FEBRUARY 2003

CIRCUIT IDEAS
LED display shows three colours—red, green, by preset VR1. One can omit automatic 5, and 7 of IC2 with SPDT switches. (Thus
and yellowish green—one after the other. selection of different colours by omitting diodes D3-D12 are also omitted.)
The speed of display can be controlled IC2 and replacing connections to pins 3, This circuit costs around Rs 250.
FEBRUARY 2003 ELECTRONICS FOR YOU

CIRCUIT IDEAS
ULTRA-BRIGHT LED LAMP S.C.

DWI
VED
I
N.S. HARISANKAR VU3NSH
T
his ultra-bright white LED lamp
works on 230V AC with minimal
power consumption. It can be used
to illuminate VU meters, SWR meters, etc.
Ultra-bright LEDs available in the mar-
ket cost Rs 8 to 15. These LEDs emit a
1000-6000mCd bright white light like weld-
ing arc and work on 3 volts, 10 mA. Their
maximum voltage is 3.6 volts and the cur-
rent is 25 mA. Anti-static precautions
should be taken when handling the LEDs. Fig. 1: The circuit of ultra-bright white LED Fig. 2: 16-LED combination
The LEDs in water-clear plastic package lamp
whereas no power is dissipated in a ca- Use AC capacitors for Cx. Filter capaci-
pacitor. The value of capacitor is calcu- tor C1 across the output provides flicker-
lated by using the following relationships: free light. The circuit can be enclosed in a
XC = 1/(2πfC) ohms —————(a) CFL round case, and thus it can be con-
XC = VRMS /I ohms ———— (b) nected directly to AC bulb holder socket. A
where XC is capacitive reactance in ohms, series combination of 16 LEDs (Fig. 2) gives
C is capacitance in farads, I is the current a luminance (lux) equivalent of a 12W
through the LED in amperes, f is the mains bulb. But if you have two series combina-
frequency in Hz, and Vrms is the input tions of 23 LEDs in parallel (total 46 LEDs
mains voltage. as shown in Fig. 3), it gives light equal to a
The 100-ohm, 2W series resistor avoids 35W bulb. 15 LEDs are suitable for a table-
Fig. 3: 46-LED combination heavy ‘inrush’ current during transients. lamp light.
MOV at the input prevents surges or spikes, Diode D1 (1N4007) and capacitor C1
emit spotlight, while diffused type LEDs protecting the circuit. The 390-kilo-ohm, act as rectifying and smoothing elements
have a wide-angle radiation pattern. ½-watt resistor acts as a bleeder to pro- to provide DC voltage to the row of LEDs.
This circuit (Fig. 1) employs capaci- vide discharge path for capacitor Cx when For a 16-LED row, use Cx of 0.22 µF, 630V;
tive reactance for limiting the current flow mains supply is disconnected. The zener C1 of 22 µF, 100V; and zener of 48V, 1W.
through the LEDs on application of mains diode at the output section prevents ex- Similarly, for 23+23 LED combination use
voltage to the circuit. If we use only a cess reverse voltage levels appearing across Cx of 0.47 mF, 630V; C1 of 33 µF, 150V;
series resistor for limiting the current with the LEDs during negative half cycles. Dur- and zener of 69V, 1W.
mains operation, the limiting resistor itself ing positive half cycle, the voltage across This circuit (inclusive of LEDs) costs
will dissipate around 2 to 3 watts of power, LEDs is limited to zener voltage. Rs 200 to Rs 400.
FEBRUARY 2003 ELECTRONICS FOR YOU

CCI IR R
C UCI U
T II TD E IAD
S EAS
VERSATILE EMERGENCY LIGHT USING S.C.

DWI
VED
I
FLUORESCENT TUBES
VIVEK KALKUR M.
E
mergency lights using incandescent
bulbs are inherently inefficient com-
pared to those using fluorescent
tubes. Here’s a versatile emergency light
using fluorescent tubes. You can operate
it using readymade SUNCA or similar other
inverter transformers, which are readily
available in the market for around Rs 25.
With this circuit you can drive two 6W,
22.8cm (9-inch) fluorescent tubes, with
the option to use a single tube or a pair
of tubes with the help of DPDT switch
S2.
Step-down transformer X1, diodes D1-
D4, capacitor C1, and 5V regulator IC1
(7805) form a regulated power supply. A
2.7V zener (ZD1) in common terminal of
the regulator props up the output voltage
to 7.7 volts. The regulated voltage is ap-
plied to the battery through diodes D6 and
D7, which cause a drop of about 1.4V
across them. Thus the effective charging
voltage is about 6.3V, which prevents over-
charging of the battery as the terminal volt-
age of the battery cannot exceed 6.3V.
When AC mains supply is present, the
battery starts charging and green LED1
glows to indicate the same. Diode D5 re-
verse biases transistor T1 forming part of
the inverter oscillator and thus the tubes An on/off switch (S1) is used to switch off vent it from thermal runaway. For good
don’t glow. the light when it is not required. illumination, use Toshiba’s FL6D fluores-
When mains supply fails, transistor T1 D882 (actually, 2SD882) is an npn cent tubes.
starts oscillating and supplies power to in- power transistor in TO-126 package. It is The circuit (excluding the cabinet)
verter transformer X2 and the tubes glow. mounted on a suitable heat-sink to pre- costs around Rs 350.

CIRCUIT IDEAS
CLAP-BASED SWITCHING FOR DEVICES S.C.

DWI
VED
I
MANOJ KUMAR SAHA filtering is performed by capacitors C5 Diodes D5 and D6 and capacitor C11
through C8 to get +12V, 0V (Gnd) and form the detector circuit. Resistor R6 is
I
t is quite difficult to find the switch –12V DC required for the operation of the used here for quick discharge of capacitor
board in a dark room to turn on the circuit. C10. The detected clap signal is used to
light. Here’s a clap switch that allows The clap sound impulses are converted switch on transistor T1. On conduction of
you to switch on lights, fans, and into electrical signals by a condenser mi- transistor T1, its collector voltage falls to
motors sequentially by just clapping in crophone that forms a Wheatstone bridge trigger timer IC4 connected as a
the vicinity of the microphone used in the together with resistors R4, R5, and R3. monostable. The combination of resistor
circuit. The microphone is suitably biased through R9 and capacitor C12 determine the
The mains supply is stepped down to resistor R3. The output of the microphone pulsewidth of the monostable (about one
15-0-15V AC by step-down transformer is coupled to op-amp IC 741 (IC3) having second, with the component values
X1. The output of the transformer is recti- a voltage gain of 45. The output of IC3, shown).
fied, filtered, and regulated by diodes D1 after passing through capacitor C10, is AND gate IC5 (4081) is used as a buffer
through D4, capacitors C1 through C4, free from any DC component of signal. between the output of IC4 and clock input
and IC1 (regulator IC 7812) and IC2 (regu- Capacitors C15 and C17 are used for spike to decade counter IC6 (CD4017). Thus each
lator IC 7912), respectively. Additional and surge suppression. clap causes outputs of IC6 to advance in
sequential manner
and switch on the
corresponding de-
vices.
If you want a
lamp to be switched
on when output Q1
goes high (after first
clap), then in place
of R11 and LED2 use
a relay driver circuit
at Q1 output similar
to that used for Q2
output (for fan).
As stated earlier,
only one output of
CD4017 can be high
at any given time.
Thus first clap causes
LED1 to go off and
LED2 to glow. The
second clap causes
only the fan to
switch on via relay
RL1. The third clap
causes the miniature
12V motor to run. On
fourth clap, Q4 out-
put goes high mo-
mentarily to reset IC6
since Q4 output is
connected to its re-
set pin 15. In reset
state, LED1 con-
nected to Q0 output
lights up.
The circuit costs
around Rs 150.

DIY Kit 130. Door Minder
INTRODUCTION The oscillators are made using a 4093 quad 2-input
This kit uses an infrared (IR) beam to monitor door & NAND gate IC. One gate, IC1:D, is used for the 250Hz
passage-ways or any other area. When the beam is broken oscillator. Resistor R1 and capacitor C1 set the frequency.
a relay is tripped which can be used to sound a bell or Another pair of gates, IC1:A and IC1:B, make up the
alarm. Suitable for detecting customers entering a shop, 38KHz oscillator. Resistors R2 and R3 and capacitor C2
cars coming up a driveway, etc. The IR beam is very set the frequency. Gate IC1:C “ANDs” these signals
strong. Distances over 25 yards can be monitored with this together.
Kit. A 12VDC unregulated supply is required to power
the kit. A 12V wall adaptor is fine. Provision has been Transistor Q1 provides a constant current source for the
made so that only one power supply needs to be used to IR LED. The zener, Z1, on the base of Q1 keeps the
power both units. The relays in this kit are rated to switch emitter at a constant voltage. Therefore the voltage across
mains voltages. R6 is also constant. For the values shown the current
through the LED, when on, is fixed at approx. 85mA. The
The kit is constructed on single-sided printed circuit peak current through the LED is set by R7 and detemines
board. Protel Autotrax & Schematic were used in the the range of the kit. Reduce it to say 22R to get greater
design. range if needed.
CONSTRUCTION Receiver Board

The kit is built on two separate PCBs – a transmitter PCB The receiver consists of an IR receiver module that
(K130T) and a receiver PCB (K130R). Refer to the parts detects the incoming IR beam. The IR signal is used to
list to see which components belong to which board. Use keep a capacitor charged which in turn holds a relay
the component overlay on each PCB to place the operated. When the beam is broken the capacitor
components. discharges and the relay releases.
Transmitter board The IR detector module, RX1, is made up of an IR LED

Insert the lowest height components first. Leave the and an amplifier/filter circuit tuned to detect a 38KHz
infrared LED and power jack until last. Make sure that the frequency. The output pin is low whenever a 38KHz
electrolytic capacitor and diode are inserted correctly. A signal is detected.
socket is supplied for the IC.
When the IR beam is present the relay is operated.
The IR LED can be mounted vertically or at right angles
to the PCB. This will depend on how the transmitter will The output of RX1 is the 250Hz signal from the
be mounted when in use. In either case the LED must be transmitter. This signal is passed via transistor Q1,
inserted the right way round. The flat edge on the LED capacitor C1and diode D2 to capacitor C2.
should line up with the flat edge on the PCB overlay.
C2 is fully charged during the high portion of the signal. It
Lastly, if the distance to be monitored is less than about starts to discharge during the low portion of the signal via
10 yards then you will need to fit the 5mm tubing over the LED L1, resistor R4 and transistor Q2. However the
IR LED. This narrows the radiating angle of the IR beam discharge time is much longer than the off time of the
and makes it much more directional. The IR output is signal so the voltage across C2 is always enough to keep
strong. It can easily bounce off walls etc to give false transistor Q2 on and therefore the relay operated.
readings.
When the beam is broken the output of RX1 is high.
Receiver board Transistor Q1 is off and capacitor C2 is no longer being
As with the transmitter board, start with the lowest height recharged. It will eventually discharge to the point where
components first - resistors, diodes, capacitors and transistor Q2 will turn off and the relay will release.
transistors. Note the polarity of the electrolytic capacitors
and diodes. Next insert the screw terminal block, power The “turn off” delay is determined by the time constant of
jacks and relay. Last of all is the infrared receiver module. resistor R5 and capacitor C3. With the values used it is
The orientation is clearly shown on the PCB overlay. approximately half a second.
CIRCUIT DESCRIPTION Capacitor C1 prevents a steady DC voltage on the

Transmitter Board collector of Q1 from charging C2. This would occur if the
The transmitter board consists of two oscillators, one beam was not present or the beam was a continuous
running at approx. 250Hz and the other running at 38KHz signal. In other words, the receiver module will
38KHz. The 38KHz frequency acts as a carrier wave and only respond to a pulsed 38KHz signal.
is required by the IR receiver module on the receiver
board. This carrier wave is “ANDed” or modulated with LED L1 gives a visual indication when the IR beam is
the 250Hz frequency to produce an output signal that present and is used to help with installation and setup. It
contains bursts of 38KHz at a rate of 250Hz. This signal can, of course, be removed if it is not wanted.
is used to drive an infrared LED.
PAGE 1
Zener diode Z1, resistor R6 and capacitor C4 provides a PARTS LIST – K130
stable 5.6V supply for the IR module. The relays provided Transmitter board
with this kit are mains rated but use with care. RUDH Resistors (0.25W carbon)
110V/10A; RWH 250V/12A, 120VAC/15A. 47 yellow violet black........ R6 ................................. 1
1K brown black red ............ R5 ................................. 1
INSTALLATION 1K8 brown grey red ............ R3 ................................. 1
For ease of operation, the transmitter board can be 6K8 blue grey red ............... R2 ................................. 1
powered from the receiver board when they are relatively 47K yellow violet orange.... R1,4 .............................. 2
close together. Two plugs have been supplied for this. Capacitors
Connecting wire for the length required must be supplied 1nF ceramic 102 ................ C2 ................................. 1
by you. Otherwise two separate power supplies are 100nF monobloc 104 ......... C1 ................................. 1
required. 100uF 25V electrolytic ....... C3 ................................. 1
Semiconductors
The receiver board contains two DC jacks connected in 4.7V 400mW zener diode... Z1.................................. 1
parallel. Power from a 12VDC source is connected to one BC557 transistor, PNP........ Q1 ................................. 1
jack. A lead can then be connected to the other jack and 4093 CMOS IC................... IC1 ................................ 1
run to the transmitter board. DC plugs to make up a lead Quad 2-input NAND with schmitt trigger inputs
are supplied with the kit. IR LED, EL-1L7................. L1.................................. 1
Miscellaneous
Aligning the transmitter and receiver is simply a matter of 2.5mm DC jack................... X1 ................................. 1
pointing the transmitter IR LED at the receiver board and Tubing, 5mm x 25mm long to fit over L1................. 1
moving it around until the red LED on the receiver board PCB, K130T .............................................................. 1
lights. This indicates that the beam is being received. The
relay will be operated. Receiver Board
Resistors (0.25W carbon)
Note: 470 yellow violet brown ..... R3,6 .............................. 2
With power applied the relay is normally operated and 6K8 blue grey red ............... R1,2,4 ........................... 3
only releases when the beam is broken. The relay contacts 47K yellow violet orange.... R5 ................................. 1
labelled “NO” (Normally Open) and “NC” (Normally Capacitors
Closed) refer to when the relay is released. 10uF 16V electrolytic ......... C1,2,3 ........................... 3
100uF 25V electrolytic ....... C4,5 .............................. 2
With the relay operated, the “NO” contact will be Semiconductors
connected to the “C” contact and the “NC” contact will be 1N4148 signal diode........... D1,2 .............................. 2
unconnected. 1N4004 power diode .......... D3 ................................. 1
5.6V 400mW zener diode... Z1.................................. 1
IF IT DOES NOT WORK BC547 transistor, NPN ....... Q2 ................................. 1
Poor soldering (“dry joints”) is the most common reason BC557 transistor, PNP........ Q1 ................................. 1
that the circuit does not work. Check all soldered joints LED, 5mm red .................... L1.................................. 1
carefully under a good light. Re-solder any that look IR receiver module ............. RX1 .............................. 1
suspicious. Check that all components are in their correct PIC-12043S
position on the PCB. Are the electrolytic capacitors and Miscellaneous
diodes the right way round? Have you fitted the 5mm 2.5mm DC jack................... X1,2 .............................. 2
tubing over the IR LED on the transmitter board? Terminal block, 3-way........ X3 ................................. 1
Relay, 12V SPDT ............... RL1 ............................... 1
Web Address & Email “Goodsky” RWH-SH-112D, or RUDH-SS-112D
You can email us at [email protected] PCB, K130R .............................................................. 1
See our website at Extras
http://kitsrus.com 2.5mm DC plugs ........................................................ 2
This is an improved (natually!) version of the door minder (to make up optional power lead to the transmitter board)
published in Silicon Chip, april, 1999. It was developed
originally by Oatley Electronics.
PAGE 2
Door Minder - Receiver Module
Door Minder - Transmitter Module
PAGE 3
Kit 49. ULTRASONIC MOVEMENT DETECTOR II
This is our second ultrasonic movement detector circuit. It slower so that it will follow this envelope. All the
also uses a crystal locked circuit to get maximum amplifiers are AC coupled to prevent DC bias problems.
performance from the ultrasonic transmitter. However, the
detection circuit is different. We think it is more sensitive. Then the signal is fed through a window detector IC1:C
which detects both positive and negative pulses. When
ASSEMBLY INSTRUCTIONS there is no movement the potential at pin 7 sits at half the
Check all the components against the parts list. It is supply potential and neither D2 or D3 can conduct. The
generally easier to solder in the lowest height components potential at pin 8 is low. If the signal rises D3 conducts
first - the resistors and diodes. Make sure to get the diodes causing the output to go high. If the signal falls then D2
in the correct way. The black circle or band on the diodes conducts which also causes the output to go high. Thus the
must match the bar of the diode symbol on the overlay. name window detector circuit because it detects potentials
There are a lot of resistors. Use the resistor color code which move both below and above a given range.
printed on the back of the header card to work out each
value. A low pass filter screens out unwanted spurious signals,
then an amp IC1:D set up as a monostable flip flop
The 40 kHz crystal can be inserted either way. Holes have converts any signal that gets through the filter into a
been provided to secure its case to the PCB. Use one of the substantial pulse to turn on the BC639. This turns on the
leads cut from the resistors. You can also quickly solder LED and provides a Signal Out to drive a separate relay or
the wire to the case of the crystal. any other device you may wish to signal to. The time
constant of the monostable flip-flop is about half a second
The ultrasonic transmitter has a T suffix on the number and is set by C8 & R10. D4 is used to separate the charge
stampedunderneath it. The receiver has an R suffix. Each & discharge time constants. It lets the circuit switch on
may be soldered either way around on the pads under the immediately movement is detected but allows about a 1/2
PCB. Make sure to get them both pointing straight out at second delay for the reset.
90o from the PCB.
WHAT TO DO IF IT DOES NOT WORK
CALIBRATION Poor soldering is the most likely reason. Check all solder
Battery operation is not recommended for this detector. As joints carefully under a good light. Next check that all
the battery potential decreases the sensitivity will change. components are in their correct position on the PCB.
This is partcuarly so if the unit is triggered often (as in Thirdly, follow the track with a voltmeter to check the
detecting a door opening.) It is better to use a power potential differences at various parts of the circuit.
supply. Use 9V to 12V DC. You could go to a maximum
of 15V but you may have to replace the 78L05 by a 7805. Other items to check; are the IC's in the correct way. Check
no IC pins are bent up. Are the diodes, transistors and the
Immediately after you connect the power let the unit stand electrolytic capacitor in the correct way. Did you mix up
for at least 20 seconds so whole circuit will settle down the 78L05 with the BC639? Check the values of the
electrically. The schematic shows that the setting of the resistors.
trimpot value is critical to the operation of the detector. We
provide a 1M trimpot. Set it to about 400K by eye. We
have found that below about 300K the detector is too COMPONENTS
sensitive and will self-trigger. Trial and error will show the Resistors: carbon film, 5%
best setting for your particular requirement. 47R R17 1
1K brown black red R6 R20 2
Note that this circuit is very sensitive. Even air moving 2K2 red red red R4 1
(hot air rising, wind blowing) will trigger it when the 10K brown black orange R13 R16 R19 3
trimpot is set near the most sensitive position. That is why 100K brown black yellow R1 R2 R15 3
we say to set it for your particular need. 150K brown green yellow R22 1
220K red red yellow R5 1
CIRCUIT DESCRIPTION 1M Brown black green R8 R9 R10 R14 4
The transmitter sends out a steady ultrasonic tone at 1M2 brown red green R12 R11 2
40kHz. At this frequency the wavelength is about 6 mm. 10M brown black blue R3 R7 R18 R21 4
Trimpot 1M 1
Any reflected sound is detected by ultrasonic receiver. The Capacitors:
signal is then amplified by IC1:A and IC1:B. IC1:A is self- 100nF monoblock (104) C1 C10 2
biasing via C2 & R5. The time constant of the first 100pF monoblock (101) C5 1
amplifier is set to let the 40kHz signal through. Between 10nF (103) ceramic C2 C6 C7 3
the first & second amplifier there is a negative peak 33pF ceramic C11 C12 2
detector (diode D1 & R8) which follows the envelope of 100 uF electrolytic C9 1
the 40kHz signal. If there is no movement the envelope is 470 nF (474) monoblock C3 C4 C8 3
just a straight line. The time constant of IC1:B is much Diode 1N4002/4 D5 1
Kit 49. ULTRASONIC MOVEMENT DETECTOR II
Diode 1N4148 D1 2 3 4 4 INFORMATION
9V battery snap 1 The manufacturers specifications (pdf format) for the
40kHz crystal 1 ultrasonic transducers see under Kit 20 or Kit 49 at
78L05 voltage regulator 1 http://kitsrus.com/kits.html
14049 hex buffer IC IC2 1
BC639 1 The data sheet for the LM324 & 4049 is available at
LM324 IC IC1 1 www.nsc.com
14 pin IC socket 1
16 pin IC socket 1
40kHz Ultrasonic Tx/Rx pair 400ST/R160 1
LED 1
Kit 49 PCB 1
Documentation
ELECTRONIC GARDENER Menu
by Andy Haryono Kartika
Abstract
This electronic gardener is used to maintain the soil moisture level, so the plants can
grow healthy. The soil moisture value from the sensor is processed by microcontroller
to activate the watering valve. If the soil moisture level is below from the expected
value, then the watering valve will be active. But, if the soil moisture level is higher
than the expected value, the watering valve will be off. We can control the expected soil
moisture level by arranging the value of Pot VR1. The LCD (Liquid Crystal Display)
will display the soil moisture level and the expected level. The main part of this
electronic gardener is a microcontroller chip 8051. This chip is used as LCD driver,
ADC driver and valve driver.
Hardware Description
I use the soil moisture sensor 200SS, which have an output range from 0 cb to 200 cb
(centibar). This sensor must be operated with square wave signal, which generated by
the timer circuit using LM555 and 7404. Basically, the sensor circuit is like an voltage
divider circuit, so the resistance of the sensor is equal to the soil moisture value.
Because the reading from the sensor is only valid when the bias signal from the timer
circuit reach the peak amplitude, so I must use the sample and hold component LF398
to keep the value untill next reading cycle.
To convert the analog signal to digital signal, I use MAX114 which have four inputs
channel and 8 bits output. The soil moisture level goes to the first channel, while the
expected value goes to the second channel. The other channels can be connected to
other sensors in different areas, so we can control the soil moisture in many areas. But,
of course the sensors must be placed far enough from the others.
The micrcontroller chip drive the ADC chip by sending low signal to CS and RD pin of
the MAX114 and get the digital data from DB0-DB7 pins after the INT pin goes low.
These digital signals will be converted to decimal format, then send to the LCD.
Because the function of the LCD is only to display data, so the RW pin can be
connected to ground. While the other control pins (i.e EN and RS pins) are controlled
by the microcontroller.
The microcontroller will compare the expected soil moisture value with the sensor
reading and determine whether the watering valve is active or not.
Software Description
I use Assembly program to design the controller for the microcontroller 8051. There are
four main procedures included on the design.
1. ADC Driver
This procedure is used to drive the ADC chip MAX114. Here is the listing program.
ADC : JBC P2.0,Two
MOV Moist,R3
SETB P2.0
SJMP Drive
Two : MOV Expect,R3
Drive : SETB P2.1
Wait : JB P2.2,Wait
MOV R3,P0
CLR P2.1
LJMP One
RET
2. Data Conversion
This procedure is used to convert the soil moisture and expected level from ADC
Driver procedure to the ASCII format, so they can be displayed on the LCD.
Convert: MOV Repeat,#3
MOV A,R3
Loop : MOV B,#10
DIV AB
MOV DPL,B
PUSH DPL
DJNZ Repeat,Loop
RET
3. LCD Driver
This procedure is used to control the LCD. First the LCD must be initialized using
InitLCD procedure. Then, to write an instruction register we must use IR procedure,
while to write an data register we must use DR procedure. The main procedure of
the LCD driver is Display procedure.
IR : CLR P2.3
CLR P2.4
LCALL Delay
SETB P2.3
MOV P1,R4
LCALL Delay
CLR P2.3
LCALL Delay
RET
DR : CLR P2.3
SETB P2.4
LCALL Delay
SETB P2.3
MOV P1,R4
LCALL Delay
CLR P2.3
LCALL Delay
RET
InitLCD: MOV R4,#30h
LCALL IR
LCALL IR
LCALL IR
MOV R4,#38h
LCALL IR
MOV R4,#08h
LCALL IR
MOV R4,#01H
LCALL IR
MOV R4,#06h
LCALL IR
MOV R4,#0Ch
LCALL IR
RET
Display: MOV R4,#8Ch ; Column 12th Row 1st position
LCALL IR
MOV R4,First_Moist ; Display soil moisture level
LCALL DR
MOV R4,Second_Moist
LCALL DR
MOV R4,Third_Moist
LCALL DR
MOV R4,#CCh ; Column 12th Row 2nd position
LCALL IR
MOV R4,First_Exp ; Display expected level
LCALL DR
MOV R4,Second_Exp
LCALL DR
MOV R4,Third_Exp
LCALL DR
4. Device Driver
This procedure is used to control the watering valve. It will compare the expected
level with soil moisture level, and decide whether the watering valve is active or
not.
Valve: MOV A,Moist
CJNE A,Expect,Level
JMP Off
Level: JNC Off
SETB P2.5
JMP Exit
Off : CLR P2.5
Exit: RET
5. Main Program
Program: LCALL InitLCD
LCALL ADC
MOV R3,Moist
LCALL Convert
POP DPL
MOV First_Moist,DPL
POP DPL
MOV Second_Moist,DPL
POP DPL
MOV Third_Moist,DPL
MOV R3,Expect
LCALL Convert
POP DPL
MOV First_Exp,DPL
POP DPL
MOV Second_Exp,DPL
POP DPL
MOV Third_Exp,DPL
LCALL Display
Parts List
Part Label Part Description
U1 LM555 Timer
U2 7404 Not Gate
U3 LM324 Operational Amplifier
U4 LF398 Sample And Hold
U5 MAX6350 Voltage Reference
U6 MAX114 Analog to Digital Converter
U7 8051 Microcontroller
U8 M1632 Liquid Crystal Display
Q1 BD139
Q2 MJ2955
C1 0.01uF
C2 100nF
C3 0.01uF
C4 1uF
C5 2.2uF
C6 4.7uF
C7 0.1uF
D1 D1N4001
R1 70K
R2 1.5K
R3 17K
R4 10K
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E2O0009-27-X2
This version: Jan. 1998

¡ Semiconductor
¡ Semiconductor MSM80C85AHRS/GS/JS
Previous version: Aug. 1996
MSM80C85AHRS/GS/JS
8-Bit CMOS MICROPROCESSOR
GENRAL DESCRIPTION
The MSM80C85AH is a complete 8-bit parallel; central processor implemented in silicon gate
C-MOS technology and compatible with MSM80C85A.
It is designed with higher processing speed (max.5 MHz) and lower power consumption
compared with MSM80C85A and power down mode is provided, thereby offering a high level
of system integration.
The MSM80C85AH uses a multiplexed address/data bus. The address is split between the 8-
bit address bus and the 8-bit data bus. The on-chip address latch : of a MSM81C55-5 memory
product allows a direct interface with the MSM80C85AH.
FEATURES
• Power down mode (HALT-HOLD)

• Low Power Dissipation: 50mW(Typ)
• Single + 3 to + 6 V Power Supply
• –40 to + 85°C, Operating Temperature
• Compatible with MSM80C85A
• 0.8 ms instruction Cycle (VCC = 5V)
• On-Chip Clock Generator (with External Crystal)
• On-Chip System Controller; Advanced Cycle Status Information Available for Large System
Control
• Bug operation in MSM80C85AH is fixed
• Four Vectored interrupt (One is non-maskable) Plus the 8080A-compatible interrupt.
• Serial, In/Serial Out Port
• Decimal, Binary and Double Precision Arithmetic
• Addressing Capability to 64K Bytes of Memory
• TTL Compatible
• 40-pin Plastic DIP(DIP40-P-600-2.54): (Product name: MSM80C85AHRS)
• 44-pin Plastic QFJ(QFJ44-P-S650-1.27): (Product name: MSM80C85AHJS)
• 44-pin Plastic QFP(QFP44-P-910-0.80-2K): (Product name: MSM80C85AHGS-2K)
1/29
FUNCTIONAL BLOCK DIAGRAM

RST
INTR INTA 5.5 6.5 7.5 TRAP SID SOD
Interrupt Control Serial I/O Control
8-Bit Internal Data Bus
Accumulator Temporary Register Flag (5) Instruction

(8) (8) Flip Flops Register (8)
Instruction B REG (8) C REG (8)

Arithmetic
Logic Unit Decoder
And D REG (8) E REG (8)
ALU(8)
Machine
H REG (8) C REG (8)
Cycle Register
Encoding Stack Pointer (16) Array
Power Program Counter (16)

+5V
Supply GND Incrementer/Decrementer
Address Latch (16)
Power Down
Timing And Control
X1 CLK
GEN Control Status DMA Reset Data/Address
X2 Address Buffer (8)
Buffer (8)
CLK READY RD WR ALE S0 S1 IO / M HOLD HLDA RESET IN RESET OUT A15 - A8 AD7 - AD0
OUT Address Bus Address/Data Bus
2/29
PIN CONFIGURATION (TOP VIEW)

40 pin Plastic DIP
X1 1 40 VCC
X2 2 39 HOLD
RESET OUT 3 38 HLDA
SOD 4 37 CLK(OUT)
SID 5 36 RESET IN
TRAP 6 35 READY
RST7.5 7 34 IO/M
RST6.5 8 33 S1
RST5.5 9 32 RD
INTR 10 31 WR
INTA 11 30 ALE
AD0 12 29 S0
44 pin Plastic QFP AD1 13 28 A15
AD2 14 27 A14
AD3 15 26 A13
42 RESET OUT
AD4 16 25 A12
35 CLK(OUT)
34 RESET IN
AD5 17 24 A11
37 HOLD
36 HLDA
43 SOD
AD6 18 23 A10
38 VCC
44 SID
39 NC
41 X2
40 X1
AD7 19 22 A9
GND 20 21 A8
TRAP 1 33 READY
RST7.5 2 32 IO/M
RST6.5 3 31 S1
RST5.5 4 30 RD
INTR 5 29 WR
INTA 6 28 ALE
AD0 7 27 S0
AD1 8 26 A15
AD2 9 25 A14
AD3 10 24 A13 44 pin Plastic QFJ
NC 11 23 A12
4 RESET OUT
AD4 12
AD5 13
AD6 14
AD7 15
GND 16
VCC 17
A8 18
A9 19
20
A11 21
NC 22
41 CLK(OUT)
40 RESET IN
A10
43 HOLD
42 HLDA
5 SOD
44 VCC
6 SID
1 NC
3 X2
2 X1
TRAP 7 39 READY
RST7.5 8 38 IO/M
RST6.5 9 37 S1
RST5.5 10 36 RD
INTR 11 35 WR
NC 12 34 NC
INTA 13 33 ALE
AD0 14 32 S0
AD1 15 31 A15
AD2 16 30 A14
AD3 17 29 A13
AD4 18
NC 19
AD5 20
AD6 21
AD7 22
GND 23
A8 24
A9 25
26
A11 27
A12 28
A10
3/29
MSM80C85AH FUNCTIONAL PIN DEFINITION
The following describes the function of each pin:
Symbol Function
A8 - A15 Address Bus: The most significant 8-bits of the memory address or the 8-bits of the I/O address,
(Output, 3-state) 3-stated during Hold and Halt modes and during RESET.
A0 - A 7 Multiplexed Address/Data Bus: Lower 8-bits of the memory address (or I/O address) appear on
(Input/Output) the bus during the first clock cycle (T state) of a machine cycle. It then becomes the data bus during
3-state the second and third clock cycles.
ALE Address Latch Enable: It occurs during the first clock state of a machine cycle and enables address to
(Output) get latched into the on-chip latch peripherals. The falling edge of ALE is set to guarantee setup and
hold times for the address information. The falling edge ALE can also be used to strobe the status
information ALE is never 3-state.
S0 , S1 , IO/M Machine cycle status:
(Output) IO/M S1 S0 States IO/M S1 S0 States
0 0 1 Memory write 1 1 1 Interrupt Acknowledge
0 1 0 Memory read . 0 0 Halt = 3-state
1 0 1 I/O write . ¥ ¥ Hold (high impedance)
1 1 0 I/O read . ¥ ¥ Reset ¥ = unspecified
0 1 1 Opcode fetch
S1 can be used as an advanced R/W status. IO/M, S0 and S1 become valid at the beginning of
a machine cycle and remain stable throughout the cycle. The falling edge of ALE may be used to latch
the state of these lines.
RD READ control: A low level on RD indicates the selected memory or I/O device is to be read that
(Output, 3-state) the Data Bus is available for the data transfer, 3-stated during Hold and Halt modes and during RESET.
WR WRITE control: A low level on WR indicates the data on the Data Bus is to be written into the selected
(Output, 3-state) memory or I/O location. Data is set up at the trailing edge of WR, 3-stated during Hold and Halt
modes and during RESET.
READY If READY is high during a read or write cycle, it indicates that the memory or peripheral is ready to
(Input) send or receive data. If READY is low, the cpu will wait an integral number of clock cycles for READY
to go high before completing the read or write cycle READY must conform to specified setup and
hold times.
HOLD HOLD indicates that another master is requesting the use of the address and data buses.
(Input) The cpu, upon receiving the hold request, will relinquish the use of the bus as soon as the completion
of the current bus transfer. Internal processing can continue. The processor can regain the bus only
after the HOLD is removed. When the HOLD is acknowledged, the Address, Data, RD, WR, and IO/M
lines are 3-stated. And status of power down is controlled by HOLD.
HLDA HOLD ACKNOWLEDGE: Indicates that the cpu has received the HOLD request and that it will
(Output) relinquish the bus in the next clock cycle. HLDA goes low after the Hold request is removed.
The cpu takes the bus one half clock cycle after HLDA goes low.
INTR INTERRUPT REQUEST: Is used as a general purpose interrupt. It is sampled on during the next to
(Output) the last clock cycle of an instruction and during Hold and Halt states. If it is active, the Program
Counter (PC) will be inhibited from incrementing and an INTA will be issued. During this cycle
a RESTART or CALL instruction can be inserted to jump to the interrupt service routine.
The INTR is enabled and disabled by software. It is disabled by Reset and immediately after
an interrupt is accepted. Power down mode is reset by INTR.
INTA INTERRUPT ACKNOWLEDGE: Is used instead of (and has the same timing as) RD during
(Output) the instruction cycle after an INTR is accepted.
RST 5.5 RESTART INTERRUPTS: These three inputs have the same timing as INTR except they cause
RST 6.5 an internal RESTART to be automatically inserted.
RST 7.5 The priority of these interrupts is ordered as shown in Table 1. These interrupts have a higher priority
(Input) than INTR. In addition, they may be individually masked out using the SIM instruction.
Power down mode is reset by these interrupts.
TRAP Trap interrupt is a nonmaskable RESTART interrupt. It is recognized at the same timing as INTR or
(Input) RST 5.5 - 7.5. It is unaffected by any mask or Interrupt Disable. It has the highest priority of any
interrupt. (See Table 1.) Power down mode is reset by input of TRAP.
4/29
Symbol Function
Sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip-flops and release
power down mode. The data and address buses and the control lines are 3-stated during RESET and
RESET IN because of the asynchronous nature of RESET IN, the processor's internal registers and flags may be
(Input) altered by RESET with unpredictable results. RESET IN is a Schmitt-triggered input, allowing
connection to an R-C network for power-on RESET delay. The cpu is held in the reset condition as
long as RESET IN is applied.
RESET OUT Indicated cpu is being reset. Can be used as a system reset. The signal is synchronized to
(Output) the processor clock and lasts an integral number of clock periods.
X1 and X2 are connected to a crystal to drive the internal clock generator. X1 can also be an external
X1, X2
clock input from a logic gate. The input frequency is divided by 2 to give the processor's internal
(Input)
operating frequency.
CLK
Clock Output for use as a system clock. The period of CLK is twice the X1, X2 input period.
(Output)
SID Serial input data line. The data on this line is loaded into accumulator bit 7 whenever a RIM instruction
(Input) is executed.
SOD
(Output) Serial output data line. The output SOD is set or reset as specified by the SIM instruction.
VCC + 5 Volt supply

GND Ground Reference.
Table 1 Interrupt Priority, Restart Address, and Sensitivity

Address Branched To (1)
Name Priority Type Trigger
When Interrupt Occurs
TRAP 1 24H Rising edge and high level unit sampled.
RST 7.5 2 3CH Rising edge (latched).
RST 6.5 3 34H High level unitl sampled.
RST 5.5 4 2CH High level until sampled.
INTR 5 (2) High level until sampled.
Notes: (1) The processor pushes the PC on the stack before branching to the indicated
address.
(2) The address branched to depends on the instruction provided to the cpu
when the interrupt is acknowledged.
5/29
FUNCTIONAL DESCRIPTION
The MSM80C85AH is a complete 8-bit parallel central processor. It is designed with silicon gate
C-MOS technology and requires a single +5 volt supply. Its basic clock speed is 5 MHz, thus
improving on the present MSM80C85A's performance with higher system speed and power
down mode. Also it is designed to fit into a minimum system of two IC's: The CPU
(MSM80C85AH), and a RAM/IO (MSM81C55-5)
The MSM80C85AH has twelve addressable 8-bit register pairs. Six others can be used
interchangeably as 8-bit registers or 16-bit register pairs. The MSM80C85AH register set is as
follows:
Mnemonic Register Contents
ACC or A Accumulator 8-bits
PC Program Counter 16-bit address
BC, DE, HL General-Purpose Registers; data pointer (HL) 8-bit ¥ 6 or 16-bits ¥ 3
SP Stack Pointer 16-bit address
Flags or F Flag Register 5 flags (8-bit space)
The MSM80C85AH uses a multiplexed Data Bus. The address is spilt between the higher 8-bit
Address Bus and the lower 8-bit Address/Data Bus. During the first T state (clock cycle) of a
machine cycle the low order address is sent out on the Address/Data Bus. These lower 8-bits
may be latched externally by the Address Latch Enable signal (ALE). During the rest of the
machine cycle the data bus is used for mamory or I/O data.
The MSM80C85AH provides RD, WR, S0, S1, and IO/M signals for bus control. An Interrupt
Acknowledge signal (INTA) is also provided. Hold and all Interrupts are synchronized with
the processor's internal clock. The MSM80C85AH also provides Serial Input Data (SID) and
Serial Output Data (SOD) lines for a simple serial interface.
In addition to these features, the MSM80C85AH has three maskable, vector interrupt pins, one
nonmaskable TRAP interrupt and power down mode with HALT and HOLD.
INTERRUPT AND SERIAL I/O
The MSM80C85AH has 5 interrupt inputs: INTR, RST 5.5 RST 6.5, RST 7.5, and TRAP. INTR is
identical in function to the 8080A INT. Each of the three RESTART inputs, 5.5, 6.5, and 7.5, has
a programmable mask. TRAP is also a RESTART interrupt but it is nonmaskable.
The three maskable interrupts cause the internal execution of RESTART ( saving the program
counter in the stack branching to the RESTART address) it the interrupts are enable and if the
interrupt mask is not set. The nonmaskable TRAP causes the internal execution of a RESTART
vector independent of the state of the interrupt enable or masks. (See Table 1.)
There are two different types of inputs in the restart interrupt. RST 5.5 and RST 6.5 are high
level-sensitive like INTR (and INT on the 8080A) and are recognized with the same timing as
INTR. RST 7.5 is rising edge-sensitive.
6/29
For RST 7.5, only a pulse is required to set an internal flip-flop which generates the internal
interrupt request. The RST 7.5 request flip-flop remains set until the request is serviced. Then
it is reset automatically, This flip-flop may also be reset by using the SIM instruction or by
issuing a RESET␣ IN to the MSM80C85AH. The RST 7.5 internal flip-flop will be set by a pulse
on the RST 7.5 pin even when the RST 7.5 interrupt is masked out.
The interrupts are arranged in a flixed priority that determines which interrupt is to be
recognized if more than one is pending, as follows: TRAP-highest priority, RST 7.5, RST 6.5, RST
5.5, INTR-lowest priority. This priority scheme does not take into account the priority of a
routine that was started by a higher priority interrupt. RST 5.5 can interrupt an RST 7.5 routine
if the interrupt are re-enabled before the end of the RST 7.5 routine.
The TRAP interrupt is useful for catastrophic evens such as power failure or bus error. The
TRAP input is recognized just as any other interrupt but has the highest priority. It is not
affected by any flag or mask. The TRAP input is both edge and level sensitive. The TRAP input
must go high and remain high until it is acknowledged. It will not be recognized again until it
goes low, then high again. This avoids any false triggering due to noise or logic glitches. Figure
3 illustrates the TRAP interrupt request circuitry within the MSM80C85AH. Note that the
servicing of any interrupt (TRAP, RST 7.5, RST 6.5, RST 5.5,INTR) disables all future interrupts
(except TRAPs) until an El instruction is executed.
The TRAP interrupt is special in that it disables interrupts, but preserves the previous interrupt
enable status. Performing the first RIM instruction following a TRAP interrupt allows you to
determine whether interrupts were enabled or disabled prior to the TRAP. All subsequent RIM
instructions provide current interrupt enable status. Performing a RIM instruction following
INTR or RST 5.5-7.5 will provide current interrupt Enable status, revealing that Interrupts are
disabled.
The serial I/O system is also controlled by the RIM and SIM instructions. SID is read by RIM,
and SIM sets the SOD data.
External TRAP Inside the MSM80C85AH
Interrupt Request TRAP
RESET
RESET IN Schmitt TRAP
Trigger
+5 V D CLK Interrupt
Request
Q
D
F/F
Clear
Internal
TRAP F.F
TRAP
Acknowledge
Figure 3 Trap and RESET IN Circuit
7/29
DRIVING THE X1 AND X2 INPUTS
You may drive the clock inputs of the MSM80C85AH with a crystal, or an external clock source.
The driving frequency must be at least 1 MHz, and must be twice the desired internal clock
frequency; hence, the MSM80C85AH is operated with a 6 MHz crystal (for 3 MHz clock). If a
crystal is used, it must have the following characteristics:
Parallel resonance at twice the clock frequency desired

CL (load capacitance) £ 30 pF
CS (shunt capacitance) £ 7 pF
RS (equivalent shunt resistance) £ 75 ohms
Drive level: 10 mW
Frequency tolerance: ±0.05% (suggested)
Note the use of the capacitors between X1, X2 and ground. These capacitors are required to
assure oscillator startup at the correct frequency.
Figure 4 shows the recommended clock driver circuits. Note in B that a pull-up resistor is
required to assure that the high level voltage of the input is at least 4 V.
For driving frequencies up to and including 6 MHz you may supply the driving signal to X, and
leave X2 open-circuited (Figure 4B). To prevent self-oscillation of the MSM80C85AH, be sure
that X2 is not coupled back to X1 through the driving circuit.
A. Quartz Crystal Clock Driver B. 1 - 10 MHz Input Frequency External

Clock Drive Circuit
X1 MSM80C85AH
C1 X1
CINT = 15 pF VIH > 0.8 VCC
C2 High time > 40 ns
Low time > 40 ns X2
X2 *
33 pF Capacitor required for crystal frequency 10 to 6.25 MHz

50 pF Capacitor required for crystal frequency 6.25 to 4 MHz * X2 Left Floating
100 pF Capacitor required for crystal frequency <4 MHz
Note: Since the constant values may vary depending on oscillator, consult the manufacturer
of the oscillator used when designing a circuit.
Figure 4 Clock Driver Circuits
8/29
BASIC SYSTEM TIMING
The MSM80C85AH has a multiplexed Data Bus. ALE is used as a strobe to sample the lower
8-bits of address on the Data Bus. Figure 5 shows an instruction fetch, memory read and I/O
write cycle (as would occur during processing of the OUT instruction). Note that during the I/
O write and read cycle that the I/O port address is copied on both the upper and lower half of
the address.
There are seven possible types of machine cycles. Which of these seven takes place is defined
by the status of the three status lines (IO/M, S1, S0) and the three control signals (RD, WR,and
INTA). (See Table 2.) The status line can be used as advanced controls (for device selection, for
example), since they become active at the T1 state, at the outset of each machine cycle. Control
lines RD and WR become active later, at the time when the transfer of data is to take place, so
are used as command lines.
A machine cycle normally consists of three T states, with the exception of OPCODE FETCH,
which normally has either four or six T states (unless WAIT or HOLD states are forced by the
receipt of READY or HOLD inputs). Any T state must be one of ten possible states, shown in
Table 3.
Table 2 MSM80C85AH Machine Cycle Chart
Status Control
Machine Cycle
IO/M S1 S0 RD WR INTA
Opcode Fetch (OF) 0 1 1 0 1 1
Memory Read (MR) O 1 O O 1 1
Memory Write (MW) O 0 1 1 0 1
I/O Read (IOR) 1 1 O O 1 1
I/O Write (IOW) 1 0 1 1 0 1
Acknowledge of INTR (INA) 1 1 1 1 1 0
Bus Idle (BI): DAD 0 1 0 1 1 1
ACK. OF
RST, TRAP 1 1 1 1 1 1
HALT TS 0 0 TS TS 1
9/29
Table 3 MSM80C85AH Machine State Chart
Status & Buses Control

Machine State
S1, S0 IO/M A8 – A15 AD0 – AD7 RD, WR INTA ALE
T1 ¥ ¥ ¥ ¥ 1 1 1 (1)
T2 ¥ ¥ ¥ ¥ ¥ ¥ 0
TWAIT ¥ ¥ ¥ ¥ ¥ ¥ 0
T3 ¥ ¥ ¥ ¥ ¥ ¥ 0
T4 1 0 (2) ¥ TS 1 1 0
T5 1 0 (2) ¥ TS 1 1 0
T6 1 0 (2) ¥ TS 1 0
1
TRESET ¥ TS TS TS TS 1 0
THALT 0 TS TS TS TS 1 0
THOLD ¥ TS TS TS TS 1 0
0 = Logic "0"
1 = Logic "1"
TS = High Impedance
¥ = Unspecified
Notes: (1) ALE not generated during 2nd and 3rd machine cycles of DAD instruction.
(2) IO/M = 1 during T4 - T6 of INA machine cycle.
M1 M2 M3
T1 T2 T3 T4 T1 T2 T3 T1 T2 T3 T
CLK
A8-15 PCH (High Order Address) (PC+1)H IO Port
AD0-7 PCL (PC+1)L1 IO Port

(Low Order Data from Memory Data from Memory Data to Memory
Address) (Instruction) (I/O Port Address) or Peripheral
ALE
RD
WR
IO/M
STATUS S1S0(Fetch) 10 (Read) 01 Write 11
Figure 5 MSM80C85AH Basic System Timing
10/29
POWER DOWN Mode
The MSM80C85AH is compatible with the MSM80C85A in function and POWER DOWN mode.
This reduces power consumption further.
There are two methods available for starting this POWER DOWN mode. One is through
software control by using the HALT command and the other is under hardware control by using
the pin HOLD. This mode is released by the HOLD, RESET, and interrupt pins (TRAP, RST7.5,
RST6.5 RST5.5, or INTR). (See Table 4.)
Since the sequence of HALT, HOLD, RESET, and INTERRUPT is compatible with MSM80C85A,
every the POWER DOWN mode can be used with no special attention.
Table 4 POWER DOWN Mode Releasing Method
Start by means of Halt command Released by using pins RESET and INTERRUPT (not by pin HOLD)
Start by means of HOLD pin Released by using RESET and HOLD pins (not by interrupt pins)
(1) Start by means of HALT command (See Figures 6 and 7.)

The POWER DOWN mode can be started by executing the HALT command.
At this time, the system is put into the HOLD status and therefore the POWER DOWN mode
cannot be released even when the HOLD is released later.
In this case, the POWER DOWN mode can be released by means of the RESET or interrupt.
(2) Start by means of HOLD pin (See Figure 8.)

During the execution of commands other than the HALT, the POWER DOWN mode is started
when the system is put into HOLD status by means of the HOLD pin.
Since no interrupt works during the execution of the HOLD, the POWER DOWN mode cannot
be released by means of interrupt pins. In this case, the POWER DOWN mode can be released
either by means of the RESET pin or by releasing the HOLD status by means of HOLD pin.
11/29
M1 M2 M1
T1 T2 T3 T4 T1 THLT TRESET T1 T2
CLK (OUT)
ALE
AD0-7 Address 76H Address Address
CPU MODE Run Power Down Run
RESET IN
Figure 6 Started by HALT and Released by RESET IN
M1 M2 M1
T1 T2 T3 T4 T1 THLT T1 T2
CLK (OUT)
ALE
RST5.5
CPU MODE Run Power Down Run
Figure 7 Started by HALT and Released by RST5.5
M1 M1
T1 T2 T3 T4 THOLD T1 T2
CLK (OUT)
ALE
HOLD
HLDA
CPU MODE Run Power Down RUN
Figure 8 Started and Released by HOLD
12/29
ABSOLUTE MAXIMUM RATINGS
Limits
Parameter Symbol Condition Units
MSM80C85AHRS MSM80C85AHGS MSM80C85AHJS
Power Supply Voltage VCC –0.5 - 7 V

With respect
Input Voltage VIN –0.5 - VCC +0.5 V
to GND
Output Voltage VOUT –0.5 - VCC +0.5 V
Storage Temperature TSTG — –55 - +150 °C
Power Dissipation PD Ta = 25°C 1.0 0.7 1.0 W
OPERATING RANGE
Parameter Symbol Limits Unit

Power Supply Voltage VCC 3-6 V
Operating Temperature TOP –40 - +85 °C
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min. Typ. Max. Unit

Power Supply Voltage VCC 4.5 5 5.5 V
Operating Temperature TOP –40 +25 +85 °C
"L" Input Voltage VIL –0.3 — +0.8 V
"H" Output Voltage VIH 2.2 — VCC +0.3 V
RESET IN
"L" VILR –0.3 — +0.8 V
Input Voltage
RESET IN
"H" VIHR 3.0 — VCC +0.3 V
Input Voltage
DC CHARACTERISTICS
Parameter Symbol Conditions Min. Typ. Max. Unit

"L" Output Voltage VOL IOL = 2.5 mA — — 0.4 V
IOH = –2.5 mA 3.0 — — V
"H" Output Voltage VOH
IOH = –100 mA VCC - 0.4 — — V
Input Leak Current ILI 0 £ VIN £ VCC VCC = 4.5 V - 5.5 V –10 — 10 mA
Output Leak Current ILO 0 £ VOUT £ VCC Ta = –40°C - +85°C –10 — 10 mA
Tcyc = 200 ns — 10 20 mA
CL = 0 pF at reset
Operating Supply ICC
Current Tcyc = 200 ns — 5 10 mA
CL = 0 pF at power
down mode
13/29
AC CHARACTERISTICS
(Ta = –40°C ~ 85°C, VCC = 4.5 V ~ 5.5 V)
Parameter Symbol Condition Min. Max. Unit
CLY Cycle Period tCYC 200 2000 ns
CLY Low Time t1 40 — ns
CLY High Time t2 70 — ns
CLY Rise and Fall Time tr, tf — 30 ns
X1 Rising to CLK Rising tXKR 25 120 ns
X1 Rising to CKK Falling tXKF 30 150 ns
A8~15 Valid to Leading Edge of Control (1) tAC 115 — ns
AD0~7 Valid to Leading Edge of Control tACL 115 — ns
AD0~15 Valid Data in tAD — 350 ns
Address Float After Leading Edge of RD INTA tAFR — 0 ns
A8~15 Valid Before Trailing Edge of ALE (1) tAL 50 — ns
AD0~7 Valid Before Trailing Edge of ALE tALL 50 — ns
READY Valid from Address Valid tARY — 100 ns
Address (A8~15) Valid After Control tCA 60 — ns
Width of Control Law (RD, WR, INTA) tCC 230 — ns
Trailing Edge of Control to Leading Edges of ALE tCL 25 — ns
Data Valid to Trailing Edge of WR tDW 230 — ns
HLDA to Bus Enable tHABE — 150 ns
Bus Float After HLDA tHABF tCYC=200 ns — 150 ns
HLDA Valid to Trailing Edge of CLK tHACK CL=150 pF 40 — ns
HOLD Hold Time tHDH 0 — ns
HOLD Step Up Time to Trailing Edge of CLK tHDS 120 — ns
INTR Hold Time tINH 0 — ns
INTR, RST and TRAP Setup Time to Falling Edge of CLK tINS 150 — ns
Address Hold Time After ALE tLA 50 — ns
Trailing Edge of ALE to Leading Edge of Control tLC 60 — ns
ALE Low During CLK High tLCK 50 — ns
ALE to Valid Data During Read tLDR — 270 ns
ALE to Valid Data During Write tLDW — 140 ns
ALE Width tLL 80 — ns
ALE to READY Stable tLRY — 30 ns
Trailing Edge of RD to Re-enabling of Address tRAE 90 — ns
RD (or INTA) to Valid Data tRD — 150 ns
Control Trailing Edge to Leading Edge of Next Control tRV 220 — ns
Data Hold Time After RD INTA (7) tRDH 0 — ns
READY Hold Time tRYH 0 — ns
READY Setup Time to Leading Edge of CLK tRYS 100 — ns
Data Valid After Trailing Edge of WR tWD 60 — ns
LEADING Edge of WR to Data Vaild tWDL — 20 ns
14/29
Notes: (1) A8 - A15 address Specs apply to IO/M, S0 and S1.

(2) Test condition: tCYC=200 ns CL=150 pF
(3) For all output timing where CL=150 pF use the following correction factors:
25 pF £ CL < 150 pF : –0.10ns/pF
150 pF < CL £ 200 pF : +0.30ns/pF
(4) Output timings are measured with purely capacitive load.
(5) All timings are measured to output voltage VL=0.8 V, VH=2.2 V, and 1.5 V
with 10 ns rise and fall time on inputs.
(6) To calculate timing specifications at other values of tCYC use Table 7.
(7) Data hold time is guaranteed under all loading conditions.
Input Waveform for A.C. Tests:
2.4
2.2 2.2
Test Points
0.8 0.8
0.45
Table 7 Bus Timing Specification as a TCYC Dependent

(Ta = -40°C - +85°C, VCC = 4.5 V - 5.5 V, CL = 150 pF)
MSM80C85AH
tAL — (1/2)T - 50 Min
tLA — (1/2)T - 50 Min
tLL — (1/2)T - 20 Min
tLCK — (1/2)T - 50 Min
tLC — (1/2)T - 40 Min
tAD — (5/2+N)T - 150 Max
tRD — (3/2+N)T - 150 Max
tRAE — (1/2)T - 10 Min
tCA — (1/2)T - 40 Min
tDW — (3/2+N)T -70 Min
tWD — (1/2)T - 40 Min
tCC — (3/2+N)T - 70 Min
tCL — (1/2)T - 75 Min
tARY — (3/2)T - 200 Max
tHACK — (1/2)T - 60 Min
tHABF — (1/2)T + 50 Max
tHABE — (1/2)T + 50 Max
tAC — (2/2)T - 85 Min
t1 — (1/2)T - 60 Min
t2 — (1/2)T - 30 Min
tRV — (3/2)T - 80 Min
tLDR — (2+N)T -130 Max
Note: N is equal to the total WAIT states.

T = tCYC
15/29
X1 INPUT
tr t2 tf
CLK
OUTPUT
tXKR t1
tXKF tCYC
Figure 6 Clock Timing Waveform
READ OPERATION
T1 T2 T3 T1
CLK
tLCK tCA
A8-A15 Address
tAD tRAE
tRDH
AD0-AD7 Address Data In
tLL tLA
tAFR tCL
ALE tLDR
tAL tRD
tCC
RD / INTA tLC
tAC
WRITE OPERATION
T1 T2 T3 T1
CLK
tLCK
A8-A15 Address
tLDW tCA
AD0-AD7 Address Data Out
tLL tLA tDW tWD
tWDL
ALE
tAL
WR tLC tCC
tCL
tAC
16/29
Read operation with Wait Cycle (Typical)–

same READY timing applies to WRITE operation
T1 T2 TWAIT T3 T1
CLK
tLCK tCA
A8~A15 Address
tAD tRAE
tRDH
AD0~AD7 Address Data In
tLL tLA
tAFR tCL
ALE tLDR
tAL tRD
tCC
RD / INTA tCL
tAC
tARY tRYS tRYH
READY
tLRY
Note: READY must remain stable during setup and hold times.
Figure 7 MSM80C85AH Bus Timing, With and Without Wait
HOLD OPERATION
T2 T3 THOLD THOLD T1
CLK
HOLD
tHDS tHACK
tHDH
HLDA
tHABF
tHABE
BUS (Address, Controls)
Figure 8 MSM80C85AH Hold Timing
17/29
T1 T2 T4 T5 T6 THOLD T1 T2
A8-15
AD0-7 Call Inst

(1)
Bus Floating
ALE
RD
INTA
tHABE
INTR
tINS tINH
HOLD
tHDS tHDH
HLDA
tHACK tHABF
NOTE: (1) IO/M is also floating during this time.
Figure 9 MSM80C85AH Interrupt and Hold Timing
18/29
Table 8 Instruction Set Summary

Instruction Code (1) Clock (2)
Mnemonic Description
D7 D6 D5 D4 D3 D2 D1 D0 Cycles
MOVE, LOAD, AND STORE
MOVr1 r2 Move register to register 0 1 D D D S S S 4
MOV M r Move register to memory 0 1 1 1 0 S S S 7
MOV r M Move memory to register 0 1 D D D 1 1 0 7
MVI r Move immediate register 0 0 D D D 1 1 0 7
MVI M Move immediate memory 0 0 1 1 0 1 1 0 10
LXI B Load immediate register Pair B & C 0 0 0 0 0 0 0 1 10
LXI D Load immediate register Pair D & E 0 0 0 1 0 0 0 1 10
LXI H Load immediate register Pair H & L 0 0 1 0 0 0 0 1 10
LXI SP Load immediate stack pointer 0 0 1 1 0 0 0 1 10
STAX B Store A indirect 0 0 0 0 0 0 1 0 7
STAX D Store A indirect 0 0 0 1 0 0 1 0 7
LDAX B Load A indirect 0 0 0 0 1 0 1 0 7
LDAX D Load A indirect 0 0 0 1 1 0 1 0 7
STA Store A direct 0 0 1 1 0 0 1 0 13
LDA Load A direct 0 0 1 1 1 0 1 0 13
SHLD Store H & L direct 0 0 1 0 0 0 1 0 16
LHLD Load H & L direct 0 0 1 0 1 0 1 0 16
XCHG Exchange D & E H & L registers 1 1 1 0 1 0 1 1 4
STACK OPS
PUSH B Push register Pair B & C on stack 1 1 0 0 0 1 0 1 12
PUSH D Push register Pair D & E on stack 1 1 0 1 0 1 0 1 12
PUSH H Push register Pair H & L on stack 1 1 1 0 0 1 0 1 12
PUSH PSW Push A and Flags on stack 1 1 1 1 0 1 0 1 12
POP B Pop register Pair B & C off stack 1 1 0 0 0 0 0 1 10
POP D Pop register Pair D & E off stack 1 1 0 1 0 0 0 1 10
POP H Pop register Pair H & L off stack 1 1 1 0 0 0 0 1 10
POP PSW Pop A and Flags off stack 1 1 1 1 0 0 0 1 10
XTHL Exchange top of stack H & L 1 1 1 0 0 0 1 1 16
SPHL H & L to stack pointer 1 1 1 1 1 0 0 1 6
JUMP
JMP Jump unconditional 1 1 0 0 0 0 1 1 10
JC Jump on carry 1 1 0 1 1 0 1 0 7/10
JNC Jump on no carry 1 1 0 1 0 0 1 0 7/10
JZ Jump on zero 1 1 0 0 1 0 1 0 7/10
JNZ Jump on no zero 1 1 0 0 0 0 1 0 7/10
JP Jump on positive 1 1 1 1 0 0 1 0 7/10
JM Jump on minus 1 1 1 1 1 0 1 0 7/10
JPE Jump on parity even 1 1 1 0 1 0 1 0 7/10
JPO Jump on parity odd 1 1 1 0 0 0 1 0 7/10
PCHL H & L to program counter 1 1 1 0 1 0 0 1 6
CALL
CALL Call unconditional 1 1 0 0 1 1 0 1 18
CC Call on carry 1 1 0 1 1 1 0 0 9/18
CNC Call on no carry 1 1 0 1 0 1 0 0 9/18
CZ Call on zero 1 1 0 0 1 1 0 0 9/18
CNZ Call on no zero 1 1 0 0 0 1 0 0 9/18
CP Call on positive 1 1 1 1 0 1 0 0 9/18
CM Call on minus 1 1 1 1 1 1 0 0 9/18
CPE Call on parity even 1 1 1 0 1 1 0 0 9/18
CPO Call on parity odd 1 1 1 0 0 1 0 0 9/18
19/29
Table 8 Instruction Set Summary cont'd

RETURN
RET Return 1 1 0 0 1 0 0 1 10
RC Return on carry 1 1 0 1 1 0 0 0 6/12
RNC Return on no carry 1 1 0 1 0 0 0 0 6/12
RZ Return on zero 1 1 0 0 1 0 0 0 6/12
RNZ Return on no zero 1 1 0 0 0 0 0 0 6/12
RP Return on positive 1 1 1 1 0 0 0 0 6/12
RM Return on minus 1 1 1 1 1 0 0 0 6/12
RPE Return on parity even 1 1 1 0 1 0 0 0 6/12
RPO Return on parity odd 1 1 1 0 0 0 0 0 6/12
RESTART
RST Restart 1 1 A A A 1 1 1 12
INPUT/OUTPUT
IN Input 1 1 0 1 1 0 1 1 10
OUT Output 1 1 0 1 0 0 1 1 10
INCREMENT AND DECREMENT
INR r Increment register 0 0 D D D 1 0 0 4
DCR r Decrement register 0 0 D D D 1 0 1 4
INR M Increment memory 0 0 1 1 0 1 0 0 10
DCR M Decrement memory 0 0 1 1 0 1 0 1 10
INX B Increment B & C registers 0 0 0 0 0 0 1 1 6
INX D Increment D & E registers 0 0 0 1 0 0 1 1 6
INX H Increment H & L registers 0 0 1 0 0 0 1 1 6
INX SP Increment stack pointer 0 0 1 1 0 0 1 1 6
DCX B Decrement B & C 0 0 0 0 1 0 1 1 6
DCX D Decrement D & E 0 0 0 1 1 0 1 1 6
DCX H Decrement H & L 0 0 1 0 1 0 1 1 6
DCX SP Decrement stack pointer 0 0 1 1 1 0 1 1 6
ADD
ADD r Add register to A 1 0 0 0 0 S S S 4
ADC r Add register to A with carry 1 0 0 0 1 S S S 4
ADD M Add memory to A 1 0 0 0 0 1 1 0 7
ADC M Add memory to A with carry 1 0 0 0 1 1 1 0 7
ADI Add immediate to A 1 1 0 0 0 1 1 0 7
ACI Add immediate to A with carry 1 1 0 0 1 1 1 0 7
DAD B Add B & C to H & L 0 0 0 0 1 0 0 1 10
DAD D Add D & E to H & L 0 0 0 1 1 0 0 1 10
DAD H Add H & L to H & L 0 0 1 0 1 0 0 1 10
DAD SP Add stack pointer to H & L 0 0 1 1 1 0 0 1 10
SUBTRACT
SUB r Subtract register from A 1 0 0 1 0 S S S 4
SBB r Subtract register from A with borrow 1 0 0 1 1 S S S 4
SUB M Subtract memory from A 1 0 0 1 0 1 1 0 7
SBB M Subtract memory from A with borrow 1 0 0 1 1 1 1 0 7
SUI Subtract immediate from A 1 1 0 1 0 1 1 0 7
SBI Subtract immediate from A with borrow 1 1 0 1 1 1 1 0 7
20/29
Table 8 Instruction Set Summary cont'd

LOGICAL
ANA r Add register with A 1 0 1 0 0 S S S 4
XRA r Exclusive Or register with A 1 0 1 0 1 S S S 4
ORA r Or register with A 1 0 1 1 0 S S S 4
CMP r Compare register with A 1 0 1 1 1 S S S 4
ANA M And memory with A 1 0 1 0 0 1 1 0 7
XRA M Exclusive Or Memory with A 1 0 1 0 1 1 1 0 7
ORA M Or memory with A 1 0 1 1 0 1 1 0 7
CMP M Compare memory with A 1 0 1 1 1 1 1 0 7
ANI And immediate with A 1 1 1 0 0 1 1 0 7
XRI Exclusive Or immediate with A 1 1 1 0 1 1 1 0 7
ORI Or immediate with A 1 1 1 1 0 1 1 0 7
CPI Compare immediate with A 1 1 1 1 1 1 1 0 7
ROTATE
RLC Rotate A left 0 0 0 0 0 1 1 1 4
RRC Rotate A right 0 0 0 0 1 1 1 1 4
RAL Rotate A left through carry 0 0 0 1 0 1 1 1 4
RAR Rotate A right through carry 0 0 0 1 1 1 1 1 4
SPECIALS
CMA Complement A 0 0 1 0 1 1 1 1 4
STC Set carry 0 0 1 1 0 1 1 1 4
CMC Complement carry 0 0 1 1 1 1 1 1 4
DAA Decimal adjust A 0 0 1 0 0 1 1 1 4
CONTROL
EI Enable Interrupts 1 1 1 1 1 0 1 1 4
DI Disable Interrupts 1 1 1 1 0 0 1 1 4
NOP No-operation 0 0 0 0 0 0 0 0 4
HLT Halt (Power down) 0 1 1 1 0 1 1 0 5
RIM Read Interrupt Mask 0 0 1 0 0 0 0 0 4
SIM Set Interrupt Mask 0 0 1 1 0 0 0 0 4
Notes: (1) DDD or SSS. B 000. C 001. D 010. E 011. H 100. L 101. Memory 110. A 111.
(2) Two possible cycle times, (6/12) indicate instruction cycles dependent on
condition flags.
Precautions for operation

(1) When the oscillation circuit is to be used, keep the RES input low until the oscillation is
sufficiently stabilized after power is turned on.
(2) When power is turned on, the output level (SOD etc.) is unknown before the equipment
is reset.
(3) Bug of MSM80C85A–2 at power down has fixed.
(4) Because Spike Noise would be output on HLDA, RESET OUT and CLK pins, depending
on the customers condition of usage; please take into account this issue at System Board
design.
21/29
SUPPLEMENTARY EXPLANATION
(1) SIM instruction: The execution of the SIM instruction uses the contents of the accumulator
to mask MSM80C85AH’S interrupts.
Accumulator Setting Value

Bit 7 6 5 4 3 2 1 0
— — — R7.5 MSE M7.5 M6.5 M5.5
R7.5 (Reset interrupt 7.5 Flip-flop): When this bit is set to 1, the edge detecting flip-flop
of RST 7.5 interrupt is reset.
MSE (Mask Set Enable): When this bit is set to 1, the interrupt mask bits are valid.
M7.5 (Mask RST7.5): When this bit is set to 1 and MSE bit is set to 1, RST7.5 interrupt is
masked.
M6.5 (Mask RST6.5): When this bit is set to 1 and MSE bit is set to 1, RST6.5 interrupt is
masked.
M5.5 (Mask RST5.5): When this bit is set to 1 and MSE bit is set to 1, RST 5.5 interrupt is
masked.
(2) RIM instruction: When the contents of the accumulator are read out after RIM instruction has
been executed, MSM80C85AH interrupt status can be known.
Accumulator Reading Value
Bit 7 6 5 4 3 2 1 0
— 17.5 16.5 15.5 IE M7.5 M6.5 M5.5
17.5 (Pending RST7.5): When RST7.5 interrupt is pending, "1" is read out.
IE (Interrupt Enable Flag): When interrupt is Enable, "1" is read out.
M7.5 (Mask RST7.5): When RST7.5 interrupt is masked, "1" is read out.
M6.5 (Mask RST6.5): When RST6.5 interrupt is masked, "1" is read out.
M5.5 (Mask RST5.5): When RST5.5 interrupt is masked ,"1" is read out.
22/29
NOTICE ON REPLACING LOW-SPEED DEVICES WITH HIGH-SPEED DEVICES
The conventional low speed devices are replaced by high-speed devices as shown below.
When you want to replace your low speed devices with high-speed devices, read the replacement
notice given on the next pages.
High-speed device (New) Low-speed device (Old) Remarks

M80C85AH M80C85A/M80C85A-2 8bit MPU
M80C86A-10 M80C86A/M80C86A-2 16bit MPU
M80C88A-10 M80C88A/M80C88A-2 8bit MPU
M82C84A-2 M82C84A/M82C84A-5 Clock generator
M81C55-5 M81C55 RAM.I/O, timer
M82C37B-5 M82C37A/M82C37A-5 DMA controller
M82C51A-2 M82C51A USART
M82C53-2 M82C53-5 Timer
M82C55A-2 M82C55A-5 PPI
23/29
Differences between MSM80C85AH and MSM80C85A/MSM80C85A-2
1) Manufacturing Process
Item MSM80C85A MSM80C85A-2 MSM80C85AH

Manufacturing Process 3mSi-CMOS 2.5mSi-CMOS 2mSi-CMOS
2) Functions
Item MSM80C85A MSM80C85A-2 MSM80C85AH

Provided Provided (The malfunction
Power-down Function Not provided (but may malfunction has been removed.)
when HOLD is used)
Address output during Undefined (compatible Not fixed The contents of data
T4 to T6 cycles with Intel devices) in T3 cycle are retained
(for low power consumption).
3) Electrical Characteristics
3-1) Operating Conditions
Parameter Symbol MSM80C85A MSM80C85A-2 MSM80C85AH

Power Supply Voltage VCC 4 to 6 V 3 to 6 V 3 to 6 V
3-2) DC Characteristics
Parameter Symbol MSM80C85A MSM80C85A-2 MSM80C85AH

''L''Level 0.45 V maximum 0.45 V maximum 0.40 V maximum
VOL
Output Voltage (+2 mA) (+2 mA) (+2.5 mA)
''H''Level 2.4 V minimum 2.4 V minimum 3.0 V maximum
VOH
Output Voltage (-400 mA) (-400 mA) (-2.5 mA)
''H''Level 4.2 V minimum 4.2 V minimum VCC-0.2 V minimum
VOH
Output Voltage (-40 mA) (-40 mA) (-100 mA)
Supply Current 22 mA maximum 20 mA maximum 20 mA maximum
ICC
(at RES) (@3 MHz) (@5 MHz) (@5 MHz)
Supply Current 7 mA maximum 10 mA maximum
ICC None
(in PD) (@5 MHz) (@5 MHz)
Notes: "at RES'' means ''at reset time'' and ''in PD'' means ''in power down mode''.
As shown above, the VOL and VOH ranges the MSM80C85AH contain those of the MSM80C85A/
MSM80C85A-2. Although the supply current range (at a power failure) of the MSM80C85AH does
not contain that of the MSM80C85A-2, this does not affect the actual use of the MSM80C85AH.
3-3) AC Characteristics
The AC characteristics (5 MHz) of the MSM80C85AH satisfy that (3 MHz) of the MSM80C85A. The
MSM80C85AH also satisfies that (5MHz) of the MSM80C85A.
24/29
AC Charasteristics
Symbol MSM80C85A MSM80C85A-2 MSM80C85AH

tCYC Min 320 ns 200 ns 200 ns
t1 Min 80 ns 40 ns 40 ns
t2 Min 120 ns 70 ns 70 ns
tXKR Min 30 ns 25 ns 25 ns
tAC Max 270 ns 115 ns 115 ns
tACL Min 240 ns 115 ns 115 ns
tAD Max 575 ns 330 ns 350 ns
tAL Min 115 ns 50 ns 50 ns
tALL Min 90 ns 50 ns 50 ns
tARY Max 220 ns 100 ns 100 ns
tCA Min 120 ns 60 ns 60 ns
tCC Min 400 ns 230 ns 230 ns
tCL Min 50 ns 25 ns 25 ns
tDW Min 420 ns 230 ns 230 ns
tHABE Min 210 ns 150 ns 150 ns
tHABF Max 210 ns 150 ns 150 ns
tHACK Min 110 ns 40 ns 40 ns
tHDS Min 170 ns 120 ns 120 ns
tINS Min 160 ns 150 ns 150 ns
tLA Min 100 ns 50 ns 50 ns
tLC Min 130 ns 60 ns 60 ns
tLCK Min 100 ns 50 ns 50 ns
tLDR Max 460 ns 250 ns 270 ns
tLDW Max 200 ns 140 ns 140 ns
tLL Min 140 ns 80 ns 80 ns
tLRY Max 110 ns 30 ns 30 ns
tRAE Min 150 ns 90 ns 90 ns
tRD Max 300 ns 150 ns 150 ns
tRV Min 400 ns 220 ns 220 ns
tWD Min 100 ns 60 ns 60 ns
tWDL Max 40 ns 20 ns 20 ns
Notes: The italicized or underlined values indicate that they are different from those of the MSM80C85AH.
25/29
4) Other notes
1) As the MSM80C85AH employs the 2 m process, its noise characteristics may be a little different from
those of the MSM80C85A. When devices are replaced for upgrading, it is recommended to perform
noise evaluation. Especially, HLDA, RESOUT, and CLKOUT pins must be evaluated.
2) The MSM80C85AH basically satisfies the characteristics of the MSM80C85A-2 and the MSM80C85A,
but their timings are a little different, Therefore, when critical timing is required in designing, it is
recommended to evaluate operating margins at various temperatures and voltages.
26/29
PACKAGE DIMENSIONS
(Unit : mm)
DIP40-P-600-2.54
Package material Epoxy resin

Lead frame material 42 alloy
Pin treatment Solder plating
Solder plate thickness 5 mm or more
Package weight (g) 6.10 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
27/29
(Unit : mm)
QFJ44-P-S650-1.27
Mirror finish

Lead frame material Cu alloy
28/29
(Unit : mm)
QFP44-P-910-0.80-2K
Mirror finish

Lead frame material 42 alloy
29/29
S E M I C O N D U C T O R 80C86
March 1997 CMOS 16-Bit Microprocessor
Features Description
• Compatible with NMOS 8086 The Harris 80C86 high performance 16-bit CMOS CPU is
manufactured using a self-aligned silicon gate CMOS pro-
• Completely Static CMOS Design
cess (Scaled SAJI IV). Two modes of operation, minimum for
- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5MHz (80C86) small systems and maximum for larger applications such as
- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . .8MHz (80C86-2) multiprocessing, allow user configuration to achieve the
highest performance level. Full TTL compatibility (with the
• Low Power Operation
exception of CLOCK) and industry standard operation allow
- lCCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500µA Max use of existing NMOS 8086 hardware and software designs.
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . 10mA/MHz Typ
• 1MByte of Direct Memory Addressing Capability
Ordering Information
• 24 Operand Addressing Modes PKG.
PACKAGE TEMP. RANGE 5MHz 8MHz NO.
• Bit, Byte, Word and Block Move Operations PDIP 0oC to +70oC CP80C86 CP80C86-2 E40.6
• 8-Bit and 16-Bit Signed/Unsigned Arithmetic -40oC to +85oC lP80C86 IP80C86-2 E40.6
- Binary, or Decimal PLCC 0oC to +70oC CS80C86 CS80C86-2 N44.65
- Multiply and Divide -40oC to +85oC lS80C86 IS80C86-2 N44.65
• Wide Operating Temperature Range CERDIP 0oC to +70oC CD80C86 CD80C86-2 F40.6
- C80C86 . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC -40oC to +85oC ID80C86 ID80C86-2 F40.6
- l80C86 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC -55oC to +125oC MD80C86/B MD80C86- F40.6
- M80C86 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC 2/B
SMD# -55oC to +125oC 8405201QA 8405202QA F40.6
CLCC -55oC to +125oC MR80C86/B MR80C86- J44.A
2/B
SMD# -55oC to +125oC 8405201XA 8405202XA J44.A
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. File Number 2957.1
Copyright © Harris Corporation 1997
3-141
80C86
Pinouts
80C86 (DIP)
TOP VIEW
MAX (MIN)
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 31 RQ/GT0 (HOLD)
AD5 11 30 RQ/GT1 (HLDA)
AD4 12 29 LOCK (WR)
AD3 13 28 S2 (M/IO)
AD2 14 27 S1 (DT/R))
AD1 15 26 S0 (DEN)
AD0 16 25 QS0 (ALE)
NMI 17 24 QS1 (INTA)
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
80C86 (PLCC, CLCC)

TOP VIEW
A16/S3
A17/S4
A18/S5
AD11
AD12
AD13
AD14
AD15
GND
VCC
NC
MAX MODE
80C86
A16/S3
A17/S4
A18/S5
AD11
AD12
AD13
AD14
AD15
GND
VCC
NC
MIN MODE
80C86
6 5 4 3 2 1 44 43 42 41 40
AD10 AD10 7 39 NC NC
AD9 AD9 8 38 A19/S6 A19/S6
AD8 AD8 9 37 BHE/S7 BHE/S7
AD7 AD7 10 36 MN/MX MN/MX
AD6 AD6 11 35 RD RD
AD5 AD5 12 34 HOLD RQ/GT0
AD4 AD4 13 33 HLDA RQ/GT1
AD3 AD3 14 32 WR LOCK
AD2 AD2 15 31 M/IO S2
AD1 AD1 16 30 DT/R S1
AD0 AD0 17 29 DEN S0
18 19 20 21 22 23 24 25 26 27 28
MIN MODE
READY
RESET
80C86
TEST
INTR
INTA
GND
CLK
ALE
NMI
NC
NC
MAX MODE
80C86
READY
RESET
TEST
INTR
GND
CLK
QS1
QS0
NMI
NC
NC
3-142
80C86
Functional Diagram
EXECUTION UNIT BUS INTERFACE UNIT
REGISTER FILE RELOCATION
REGISTER FILE
DATA POINTER SEGMENT REGISTERS
AND AND
INDEX REGS INSTRUCTION POINTER
(8 WORDS) (5 WORDS)
BHE/S7
16-BIT ALU A19/S6
4
A16/S3
FLAGS
16 AD15-AD0
BUS INTERFACE UNIT
3 INTA, RD, WR
4 DT/R, DEN, ALE, M/IO
6-BYTE
INSTRUCTION
QUEUE
TEST
INTR LOCK
NMI
CONTROL AND TIMING 2 QS0, QS1
RQ/GT0, 1 2
HOLD 3 S2, S1, S0
HLDA
3
CLK RESET READY MN/MX GND
VCC
MEMORY INTERFACE
C-BUS
INSTRUCTION
STREAM BYTE
B-BUS QUEUE
ES
BUS CS
INTERFACE SS
UNIT DS
IP
EXECUTION UNIT
CONTROL SYSTEM
A-BUS
AH AL
BH BL ARITHMETIC/
LOGIC UNIT
CH CL
EXECUTION DH DL
UNIT
SP
BP
SI
DI FLAGS
3-143
80C86
Pin Description
The following pin function descriptions are for 80C86 systems in either minimum or maximum mode. The “Local Bus” in these description is
the direct multiplexed bus interface connection to the 80C86 (without regard to additional bus buffers).
PIN
SYMBOL NUMBER TYPE DESCRIPTION
AD15-AD0 2-16, 39 I/O ADDRESS DATA BUS: These lines constitute the time multiplexed memory/lO address (T1) and
data (T2, T3, TW, T4) bus. A0 is analogous to BHE for the lower byte of the data bus, pins D7-
D0. It is LOW during Ti when a byte is to be transferred on the lower portion of the bus in memory
or I/O operations. Eight-bit oriented devices tied to the lower half would normally use A0 to con-
dition chip select functions (See BHE). These lines are active HIGH and are held at high imped-
ance to the last valid logic level during interrupt acknowledge and local bus “hold acknowledge”
or “grant sequence”.
A19/S6 35-38 O ADDRESS/STATUS: During T1, these are the four most significant address lines for memory op-
A18/S5 erations. During I/O operations these lines are LOW. During memory and I/O operations, status
A17/S4 information is available on these lines during T2, T3, TW, T4. S6 is always LOW. The status of
A16/S3 the interrupt enable FLAG bit (S5) is updated at the beginning of each clock cycle. S4 and S3
are encoded as shown.
This information indicates which segment register is presently being used for data accessing.
These lines are held at high impedance to the last valid logic level during local bus “hold ac-
knowledge” or “grant sequence”.
S4 S3 CHARACTERISTICS
0 0 Alternate Data
0 1 Stack
1 0 Code or None
1 1 Data
BHE/S7 34 O BUS HIGH ENABLE/STATUS: During T1 the bus high enable signal (BHE) should be used to
enable data onto the most significant half of the data bus, pins D15-D8. Eight bit oriented devices
tied to the upper half of the bus would normally use BHE to condition chip select functions. BHE
is LOW during T1 for read, write, and interrupt acknowledge cycles when a byte is to be trans-
ferred on the high portion of the bus. The S7 status information is available during T2, T3 and
T4. The signal is active LOW, and is held at high impedance to the last valid logic level during
interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”, it is LOW during
T1 for the first interrupt acknowledge cycle.
BHE A0 CHARACTERISTICS
0 0 Whole Word
0 1 Upper Byte From/to Odd Address
1 0 Lower Byte From/to Even address
1 1 None
RD 32 O READ: Read strobe indicates that the processor is performing a memory or I/O read cycle, de-
pending on the state of the M/IO or S2 pin. This signal is used to read devices which reside on
the 80C86 local bus. RD is active LOW during T2, T3 and TW of any read cycle, and is guaran-
teed to remain HIGH in T2 until the 80C86 local bus has floated.
This line is held at a high impedance logic one state during “hold acknowledge” or “grand se-
quence”.
READY 22 I READY: is the acknowledgment from the addressed memory or I/O device that will complete the
data transfer. The RDY signal from memory or I/O is synchronized by the 82C84A Clock Gener-
ator to form READY. This signal is active HIGH. The 80C86 READY input is not synchronized.
Correct operation is not guaranteed if the Setup and Hold Times are not met.
3-144
80C86
Pin Description (Continued)
The following pin function descriptions are for 80C86 systems in either minimum or maximum mode. The “Local Bus” in these description is
the direct multiplexed bus interface connection to the 80C86 (without regard to additional bus buffers).
PIN
INTR 18 I INTERRUPT REQUEST: is a level triggered input which is sampled during the last clock cycle
of each instruction to determine if the processor should enter into an interrupt acknowledge op-
eration. A subroutine is vectored to via an interrupt vector lookup table located in system mem-
ory. It can be internally masked by software resetting the interrupt enable bit.
lNTR is internally synchronized. This signal is active HIGH.
TEST 23 I TEST: input is examined by the “Wait” instruction. If the TEST input is LOW execution continues,
otherwise the processor waits in an “Idle” state. This input is synchronized internally during each
clock cycle on the leading edge of CLK.
NMI 17 I NON-MASKABLE INTERRUPT: is an edge triggered input which causes a type 2 interrupt. A
subroutine is vectored to via an interrupt vector lookup table located in system memory. NMI is
not maskable internally by software. A transition from LOW to HIGH initiates the interrupt at the
end of the current instruction. This input is internally synchronized.
RESET 21 I RESET: causes the processor to immediately terminate its present activity. The signal must tran-
sition LOW to HIGH and remain active HIGH for at least four clock cycles. It restarts execution,
as described in the Instruction Set description, when RESET returns LOW. RESET is internally
synchronized.
CLK 19 I CLOCK: provides the basic timing for the processor and bus controller. It is asymmetric with a
33% duty cycle to provide optimized internal timing.
VCC 40 VCC: +5V power supply pin. A 0.1µF capacitor between pins 20 and 40 is recommended for de-
coupling.
GND 1, 20 GND: Ground. Note: both must be connected. A 0.1µF capacitor between pins 1 and 20 is rec-
ommended for decoupling.
MN/MX 33 I MINIMUM/MAXIMUM: Indicates what mode the processor is to operate in. The two modes are
discussed in the following sections.
Minimum Mode System

The following pin function descriptions are for the 80C86 in minimum mode (i.e., MN/MX = VCC). Only the pin functions which are unique to
minimum mode are described; all other pin functions are as described below.
PIN
M/IO 28 O STATUS LINE: logically equivalent to S2 in the maximum mode. It is used to distinguish a mem-
ory access from an I/O access. M/lO becomes valid in the T4 preceding a bus cycle and remains
valid until the final T4 of the cycle (M = HIGH, I/O = LOW). M/lO is held to a high impedance logic
one during local bus “hold acknowledge”.
WR 29 O WRITE: indicates that the processor is performing a write memory or write I/O cycle, depending
on the state of the M/IO signal. WR is active for T2, T3 and TW of any write cycle. It is active
LOW, and is held to high impedance logic one during local bus “hold acknowledge”.
INTA 24 O INTERRUPT ACKNOWLEDGE: is used as a read strobe for interrupt acknowledge cycles. It is
active LOW during T2, T3 and TW of each interrupt acknowledge cycle. Note that INTA is never
floated.
ALE 25 O ADDRESS LATCH ENABLE: is provided by the processor to latch the address into the
82C82/82C83 address latch. It is a HIGH pulse active during clock LOW of T1 of any bus cycle.
Note that ALE is never floated.
3-145
80C86
Minimum Mode System (Continued)

The following pin function descriptions are for the 80C86 in minimum mode (i.e., MN/MX = VCC). Only the pin functions which are unique to
minimum mode are described; all other pin functions are as described below.
PIN
DT/R 27 O DATA TRANSMIT/RECEIVE: is needed in a minimum system that desires to use a data bus
transceiver. It is used to control the direction of data flow through the transceiver. Logically,
DT/R is equivalent to S1 in maximum mode, and its timing is the same as for M/IO (T = HIGH,
R = LOW). DT/R is held to a high impedance logic one during local bus “hold acknowledge”.
DEN 26 O DATA ENABLE: provided as an output enable for a bus transceiver in a minimum system which
uses the transceiver. DEN is active LOW during each memory and I/O access and for INTA cy-
cles. For a read or INTA cycle it is active from the middle of T2 until the middle of T4, while for a
write cycle it is active from the beginning of T2 until the middle of T4. DEN is held to a high im-
pedance logic one during local bus “hold acknowledge”.
HOLD 31, 30 I HOLD: indicates that another master is requesting a local bus “hold”. To be an acknowledged,
HLDA O HOLD must be active HIGH. The processor receiving the “hold” will issue a “hold acknowledge”
(HLDA) in the middle of a T4 or TI clock cycle. Simultaneously with the issuance of HLDA, the
processor will float the local bus and control lines. After HOLD is detected as being LOW, the
processor will lower HLDA, and when the processor needs to run another cycle, it will again drive
the local bus and control lines.
HOLD is not an asynchronous input. External synchronization should be provided if the system
cannot otherwise guarantee the setup time.
Maximum Mode System

The following pin function descriptions are for the 80C86 system in maximum mode (i.e., MN/MX - GND). Only the pin functions which are
unique to maximum mode are described below.
PIN
S0 26 O STATUS: is active during T4, T1 and T2 and is returned to the passive state (1, 1, 1) during T3
S1 27 O or during TW when READY is HIGH. This status is used by the 82C88 Bus Controller to generate
S2 28 O all memory and I/O access control signals. Any change by S2, S1 or S0 during T4 is used to
indicate the beginning of a bus cycle, and the return to the passive state in T3 or TW is used to
indicate the end of a bus cycle.
These signals are held at a high impedance logic one state during “grant sequence”.
S2 S1 S0 CHARACTERISTICS
0 0 0 Interrupt Acknowledge
0 0 1 Read I/O Port
0 1 0 Write I/O Port
0 1 1 Halt
1 0 0 Code Access
1 0 1 Read Memory
1 1 0 Write Memory
1 1 1 Passive
3-146
80C86
Maximum Mode System (Continued)

The following pin function descriptions are for the 80C86 system in maximum mode (i.e., MN/MX - GND). Only the pin functions which are
unique to maximum mode are described below.
PIN
RQ/GT0 31, 30 I/O REQUEST/GRANT: pins are used by other local bus masters to force the processor to release
RQ/GT1 the local bus at the end of the processor’s current bus cycle. Each pin is bidirectional with
RQ/GTO having higher priority than RQ/GT1. RQ/GT has an internal pull-up bus hold device so
it may be left unconnected. The request/grant sequence is as follows (see RQ/GT Sequence
Timing)
1. A pulse of 1 CLK wide from another local bus master indicates a local bus request (“hold”)
to the 80C86 (pulse 1).
2. During a T4 or TI clock cycle, a pulse 1 CLK wide from the 80C86 to the requesting master
(pulse 2) indicates that the 80C86 has allowed the local bus to float and that it will enter the
“grant sequence” state at the next CLK. The CPU’s bus interface unit is disconnected logi-
cally from the local bus during “grant sequence”.
3. A pulse 1 CLK wide from the requesting master indicates to the 80C86 (pulse 3) that the
“hold” request is about to end and that the 80C86 can reclaim the local bus at the next CLK.
The CPU then enters T4 (or TI if no bus cycles pending).
Each Master-Master exchange of the local bus is a sequence of 3 pulses. There must be one
idle CLK cycle after each bus exchange. Pulses are active low.
If the request is made while the CPU is performing a memory cycle, it will release the local
bus during T4 of the cycle when all the following conditions are met:
1. Request occurs on or before T2.

2. Current cycle is not the low byte of a word (on an odd address).
3. Current cycle is not the first acknowledge of an interrupt acknowledge sequence.
4. A locked instruction is not currently executing.
If the local bus is idle when the request is made the two possible events will follow:
1. Local bus will be released during the next cycle.
2. A memory cycle will start within three clocks. Now the four rules for a currently active memory
cycle apply with condition number 1 already satisfied.
LOCK 29 O LOCK: output indicates that other system bus masters are not to gain control of the system bus
while LOCK is active LOW. The LOCK signal is activated by the “LOCK” prefix instruction and
remains active until the completion of the next instruction. This signal is active LOW, and is held
at a high impedance logic one state during “grant sequence”. In MAX mode, LOCK is automat-
ically generated during T2 of the first INTA cycle and removed during T2 of the second INTA
cycle.
QS1, QSO 24, 25 O QUEUE STATUS: The queue status is valid during the CLK cycle after which the queue opera-
tion is performed.
QS1 and QS0 provide status to allow external tracking of the internal 80C86 instruction queue.
Note that QS1, QS0 never become high impedance.
QSI QSO
0 0 No Operation
0 1 First byte of op code from queue
1 0 Empty the queue
1 1 Subsequent byte from queue
3-147
80C86
Functional Description code, data, extra and stack segments of up to 64K bytes
each, with each segment falling on 16-byte boundaries. (See
Static Operation Figure 1).
All 80C86 circuitry is of static design. Internal registers, FFFFFH

counters and latches are static and require no refresh as
with dynamic circuit design. This eliminates the minimum
operating frequency restriction placed on other microproces- 64K-BIT CODE SEGMENT
sors. The CMOS 80C86 can operate from DC to the speci-
fied upper frequency limit. The processor clock may be XXXXOH
stopped in either state (HIGH/LOW) and held there indefi-
nitely. This type of operation is especially useful for system
STACK SEGMENT
debug or power critical applications.
+ OFFSET
The 80C86 can be single stepped using only the CPU clock.
This state can be maintained as long as is necessary. Single SEGMENT
step clock operation allows simple interface circuitry to pro- REGISTER FILE
DATA SEGMENT
vide critical information for bringing up your system. CS
SS
Static design also allows very low frequency operation
(down to DC). In a power critical situation, this can provide DS
extremely low power operation since 80C86 power dissipa- ES

tion is directly related to operating frequency. As the system EXTRA SEGMENT
frequency is reduced, so is the operating power until, ulti-
mately, at a DC input frequency, the 80C86 power require-
ment is the standby current, (500µA maximum). 00000H
Internal Architecture
FIGURE 1. 80C86 MEMORY ORGANIZATION
The internal functions of the 80C86 processor are parti-
tioned logically into two processing units. The first is the Bus TABLE 1.
Interface Unit (BlU) and the second is the Execution Unit
(EU) as shown in the CPU functional diagram. TYPE OF DEFAULT ALTERNATE
MEMORY SEGMENT SEGMENT
These units can interact directly, but for the most part perform REFERENCE BASE BASE OFFSET
as separate asynchronous operational processors. The bus
Instruction Fetch CS None IP
interface unit provides the functions related to instruction
fetching and queuing, operand fetch and store, and address Stack Operation SS None SP
relocation. This unit also provides the basic bus control. The Variable (except DS CS, ES, SS Effective
overlap of instruction pre-fetching provided by this unit serves following) Address
to increase processor performance through improved bus
String Source DS CS, ES, SS SI
bandwidth utilization. Up to 6 bytes of the instruction stream
can be queued while waiting for decoding and execution. String Destination ES None DI
The instruction stream queuing mechanism allows the BIU BP Used As Base SS CS, DS, ES Effective
to keep the memory utilized very efficiently. Whenever there Register Address
is space for at least 2 bytes in the queue, the BlU will attempt
a word fetch memory cycle. This greatly reduces “dead-time” All memory references are made relative to base addresses
on the memory bus. The queue acts as a First-In-First-Out contained in high speed segment registers. The segment
(FIFO) buffer, from which the EU extracts instruction bytes types were chosen based on the addressing needs of pro-
as required. If the queue is empty (following a branch grams. The segment register to be selected is automatically
instruction, for example), the first byte into the queue imme- chosen according to the specific rules of Table 1. All informa-
diately becomes available to the EU. tion in one segment type share the same logical attributes
(e.g. code or data). By structuring memory into re-locatable
The execution unit receives pre-fetched instructions from the
areas of similar characteristics and by automatically select-
BlU queue and provides un-relocated operand addresses to
ing segment registers, programs are shorter, faster and
the BlU. Memory operands are passed through the BIU for pro-
more structured. (See Table 1).
cessing by the EU, which passes results to the BIU for storage.
Word (16-bit) operands can be located on even or odd
Memory Organization address boundaries and are thus, not constrained to even
boundaries as is the case in many 16-bit computers. For
The processor provides a 20-bit address to memory, which
address and data operands, the least significant byte of the
locates the byte being referenced. The memory is organized
word is stored in the lower valued address location and the
as a linear array of up to 1 million bytes, addressed as
most significant byte in the next higher address location. The
00000(H) to FFFFF(H). The memory is logically divided into
BIU automatically performs the proper number of memory
3-148
80C86
accesses; one, if the word operand is on an even byte 80C86 provides DEN and DT/R to control the transceiver, and
boundary and two, if it is on an odd byte boundary. Except ALE to latch the addresses. This configuration of the minimum
for the performance penalty, this double access is transpar- mode provides the standard demultiplexed bus structure with
ent to the software. The performance penalty does not occur heavy bus buffering and relaxed bus timing requirements.
for instruction fetches; only word operands.
The maximum mode employs the 82C88 bus controller (See
Physically, the memory is organized as a high bank (D15- Figure 6B). The 82C88 decodes status lines S0, S1 and S2,
D8) and a low bank (D7-D0) of 512K bytes addressed in par- and provides the system with all bus control signals.
allel by the processor’s address lines.
Moving the bus control to the 82C88 provides better source
Byte data with even addresses is transferred on the D7-D0 and sink current capability to the control lines, and frees the
bus lines, while odd addressed byte data (A0 HIGH) is trans- 80C86 pins for extended large system features. Hardware
ferred on the D15-D8 bus lines. The processor provides two lock, queue status, and two request/grant interfaces are pro-
enable signals, BHE and A0, to selectively allow reading vided by the 80C86 in maximum mode. These features allow
from or writing into either an odd byte location, even byte coprocessors in local bus and remote bus configurations.
location, or both. The instruction stream is fetched from
memory as words and is addressed internally by the proces- Bus Operation
sor at the byte level as necessary. The 80C86 has a combined address and data bus com-
In referencing word data, the BlU requires one or two memory monly referred to as a time multiplexed bus. This technique
cycles depending on whether the starting byte of the word is provides the most efficient use of pins on the processor
on an even or odd address, respectively. Consequently, in ref- while permitting the use of a standard 40 lead package. This
erencing word operands performance can be optimized by “local bus” can be buffered directly and used throughout the
locating data on even address boundaries. This is an espe- system with address latching provided on memory and I/O
cially useful technique for using the stack, since odd address modules. In addition, the bus can also be demultiplexed at
references to the stack may adversely affect the context the processor with a single set of 82C82 address latches if a
switching time for interrupt processing or task multiplexing. standard non-multiplexed bus is desired for the system.
Certain locations in memory are reserved for specific CPU Each processor bus cycle consists of at least four CLK
operations (See Figure 2). Locations from address FFFF0H cycles. These are referred to as T1, T2, T3 and T4 (see Fig-
through FFFFFH are reserved for operations including a jump ure 3). The address is emitted from the processor during T1
to the initial program loading routine. Following RESET, the and data transfer occurs on the bus during T3 and T4. T2 is
CPU will always begin execution at location FFFF0H where used primarily for changing the direction of the bus during
the jump must be located. Locations 00000H through 003FFH read operations. In the event that a “NOT READY” indication
are reserved for interrupt operations. Each of the 256 possible is given by the addressed device, “Wait” states (TW) are
interrupt service routines is accessed thru its own pair of 16- inserted between T3 and T4. Each inserted wait state is the
bit pointers (segment address pointer and offset address same duration as a CLK cycle. Periods can occur between
pointer). The first pointer, used as the offset address, is 80C86 driven bus cycles. These are referred to as idle”
loaded into the lP and the second pointer, which designates states (TI) or inactive CLK cycles. The processor uses these
the base address is loaded into the CS. At this point program cycles for internal housekeeping and processing.
control is transferred to the interrupt routine. The pointer ele- During T1 of any bus cycle, the ALE (Address Latch Enable)
ments are assumed to have been stored at the respective signal is emitted (by either the processor or the 82C88 bus
places in reserved memory prior to occurrence of interrupts. controller, depending on the MN/MX strap). At the trailing
edge of this pulse, a valid address and certain status infor-
Minimum and Maximum Operation Modes
mation for the cycle may be latched.
The requirements for supporting minimum and maximum
Status bits S0, S1 and S2 are used by the bus controller, in
80C86 systems are sufficiently different that they cannot be
maximum mode, to identify the type of bus transaction
met efficiently using 40 uniquely defined pins. Consequently,
according to Table 2.
the 80C86 is equipped with a strap pin (MN/MX) which
defines the system configuration. The definition of a certain TABLE 2.
subset of the pins changes, dependent on the condition of the S2 S1 S0 CHARACTERISTICS
strap pin. When the MN/MX pin is strapped to GND, the
80C86 defines pins 24 through 31 and 34 in maximum mode. 0 0 0 Interrupt
When the MN/MX pin is strapped to VCC, the 80C86 gener- 0 0 1 Read I/O
ates bus control signals itself on pins 24 through 31 and 34.
0 1 0 Write I/O
The minimum mode 80C86 can be used with either a multi- 0 1 1 Halt
plexed or demultiplexed bus. This architecture provides the
80C86 processing power in a highly integrated form. 1 0 0 Instruction Fetch
The demultiplexed mode requires two 82C82 latches (for 64K 1 0 1 Read Data from Memory
addressability) or three 82C82 latches (for a full megabyte of 1 1 0 Write Data to Memory
addressing). An 82C86 or 82C87 transceiver can also be
1 1 1 Passive (No Bus Cycle)
used if data bus buffering is required. (See Figure 6A.) The
3-149
80C86
Status bits S3 through S7 are time multiplexed with high I/O Addressing
order address bits and the BHE signal, and are therefore
In the 80C86, I/O operations can address up to a maximum
valid during T2 through T4. S3 and S4 indicate which seg-
of 64K I/O byte registers or 32K I/O word registers. The I/O
ment register (see Instruction Set Description) was used for
address appears in the same format as the memory address
this bus cycle in forming the address, according to Table 3.
on bus lines A15-A0. The address lines A19-A16 are zero in
S5 is a reflection of the PSW interrupt enable bit. S3 is I/O operations. The variable I/O instructions which use regis-
always zero and S7 is a spare status bit. ter DX as a pointer have full address capability while the
direct I/O instructions directly address one or two of the 256
TABLE 3. I/O byte locations in page 0 of the I/O address space.
S4 S3 CHARACTERISTICS I/O ports are addressed in the same manner as memory loca-
0 0 Alternate Data (Extra Segment) tions. Even addressed bytes are transferred on the D7-D0 bus
lines and odd addressed bytes on D15-D8. Care must be taken
0 1 Stack to ensure that each register within an 8-bit peripheral located on
1 0 Code or None the lower portion of the bus be addressed as even.
1 1 Data
FFFFFH RESET BOOTSTRAP

FFFF0H PROGRAM JUMP
3FFH TYPE 225 POINTER

3FCH (AVAILABLE)
AVAILABLE
INTERRUPT
POINTERS
(224)
TYPE 33 POINTER
084H (AVAILABLE)
TYPE 32 POINTER
080H (AVAILABLE)
TYPE 31 POINTER
07FH (AVAILABLE)
RESERVED
INTERRUPT
POINTERS
(27)
TYPE 5 POINTER
014H (RESERVED)
TYPE 4 POINTER
010H OVERFLOW
TYPE 3 POINTER
00CH 1 BYTE INT INSTRUCTION
DEDICATED TYPE 2 POINTER
INTERRUPT NON MASKABLE
POINTERS 008H
(5) TYPE 1 POINTER
004H SINGLE STEP
TYPE 0 POINTER CS BASE ADDRESS
000H DIVIDE ERROR IP OFFSET
16 BITS
FIGURE 2. RESERVED MEMORY LOCATIONS
3-150
80C86
(4 + NWAIT) = TCY (4 + NWAIT) = TCY

T1 T2 T3 TWAIT T4 T1 T2 T3 TWAIT T4
CLK
GOES INACTIVE IN THE STATE

JUST PRIOR TO T4
ALE
S2-S0
ADDR/ BHE, BHE

A19-A16 S7-S3 A19-A16 S7-S3
STATUS
BUS RESERVED
FOR DATA IN
D15-D0
ADDR/DATA A15-A0 A15-A0 DATA OUT (D15-D0)
VALID
RD, INTA
READY READY
READY
WAIT WAIT
DT/R
DEN
MEMORY ACCESS TIME
WR
FIGURE 3. BASIC SYSTEM TIMING
3-151
80C86
External Interface Interrupt Operations

Interrupt operations fall into two classes: software or hard-
Processor RESET and Initialization
ware initiated. The software initiated interrupts and software
Processor initialization or start up is accomplished with activa- aspects of hardware interrupts are specified in the Instruc-
tion (HIGH) of the RESET pin. The 80C86 RESET is required to tion Set Description. Hardware interrupts can be classified
be HIGH for greater than 4 CLK cycles. The 80C86 will termi- as non-maskable or maskable.
nate operations on the high-going edge of RESET and will
Interrupts result in a transfer of control to a new program loca-
remain dormant as long as RESET is HIGH. The low-going
tion. A 256-element table containing address pointers to the
transition of RESET triggers an internal reset sequence for
approximately 7 clock cycles. After this interval, the 80C86 interrupt service program locations resides in absolute loca-
operates normally beginning with the instruction in absolute tions 0 through 3FFH, which are reserved for this purpose.
location FFFF0H. (See Figure 2). The RESET input is internally Each element in the table is 4 bytes in size and corresponds
synchronized to the processor clock. At initialization, the HIGH- to an interrupt “type”. An interrupting device supplies an 8-bit
to-LOW transition of RESET must occur no sooner than 50µs type number during the interrupt acknowledge sequence,
(or 4 CLK cycles, whichever is greater) after power-up, to allow which is used to “vector” through the appropriate element to
complete initialization of the 80C86. the new interrupt service program location. All flags and both
the Code Segment and Instruction Pointer register are saved
NMl will not be recognized prior to the second CLK cycle follow- as part of the lNTA sequence. These are restored upon exe-
ing the end of RESET. If NMl is asserted sooner than nine clock cution of an Interrupt Return (IRET) instruction.
cycles after the end of RESET, the processor may execute one
instruction before responding to the interrupt. Non-Maskable Interrupt (NMI)
Bus Hold Circuitry The processor provides a single non-maskable interrupt pin
(NMI) which has higher priority than the maskable interrupt
To avoid high current conditions caused by floating inputs to
request pin (INTR). A typical use would be to activate a
CMOS devices and to eliminate need for pull-up/down resistors,
power failure routine. The NMI is edge-triggered on a LOW-
“bus-hold” circuitry has been used on the 80C86 pins 2-16, 26-
to-HIGH transition. The activation of this pin causes a type 2
32 and 34-39. (See Figure 4A and Figure 4B). These circuits
interrupt.
will maintain the last valid logic state if no driving source is
present (i.e., an unconnected pin or a driving source which NMl is required to have a duration in the HIGH state of
goes to a high impedance state). To overdrive the “bus hold” cir- greater than two CLK cycles, but is not required to be syn-
cuits, an external driver must be capable of supplying approxi- chronized to the clock. Any positive transition of NMI is
mately 400µA minimum sink or source current at valid input latched on-chip and will be serviced at the end of the current
voltage levels. Since this “bus hold” circuitry is active and not a instruction or between whole moves of a block-type instruc-
“resistive” type element, the associated power supply current is tion. Worst case response to NMI would be for multiply,
negligible and power dissipation is significantly reduced when divide, and variable shift instructions. There is no specifica-
compared to the use of passive pull-up resistors. tion on the occurrence of the low-going edge; it may occur
before, during or after the servicing of NMI. Another positive
BOND
edge triggers another response if it occurs after the start of
PAD
EXTERNAL
the NMI procedure. The signal must be free of logical spikes
OUTPUT PIN in general and be free of bounces on the low-going edge to
DRIVER avoid triggering extraneous responses.
INPUT Maskable Interrupt (INTR)

BUFFER
INPUT
PROTECTION The 80C86 provides a single interrupt request input (lNTR)
CIRCUITRY which can be masked internally by software with the reset-
ting of the interrupt enable flag (IF) status bit. The interrupt
FIGURE 4A. BUS HOLD CIRCUITRY PIN 2-16, 34-39
request signal is level triggered. It is internally synchronized
during each clock cycle on the high-going edge of CLK. To
be responded to, lNTR must be present (HIGH) during the
BOND clock period preceding the end of the current instruction or
PAD EXTERNAL
VCC P PIN the end of a whole move for a block type instruction. lNTR
OUTPUT may be removed anytime after the falling edge of the first
DRIVER
INTA signal. During the interrupt response sequence further
interrupts are disabled. The enable bit is reset as part of the
INPUT
BUFFER response to any interrupt (lNTR, NMI, software interrupt or
INPUT
PROTECTION single-step), although the FLAGS register which is automati-
CIRCUITRY cally pushed onto the stack reflects the state of the proces-
FIGURE 4B. BUS HOLD CIRCUITRY PIN 26-32 sor prior to the interrupt. Until the old FLAGS register is
restored, the enable bit will be zero unless specifically set by
an instruction.
3-152
80C86
During the response sequence (Figure 5) the processor exe- External Synchronization Via TEST
cutes two successive (back-to-back) interrupt acknowledge
As an alternative to interrupts, the 80C86 provides a single
cycles. The 80C86 emits the LOCK signal (Max mode only)
software-testable input pin (TEST). This input is utilized by
from T2 of the first bus cycle until T2 of the second. A local
executing a WAIT instruction. The single WAIT instruction is
bus “hold” request will not be honored until the end of the
repeatedly executed until the TEST input goes active (LOW).
second bus cycle. In the second bus cycle, a byte is supplied
The execution of WAIT does not consume bus cycles once
to the 80C86 by the 82C59A Interrupt Controller, which iden-
the queue is full.
tifies the source (type) of the interrupt. This byte is multiplied
by four and used as a pointer into the interrupt vector lookup If a local bus request occurs during WAIT execution, the
table. An INTR signal left HIGH will be continually responded 80C86 three-states all output drivers while inputs and I/O
to within the limitations of the enable bit and sample period. pins are held at valid logic levels by internal bus-hold circuits.
The INTERRUPT RETURN instruction includes a FLAGS If interrupts are enabled, the 80C86 will recognize interrupts
pop which returns the status of the original interrupt enable and process them when it regains control of the bus. The
bit when it restores the FLAGS. WAIT instruction is then refetched, and re-executed.
T1 T2 T3 T4 TI T1 T2 T3 T4 TABLE 4. 80C86 REGISTER
ALE
AX AH AL ACCUMULATOR
BX BH BL BASE
LOCK
CX CH CL COUNT
DX DH DL DATA
INTA
SP STACK POINTER
AD0- FLOAT TYPE BP BASE POINTER
AD15 VECTOR
SI SOURCE INDEX
DI DESTINATION INDEX
FIGURE 5. INTERRUPT ACKNOWLEDGE SEQUENCE
Halt IP INSTRUCTION POINTER

FLAGSH FLAGSL STATUS FLAG
When a software “HALT” instruction is executed the proces-
sor indicates that it is entering the “HALT” state in one of two
ways depending upon which mode is strapped. In minimum CS CODE SEGMENT
mode, the processor issues one ALE with no qualifying bus DS DATA SEGMENT
control signals. In maximum mode the processor issues SS STACK SEGMENT
appropriate HALT status on S2, S1, S0 and the 82C88 bus
ES EXTRA SEGMENT
controller issues one ALE. The 80C86 will not leave the
“HALT” state when a local bus “hold” is entered while in
“HALT”. In this case, the processor reissues the HALT indi- Basic System Timing
cator at the end of the local bus hold. An NMI or interrupt
request (when interrupts enabled) or RESET will force the Typical system configurations for the processor operating in
80C86 out of the “HALT” state. minimum mode and in maximum mode are shown in Figures
6A and 6B, respectively. In minimum mode, the MN/MX pin
is strapped to VCC and the processor emits bus control sig-
Read/Modify/Write (Semaphore) nals (e.g. RD, WR, etc.) directly. In maximum mode, the
MN/MX pin is strapped to GND and the processor emits
Operations Via Lock
coded status information which the 82C88 bus controller
The LOCK status information is provided by the processor uses to generate MULTIBUS compatible bus control signals.
when consecutive bus cycles are required during the execution Figure 3 shows the signal timing relationships.
of an instruction. This gives the processor the capability of per-
forming read/modify/write operations on memory (via the System Timing - Minimum System
Exchange Register With Memory instruction, for example) with- The read cycle begins in T1 with the assertion of the
out another system bus master receiving intervening memory Address Latch Enable (ALE) signal. The trailing (low-going)
cycles. This is useful in multiprocessor system configurations to edge of this signal is used to latch the address information,
accomplish “test and set lock” operations. The LOCK signal is which is valid on the address/data bus (AD0-AD15) at this
activated (forced LOW) in the clock cycle following decoding of time, into the 82C82/82C83 latch. The BHE and A0 signals
the software “LOCK” prefix instruction. It is deactivated at the address the low, high or both bytes. From T1 to T4 the M/lO
end of the last bus cycle of the instruction following the “LOCK” signal indicates a memory or I/O operation. At T2, the
prefix instruction. While LOCK is active a request on a RQ/GT address is removed from the address/data bus and the bus
pin will be recorded and then honored at the end of the LOCK. is held at the last valid logic state by internal bus hold
3-153
80C86
devices. The read control signal is also asserted at T2. The Bus Timing - Medium Size Systems
read (RD) signal causes the addressed device to enable its
For medium complexity systems the MN/MX pin is con-
data bus drivers to the local bus. Some time later, valid data
nected to GND and the 82C88 Bus Controller is added to the
will be available on the bus and the addressed device will
system as well as an 82C82/82C83 latch for latching the
drive the READY line HIGH. When the processor returns the
system address, and an 82C86/82C87 transceiver to allow
read signal to a HIGH level, the addressed device will again
for bus loading greater than the 80C86 is capable of han-
three-state its bus drivers. If a transceiver (82C86/82C87) is
dling. Signals ALE, DEN, and DT/R are generated by the
required to buffer the 80C86 local bus, signals DT/R and
82C88 instead of the processor in this configuration,
DEN are provided by the 80C86.
although their timing remains relatively the same. The
A write cycle also begins with the assertion of ALE and the 80C86 status outputs (S2, S1 and S0) provide type-of-cycle
emission of the address. The M/IO signal is again asserted information and become 82C88 inputs. This bus cycle infor-
to indicate a memory or I/O write operation. In T2, immedi- mation specifies read (code, data or I/O), write (data or I/O),
ately following the address emission, the processor emits interrupt acknowledge, or software halt. The 82C88 issues
the data to be written into the addressed location. This data control signals specifying memory read or write, I/O read or
remains valid until at least the middle of T4. During T2, T3 write, or interrupt acknowledge. The 82C88 provides two
and TW, the processor asserts the write control signal. The types of write strobes, normal and advanced, to be applied
write (WR) signal becomes active at the beginning of T2 as as required. The normal write strobes have data valid at the
opposed to the read which is delayed somewhat into T2 to leading edge of write. The advanced write strobes have the
provide time for output drivers to become inactive. same timing as read strobes, and hence, data is not valid at
the leading edge of write. The 82C86/82C87 transceiver
The BHE and A0 signals are used to select the proper
receives the usual T and OE inputs from the 82C88 DT/R
byte(s) of the memory/lO word to be read or written accord-
and DEN signals.
ing to Table 5.
TABLE 5. The pointer into the interrupt vector table, which is passed
during the second INTA cycle, can be derived from an
BHE A0 CHARACTERISTICS 82C59A located on either the local bus or the system bus. If
0 0 Whole word the master 82C59A Priority Interrupt Controller is positioned
on the local bus, the 82C86/82C87 transceiver must be dis-
0 1 Upper Byte From/To Odd Address abled when reading from the master 82C59A during the
1 0 Lower Byte From/To Even Address interrupt acknowledge sequence and software “poll”.
1 1 None
I/O ports are addressed in the same manner as memory

location. Even addressed bytes are transferred on the D7-D0
bus lines and odd address bytes on D15-D8.
The basic difference between the interrupt acknowledge
cycle and a read cycle is that the interrupt acknowledge sig-
nal (INTA) is asserted in place of the read (RD) signal and
the address bus is held at the last valid logic state by internal
bus hold devices. (See Figure 4). In the second of two suc-
cessive INTA cycles a byte of information is read from the
data bus (D7-D0) as supplied by the interrupt system logic
(i.e., 82C59A Priority Interrupt Controller). This byte identi-
fies the source (type) of the interrupt. It is multiplied by four
and used as a pointer into an interrupt vector lookup table,
as described earlier.
3-154
80C86
VCC
MN/MX VCC
M/IO
82C8A/85 INTA
CLOCK CLK
GENERATOR RD
READY
WR
RES RESET
RDY
DT/R
DEN
WAIT ALE
GND STATE
GENERATOR 80C86
CPU STB
GND OE
GND
AD0-AD15 ADDR
1 A16-A19 ADDR/DATA 82C82
VCC C1 LATCH
BHE 2 OR 3
GND
20
C2
T
VCC
40 OE
82C86 DATA
C1 = C2 = 0.1µF
TRANSCEIVER A0
(2) BHE
OPTIONAL EH EL W G E G CS RD WR
FOR INCREASED HM-6516 HM-6616 CMOS
DATA BUS DRIVE CMOS RAM CMOS PROM (2) 82CXX
2K x 8 2K x 8 PERIPHERALS
2K x 8 2K x 8
FIGURE 6A. MINIMUM MODE 80C86 TYPICAL CONFIGURATION
VCC
MN/MX GND CLK MRDC

82C84A/85 CLK S0 S0 MWTC
CLOCK 82C88 NC
GENERATOR/
READY S1 S1 BUS AMWC
RES RESET S2 S2 CTRLR IORC
RDY DEN IOWC
80C86 DT/R AIOWC NC
CPU ALE INTA
WAIT LOCK NC
GND STATE
GENERATOR
STB
GND OE
GND ADDR
AD0-AD15
1 A16-A19 ADDR/DATA 82C82
VCC C1 (2 OR 3)
BHE
GND
20
C2
T
VCC
40 OE DATA
82C86
C1 = C2 = 0.1µF TRANSCEIVER A0
(2) BHE
EH EL W G E G CS RDWR
HM-65162 HM-6616 CMOS
CMOS RAM CMOS PROM (2) 82CXX
PERIPHERALS
2K x 8 2K x 8 2K x 8 2K x 8
FIGURE 6B. MAXIMUM MODE 80C86 TYPICAL CONFIGURATION
3-155
80C86
Absolute Maximum Ratings Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)
Input, Output or I/O Voltage . . . . . . . . . . . .GND -0.5V to VCC +0.5V PDIP Package . . . . . . . . . . . . . . . . . . . 50 N/A
Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC PLCC Package . . . . . . . . . . . . . . . . . . 46 N/A
Junction Temperature SBDIP Package . . . . . . . . . . . . . . . . . . 30 6
Ceramic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC CLCC Package . . . . . . . . . . . . . . . . . . 40 6
Plastic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9750 Gates
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC
(Lead tips only for surface mount packages)
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Operating Conditions
Operating Supply Voltage. . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range: C80C86/-2 . . . . . . . . 0oC to +70oC
M80C86-2 ONLY. . . . . . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V I80C86/-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
M80C86/-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
DC Electrical Specifications VCC = 5.0V, ±10%; TA = 0oC to +70oC (C80C86, C80C86-2)

VCC = 5.0V, ±10%; TA = -40oC to +85oC (l80C86, I80C86-2)
VCC = 5.0V, ±10%; TA = -55oC to +125oC (M80C86)
VCC = 5.0V, ±5%; TA = -55oC to +125oC (M80C86-2)
SYMBOL PARAMETER MIN MAX UNITS TEST CONDITION

VlH Logical One 2.0 V C80C86, I80C86 (Note 5)
Input Voltage 2.2 V M80C86 (Note 5)
VIL Logical Zero Input Voltage 0.8 V
VIHC CLK Logical One Input Voltage VCC -0.8 V
VILC CLK Logical Zero Input Voltage 0.8 V
VOH Output High Voltage 3.0 V lOH = -2.5mA
VCC -0.4 V lOH = -100µA
VOL Output Low Voltage 0.4 V lOL = +2.5mA
II Input Leakage Current -1.0 1.0 µA VIN = GND or VCC DIP
Pins 17-19, 21-23, 33
lBHH Input Current-Bus Hold High -40 -400 µA VIN = - 3.0V (Note 1)
lBHL Input Current-Bus Hold Low 40 400 µA VIN = - 0.8V (Note 2)
IO Output Leakage Current - -10.0 µA VOUT = GND (Note 4)
ICCSB Standby Power Supply Current - 500 µA VCC = - 5.5V (Note 3)
ICCOP Operating Power Supply Current - 10 mA/MHz FREQ = Max, VIN = VCC or GND,
Outputs Open
Capacitance TA = 25oC
SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS

CIN Input Capacitance 25 pF FREQ = 1MHz. All measurements are referenced to device GND
COUT Output Capacitance 25 pF FREQ = 1MHz. All measurements are referenced to device GND
CI/O I/O Capacitance 25 pF FREQ = 1MHz. All measurements are referenced to device GND
NOTES:
2. lBHH should be measured after raising VIN to VCC and then lowering to 3.0V on the following pins 2-16, 26-32, 34-39.
3. IBHL should be measured after lowering VIN to GND and then raising to 0.8V on the following pins: 2-16, 34-39.
4. lCCSB tested during clock high time after halt instruction executed. VIN = VCC or GND, VCC = 5.5V, Outputs unloaded.
5. IO should be measured by putting the pin in a high impedance state and then driving VOUT to GND on the following pins: 26-29 and 32.
6. MN/MX is a strap option and should be held to VCC or GND.
3-156
80C86
AC Electrical Specifications VCC = 5.0V ±10%; TA = 0oC to +70oC (C80C86, C80C86-2)

VCC = 5.0V ±100%; TA = -40oC to +85oC (I80C86, I80C86-2)
VCC = 5.0V ±100%; TA = -55oC to +125oC (M80C86)
VCC = 5.0V ±5%; TA = -55oC to +125oC (M80C86-2)
MINIMUM COMPLEXITY SYSTEM
80C86 80C86-2
TEST
SYMBOL PARAMETER MIN MAX MIN MAX UNITS CONDITIONS
TIMING REQUIREMENTS
(1) TCLCL Cycle Period 200 125 ns
(2) TCLCH CLK Low Time 118 68 ns
(3) TCHCL CLK High Time 69 44 ns
(4) TCH1CH2 CLK Rise Time 10 10 ns From 1.0V to 3.5V
(5) TCL2C1 CLK FaIl Time 10 10 ns From 3.5V to 1.0V
(6) TDVCL Data In Setup Time 30 20 ns
(7) TCLDX1 Data In Hold Time 10 10 ns
(8) TR1VCL RDY Setup Time into 82C84A 35 35 ns

(Notes 7, 8)
(9) TCLR1X RDY Hold Time into 82C84A 0 0 ns

(Notes 7, 8)
(10) TRYHCH READY Setup Time into 80C86 118 68 ns
(11) TCHRYX READY Hold Time into 80C86 30 20 ns
(12) TRYLCL READY Inactive to CLK (Note 9) -8 -8 ns
(13) THVCH HOLD Setup Time 35 20 ns
(14) TINVCH lNTR, NMI, TEST Setup Time 30 15 ns

(Note 8)
(15) TILIH Input Rise Time (Except CLK) 15 15 ns From 0.8V to 2.0V
(16) TIHIL Input FaIl Time (Except CLK) 15 15 ns From 2.0V to 0.8V
TIMING RESPONSES
(17) TCLAV Address Valid Delay 10 110 10 60 ns CL = 100pF
(18) TCLAX Address Hold Time 10 10 ns CL = 100pF
(19) TCLAZ Address Float Delay TCLAX 80 TCLAX 50 ns CL = 100pF
(20) TCHSZ Status Float Delay 80 50 ns CL = 100pF
(21) TCHSV Status Active Delay 10 110 10 60 ns CL = 100pF
(22) TLHLL ALE Width TCLCH-20 TCLCH-10 ns CL = 100pF
(23) TCLLH ALE Active Delay 80 50 ns CL = 100pF
(24) TCHLL ALE Inactive Delay 85 55 ns CL = 100pF
3-157
80C86
AC Electrical Specifications VCC = 5.0V ±10%; TA = 0oC to +70oC (C80C86, C80C86-2)

VCC = 5.0V ±100%; TA = -55oC to +125oC (M80C86)
VCC = 5.0V ±5%; TA = -55oC to +125oC (M80C86-2) (Continued)
MINIMUM COMPLEXITY SYSTEM
80C86 80C86-2
TEST
SYMBOL PARAMETER MIN MAX MIN MAX UNITS CONDITIONS
(25) TLLAX Address Hold Time to ALE Inactive TCHCL-10 TCHCL-10 ns CL = 100pF
(26) TCLDV Data Valid Delay 10 110 10 60 ns CL = 100pF
(27) TCLDX2 Data Hold Time 10 10 ns CL = 100pF
(28) TWHDX Data Hold Time After WR TCLCL-30 TCLCL-30 ns CL = 100pF
(29) TCVCTV Control Active Delay 1 10 110 10 70 ns CL = 100pF
(30) TCHCTV Control Active Delay 2 10 110 10 60 ns CL = 100pF
(31) TCVCTX Control Inactive Delay 10 110 10 70 ns CL = 100pF
(32) TAZRL Address Float to READ Active 0 0 ns CL = 100pF
(33) TCLRL RD Active Delay 10 165 10 100 ns CL = 100pF
(34) TCLRH RD Inactive Delay 10 150 10 80 ns CL = 100pF
(35) TRHAV RD Inactive to Next Address Active TCLCL-45 TCLCL-40 ns CL = 100pF
(36) TCLHAV HLDA Valid Delay 10 160 10 100 ns CL = 100pF
(37) TRLRH RD Width 2TCLCL-75 2TCLCL-50 ns CL = 100pF
(38) TWLWH WR Width 2TCLCL-60 2TCLCL-40 ns CL = 100pF
(39) TAVAL Address Valid to ALE Low TCLCH-60 TCLCH-40 ns CL = 100pF
(40) TOLOH Output Rise Time 20 15 ns From 0.8V to 2.0V
(41) TOHOL Output Fall Time 20 15 ns From 2.0V to 0.8V
NOTES:
7. Signal at 82C84A shown for reference only.
8. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.
9. Applies only to T2 state (8ns into T3).
3-158
80C86
Waveforms
T1 T2 T3 T4
(5) TW
(1)
TCLCL TCL2CL1
TCH1CH2
CLK (82C84A OUTPUT) (4)
(3) (2)
TCHCL TCLCH TCHCTV
(30) TCHCTV (30)
M/IO
(17) (26) TCLDV (17)

TCLAV (18) TCLAX TCLAV
BHE/S7, A19/S6-A16/S3 BHE, A19-A16 S7-S3
(23) TCLLH TLHLL

(22) TLLAX
(25)
ALE
(24)
TCHLL TR1VCL (8)
RDY (82C84A INPUT) VIH
TAVAL
SEE NOTE (39)
VIL
TCLR1X (9)
(12)
TRYLCL
(11)
READY (80C86 INPUT)
TCHRYX
(10)
TRYHCH (7)
(19) (16) TCLDX1
TCLAZ TDVCL
AD15-AD0 AD15-AD0 DATA IN
(32) TAZRL (34) TCLRH TRHAV (35)
RD
READ CYCLE (30) (30)
TRLRH TCHCTV
(WR, INTA = VOH) TCHCTV TCLRL (37)
(33)
DT/R
(29) TCVCTV TCVCTX

(31)
DEN
FIGURE 7A. BUS TIMING - MINIMUM MODE SYSTEM

NOTE: Signals at 82C84A are shown for reference only. RDY is sampled near the end of T2, T3, TW to determine if TW machine states are
to be inserted.
3-159
80C86
Waveforms (Continued)
T1 T2 T3 TW T4
(4) (5)
TCH1CH2 TCL2CL1
CLK (82C84A OUTPUT) TW
(26) (27)
(17) TCLDV TCLDX2
TCLAV TCLAX (18)
AD15-AD0 AD15-AD0 DATA OUT
TWHDX (28)
TCVCTV (29) (31) TCVCTX
WRITE CYCLE
(RD, INTA, DEN
DT/R = VOH)
(29) TCVCTV (38)
TWLWH
WR
TCVCTX (31)
(19)
TCLAZ TDVCL (6)
TCLDX1 (7)
AD15-AD0 POINTER
TCHCTV (30)
TCHCTV
(30)
DT/R
INTA CYCLE
(SEE NOTE) (29) TCVCTV
(RD, WR = VOH
BHE = VOL) INTA
(29) TCVCTV TCVCTX

(31)
DEN
SOFTWARE
HALT -
AD15-AD0 INVALID ADDRESS SOFTWARE HALT
DEN, RD,
WR, INTA = VOH TCLAV
(17)
DT/R = INDETERMINATE
FIGURE 7B. BUS TIMING - MINIMUM MODE SYSTEM

NOTE: Two INTA cycles run back-to-back. The 80C86 local ADDR/DATA bus is floating during both INTA cycles. Control signals are shown
for the second INTA cycle.
3-160
80C86
AC Electrical Specifications VCC = 5.0V ±10% TA = 0oC to +70oC (C80C86, C80C86-2)

VCC = 5.0V ±10%; TA = -55oC to +125oC (M80C86)
VCC = 5.0V ±5%; TA = -55oC to +125oC (M80C86-2)
MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER)
TIMING REQUIREMENTS 80C86 80C86-2
SYMBOL PARAMETER MIN MAX MIN MAX UNITS TEST CONDITIONS
(1) TCLCL CLK Cycle Period 200 125 ns
(2) TCLCH CLK Low Time 118 68 ns
(3) TCHCL CLK High Time 69 44 ns
(4) TCH1CH2 CLK Rise Time 10 10 ns From 1.0V to 3.5V
(5) TCL2CL1 CLK Fall Time 10 10 ns From 3.5V to 1.0V
(6) TDVCL Data in Setup Time 30 20 ns
(7) TCLDX1 Data In Hold Time 10 10 ns
(8) TR1VCL RDY Setup Time into 82C84A 35 35 ns

(Notes 10, 11)
(9) TCLR1X RDY Hold Time into 82C84A 0 0 ns

(Notes 10, 11)
(10) TRYHCH READY Setup Time into 80C86 118 68 ns
(11) TCHRYX READY Hold Time into 80C86 30 20 ns
(12) TRYLCL READY Inactive to CLK (Note 12) -8 -8 ns
(13) TlNVCH Setup Time for Recognition (lNTR, 30 15 ns

NMl, TEST) (Note 11)
(14) TGVCH RQ/GT Setup Time 30 15 ns
(15) TCHGX RQ Hold Time into 80C86 (Note 13) 40 TCHCL+ 30 TCHCL+ ns
10 10
(16) TILlH Input Rise Time (Except CLK) 15 15 ns From 0.8V to 2.0V
(17) TIHIL Input Fall Time (Except CLK) 15 15 ns From 2.0V to 0.8V
TIMING RESPONSES
(18) TCLML Command Active Delay (Note 10) 5 35 5 35 ns CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
(19) TCLMH Command Inactive (Note 10) 5 35 5 35 ns CL = 100pF for All

80C86 Outputs (In
Addition to 80C86
Self Load)
(20) TRYHSH READY Active to Status Passive 110 65 ns CL = 100pF for All
(Notes 12, 14) 80C86 Outputs (In
Addition to 80C86
Self Load)
(21) TCHSV Status Active Delay 10 110 10 60 ns CL = 100pF for All

80C86 Outputs (In
Addition to 80C86
Self Load)
(22) TCLSH Status Inactive Delay (Note 14) 10 130 10 70 ns CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
3-161
80C86

VCC = 5.0V ±10%; TA = -55oC to +125oC (M80C86)

(23) TCLAV Address Valid Delay 10 110 10 60 ns CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
(24) TCLAX Address Hold Time 10 10 ns CL = 100pF for All

80C86 Outputs (In
Addition to 80C86
Self Load)
(25) TCLAZ Address Float Delay TCLAX 80 TCLAX 50 ns CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
(26) TCHSZ Status Float Delay 80 50 ns CL = 100pF for All

80C86 Outputs (In
Addition to 80C86
Self Load)
(27) TSVLH Status Valid to ALE High (Note 10) 20 20 ns CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
(28) TSVMCH Status Valid to MCE High (Note 10) 30 30 ns CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
(29) TCLLH CLK low to ALE Valid (Note 10) 20 20 ns CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
(30) TCLMCH CLK low to MCE High (Note 10) 25 25 ns CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
(31) TCHLL ALE Inactive Delay (Note 10) 4 18 4 18 ns CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
(32) TCLMCL MCE Inactive Delay (Note 10) 15 15 ns CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
(33) TCLDV Data Valid Delay 10 110 10 60 ns CL = 100pF for All

80C86 Outputs (In
Addition to 80C86
Self Load)
(34) TCLDX2 Data Hold Time 10 10 ns CL = 100pF for All

80C86 Outputs (In
Addition to 80C86
Self Load)
3-162
80C86

VCC = 5.0V ±10%; TA = -55oC to +125oC (M80C86)

(35) TCVNV Control Active Delay (Note 10) 5 45 5 45 ns CL = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
(36) TCVNX Control Inactive Delay (Note 10) 10 45 10 45 ns CL = 100pF
(37) TAZRL Address Float to Read Active 0 0 ns CL = 100pF
(38) TCLRL RD Active Delay 10 165 10 100 ns CL = 100pF
(39) TCLRH RD Inactive Delay 10 150 10 80 ns CL = 100pF
(40) TRHAV RD Inactive to Next Address Active TCLCL TCLCL ns CL = 100pF

-45 -40
(41) TCHDTL Direction Control Active Delay 50 50 ns CL = 100pF

(Note 10)
(42) TCHDTH Direction Control Inactive Delay 30 30 ns CL = 100pF

(Note 10)
(43) TCLGL GT Active Delay 10 85 0 50 ns CL = 100pF
(44) TCLGH GT Inactive Delay 10 85 0 50 ns CL = 100pF
(45) TRLRH RD Width 2TCLC 2TCLC ns CL = 100pF

L -75 L -50
(46) TOLOH Output Rise Time 20 15 ns From 0.8V to 2.0V
(47) TOHOL Output Fall Time 20 15 ns From 2.0V to 0.8V
NOTES:
10. Signal at 82C84A or 82C88 shown for reference only.
11. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.
12. Applies only to T2 state (8ns into T3).
13. The 80C86 actively pulls the RQ/GT pin to a logic one on the following clock low time.
14. Status lines return to their inactive (logic one) state after CLK goes low and READY goes high.
3-163
80C86
Waveforms
T1 T2 T3 T4
(4)
TCH1CH2
(1) (5)
TCLCL TCL2CL1 TW
CLK
(23)
TCLAV TCLCH
TCHCL (3)
(2)
QS0, QS1
TCLSH
(21) TCHSV (22)
S2, S1, S0 (EXCEPT HALT) (33) (SEE NOTE 17)
(23) TCLAV TCLDV TCLAV (23)

TCLAX (24)
BHE/S7, A19/S6-A16/S3 BHE, A19-A16 S7-S3

TSVLH
(27) TCHLL (31)
ALE (82C88 OUTPUT) TCLLH

(29)
NOTE TR1VCL (8)
RDY (82C84 INPUT)

TCLR1X (9)
(12) TRYLCL
(11)
READY 80C86 INPUT) TCHRYX
TRYHSH
(24) (20)
TCLAX
(10)
TRYHCH
(7)
(25) (6) TCLDX1
READ CYCLE TCLAV (23) TCLAZ TDVCL
AD15-AD0 AD15-AD0 DATA IN
(37) TAZRL (39) TCLRH TRHAV (40)
RD
(42)
(41) TCHDTL TCHDTH
TRLRH
TCLRL (45)
DT/R (38)
TCLML (18) TCLMH (19)

82C88
OUTPUTS MRDC OR IORC
SEE NOTES
15, 16
(35) TCVNV
DEN
TCVNX (36)
FIGURE 8A. BUS TIMING - MAXIMUM MODE (USING 82C88)

NOTES:
15. Signals at 82C84A or 82C88 are shown for reference only. RDY is sampled near the end of T2, T3, TW to determine if TW machine states
are to be inserted.
16. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA, and DEN) lags the active
high 82C88 CEN.
17. Status inactive in state just prior to T4.
3-164
80C86
T1 T2 T3 TW T4
CLK
TCHSV (21)
S2, S1, S0 (EXCEPT HALT) (SEE NOTE 20))
(23)
TCLDV (33) (22) TCLDX2 (34)
WRITE CYCLE TCLAV TCLSH
TCLAX (24)
AD15-AD0 DATA
TCVNV TCVNX (36)

(35)
DEN
TCLMH
82C88 (19)
(18) TCLML
OUTPUTS
SEE NOTES AMWC OR AIOWC
18, 19
(18)TCLML TCLMH (19)
MWTC OR IOWC
INTA CYCLE
AD15-AD0 RESERVED FOR
(SEE NOTES 21, 22) CASCADE ADDR
(25) TCLAZ (6) TDVCL TCLDX1 (7)
AD15-AD0 POINTER
TCLMCL (32)
(28) TSVMCH
(41)
MCE/PDEN TCHDTL
(30) TCLMCH (42) TCHDTH
DT/R
82C88 OUTPUTS
SEE NOTES 18, 19 (18) TCLML
INTA
TCVNV (19) TCLMH

(35)
DEN
TCVNX
SOFTWARE (36)
HALT - RD, MRDC, IORC, MWTC, AMWC, IOWC, AIOWC, INTA, S0, S1 = VOH
AD15-AD0 INVALID ADDRESS
TCLAV
(23)
S2
TCHSV TCLSH
(21) (22)
FIGURE 8B. BUS TIMING - MAXIMUM MODE (USING 82C88)

NOTES:
18. Signals at 82C84A or 82C86 are shown for reference only.
19. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA and DEN) lags the active
high 82C88 CEN.
20. Status inactive in state just prior to T4.
21. Cascade address is valid between first and second INTA cycles.
22. Two INTA cycles run back-to-back. The 80C86 local ADDR/DATA bus is floating during both INTA cycles. Control for pointer address is
shown for second INTA cycle.
3-165
80C86
ANY >0-CLK
CLK
CYCLE CYCLES
CLK
TCLGH (44) TGVCH (14) TCLGL TCLGH (44)

(1) (43)
TCLCL TCHGX (15) PULSE 2
80C86 GT
RQ/GT
PULSE 1 PULSE 3
COPROCESSOR COPROCESSOR
PREVIOUS GRANT RQ TCLAZ (25) RELEASE
AD15-AD0 80C86 COPROCESSOR
TCHSV (21)
TCHSZ (26) (SEE NOTE)
RD, LOCK
BHE/S7, A19/S0-A16/S3
S2, S1, S0
NOTE: The coprocessor may not drive the busses outside the region shown without risking contention.
FIGURE 9. REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY)
≥ 1CLK 1 OR 2
CYCLE CYCLES
CLK
THVCH (13) THVCH (13)
HOLD
TCLHAV (36) TCLHAV (36)
HLDA
TCLAZ (19)
AD15-AD0 80C86 COPROCESSOR 80C86
TCHSZ (20) TCHSV (21)

BHE/S7, A19/S6-A16/S3
RD, WR, M/IO, DT/R, DEN
FIGURE 10. HOLD/HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLY)
CLK ANY CLK CYCLE

ANY CLK CYCLE
CLK
(13)
NMI TINVCH (SEE NOTE) TCLAV TCLAV
(23) (23)
INTR SIGNAL
LOCK
TEST
NOTE: Setup requirements for asynchronous signals only to guar-

antee recognition at next CLK.
FIGURE 11. ASYNCHRONOUS SIGNAL RECOGNITION FIGURE 12. BUS LOCK SIGNAL TIMING (MAXIMUM MODE
ONLY)
3-166
80C86
≥ 50µs
VCC
CLK
(7) TCLDX1
(6) TDVCL
RESET
≥ 4 CLK CYCLES
FIGURE 13. RESET TIMING
AC Test Circuit
OUTPUT FROM TEST POINT

DEVICE UNDER TEST
CL (SEE NOTE)
NOTE: Includes stay and jig capacitance.
AC Testing Input, Output Waveform
INPUT OUTPUT
VIH + 20% VIH
VOH
1.5V 1.5V
VOL
VIL - 50% VIL
NOTE: AC Testing: All input signals (other than CLK) must switch between VILMAX -50% VIL and VIHMIN +20% VIH. CLK must switch between
0.4V and VCC.-0.4 Input rise and fall times are driven at 1ns/V.
3-167
80C86
Burn-In Circuits
MD80C86 CERDIP
C
GND
GND 1 GND VCC 40 VCC
RIO RIO
GND 2 AD14 AD15 39 VCL
RIO RO
VCL 3 AD13 AD16 38 VCC/2
RIO RO
GND 4 AD12 AD17 37 VCC/2
RIO RO
GND 5 AD11 AD18 36 VCC/2
RIO RO
VCL 6 AD10 AD19 35 VCC/2
RIO RO
GND 7 AD9 BHE 34 VCC/2
RIO
GND 8 AD8 MX 33 GND
RIO RO
GND 9 AD7 RD 32 VCC/2
RIO RI
VCL 10 AD6 RQ0 31 VCL
RIO RO
VCL 11 AD5 RQ1 30 VCL
RIO RO
VCL 12 AD4 LOCK 29 VCC/2
RO
OPEN 13 AD3 S2 28 VCC/2
RO
RO
RO
OPEN 16 AD0 QS0 25 VCC/2
RO
GND 17 NMI QS2 24 VCC/2
GND 18 INTR TEST 23 GND
RC RI
F0 19 CLK READY 22 VCL
RI
GND 20 GND RESET 21 NODE A
FROM
PROGRAM
CARD
NOTES: COMPONENTS:
VCC = 5.5V ±0.5V, GND = 0V. 1. RI = 10kΩ ±5%, 1/4W
Input voltage limits (except clock): 2. RO = 1.2kΩ ±5%, 1/4W
VIL (maximum) = 0.4V 3. RIO = 2.7kΩ ±5%, 1/4W
VIH (minimum) = 2.6V, VIH (clock) = (VCC -0.4V) minimum. 4. RC = 1kΩ ±5%, 1/4W
VCC/2 is external supply set to 2.7V ±10%. 5. C = 0.01µF (Minimum)
VCL is generated on program card (VCC - 0.65V).
Pins 13 - 16 input sequenced instructions from internal hold devices.
F0 = 100kHz ±10%.
Node A = a 40µs pulse every 2.56ms.
3-168
80C86
Burn-In Circuits (Continued)

MR80C86 CLCC
VCC
C VCL
RIO
RIO
RIO
RIO
RIO
RO
RO
RO
RIO 6 5 4 3 2 1 44 43 42 41 40
7 39
RIO RO
8 38
RIO RO
9 37
RIO
10 36
RIO RO
11 35
RIO RI
12 34
RIO RI
13 33
RO
14 32
RO
15 31
RO
16 30
RO
17 29
18 19 20 21 22 23 24 25 26 27 28
RO
RO
RC
RI
RI
VCC/2
GND
F0
A (FROM PROGRAM CARD)
NOTES: COMPONENTS:
VCC = 5.5V ±0.5V, GND = 0V. 1. RI = 10kΩ ±5%, 1/4W
Input voltage limits (except clock): 2. RO = 1.2kΩ ±5%, 1/4W
VIL (maximum) = 0.4V 3. RIO = 2.7kΩ ±5%, 1/4W
VIH (minimum) = 2.6V, VIH (clock) = (VCC -0.4V) minimum. 4. RC = 1kΩ ±5%, 1/4W
VCC/2 is external supply set to 2.7V ±10%. 5. C = 0.01µF (Minimum)
VCL is generated on program card (VCC - 0.65V).
Pins 13 - 16 input sequenced instructions from internal hold devices.
F0 = 100kHz ±10%.
Node A = a 40µs pulse every 2.56ms.
3-169
80C86
Metallization Topology
DIE DIMENSIONS: GLASSIVATION:
249.2 x 290.9 x 19 Type: Nitrox
Thickness: 10kÅ ±2kÅ
METALLIZATION:
Type: Silicon - Aluminum WORST CASE CURRENT DENSITY:
Thickness: 11kÅ ±2kÅ 1.5 x 105 A/cm2
Metallization Mask Layout

80C86
AD11 AD12 AD13 AD14 GND VCC AD15 A16/S3 A17/S4 A18/S5
A19/S6
AD10
AD9
BHE/S7
MN/MX
AD8
AD7 RD
AD6 RQ/GT0
AD5
RQ/GT1
AD4
AD3
LOCK
S2
AD2
AD1 S1
AD0 S0
NMI INTR CLK GND RESET READY TEST QS1 QS0
3-170
80C86
Instruction Set Summary

INSTRUCTION CODE
MNEMONIC AND DESCRIPTION 76543210 76543210 76543210 76543210
DATA TRANSFER
MOV = MOVE:
Register/Memory to/from Register 100010dw mod reg r/m
Immediate to Register/Memory 1100011w mod 0 0 0 r/m data data if w 1
Immediate to Register 1 0 1 1 w reg data data if w 1
Memory to Accumulator 1010000w addr-low addr-high
Accumulator to Memory 1010001w addr-low addr-high
Register/Memory to Segment Register †† 10001110 mod 0 reg r/m
Segment Register to Register/Memory 10001100 mod 0 reg r/m
PUSH = Push:
Register/Memory 11111111 mod 1 1 0 r/m
Register 0 1 0 1 0 reg
Segment Register 0 0 0 reg 1 1 0
POP = Pop:
Register/Memory 10001111 mod 0 0 0 r/m
Segment Register 0 0 0 reg 1 1 1
XCHG = Exchange:
Register/Memory with Register 1000011w mod reg r/m
Register with Accumulator 1 0 0 1 0 reg
IN = Input from:
Fixed Port 1110010w port
Variable Port 1110110w
OUT = Output to:
Fixed Port 1110011w port
Variable Port 1110111w
XLAT = Translate Byte to AL 11010111
LEA = Load EA to Register2 10001101 mod reg r/m
LDS = Load Pointer to DS 11000101 mod reg r/m
LES = Load Pointer to ES 11000100 mod reg r/m
LAHF = Load AH with Flags 10011111
SAHF = Store AH into Flags 10011110
PUSHF = Push Flags 10011100
POPF = Pop Flags 10011101
ARITHMETIC
ADD = Add:
Register/Memory with Register to Either 000000dw mod reg r/m
Immediate to Register/Memory 100000sw mod 0 0 0 r/m data data if s:w = 01
Immediate to Accumulator 0000010w data data if w = 1
ADC = Add with Carry:
Register/Memory with Register to Either 000100dw mod reg r/m
3-171
80C86
Instruction Set Summary (Continued)
INSTRUCTION CODE
Immediate to Register/Memory 100000sw mod 0 1 0 r/m data data if s:w = 01
INC = Increment:
Register/Memory 1111111w mod 0 0 0 r/m
AAA = ASCll Adjust for Add 00110111
DAA = Decimal Adjust for Add 00100111
SUB = Subtract:
Register/Memory and Register to Either 001010dw mod reg r/m
Immediate from Register/Memory 100000sw mod 1 0 1 r/m data data if s:w = 01
Immediate from Accumulator 0010110w data data if w = 1
SBB = Subtract with Borrow
Immediate from Register/Memory 100000sw mod 0 1 1 r/m data data if s:w = 01
Immediate from Accumulator 0001110w data data if w = 1
DEC = Decrement:
Register/Memory 1111111w mod 0 0 1 r/m
NEG = Change Sign 1111011w mod 0 1 1 r/m
CMP = Compare:
Register/Memory and Register 001110dw mod reg r/m
Immediate with Register/Memory 100000sw mod 1 1 1 r/m data data if s:w = 01
Immediate with Accumulator 0011110w data data if w = 1
AAS = ASCll Adjust for Subtract 00111111
DAS = Decimal Adjust for Subtract 00101111
MUL = Multiply (Unsigned) 1111011w mod 1 0 0 r/m
IMUL = Integer Multiply (Signed) 1111011w mod 1 0 1 r/m
AAM = ASCll Adjust for Multiply 11010100 00001010
DlV = Divide (Unsigned) 1111011w mod 1 1 0 r/m
IDlV = Integer Divide (Signed) 1111011w mod 1 1 1 r/m
AAD = ASClI Adjust for Divide 11010101 00001010
CBW = Convert Byte to Word 10011000
CWD = Convert Word to Double Word 10011001
LOGIC
NOT = Invert 1111011w mod 0 1 0 r/m
SHL/SAL = Shift Logical/Arithmetic Left 110100vw mod 1 0 0 r/m
SHR = Shift Logical Right 110100vw mod 1 0 1 r/m
SAR = Shift Arithmetic Right 110100vw mod 1 1 1 r/m
ROL = Rotate Left 110100vw mod 0 0 0 r/m
ROR = Rotate Right 110100vw mod 0 0 1 r/m
RCL = Rotate Through Carry Flag Left 110100vw mod 0 1 0 r/m
3-172
80C86
INSTRUCTION CODE
RCR = Rotate Through Carry Right 110100vw mod 0 1 1 r/m
AND = And:
Reg./Memory and Register to Either 0010000dw mod reg r/m
Immediate to Register/Memory 1000000w mod 1 0 0 r/m data data if w = 1
TEST = And Function to Flags, No Result:
Register/Memory and Register 1000010w mod reg r/m
Immediate Data and Register/Memory 1111011w mod 0 0 0 r/m data data if w = 1
Immediate Data and Accumulator 1010100w data data if w = 1
OR = Or:
XOR = Exclusive or:
STRING MANIPULATION
REP = Repeat 1111001z
MOVS = Move Byte/Word 1010010w
CMPS = Compare Byte/Word 1010011w
SCAS = Scan Byte/Word 1010111w
LODS = Load Byte/Word to AL/AX 1010110w
STOS = Stor Byte/Word from AL/A 1010101w
CONTROL TRANSFER
CALL = Call:
Direct Within Segment 11101000 disp-low disp-high
Indirect Within Segment 11111111 mod 0 1 0 r/m
Direct Intersegment 10011010 offset-low offset-high
seg-low seg-high
Indirect Intersegment 11111111 mod 0 1 1 r/m
JMP = Unconditional Jump:

Direct Within Segment 11101001 disp-low disp-high
Direct Within Segment-Short 11101011 disp
Indirect Within Segment 11111111 mod 1 0 0 r/m
Direct Intersegment 11101010 offset-low offset-high
seg-low seg-high
Indirect Intersegment 11111111 mod 1 0 1 r/m
RET = Return from CALL:
Within Segment 11000011
Within Seg Adding lmmed to SP 11000010 data-low data-high
3-173
80C86
INSTRUCTION CODE
Intersegment 11001011
Intersegment Adding Immediate to SP 11001010 data-low data-high
JE/JZ = Jump on Equal/Zero 01110100 disp
JL/JNGE = Jump on Less/Not Greater or Equal 01111100 disp
JLE/JNG = Jump on Less or Equal/ Not Greater 01111110 disp
JB/JNAE = Jump on Below/Not Above or Equal 01110010 disp
JBE/JNA = Jump on Below or Equal/Not Above 01110110 disp
JP/JPE = Jump on Parity/Parity Even 01111010 disp
JO = Jump on Overflow 01110000 disp
JS = Jump on Sign 01111000 disp
JNE/JNZ = Jump on Not Equal/Not Zero 01110101 disp
JNL/JGE = Jump on Not Less/Greater or Equal 01111101 disp
JNLE/JG = Jump on Not Less or Equal/Greater 01111111 disp

JNB/JAE = Jump on Not Below/Above or Equal 01110011 disp
JNBE/JA = Jump on Not Below or Equal/Above 01110111 disp
JNP/JPO = Jump on Not Par/Par Odd 01111011 disp
JNO = Jump on Not Overflow 01110001 disp
JNS = Jump on Not Sign 01111001 disp
LOOP = Loop CX Times 11100010 disp
LOOPZ/LOOPE = Loop While Zero/Equal 11100001 disp
LOOPNZ/LOOPNE = Loop While Not Zero/Equal 11100000 disp
JCXZ = Jump on CX Zero 11100011 disp
INT = Interrupt
Type Specified 11001101 type
Type 3 11001100
INTO = Interrupt on Overflow 11001110
IRET = Interrupt Return 11001111
PROCESSOR CONTROL
CLC = Clear Carry 11111000
CMC = Complement Carry 11110101
STC = Set Carry 11111001
CLD = Clear Direction 11111100
STD = Set Direction 11111101

CLl = Clear Interrupt 11111010
ST = Set Interrupt 11111011
HLT = Halt 11110100
WAIT = Wait 10011011
ESC = Escape (to External Device) 11011xxx mod x x x r/m
LOCK = Bus Lock Prefix 11110000
3-174
80C86
INSTRUCTION CODE
NOTES: if s:w = 01 then 16-bits of immediate data form the operand.
AL = 8-bit accumulator if s:w. = 11 then an immediate data byte is sign extended
AX = 16-bit accumulator to form the 16-bit operand.
CX = Count register if v = 0 then “count” = 1; if v = 1 then “count” in (CL)
DS= Data segment x = don't care
ES = Extra segment z is used for string primitives for comparison with ZF FLAG.
Above/below refers to unsigned value.
Greater = more positive; SEGMENT OVERRIDE PREFIX
Less = less positive (more negative) signed values
if d = 1 then “to” reg; if d = 0 then “from” reg 001 reg 11 0
if w = 1 then word instruction; if w = 0 then byte REG is assigned according to the following table:
instruction
if mod = 11 then r/m is treated as a REG field 16-BIT (w = 1) 8-BIT (w = 0) SEGMENT
if mod = 00 then DISP = O†, disp-low and disp-high 000 AX 000 AL 00 ES
are absent
if mod = 01 then DISP = disp-low sign-extended 001 CX 001 CL 01 CS
16-bits, disp-high is absent 010 DX 010 DL 10 SS
if mod = 10 then DISP = disp-high:disp-low
if r/m = 000 then EA = (BX) + (SI) + DISP 011 BX 011 BL 11 DS
if r/m = 001 then EA = (BX) + (DI) + DISP 100 SP 100 AH 00 ES
if r/m = 010 then EA = (BP) + (SI) + DISP
if r/m = 011 then EA = (BP) + (DI) + DISP 101 BP 101 CH 00 ES
if r/m = 100 then EA = (SI) + DISP 110 SI 110 DH 00 ES
if r/m = 101 then EA = (DI) + DISP
if r/m = 110 then EA = (BP) + DISP † 111 DI 111 BH 00 ES
if r/m = 111 then EA = (BX) + DISP Instructions which reference the flag register file as a 16-bit
DISP follows 2nd byte of instruction (before data object use the symbol FLAGS to represent the file:
if required)
† except if mod = 00 and r/m = 110 then FLAGS =
EA = disp-high: disp-low. X:X:X:X:(OF):(DF):(IF):(TF):(SF):(ZF):X:(AF):X:(PF):X:(CF)
†† MOV CS, REG/MEMORY not allowed.
Mnemonics  Intel, 1978
3-175
LPRS Data Sheet Micro Tx Transmitter Module
The Micro TX is a Type Approved AM radio transmitter module operating at UHF frequencies. It is compatible
with both low cost super-regenerative and AM superhet receivers. By providing excellent RF performance in a
Type Approved module, the Micro TX minimises design costs and delays. The sub-miniature two-pin package
ensures that the module can be fitted into any convenient space on the user's board. This makes it ideally
suited to keyfob designs, where space is often limited due to the demand for ever more compact designs.
The unique design (Patent Pending) of this module allows operation on any supply voltage between 2.5 and
13V, simply by changing one external resistor. Users requiring high performance from a compact transmitter
will appreciate the efficient operation of the module when driving a tuned loop or short whip antenna. Up to -6
dBm radiated power can be achieved with a 90 mm whip, just over half the length of the usual 1/4 wave
antenna. It is compatible with most encoding ICs operating from 3V to 12V.
Features Applications
Type Approved to MPT 1340 Low cost key-fob designs

Ultra-compact two pin package Car alarm “blippers”
Wide supply voltage 2.5 to 13 V Garage door openers
Lighting controls
Package Dimensions
+Ve
7.0mm
-Ve
8.5mm
Technical Specification
Ambient Temperature 20 ° C
Parameter Min Typical Max Units
Frequency (UK) 417.925 418.000 418.075 MHz

Frequency (Europe) 433.845 433.920 433.995 MHz
Module voltage 2.2 3.0 Volts
Supply voltage (RD = 100 ohms ) 2.5 3.5 Volts
Supply voltage (RD = 2200 ohms) 8.8 13.1 Volts
Input current (mark ) 3.0 4.6 mA
Input current (space ) 0 mA
Effective Radiated Power (ERP) -6dBm
Maximum baud rate 1200 bps
Range (with suitable receiver ) 100 Metres
Dimensions 8.5 x 7.0 x 4.2 +/- 10% mm
Pin Pitch 5.08 mm
Operating temperature -10 +40 deg. C
Storage Temperature -40 +85 deg. C
Patent Pending
MicroTx.doc Issue 1.5 Jul-98 P/N xxxxx  The Quantelec Group Page 1 of 5
Antenna
Fig. 1 shows a typical circuit for a design using a printed circuit board (PCB) loop antenna. A 1 to 5pF ceramic
trimmer is used to tune the loop for maximum output. Fig. 2 shows a typical board layout for a key fob style
transmitter. The dimensions of the loop are not critical, but excessively small or large loops should be
avoided, as these will affect antenna tuning and efficiency. The loop should enclose an area of about 700mm2
using a PCB track width of 1.5-2.5mm. Alternatively 1-1.5mm tinned copper wire may be used to form the
loop.
The module can also drive a short whip antenna by using the matching network as shown in the circuit
diagrams. The whip can be a wire rod or PCB track of about 90mm length. The inductor can be a 15nH
surface mount inductor or an air cored solenoid of 0.8mm ID, close wound with 9 turns of 0.56mm enamel
covered wire. A trimming capacitor of 1.5-5pF will generally be adequate.
When using a printed antenna on the PCB, always specify a good quality fibreglass base material. Lower cost
materials such as SRBP (paper) will cause excessive losses at UHF. For printed circuit board aerials the
variable trimmer capacitor can be replaced with two fixed value capacitors in series allowing intermediate
values of capacitance to be obtained. The aerial should then be tuned for resonance to determine the values
of the capacitors. However the variable capacitor is preferable if maximum output power and therefore range
is required for all production transmitters.
Circuit Board Layout and Decoupling
In order to achieve satisfactory RF performance, good PCB layout practice should be observed. The loop
antenna should be free of any components or tracks except for the module and the tuning capacitor. All
aerials radiate more efficiently against ground planes and the PCB should therefore be “flooded” with copper
in the areas not being used for the aerial. Double sided PCBs can provide extra area for ground planes and
the top and bottom ground plane layers should be generously connected with vias. Always use ceramic
capacitors to decouple the supply at RF.
CMOS ICs can be susceptible to local RF fields and the use of the above techniques minimises this
possibility. Do not use stripboard for prototypes as results may be misleading.
Power Supply
The Micro Tx can be matched to any power supply voltage by varying the resistor in series with the module.
The module typically requires an operating current of 4mA and drops 2.5V across it. The required series
resistor can thus be easily calculated by Ohms Law, alternatively the following table can be used. As it is a
two pin device it can be driven from either a current source or a current sink. However, ensure that the
encoding device can source or sink sufficient current. and be aware that if “sinking” current the transmitter is
“on” when the output is low, thus inverting the data if using standard encoders.
Supply Voltage Resistor Value

Min Max
-1.0 0.5 Off
2.5 3.5 100
2.8 4.0 220
3.2 4.5 330
3.6 5.2 470
4.2 6.1 680
5.2 7.6 1k
6.7 9.9 1k5
8.8 13.1 2k2
For operation at low voltages (<3V) a 100uH RF choke should be placed in series with Rd. This minimises RF
energy being absorbed by low impedance drive circuitry.
Fig.1 Application Circuits
1N4148 100n
PCB Loop Antenna

1 16 1 18
A0 VCC
2 15 2 A1 DOUT 17
3 14 3 16
A2 OSC ** See Note **
BATTERY 4 13 4 15
5 12 5 A3 OSC 14 Rd
A4 TE
6 11 6 13
7 10 7 A5 D3 12
8 9 8 A6 D2 11
A7 D1
9 GND D0 10 +VE
HT-12E -VE
UTX
RF Ground 2-5pF
220p
Short Whip Antenna Short Whip Antenna
RF Ground
** See Note **
90mm
Rd Max
+VE
15nH
+VE -VE
Encoder Encoder
Circuit Circuit 15nH 2-5pF
-VE
220p
Rd
** See Note **
220p RF Ground 2-5pF
Fig.2 Typical Tuned Loop Transmitter PCB Layout

Tuning Capacitor
Ground Plane
2.5mm
Encoding Circuits Track width
RF Out
Vcc
Notes
The Transmitter module should ideally be placed over the ground plane as shown. The loop aerial should be
completely clear of the ground plane and all other components. Do not place other components within the
loop area.
For operation at low voltages (<3V) a 100uH RF choke should be placed in series with Rd. This minimises RF
energy being absorbed by low impedance drive circuitry.
A variable tuning capacitor is preferable to one, or two fixed capacitors in series, if maximum output power is
required for all production transmitters. This allows for various tolerances in the device.
MPT 1340 Requirements (UK only)
MPT 1340 is the appropriate Type Approval specification issued by the Radio Agency (DTI) and copies may
be obtained from the RA's library service on 0171 211 0211.
The Type Approval number for this device is : 12321
Users should be aware of the following requirement:
"The equipment in which the module is used must carry an inspection mark located on the outside of the
equipment and be clearly visible. The minimum dimensions of the inspection mark shall be 10 x 15 mm and
the letter and figure height must be no less than 2mm. The wording shall read " MPT 1340 W.T. LICENCE
EXEMPT ".
Example Label:
MPT 1340
W.T. Licence Exempt
Type Approval No:
12321
MPT1340 also states that: "All transmitters shall use integral antennas only. In this specification an integral
antenna is defined as one which is designed to be connected permanently to the transmitter or receiver
without the use of an external feeder. Receivers may use an external antenna or an integral antenna.
Product Order Codes
Part No Description
LQ-TX418A-S Transmitter Module 418MHz

LQ-TX433A-S Transmitter Module 433MHz
Document History
Issue Date Revision
1.0 Nov 96 Preliminary

1.1 Jan 97 Minor corrections
1.2 Mar 97 Package dimensions modified
1.3 Aug 97 Application circuits clarified
1.4 Apr 98 Change of address, font size increased.
1.5 Apr 98 Series choke & notes added
Copyright
The information contained in this data sheet is the property of The Quantelec Group Ltd and copyright is
vested in them with all rights reserved. Under copyright law this documentation may not be copied,
photocopied, reproduced, translated or reduced to any electronic medium or machine readable form in whole
or in part without the written consent of The Quantelec Group Ltd.
The circuitry and design of the modules is also protected by copyright law.
Disclaimer
The Quantelec Group Ltd has an on going policy to improve the performance and reliability of their products,
we therefore reserve the right to make changes without notice. The information contained in this data sheet is
believed to be accurate however we do not assume any responsibility for errors nor any liability arising from
the application or use of any product or circuit described herein. This data sheet neither states nor implies
warranty of any kind, including fitness for any particular application.
For further information or technical assistance please contact: LOW POWER RADIO SOLUTIONS
A Division of The Quantelec Group Ltd.
Two Rivers Industrial Estate
Station Lane
Tel: +44 (0)1993 709418 Witney
Fax: +44 (0)1993 708575 Oxon. OX8 6BH
Web: http://www.lprs.co.uk England
Email: [email protected] .
CCD Imaging
Systems
• The CCD Element ............................................. 7.3
• Preamplifier Stage .......................................... 7.11
– Requirements ........................................... 7.12
– With DC-Restoration ................................ 7.15
• Correlated Double Sampling ......................... 7.18
• A/D Converter ................................................. 7.26
Contributing Author: Stephan Baier
7.1
CCD Imaging System
Typical Block Diagram
V/H - Driver Timing Generator
Correlated
Preamp Gain and DSP
Double A/D
and Clamp Driver
Sampling (CDS)
DC-Restore
CCD Coarse Offset D/A
Level Shift
Fine Offset
7 .2
Technology advances with CCDs (Charge Coupled Device), like increased

resolution at lower manufacturing costs, have fueled the growth in the electronic
imaging industry. However, some of the typical constraints of CCDs remain
unchanged, such as the very low output signal level and the inherent noise sources.
Furthermore, increased resolution generally equals higher read-out speed, which in
turn dictates the requirements for the subsequent electronics.
The CCD is the central element in an imaging system. Designers need to be aware
of the special requirements for the signal conditioning of the CCD in order to achieve
the maximum performance. The output signal of the CCD is a constant stream of the
individual pixel “charges” and this results in the typical form of stepped DC voltage
levels. This output signal also contains a DC-bias voltage, which is in the order of
several volts. The signal is then passed through a capacitor to block the DC voltage
before going into the preamplifier. To maintain the necessary relationship between
the pixel information and the baseline, a clamp or DC-restore circuit is usually
situated in the first processing stage. The next stage is used as a noise reduction
circuit specific to CCD based systems: the correlated double sampler (CDS).
Following is another gain stage, which could be a automatic gain control amplifier
(AGC), or a fixed gain stage with offset adjustment. Before going into the A/D
converter it usually passes through a dedicated buffer or driver circuit optimized for
the selected converter type. Further baseline stabilization can be achieved by having
a D/A converter in a digital control loop. In the following discussion the CCD itself is
looked at and design techniques are explored.
7.2
Basic CCD Theory
• Raindrops = Photons • Conveyor Belts = CCD Shift Register

• Buckets = Pixel • Metering Glass = Sense Capacitor
7 .3
In its principle, the operation of a CCD array is quiet simple. A common

analogy1 is shown here, using an array of buckets on conveyor belts. During a
rain shower the raindrops will fill the lined up buckets more or less. Then the
conveyor belts transport the buckets to the front belt and dump their content
into another row of buckets. As they move forward the rainwater is spilled into
the metering glass. The scale on the metering glass indicates how much water
was collected in the individual bucket. When relating this model to a real CCD
element, the “raindrops” are the light (photons) falling onto the CCD surface,
the buckets are the many pixels of a CCD array and the “conveyor belts” are
the shift registers that transport the pixel charge to the output stage. This
output stage is mainly the sense capacitor, here the “metering glass”, and an
output source follower is used to buffer this sense capacitor.
7.3
Basic CCD Theory
The CCD Array Configuration
Pixel
Vertical Shift
Register
Output
Horizontal CCD Shift Register Stage
7 .4
The CCD array is configured into multiple vertical shift registers and usually
one horizontal shift register, both requiring different clock patterns. The flow is
as follows: the pixel converts the light (incoming photons) into electrons which
are stored as electrical charge. Then the charge is transferred down the
vertical register in a conveyor-belt fashion to the horizontal shift register. This
register collects one line at a time and transports the pixel charges in a serial
manner to the on-chip output stage. The on-chip output converts the charge
into a voltage. This voltage is then available at the output in the typical CCD
pulse form.
With the standard CCD, most of the pixels can detect the light. The CCD also
has small sections at the beginning and at the end of each vertical segment
that are covered and therefore “optically black”. Those pixels will always have
the voltage level representing black. Some image circuits use those as
reference pixels to adjust the signal offset.
Some numbers:
The horizontal read-out speed for systems with up to 12-bit resolution is up to
10MHz. For higher resolutions (≤16-bit) the clock speed is around 1MHz.
Typical pixel dimensions are: ~27µm 2 for a 512x512 array or ~12µm 2 for a
1024x1024 array.
7.4
Basic CCD Theory
Built-In CCD Output Stage — Charge Detection
Reference
FET-Switch Drain
From Horiz. Reg.

e—
CS 1 1 1
Sense Cap. 2 2 2
VOUT
Signal Out
RLOAD
3
7 .5
Shown here is the conceptual schematic of the output stage inside the CCD element.
This stage is responsible for the so called ‘charge detection’. As discussed earlier, the
charge e— generated is moved into the horizontal shift register. The charge of each
individual pixel is controlled by the horizontal clock and stored onto the Sense
Capacitor (CS). A typical value for such a capacitor is 0.1pF to 0.5pF. According to
V = Q/C, the charge will develop a voltage across capacitor CS, representing the light
intensity for the particular pixel. A MOSFET transistor configured as a source follower
buffers the capacitor from the output node, which connects to the load resistor, RLOAD.
At this point, the image (video) signal becomes available at VOUT for further signal
processing.
As indicated in the figure above, the output voltage is a series of stepped DC voltages.
One pixel period is composed of three different levels: (1) the “reset feedthrough”, (2)
the “reference level”, (3) and the “pixel level”.
A readout sequence begins with the reset. Where the FET-switch is closed, set the
sense capacitor to the initial reference voltage. The reference voltage can be relatively
high, up to +12V. The closing of the switch causes the reset feedthrough, a result of
capacitive coupling through the MOSFET. After the decay of this feedthrough the
capacitor will reflect the reference voltage level (2). Once the capacitor has been reset,
the switch opens and pixel charge is transferred to the capacitor, altering its voltage.
An important specification for CCD elements is the sensitivity. This is a measure of the
achievable output voltage per electron, SV = VOUT /e— . With a 0.1pF capacitor, the
output voltage would be -1.6µV per electron. Unfortunately, the source follower has a
gain of less than 1 (~0.8).
7.5
System Performance Limitations
The Main Limiting Factor: NOISE
Noise Sources:
• CCD — output stage kT/C-noise
• Semiconductor Noise — Shot, Flicker, White Noise
• Resistor / Thermal Noise
• ADC Quantization Noise
• Line Frequency, 50/60Hz
7 .6
The lower limit of the dynamic range in an image system is set by the noise
floor. Different techniques are available to maximize the dynamic range and
optimize for the input range of the A/D converter, but a thorough
understanding about the noise sources is crucial. The main noise source,
besides digital feedthrough, is the so called kT/C-noise of the FET reset switch
caused by its channel resistance.
The MOSFET also contributes noise — the flicker (1/f ) noise and some white
(thermal) noise. Additionally, each resistor is a source of thermal/white noise.
Another limit is set by the quantization noise of the A/D converter. The rms
quantization noise is expressed by the equation q/√12, with q being the bit size
or LSB weight of the converter. For example, a 10-bit converter with a full-
scale input range of 2V has a bit size of 2.0V/1024 = 1.953mV. Hence, the
quantization noise is 564µVrms. Assuming a 0.1pF sense capacitor the
detection limit would be at about 350 electrons due to the quantization noise.
One obvious way to reduce this limitation is to use an A/D converter with a
higher resolution, e.g., 12 bits.
Another example for a noise source would be the line frequency with 50Hz or
60Hz.
7.6
On-chip Output Stage Noise
Reference
SW Drain
ROFF
RON Flicker Noise
Q
VOUT
CS
Reset RL
Noise
White Noise
7 .7
Looking again at the built-in output stage of the CCD, we can identify the
different noise sources previously discussed.
• RESET NOISE: The thermal noise of the channel resistance (RON ) of the
FET switch (SW). This noise is often termed as kT/C-noise. With a typical
value of 100 to 300 electrons (rms), this is the dominant limitation for the
detection of small signals.
• FLICKER NOISE: Also 1/f-noise. Originates in the MOSFET, and relates
to the presence of traps associated with contamination and crystal defects in
the semiconductor. Its magnitude is therefore process dependent.
• WHITE NOISE also known as resistor noise: It is temperature dependent and
equal to √(4kTRB). White Noise has several origins. For example, the noise
of the load resistor (RL).
7.7
A closer look at the RESET NOISE
Ref
SW
RON
ROFF
ROFF
RON
Q VOUT
CS
Reset Noise (kT/C)

+ White Noise
7 .8
The main components of reset-noise come from the sense capacitor CS and the switch (SW),
represented by its On-resistance, RON. Capacitors are usually thought of as noise-free devices.
In the case of sampling systems, however, they exhibit a theoretical noise because the
capacitor is periodically reset. The finite resistance of the reset switch has an associated
thermal noise. This noise is transferred to the capacitor when the reset switch opens. As the
resistor, RON, is made smaller, its noise will decrease, but the RC bandwidth will increase at the
same time. The noise can be calculated as follows:
The thermal noise of a resistor is given by: en = √4kTRB (Vrms).
Where:
k = Boltzmann’s constant = 1.38054 E -23
T = absolute temperature in Kelvin, (298°K = +25°C)
R = on resistance of switch in Ω
B = Noise Bandwidth in Hz
Since the CCD model has a single-pole response, B is the -3dB bandwidth times π/2, which will
be called NBW indicating the noise bandwidth for a single pole response. Therefore:
NBW = 1/ (2 π R C) • π /2 = 1/(4RC)
==> en = √ (4kTR)/(4RC) = √ (kT/C)
Using an example relevant to CCDs: CS = 0.1pF, RON = 2kΩ
The Noise Bandwidth would be: NBW = 1.25GHz
The Reset Noise would be: enr = 0.203mVrms
Taking the lowest detectable charge, one electron (e— = 1.6 E-19A-sec), the reset noise relates
to 126e— of charge. With a maximum video signal amplitude of about 0.3V (187500e— ), the
signal-to-noise ratio would be 1500 or 63dB. The dynamic range is about 11.5 bits.
7.8
A Closer Look at the White Noise
White Noise: enw = √4kTBRO
With: RO = output impedance of CCD output stage

typical RO = 200Ω to 20kΩ
Example: B = 1MHz, RO = 2000Ω

enw = 5.75µVrms
7 .9
White noise or thermal noise is present in any resistor or conductor. The rms-
voltage noise is proportional to the square root of the temperature, T, the
bandwidth, B, and the resistance, R, as given by the equation enw =√4kTRB.
The typical output resistance of a CCD, which includes the external load
resistor, is in the range of 200Ω to 20kΩ. The output impedance of the CCD
output stage (RO ) is formed by the load resistor (RL) and the channel
resistance of the output MOSFET.
7.9
The CCD Output Signal
Reset Feedthrough
Reset Level
Reference
Level
(+10VD C)
Actual
Pixel
Width Signal Amplitude
per Pixel
One Pixel Period ( V ≈ 0.3V)
7 .10
This is a typical output voltage waveform from a CCD element. The signal can
be described by five characteristics: the Reset Feedthrough, the Reset Level,
the Signal Amplitude, the Pixel Period and the actual Pixel Width.
As mentioned before, this CCD signal is not a continuous sinusoidal
waveform, but rather is a sequence of stepped DC levels.
The sequence for one pixel is as follows:
• Reset Feedthrough: This can be a relatively large pulse, as a result of
capacitive coupling through the FET.
• Reset Level: The “Sense Capacitor” will be charged to this final reset voltage.
This level can be in the order of +10V or more, creating the requirement
for a DC-decoupling capacitor at the output of the CCD element.
• Pixel Level: After the reset period, the pixel is transferred. The amplitude
corresponds to the charge representing the incident light level of the
addressed pixel. Because of the electron charge (e–) the CCD output signal
is inherently unipolar (negative).
Typical CCD pixel rates can vary between 1Mpixel/sec up to 20Mpixel/sec,
depending on the application.
7.10
First Stage - The Preamplifier
CCD Drain
DC - Block
CB
0.1µF
OPA655
+
A1 VOUT
-
RL SW
R2 R1
50Ω 200Ω
7 .11
The CCD output signal is immediately gained up by the preamplifier, as shown

in this circuit schematic. The amplifier itself uses the wideband FET input op
amp OPA655, set in a gain of +5V/V. With a -3dB bandwidth of 400MHz for a
gain of +1, the bandwidth of the OPA655, in a gain of +5V/V, is 75MHz. The
specified 12-bit settling time for this part is about 16ns. To estimate the total
response time, the slewing time for the 1Vp-p output needs to be added to the
16ns settling time. With a slewing time of 3.3ns, this adds up to a total of about
20ns. Considering a system with a 5MHz readout frequency, one pixel period
takes 200ns. The actual pixel width will be approximately half of that time, or
100ns. The OPA655 will take only 1/5 of the pixel time and still be accurate to
12 bits. The fast response of the OPA655 leaves sufficient time for the
subsequent stages and for the acquisition time of the A/D converter.
As discussed previously, the pixel information rides on the reference voltage,
which can be +10V or more. This could cause unwanted common-mode
effects or even saturation. The series capacitor, CB, blocks this DC component
from the video signal and the reference of the baseline is lost. A new baseline
can be established with the switch, SW, to ground. For each reset period the
switch closes and grounds one side of the capacitor, setting its charge to a
defined potential, ground or 0V, in this case.
7.11
The Preamplifier
Op Amp Selection Criteria
– Gain Bandwidth Product

– Slew Rate
– Settling Time
– Low Noise
– Overload Recovery
7 .12
Because of the nature of the CCD output voltage, the performance

requirements for the processing components, like the preamplifier, focus on
the time domain specifications of the ICs.
For the operational amplifier specifications like slew-rate, settling time and
overload, recovery time is important. Of course, the components should have
low noise specifications and not add too much noise to the CCD signal,
reducing the dynamic range.
7.12
High Speed Design Help
First-Order Relationships between Frequency and Time Domain
• Risetime = 0.35/Bandwidth
• Time Constant = Risetime/2.2
• Settling Time = - Time Constant x ln (% / 100)
[ % = error band in % (e.g., 0.01%) ]
• Caution: These are approximations and have their limits

due to second-order effects in High-Speed designs.
7 .13
When designing a CCD imaging system, time domain parameters of the ICs
are the specifications that the designer will look at. A designer may not always
be able to find all of them in the product data sheets and a good first-order
approximation of the missing specification can be obtained using the
relationships between the frequency and time domain shown above. For
example, the rise time may be calculated by using the simple relationship
between the -3dB bandwidth and the rise time of a first-order system: Risetime
= 0.35/Bandwidth.
This rise time may then be used to obtain the system’s time constant, which
will lead to the settling time: Time Constant = Risetime/2.2.
Another familiar relationship for a single pole system is its pulse response:
VOUT (t) = VIN (1 - e -t/τ). Here, τ is the time constant formed by RC. Solving this
equation for t results in t = - τ x ln(%/100). This provides the settling time for
any desired settling accuracy, usually used as a % term.
Again, keep in mind that all these design equations are based on a single-pole
response. The actual values may differ due to second-order effects of the ICs.
7.13
High Speed FET Op Amps
BANDWIDTH SLEW RATE SETTLING TIME NOISE
OPA655 400MHz 290V/µs 17ns 6nV/√ Hz
OPA637 80MHZ 135V/µs 450ns 4nV/√ Hz
7 .14
This table provides a selection of high speed op amps that feature a FET
input. The advantage over bipolar input stages is the very low bias current.
The bias current becomes important in applications where a capacitor is
connected to the input, or where the source impedance is high. The typical
input bias current of all three listed op amps is 5pA or better. Input bias
currents on high speed bipolar op amps are in the range of 1 to 30µA. All of
the listed op amps operate on ±5V supplies, except for the OPA671, which
requires ±15V supplies. The OPA637 is a decompensated version of the
OPA627 and therefore only stable in gains of 5 or higher. The decision
whether to use a FET input or bipolar input device will always depend on the
requirements of the individual application.
7.14
Preamplifier with DC - Restore
CB OPA655
VIN +
A1 VOUT
-
RB 402Ω
100Ω 100Ω
VREF
(variable
B + - DC - baseline)
C +
OTA SC Clamp Pulse
- E
SHC615 150Ω
150Ω CH O L D
7 .15
Another circuit example for the preamplifier and the clamp circuit is shown
here. The preamplifier uses the wideband, low noise OPA655, again
configured in a gain of +5V/V. Here, the OPA655 has a typical bandwidth of
57MHz with a 12-bit settling time of about 30ns (0.01%).
The video signal passes through the capacitor CB , blocking the DC
component. To restore the DC level to the desired baseline, the DC-restoration
IC SHC615 is used. The SHC615 basically incorporates two OTAs, or voltage
controlled current sources. One of the OTAs can be digitally controlled and
resembles a switched difference amplifier. The inverting input is connected to
a reference voltage. During the high time of the clamp pulse the switching
comparator (SC) will compare the output of the op amp to the reference level.
Any voltage difference between those pins will result in an output current that
either charges or discharges the hold capacitor, CHOLD. This charge creates a
voltage across the capacitor, which is buffered by the OTA. Multiplied by the
transconductance the voltage will cause a current flow in the collector, C,
terminal of the OTA. This current will level shift the OPA655 up to the point
where its output voltage is equal to the reference voltage. This also closes the
control loop. Because of the buffer, the voltage across CHOLD stays constant
and maintains the baseline correction during the off - time of the clamp pulse.
The external capacitor (CHOLD) allows for a wide range of flexibility. By
choosing small values, the circuit can be optimized for a short clamping period
or with higher values for a low droop rate. Another advantage of this circuit is
that small clamp peaks at the output of the switching comparator are
integrated and do not cause problems in the signal path.
7.15
DC-Restore Circuit with SHC615
511Ω
102Ω OPA643
VIN -
A1 VOUT
+
100Ω
VREF
(variable
B DC - baseline)
+ + -
C SC
OTA Clamp Pulse
- E
SHC615 150Ω
150Ω CH O L D
7 .16
This circuit shows a slight alteration of the previous restoration circuit. Here,
the FET op amp, OPA655, is replaced with the wideband, low noise amplifier,
OPA643. The OPA643 is configured in an inverting gain of 5V/V. The typical
bandwidth of the OPA643 is 250MHz, making the op amp ideal for CCD
systems with high pixel rates. The common mode voltage problem
encountered in the previous circuit is avoided with this configuration by
selecting the inverting topology for the signal processing op amp. Depending
on the individual application, the resistor values may need to be changed in
order not to load the previous stage.
7.16
The DC - Restoration Circuit SHC615
Features:
Bandwidth 280MHz
Hold Command Delay 3.8ns
Propagation Delay 2.2ns
OTA, Input IBIAS 0.3µA
SC, Hold Output IBIAS 10pA
Feedthrough Rejection -100dB
7 .17
The SHC615 is a complete monolithic IC for very fast and precise DC-
restoration, offset clamping, and low frequency hum suppression. This function
can be realized with just the SHC615 alone or having the SHC615 alongside a
video op amp for out-of-path restoration. The application list for the SHC615
also includes high speed sample and holds, high speed integrators, or peak
detectors for fast pulses. The functions inside the SHC615 are a sampling
comparator (SC) and an operational transconductance amplifier (OTA) for
buffering the external hold capacitor. The transconductance of the OTA and
the sampling comparator can be adjusted by an external resistor, allowing
bandwidth, quiescent current, and gain tradeoffs to be optimized.
7.17
Improving SNR with Correlated Double Sampling
Simplified CCD Output Signal

S1
kT/C - Noise p-p
Reset Level ∆V
Video Level S2
Note: Signals are out of scale
7 .18
As shown before, the noise is the limiting factor for the resolution in a CCD
system, where the kT/C noise is dominant. To reduce this noise, imaging
systems use a circuit called a “Correlated Double Sampler” (CDS). The name
comes from the double sampling technique of the CCD charge signal. The first
sample (S1) is taken at the end of the reset period. When the reset switch
opens again, the effective noise bandwidth changes because of the large
difference in the switch’s RON and ROFF resistance. This causes the dominating
kT/C noise essentially to “freeze” in its last point.
The other sample (S2) is taken during the video portion of the signal. Ideally,
the two samples differ only by a voltage corresponding to the transferred
charge signal. This is the video level minus the noise (∆V).
The CDS function will eliminate the kT/C noise as well as much of the 1/f and
white noise.
7.18
CDS - Circuit Concept
S/H 1
+
VIN VOUT = VRESET - VVIDEO
-
S/H 2 Difference
Amplifier
t1
t2
Reset Hold
Video Hold
Vin
S1
t1
S2
t2
Video Out 0V
7 .19
Here is a block diagram of a CDS circuit. Two sample and hold amplifiers and
one difference amplifier constitute the correlated double sampler.
The signal coming from the CCD is applied to the two sample and hold, with
their outputs connected to the difference amplifier. The timing diagram will
clarify the operation. At time t1, the sample & hold (S/H1) goes into the hold
mode, taking a sample of the reset level including the noise. This voltage
(VRESET) is applied to the non-inverting input of the difference amplifier. At time
t2, the sample and hold (S/H2) will take a sample of the video level, which is
VRESET -VVIDEO . The output voltage of the difference amplifier is defined by the
equation VOUT = VIN+ - VIN-. The sample of the reset voltage contains the kT/C
noise, which is eliminated by the subtraction of the difference amplifier.
The double sampling technique also reduces the white noise. The white noise
is part of the reset voltage (VRESET) as well as of the video amplitude (VRESET -
VVIDEO). With the assumption that the noise of the second sample was
unchanged from the instant of the first sample, the noise amplitudes are the
same and are correlated in time. Therefore, the noise can be reduced by the
CDS function.
7.19
CDS Circuit with S/H, Example #1
50Ω
-
402Ω 402Ω
SHC605 S/H1
VIN +
-
HOLD2 VOUT
200Ω A1
HOLD1
+
+ OPA658
SHC605 S/H2
200Ω
-
50Ω
7 .20
This is a circuit implementation of a correlated double sampler, CDS. It uses

two SHC605 sample and hold ICs and the current-feedback op amp OPA658.
The SHC605 has a differential input and can be connected in inverting or non-
inverting configurations. In this design both sample and holds are connected
as unity gain buffers, with a 50Ω resistor in the feedback. S/H1 will capture a
sample from the reset level. The other sample and hold, S/H2, takes the
sample of the video signal. The held output signals drive the positive and
negative inputs of the difference amplifier, A1. Its function is described by the
equation VOUT = VIN+ - VIN-. As previously shown, the result will be the charge
signal reduced by the noise component.
To match the output load of the two sample and holds, S/H2 drives into two
200Ω resistors. This matches the load S/H1 sees driving the one 402Ω resistor
to the inverting input of the amplifier A1.
For more details on the difference amplifier employing a current feedback
amplifier and optimizing it, see section 6 (High Speed Amplifiers).
7.20
CDS Circuit with S/H, Example #2
50Ω
-
200Ω 402Ω
SHC605 S/H1
VIN +
200Ω
249Ω
-
249Ω A1 VOUT
HOLD1
+
- OPA658
SHC605 S/H2
+
125Ω
HOLD2
7 .21
This circuit shows a slight modification from the previous one. It also uses two
sample and hold circuits (SHC605) to take the two samples needed for the
correlated double sampling function. Again, sample and hold amplifier S/H1 is
set in a unity gain configuration. To implement the subtract function now,
sample and hold amplifier S/H2 is used for the signal inversion. This is done by
configuring it in a gain of -1V/V. The difference amplifier can now be replaced
by a simple summing amplifier, A1. A current feedback amplifier, like the
OPA658, is the preferred choice for this function because of its wide
bandwidth and the independence of the bandwidth to the input resistors.
7.21
CDS with “Clamp and Sample” Circuit
CCD
Preamp Clamp Buffer S/H

C1 C2
VOUT
Sample
Clamp C3
7 .22
Another implementation of correlated double sampling is the “clamp and

sample” technique as shown in this circuit. Capacitor C1 blocks the high DC
level from the first amplifier stage leaving only the signal amplitude. As already
discussed, the preamplifier will gain up this signal. The capacitor C2 and the
clamp switch are the main elements within the CDS function. During the reset
period of the CCD, the clamp switch is closed, grounding one side of the
capacitor. At that time, the noise will charge the capacitor. In the next phase
the clamp switch opens and the signal charge is processed through the
amplifiers. By passing through C2 the signal level gets subtracted by the
amount of charge previously stored, thus eliminating the noise. The “noise
free” signal level gets sampled in the subsequent sample and hold stage. This
stage could be implemented by a monolithic S/H IC, like the SHC605.
7.22
CDS Clamp Circuit
402Ω
RIN C1 Clamp Buffer

VIN - 0.1µF OPA655
A1 +
Gain = - 402Ω / RIN + A2 VOUT
OPA658
-
S1 200Ω
Clamp
Pulse
100Ω
7 .23
To further improve the signal-to-noise ratio, the first amplifier, A1, gains the
input signal by G = -402Ω/RIN. This also gains the noise, but it will be removed
from the signal with the CDS function. During the CCD reset period the clamp
pulse is applied to switch S1, grounding the capacitor C1. The voltage on the
ungrounded side of this clamp capacitor remains stationary, leaving the noise
sample stored on the capacitor. The CCD reset period ends and switch S1
opens. Now the pixel information, which is also contaminated with the noise, is
transferred. Gained up by amplifier A1 the signal passes through the clamp
capacitor. Here a subtraction takes place, eliminating the noise component
from the signal. Again, this is because the capacitor carries a charge (voltage)
representing a sample of the rms-noise. As the signal passes the capacitor
C1, it is reduced by the noise sample stored on the capacitor. This effectively
eliminates the noise. The “on” and “off” state of the switch implements the
correlated double sampling.
The clamp buffer insures a decoupling of the sensitive node. The wideband
FET op amp OPA655 is used here, since the FET input assures a very low
bias current (10pA, typ). Bias current causes droop on the clamp capacitor,
which could create a significant error depending on the timing.
The output of amplifier A2 would be sampled by a sample and hold IC.
The drawback of this circuit is that the used electronic switches can introduce
kT/C-noise again. A standard CD4066 switch could be used for slow speed
systems, whereas switches like the DG611 from Siliconix could be employed
for high speed systems.
7.23
CDS with “Dual Slope Integrator”
SW2
CCD
4
1 C2
A1 -1 R1
2 -
C1 SW1
A2
3
+
1 - Integrate (-)
2 - Integrate (+)
3 - Hold
4 - Reset
7 .24
Another example of a CDS circuit is known as the dual slope integrator,

named after the method used for its implementation. A basic design schematic
is shown here. The principle function is as follows:
• During the reset time the first sample is taken with the switch (SW1) in
position 1. The sample is inverted before stored on the capacitor of the
integrator.
• The second sample is taken shortly after the signal charge is transferred from
the CCD output. Now the inverting stage is bypassed and the integrator sees
the signal without the sign inversion.
• The switch goes into position 3, which is the HOLD position. Because of the
sign inversion of the first sample, this charge will be subtracted from the
signal charge of the second sample. Because of its correlation, the portion of
the signal that gets eliminated is the noise. The signal sample is now
available for further processing.
• Before the above procedure is repeated, the charge on the integration
capacitor is zeroed by closing the reset switch (SW2) across it.
• This CDS method is often used in low-light detecting systems. The
integration time can range from ms up to several hours. The integrator CDS
is found in applications for Astronomy, Spectroscopy, Microscopy, and
Photometry. Those applications demand a wide range and high resolution.
7.24
CDS with Dual Slope Integrator
Circuit Example
Double Sampler 402Ω
Integrator
402Ω SW3
VIN -
A1 C1
+ SW1
1kΩ 1nF
-
A1, A2: OPA2650
SW2
A3 VOUT
+
+ OPA655
A2
-
25Ω
Switch: CD4066
DG611
7 .25
Another way of implementing the CDS function is by using a dual slope

integrator. The simplified circuit shown here realizes this function. The
requirement for an integrating CDS is that the video signal needs to be
preconditioned in a way that it is available as a straight signal (0° phase) and
as an inverted signal (180° phase). Here, amplifier A1 and A2 respectively,
perform this function. A dual op amp, like the OPA2650, is well suited for this,
since both amplifiers are closely matched in bandwidth and phase
characteristics. During the CCD reset phase switch SW1 closes, allowing the
integrator A3 to store the noise sample (kT/C-noise) for a finite time period.
In the next phase switch SW1 opens and switch SW2 closes, transferring the
pixel information, which also includes the noise, to the integrator. Because this
signal is now inverted, the common signal contents, which is the noise, will
cancel out leaving only the video signal.
Note that a 25Ω feedback resistor, rather than a direct short, is used for the
unity gain follower, A2. This effectively reduces the Q of what would otherwise
be a parasitic inductance (the feedback wire) into the parasitic capacitance at
the inverting input.
Depending on the application and the desired speed, the current feedback
equivalent to the OPA2650 can be used, which is the OPA2658.
The integrator circuit uses the FET input wideband amplifier OPA655.
7.25
Driver and A/D Converter
From CDS
circuit • Gain To DSP
High-Speed
• Level Shift A/D
• A/D Driver
7 .26
The last two analog processing stages within this CCD image system are the
A/D converter and its driving circuit. This circuit could also be used to make
the last span or offset adjustments to the signal to accommodate for the
maximum input range of the converter. Compared to their industrial
counterparts, converters in the imaging arena usually have a much smaller
input range, for example ±1V. One reason for this is that a ±10V input range
would require the driving amplifier to slew ten times faster for a fixed time
interval. On the other hand, the limited ±1V input range sets tighter limits on
the signal-to-noise ratio, and designers always strive to optimize the signal to
the full scale range.
On the next few pages some general design ideas will be discussed.
7.26
Fast Switching Gain Amplifier
301Ω 301Ω
TTL/ECL
Channel Select
G=2 -
OPA678
+ A
VIN A/D
B
+ CC
G=5 - 1- 4pF
75Ω 301Ω
7 .27
As the signal magnitude becomes smaller, the signal-to-noise ratio decreases.

Small signals might need to be gained in order to keep SNR at the required
level. Of course, many techniques of implementing gain are available. Besides
the continuous level adjust performed by AGCs the signal can also be
adjusted in discrete gain steps.
One circuit example that switches between two different fixed gains is given
here. The main component in this circuit is the switched op amp, or SWOP
AMP, OPA678. The OPA678 is a wideband (200MHz) op amp with two
independent differential inputs. Either one of the inputs can be selected by the
TTL or ECL logic channel select pin, which takes only 4ns. The settling time to
0.01% for a 1V step takes about 30ns. Therefore, the gain could be switched
between channel A and channel B immediately after a weak signal has been
detected. To optimize the frequency response, an external compensation
capacitor, CC, in the range of 1 to 4pF is used.
7.27
High Speed Op Amps
Implementing Level Shifting - Inverting Configuration
R2
+ R1
R1 VOUT VIN -
VIN -
VOUT
R2 +
R4
R3 R3
VOS VOS
P1 P2 P1 P2
-VS +VS -VS +VS
R2 R2 R2 R2 RP
Gain = - ± • VOS Gain = - ± 1+ • VOS
R1 R3 R1 R1 RP + R3
R2 R2
Noise Gain = 1+ Noise Gain = 1+
R1 || (R3 + P1 || P2) R1
7 .28
The driver circuit for the A/D converter can be configured for the final gain
offset adjustment. Because high speed op amps usually do not have offset
adjust capabilities directly on the IC, designers are required to implement the
appropriate level shifting externally.
Two inverting level shifting circuits are shown here. In the left figure, a current
is injected into the summing junction through R1. Even though it’s a simple
method it has the disadvantage of an increased noise gain due to R3 and the
potentiometer resistance. If R3 can be made much greater than R1 and R2, the
increase in noise gain can be limited.
The circuit on the right avoids this noise gain problem. Here, the offset voltage
is added to the signal through the non-inverting input. However, another
resistor, R4, is needed. The current noise of the non-inverting input creates,
together with R4, another noise source besides R4 itself. To reduce this noise
R4 could be bypassed with a small capacitor in parallel.
7.28
High Speed Op Amps
Implementing Level Shifting - Noninverting Configuration
VIN +
VOUT
-
R2
R1
R3
VOS
P1 P2
-VS +VS
R2 R2 R2
Gain ≈ 1+ ± • VOS Noise Gain = 1+
R1 R3 R1 || (R3+P1 || P2)
7 .29
This circuit shows the level shifting scheme for the non-inverting op amp
configuration. Similar to the first circuit, it adds a current to the summing
junction. This works well for a small adjustment range, when R3 could have a
much higher value than R1. Because the offset adjustment is in parallel to R1 it
affects the signal gain. For example, if R3 plus the potentiometer resistance is
100 times higher than R1, the gain will be altered by about 1%.
A common practice is to place the potentiometer between the two supply rails.
The disadvantage of this can be easily seen; any variations in the power
supplies will have an immediate effect to the signal.
7.29
The A/D Converter
f SAMPLING DNL Power
10-Bit
- ADS820 20MHz ± 0.2LSB 195mW
- ADS821 40MHz ± 0.5LSB 380mW
12-Bit
- ADS800 40MHz ± 0.4LSB 390mW
- ADS801 25MHz ± 0.3LSB 270mW
- ADS802 10MHz ± 0.4LSB 250mW
14-Bit
- ADC614 5.12MHz ± 0.8LSB 6.0W, Hybrid
16-Bit
- ADC701 0.5MHz ± 0.4LSB 2.8W, Hybrid
7 .30
CCDs sensors come in a wide range of capabilities which make them well-
suited for a variety of industrial and commercial applications. For example,
CCDs are largely used in commercial products like video cameras, fax
machines or document scanners. Here, the requirements are mainly focused
on the price of using an A/D converter with 8- to 12-bit resolution. Suitable A/D
converters for this market segment are the ADS8xx family, offering different
speeds and resolutions. The ADS8xxs are monolithic ICs using the pipeline
topology, allowing fast clock speeds. Built on a 0.6µm CMOS process they
come in a small 28-pin SOIC package.
In the following “High Speed A/D Converter” section we will take a closer look
into the pipeline technology and its driving circuitry.
Scientific or medical applications often need higher resolution. Using larger
CCD arrays to gather more light they usually operate with longer integration
times. This means that the throughput rate of the A/D converter does not need
to be that high. In this segment, converters with more than 12 bits of resolution
have their place. Converters like the ADC614 (14-bit) or the ADC701(16-bit)
could be used here.
7.30
KIT 48. INTRODUCTION TO POWER AUDIO AMPLIFIERS
Using complete amplifier chips like the LM386, increase. If you use 9V power supply the resistance needed
TDA2004, etc. ARE modern, quick and easy but they teach will be about 180 ohms. This is why a 200R pot has been
nothing about how power amplification actually work. used. If you will always use an 18V supply then you can
Here is a Class A & AB amplifier made from individual use a lower value pot for greater accuracy.
components. It will deliver several watts of power into an
ordinary 8 ohm speaker. It provides hands-on learning WHAT TO DO IF IT DOES NOT WORK
about audio topics such as cross-over distortion, Poor soldering is the most likely reason that the circuit
bootstrapping, complementary pairs, and push-pull. We does not work. Check all solder joints carefully under a
have given a description of these topics. good light. Next check that all components are in their
correct position on the PCB.
ASSEMBLY INSTRUCTIONS
Solder in the lowest height components first, then work up CIRCUIT DESCRIPTION
to the highest. The 10K pot is connected to the PCB by The power module has been designed for a maximum input
some 3 strand cable which you have to supply to the length signal of about 50mV. With a signal larger than this the
you require. 10K volume control acts as a potential divider to reduce
the signal and prevent distortion. For smaller signals you
Add the power transistors BD139 & BD140 last. Make will need to use a pre-amplifier. Or you could increase the
sure to get the BD139 & BD140 in the correct way around value of the 10K feedback resistor R5 and so increase the
and in their correct positions - the metal back of the amplifier gain above 11 (the ratio of (R3+R5) to R3.) Do
package goes in above the bar marked on the overlay. not reduce R3 which will also affect the frequency
Screw on the heat sinks before you solder them into the response of the amplifier.
board. You will find that both transistors must be soldered
some distance above the board so the heat sinks do not There are various classes of amplifiers which can be used
touch any of the other components. Join the two 9V battery to drive a loud speaker. The text books list them: class A,
snaps together in series to make the 18V DC. (Solder B, AB & C. The classes are defined in terms of the amount
together one red lead to the black lead of the other snap.) of bias which is applied to the amplifier input. Class A is
The metal plates of both power transistors are joined to permanently and fully biased on, while Class C only
their collectors so there is no need to insulate the heat conducts on the peaks of the signals. In this design we have
sinks. used Classes A and AB.
SETUP First Stage. Q1 & Q2 are arranged as a complementary

First remove the heat sink of Q6. This will allow easy pair in a common emitter mode. This gives a high voltage
access to the trimpot. The first setup step is to adjust the amplification. However, it has a high output impedence
trimpot to remove any crossover distortion in the power which means it is not suitable for driving an 8 ohm speaker
transistors. Because the amount of bias applied to directly. R1 & R2 apply sufficient bias to keep the
transistors increases as the resistance increases, start by transistor pair permanently turned on. The amount of bias
rotating the pot fully clockwise. This should give a places them in the middle of their conduction range so that
resistance of zero. Do this before turning on the power to they react to both positive and negative swings of the input
avoid giving too much bias. signal. There is continuous current flowing whether or not
a signal is actually present and being amplified.
Ideally to do this adjustment you should apply a 1 kHz sine
wave input. (If you have our Kit 23 you can use that.) As To reduce the wastage of quiescent current another class of
you listen to the speaker gradually rotate the pot until the amplifier, Class B, uses a pair of complementary transistors
distortion disappears. The increase in sound quality should which are not quite biased on. The signal is amplified by
be quite obvious. However check that you have not set the using the NPN transistor to react to the positive voltage
bias too high which will cause quiescent current to flow. If side of the input signal while the PNP reacts to the negative
the power transistors feel quite hot to touch without any side. At any instant only one transistor is turned on. This is
input signal then the bias is set too high. called push-pull; when the NPN transistor (like out Q5)
turns on the output voltage is pulled up towards the
If you do not have a sine wave input then a second method positive supply rail, while turning on the PNP (Q6) pushes
is to monitor the current drawn by the amplifier as the it towards ground. Class B solves the quiescent current
resistance is increased. Put an ammeter into the circuit. problem of Class A amplifiers, but introduces another -
Increasing the pot resistance will increase the current, but crossover distortion. Because the first part of the signal is
the rate of increase will become much more rapid as Q5 & used to complete the turn-on bias for each transistor you
Q6 turn on more. The elbow in the rate of current drawn introduce distortion in the output whenever the input signal
should occur about 14mA. swings between positive and negative, or negative to
positive. Enter Class AB Amplifiers.
As we will discuss below the pot resistance for no
crossover distortion should be about 22 ohms. If the Second Stage. Class AB also uses a pair of complementary
battery voltage falls below 18V the resistance will transistors acting in the same push-pull arrangement, but it
adds sufficient bias between the base-emitter junctions to combining high current with high voltage gives high power
just turn on both transistors when there is no signal (P=E x I).
flowing. When a signal is applied one of the transistors will
turn on more and the other turned off. A diode in series In general, bootstrapping provides positive feedback from
with an adjustable resistance (as in our circuit), or the the output to the input of a unity gain amplifier in such a
controlled output voltage of another transistor is normally way that a particular point of the circuit is 'pulled up by its
used to apply precise bias. If the bias is too small then own bootstraps'. The signal voltages at the opposite ends of
there will still be some distortion; but if it is too large an the bootstrap rise & fall together, with virtually the same
increased quiescent current will flow which will waste AC signal appearing on both side, providing a higher
power. impedence load for the driver transistor than its ohmic
value would indicate. Let us look at how this works for our
In the schematic you can see that the second stage of our circuit.
amplifier is set up as an emitter follower with the load
connected to the emitter of the transistor rather than the Resistor R4 is the bootstrapped load. Because it is
collector as in the first stage. The voltage at the output connected after the capacitor C3, the bootstrap is effective
'follows' the voltage at the input. They are the same value only for the AC signal and the extent of the multiplying
except from a 0.65V drop across the base-emitter junction. effect will be determined by the true voltage gain of the
The advantage of the arrangement is that it produces a nominally unity gain amplifier. Suppose the amp has true
large output current at a low output impedence. This is unity gain. Then the voltage gain at both ends of resistor
ideal for driving a speaker. R4 would be exactly the same. With no AC voltage drop
across R4 no current would flow through it so it would
Now let us look at the bias needed to remove the crossover have an effectively infinite resistance. Now suppose that
distortion which is the special feature of Class AB the voltage gain is a more realistic 0.9. This means that the
amplifiers. Because our circuit uses two Darlington pairs in voltage at the top & bottom of R4 would be 1V and 0.9V
the final amplifier stage, the bias needed to just turn on Q3 respectively making the voltage drop across it 0.1V. This is
- Q6 should be about 2.6V (4 x 0.65V.) This is supplied by only one-tenth of the full V which would occur across R4 if
the voltage drop across the green LED and the trimpot. it were connected directly to ground. Hence, R4's
After adjusting the pot to remove crossover distortion you 'bootstrapped' resistance is 10 times greater than its 1K5
you should have the following circuit values: the bias value. So to the driver transistor Q2, R4 now provides an
voltage is about 2.05V - 1.93V across the LED and 0.12V AC load impedence of 15K. The closer the gain
across the pot; a collector current of 5.44 mA and a pot approaches unity the greater the effective impedence
resistance of 22 ohm. provided by the bootstrap.
Overall Description. Q1 & Q2 form a complementary pair The advantage of such a setup is that Q1 & Q2 achieve a
for the audio voltage amplification. The advantage of using higher AC voltage gain because their output is developed
two transistors for this stage is that the arrangement has a across a higher value load resistor. If R4 were not
very high input impedence and hence does not load down bootstrapped but simply connected to ground the value of
the input signal. That means it draws very little current R4 would have to be increased to 15K to achieve the same
from the previous stage. The load for transistor Q2 is the effect. But such an increase would result in the base
green LED, the pot resistance plus R4. Note that R4 is not currents of Q4 & Q6 (which also flow through R4)
joined directly to the ground rail (as you might expect) but developing a far larger voltage across the resistor. This
indirectly via the speaker. This is called bootstrapping, a voltage could easily be large enough to turn off Q2 on the
topic we will shortly return to. negative sections of the signal preventing its voltage swing
going anywhere near ground.
The pairs of transistors Q3/Q5 & Q4/Q6 form a current
amplifier. The small valued R6 & R7 help to stabalize the Calculation. An 8 ohm speaker dissipating 1W of power
circuit. Voltage changes across these resistors act as draws an RMS current of 354 mA (P=I2R), or a peak
negative feedback and help to counteract any alterations in current of 500mA (354 x sqrt2). If the current gain of each
current caused by temperature, or differential gains in transistor Q4 & Q6 is 30 (typical) then the base current of
different transistors. There is also a negative feedback loop Q4 is 556 uA. This small current still produces a voltage
provided by R5. drop across 15K of 8.3V, restricting the negative output
voltage swing to only 0.7V (9 - 8.3V). Clearly the driver
Bootstrapping. This is a technique which allows you to transistor Q2 will shut down long before the amplifier
unlock or separate the AC & DC operations of an amplifier delivers a peak load to the speaker.
in order to get an increased power output. In some ways it
is like the operation of an inductor which has a low DC Hence the advantages of bootstrapping - the multiplied
resistance but a high AC impedence. The smaller DC resistance of the load resistor - gives us an increased AC
resistance of the bootstrapped load does not restrict the voltage gain from the first stage of the amplifier without
current flow, while the higher AC impedence results in a decreasing the AC current from the second stage. This
large voltage being generated across the load. And results in higher output power.
Supply Voltage. This calculation also explains why COMPONENTS
increasing the supply voltage will increase the volume of Resistors, 5% carbon:
the output. A higher supply voltage means that the input 1R2 R6 R7 2
signal to the power stage can have a greater voltage swing 100R R3 1
before clipping which results in a greater swing for the 1K5 R4 1
output. If the same current still flows then doubling the 1M R2 1
voltage (RMS) will double the output power. To show this 2K7 R8 1
the power output of the module was measured at various 820K R1 1
supply voltages. To do this the speaker was replaced by a 10K R5 1
5W, 8 ohm resistance, a 1kHz signal was the input and the 10K pot 1
output viewed on a CRO. The pot was adjusted for each 200R Koa trimpot 1
voltage. 0.1 uF capacitor C5 1
Electrolytic capacitors:
Next the amplitude of the input signal was adjusted to 10uF C1 1
achieve the maximum output signal without distortion (by 47uF C2 1
looking at the output on the CRO.) Then the AC voltage 100uF C3 C4 2
across the load resistor was measured. This gave an BC548B Q1 Q3 2
approximate RMS value. The power dissipated in the 8 BC558B Q2 Q4 2
ohm load was calculated from P = Vrms2/R. This gave the BD139 Q5 1
following results: BD140 Q6 1
5mm Green LED 1
VCC VRMS Power 5mm Red LED 1
9V 1.70V 361mW Speaker 8 ohm, 3" 1
12V 2.34V 684mW 9V battery snap 2
15V 3.13V 1.22W SPDT PCB switch 1
18V 3.67V 1.68W 2 Pole Terminal blocks 3
Heat sinks HS103 2
So it can be seen that any increase in supply voltage gives a Nut & bolt set 2
substantial power increase. Doubling its value gives four Kit 48 PCB 1
times the power. This is why very large power amplifiers
(hundreds of watts) need very high supply rail voltages.
Web Address & Email. You can email us at

peter@kitsrus if you have any problems or requests.
See our Web page at:
http://kitsrus.com
Acknowledgements. This module was first published in

ElectronicsAustralia December, 1993, and is adapted here
with permission. The PCB has been redesigned by DIY
Electronics.
KIT 53. CODEPAD/ALARM USING 68HC705P9
This project started out to use the K1 micro-controller (as 3 programmable User Access Codes (UAC):
used in some of our other Kits) for a codepad - entering a • UAC1 operates door strike relay only
four digit code would operate a relay. The most common • UAC2 operates auxiliary relay only
use of such a codepad is to open a security door using a • UAC3 operates both door & auxiliary relays
door relay (also called a door strike.) Then we looked at
other codepads on the market. We tried to incorporate all Programmable Master Access Code. If you forget the
their good features into our software to produce the best Master Access Code, you can enter programming mode
codepad possible. (And at the same time learn what not to and make another one if you have access to the PCB.
do from some of the very poor features we came across.)
The project outgrew the K1 and we ended up using a EEPROM for data retention and security.
Motorola 68HC705P9.
Momentary or latch output for either door strike or auxiliary
We found some codepads which already used a micro- relay.
controller (uC) did not use it to its full advantage. Other
codepads were so complicated to program that you almost Programmable access time from 1 to 9 seconds. Normally
needed a PhD in electronics! We have put together a Open (NO) and Normally Closed (NC) alarm inputs which
combined codepad & independent burglar alarm into a operate an alarm relay. Alarm inputs are turned off after
hopefully easy to understand package. It has all the normal entering a valid User Access Code 1. (Why? Because the
features of a modern codepad (EEPROM storage, alarm may be connected to a device - reed switch on the
programmable alarm times, master & user access codes, door, PIR - inside the room you are just about to enter.)
panic, tamper alarm etc.) But we have added other features Alarm inputs are re-enabled when you leave the room by
such as an independent burglar alarm with its own relay, a entering '*' followed by a valid user access code.
second relay on board with its own user access code and
direct triggering of the main door relay (used for the door Alarm inputs may be completely disabled.
strike) in software if required. We have tried to use the
power & capability of the P9 uC to make all features logical Programmable alarm time from 0001 to 9999 seconds (0000
& easy to use. The 3x4 matrix keypad is located remote from disables alarms). Alarm turned off by entering a valid user
the main board. The software code fully commented is access code. Visual indication that alarm was set off.
supplied on 3 1/2" floppy disk so you can learn how to
program these uC's for yourself. Keypad Tampering. The alarm is triggered after 4 invalid
access codes are entered consecutively over any length of
time. The invalid count is cleared by entering a valid access
code.
Panic Alarm. The alarm is triggered by pressing '*' and '#'

keys together. This feature can be disabled.
Hardware test point to check software operation.
Construction
First check the tracks on the top and bottom layers of the
PCB under a strong light. Look for any defects in the track
work. Next check the components against the listing on the
next page. The 68HC705P9P, or (P9CP) comes
preprogrammed. However, we have supplied a copy of the
source code with full comments on the floppy disk so you
can learn how to program these uC's.
It is generally good practice to insert & solder all the lowest

height components first. Note the orientation for the
Figure 1. Keypad Connections electrolytic capacitors, the ICs, the piezo buzzer and the
LED's. Bend the legs of the 7805 using needle-nosed p liers.
Do not just solder it into place then push it over; you may
Features
break the case where the legs enter it. Screw down the
3 relay outputs:
body using the nut & bolt provided.
• door strike relay (with green LED indicator)
• auxiliary relay (with yellow LED indicator)
Follow the overlay as you place the components and check
• alarm relay (flashing red LED)
them against the reference designator in the Components
list. Note that the terminal blocks slide-fit together.
Second, there are no preprogrammed defaults. When you
Keypad. Although most commercial codepads place the power-up for the first time hold down the Lost Code button
keypad & the main PCB together as a single unit we felt the - the zippy switch - in the centre of the PCB. This will take
kit was more versatile by allowing them to be separate. For you straight into program mode. This is indicated by the
example, to have the codepad unit outside a door but the rapidly flashing red & green LEDs. Press 0 (the yellow LED
expensive PCB board to be on the other side of the wall. will go on) to set the Master Access Code of 4 digits. The
We have supplied some flat rainbow cable with the kit. It is yellow LED will go out when you have entered 4 digits &
up to the user to attach the keypad to the code pad to suit the red & green LEDs will keep flashing. You have 30
their own application. The GND pad of the keypad, KP1 on seconds to continue with programming. Press 1 to set the
the PCB goes to pin 8 of the keypad unit. Then all the wires user access code 1; the yellow LED come on then goes off
connect in turn to pin 1 on the keypad unit which goes to after 4 digits are entered. Then press 2 to set user access
the top pad of KP1 in the box marked on the overlay by a code 2. (After 30 seconds of inactivity the program jumps
box. out of program mode back to normal mode.)
Looking at the back of the keypad, pin 1 is on the right and If you press an option then decide you do not want to go
pin 8 is on the left. on then press #. Pressing # a second time will take you out
of program mode. Now play with it. When you have a good
The internal matrix arrangement of the keypad can be seen idea of what is going on go into program mode again & set
on the previous page. A '1' for example is indicated to the the other program options:
microcontroller by shorting together of pins 1 & 5.
− 3. Set User Access Code 3 (4 digits)
PCB I/O. At the top of the PCB is terminal block X1. A 12V − 4. Set Door Strike relay ON time from 1 to 9 seconds
unregulated supply is satisfactory but a regulated supply (0= latch mode). (1 digit)
would be preferred. Note that the voltage output for the − 5. Set Auxiliary relay ON time from 1 to 9 seconds (0 =
door strike at X2 will draw well over 1A when operating latch mode). (1 digit)
(typically 1.4A) so the power supply must be able to deliver − 6. Set alarm ON time from 0001 to 9999 seconds (0000 =
this. A 1A supply is not enough. X2 supplies 12V when a disable). (4 digits). See below for how this option also
correct UAC1 or UAC3 is entered. X3 outputs the auxilliary affects the red LED L1.
relay triggered by UAC2. The Common, NO & NC terminals − 7. Enable/disable panic alarm (0 = disable, 1 = enable).
are available. UAC2 allows you to use the codepad to (1 digit)
operate another device from it − 8. Enable/disable user access code (1, 2 or 3) followed
by 0 (disable) or 1 (enable). (2 digits.)
X4 makes available the Common, NC & NO outputs from
the alarm relay. All these entered options are now remembered by the
93LC46. Even when the power is turned off they will be
X5 accepts NC & NO external alarm loops. Eg, the NC loop loaded automatically into the P9 upon power-up.
could go to a tamper switch; if someone forces open the
container & the switch opens then the alarm is triggered. Or Operation Guide
it could go to a reed switch that the door strike opens. If Overview. We have tried to make this Codepad & Burglar
not used put a wire connection between GND & NC Alarm as simple & logical to use as possible. We have tried
(otherwise the alarm will go off continuously.) to include different options.
Closing the terminals of X6 triggers the door strike. In other The Codepad has two modes of operation - NORMAL
codepads this is usually done in the power supply to the mode and PROGRAM mode. Normal mode is the day to
door relay itself. But it is easier & neater to incorporate the day running mode of the codepad. Program mode is used to
function into software. set or alter the various options available.
Software Test Point. Test point TP1 has been provided on NORMAL mode. The red LED L1 can be on or off. If Option
the PCB to test that the software is working. The software 6 is set to '0000' then the alarm inputs are peranently
generates a continuous 250 Hz square wave at pin 24 of the disabled & the red LED is off. If Option 6 is set between
P9. You can use a CRO or frequency meter to test for the '0001' to '9999' seconds then the alarm inputs are enabled &
presence of this signal. the L1 LED is continuously on. See "Alarm Conditions" for
further information. Let us assume for the following
First Time Start. First, did you put a wire connection discussion that the Alarm Option is on & the red LED L1 is
between the GND & NC terminals of the terminal block X5, on.
Alarm Inputs? This is the NC burglar alarm input. If there is
no connection between NC and GND then the alarm will be Entering User Access Code 1 operates the door strike relay
triggered continuously. and turns on the green LED. The red LED starts to flash.
The door strike relay remains operated for the user-
programmed entry time (1 - 9 seconds). If the door strike alarm time has elapsed. (This is to let you know that the
relay is set up for latch mode operation (0 seconds), it will alarm has been triggered.)
remain on until UAC 1 is entered again. After the relay
entry time the green LED goes but the red LED L1 keeps The alarm (and flashing LED) may be turned off by entering
flashing. For the reason see 3 paragraphs below. any valid User Access Code either with or without a *
before it.
The door strike relay may also be operated via the External
Strike Control input. (For example, a guard on the inside of If both L1 & L4 are flashing then the one entry of a UAC
the door sees you, recognises you as allowed to enter and preceeded by a '*' will turn of both of them.
presses a button to open the door for you to save you
entering the UAC.) The burglar alarm can be either the closing of a normally
open loop, or the opening of a normally closed loop. It
Entering User Access Code 2 operates the auxiliary relay operates independently of the Codepad. It could be the
and turns on the yellow LED. It remains operated for a user- input to a tamper switch if the PCB is mounted inside a box.
programmed time (1 - 9 seconds). This may be a different The burglar alarm inputs may be permanently disabled by
time to that programmed for the door strike relay. Latch setting the alarm ON time to "0000" (programming option
mode is also available if 0 seconds is set. Note that this 6). This turns the red LED off completely. Keyboard tamper
Auxilliary Relay is only rated at 1A and must not be used to and panic alarms (if enabled) are not affected except that
directly control a second door strike relay. the alarm ON time
is now automatically set to 10 minutes.
Entering User Access Code 3 operates both the door strike
and auxiliary relays. Both the green and yellow LEDs will Alarm conditions are continually monitored, even if the
turn on for their respectivelyprogrammed entry times. codepad is in Program mode. To turn off the alarm while in
Program mode, first exit Program mode then enter a valid
Flashing Red LED. Entering a valid user access code user access code.
automatically disables the alarm inputs. The red LED L1
starts to flash, indicating that the alarm inputs have been The panic alarm feature can be disabled if not required
temporarily disabled. Why do this? Because the alarm may (Program Mode Option 7).
be connected to a device - reed switch on the door, PIR -
inside the room you are just about to enter. When PROGRAM Mode. Program mode can be accessed at any
you leave the room or you want to re-enable the alarm time by entering the Master Access Code. The codepad
inputs enter '*' followed by a valid user access code. This will beep 4 times and the red and green LEDs will flash.
reactivation of the alarm input - by putting * in front of a
valid UAC will not activate a relay. It will just stop the LED When using the codepad for the first time or if you forget
flashing as the alarm input is re-enabled. All UAC's still the Master Access Code, hold down the Lost Code button
work and operate the relays. (If you want to completely when you turn on the power. This will take you directly
disable the alarm inputs and at the same time stop the LED into Program mode. There are no pre-programmed default
flashing enter '0000' for Option 6.) codes or conditions in the codepad. When first used, all
access codes and time settings must be entered by the
Each UAC may be disabled (see Program Mode). user.
Once started, each digit of an access code must be entered The flashing LEDs indicate that the codepad is waiting for
within 5 seconds of the previous one. If not, any entered a valid programming option to be entered. The codepad will
digits are "thrown away" and the sequence automatically automatically exit Program mode after 30 seconds if a valid
re-started. If you make a mistake while entering the access programming option is not entered at this point. The
code, press ' * ' or ' # ' to start again. codepad will beep 4 times and normal mode re-entered.
Alarm Conditions. The alarm relay may be triggered in Program mode may be exited by pressing ' # '.
threeways:
There are 9 valid programming options, 0 - 8:
− Burglar alarm input (provided it is enabled) − 0. Set Master Access Code (4 digits)
− Entering 4 successive invalid access codes − 1. Set User Access Code 1 (4 digits)
− Panic alarm (provided it is enabled) − 2. Set User Access Code 2 (4 digits)
− 3. Set User Access Code 3 (4 digits)
If any of the above conditions are met, the alarm relay will − 4. Set Door Strike relay ON time from 1 to 9 seconds (0
operate and remain operated for the programmed alarm time = latch mode). (1 digit)
(0001 - 9999 seconds). The alarm LED L4 will also start − 5. Set Auxiliary relay ON time from 1 to 9 seconds (0 =
flashing, giving visual indication that an alarm has been latch mode). (1 digit)
triggered. This LED L4 will continue to flash even after the
− 6. Set alarm ON time from 0001 to 9999 seconds (0000 = completely. We now use the Microchip 93LC46A (8 bit)
disable). (4 digits) NOT the B (16 bit.)
− 7. Enable/disable panic alarm (0 = disable, 1 = enable).
(1 digit) COMPONENTS
− 8. Enable/disable user access code (1, 2 or 3) followed Resistors 1/4W, 5%:
by 0 (disable) or 1 (enable). (2 digits.) 10K R5 to R15, R17 12
560R R2 R3 R4 R16 4
Once a programming option has been entered, the yellow 10M R1 1
LED will turn on. This indicates that the codepad is waiting
for new programming data to be entered. Capacitors:
10nF mono cap C7 1
Data entry must commence within 5 seconds of the 100nF mono caps C1 C4 2
programming option being selected. Where more than 1 10uF mini elcap C5 1
digit of data is required (e.g. access codes), each digit must 1uF mini elcap C6 1
be entered within 5 seconds of the previous one. If not, the 27pF ceramic C2 C3 2
codepad will automatically exit the programming option
selected. Pressing '#' will abort the option selected without Regulator 7805 1
any change taking place. In either case, a long beep will EEPROM 93LC46A IC2 1
sound to indicate the "error" condition. Programmed 68HC705P9CP 1
BC547 Q1 Q2 Q3 Q4 4
Four beeps will sound when the correct data is entered and Piezo Buzzer B1 1
the codepad will return to Program mode entry (flashing Zippy tact switch SW1 1
red/green LEDs and yellow LED off). There is no "enter" 1N4004 diode D1 D2 D3 D4 4
key. 4.7V zener diode D5 1
12V Relay RWH-SH-112D / RUDH-SS-112D 1
Options 0,1,2,3 and 6 require 4 digits, options 4, 5 and 7 Mini 12V relay UA-SH-112D 2
require 1 digit and option 8 requires 2 digits. 4.000 mHz crystal (49U/S) Y1 1
3mm green LED L2 1
External Control Input. This normally open input allows a 3mm red LED L1 L4 2
pushbutton switch or remote control device to be 3mm yellow LED L3 1
connected to the codepad. Shorting the two input pins 3x4 key X-Y Codepad 1
together operates the door strike relay for the programmed 2 pole terminal block 3
ON time. This input is disabled when the codepad is in 3 pole terminal block 3
program mode. Nut & bolt for 7805 1 set
K53 PCB 1
Access Code Priorities. The Master Access Code has 8 pin IC socket 1
priority over all the User Access Codes. This means that 28 pin IC socket 1
any User Access Code that is the same as the Master Rainbow ribbon cable, 8 strand 12"
Access Code will be ignored. The User Access Codes also Floppy disk 1
have a priority order, 1-2-3. Setting 2 or more User Access Documentation
Codes the same will cause the lower priority code to be
ignored.
For questions email the kit designer Frank Crivelli at
Some Technical Information. The MC68HC705P9P (or
P9CP) is a member of the HC05 family of 8-bit [email protected]
microcontrollers from Motorola. The P9 contains 2112 -------------------
bytes of one-time programmable ROM, and 128 bytes of
user RAM. There are 20 bi-directional I/O port pins and one
input-only port pin. There is a 4 channel, 8 bit ADC. Single
3.3V - 5.0V supply. The P suffix means that it is a One Time
Programmable device. There is no window in it to allow the
program to be erased. See the MC68HC705P9 Data Book
from Motorola for full information or download it from their
website.
93LC46/93C46. This IC can be a trap. There are 8 bit & 16

bit versions & not all manufacturers support both versions.
Some manufacturers pull a pin high or low to switch
between versions. Others like Microchip use different parts

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K55.

SUCTION CUP PHONE PICKUP

The telephone pickup circuit consists of two high gain COMPONENTS

The decoder is activated whenever the phone is picked Power Consumption

Call progress detection is not implemented on this --------------------

8031 Single Board Computer

DIY Electronics (HK) Ltd

Fax: (852) 2725-0610

Running in 8031 mode

1. Insert a link on jumper JP1.

Running in BASIC mode

1. Remove the link from jumper JP1.

Southern Cross II Memory Map

Figure 1 gives an overall picture of the Southern Cross II memory map.

The Southern Cross II has two serial ports.

RS-232 Interface - J5, J6

8031 I/O ports - J1

J1 pin Signal J1 pin Signal

8255 I/O Ports - J2

J2 pin Signal J2 pin Signal

Bit port 1 FC00h

J4 pin Signal J4 pin Signal

I/O Expansion Interface - J3

J3 pin Signal J3 pin Signal

1. Disconnect any device attached to connector J1.

The following web sites contain 80xx code & material

Question: Why Register?

Please fill in the form below and return to:

DIY ELECTRONICS (HK) LTD

or fax to (852) 2725-0610.

Your comments about the Southern Cross II are most welcome.

MVS-31 Disk size for 360K 1.2M 720K 1.44M

T.K. HAREENDRAN also pulled down by resistor R5. Clock in-

ELECTRONICS FOR YOU APRIL 2003

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ASHOK K. DOCTOR the figure. The IC is pro-

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DAVID NASH PIOUS

mitter is 60 to 100 The transmitted message can be heard over

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Fig. 1: Flow of traffic in all possible directions

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ELECTRONICS FOR YOU NOVEMBER 2002

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#include<stdio.h> c=(seq&1);b=(seq&2)>>1;a=(seq&4)>>2; walk_ns,stop_ns,

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INFRARED TOY CAR SAN

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ANTI-THEFT SECURITY mately 5 seconds as ‘on’ and 5 seconds as

FOR CAR AUDIOS S.C.

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RING TONE GENERATOR

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DTMF PROXIMITY DETECTOR

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