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    Appendix A-Project Planning Chart: Legend

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    abdul.azeez
    The document outlines a project planning chart for designing a high speed link buffer for an HDLC processor over 12 steps from August 2009 to May 2010. The steps include literature surveys, studying tools and simulation techniques, defining the architecture at the top and block levels, RTL coding, simulation and analysis, implementation on an FPGA, and a final software and hardware demo.

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    Appendix A-Project Planning Chart: Legend

    Uploaded by

    abdul.azeez
    4 views2 pages
    The document outlines a project planning chart for designing a high speed link buffer for an HDLC processor over 12 steps from August 2009 to May 2010. The steps include literature surveys, studying tools and simulation techniques, defining the architecture at the top and block levels, RTL coding, simulation and analysis, implementation on an FPGA, and a final software and hardware demo.

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    PERT1 ,apendix

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    The document outlines a project planning chart for designing a high speed link buffer for an HDLC processor over 12 steps from August 2009 to May 2010. The steps include literature surveys, studying tools and simulation techniques, defining the architecture at the top and block levels, RTL coding, simulation and analysis, implementation on an FPGA, and a final software and hardware demo.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as XLSX, PDF, TXT or read online from Scribd
    Download as xlsx, pdf, or txt
    4 views2 pages

    Appendix A-Project Planning Chart: Legend

    Uploaded by

    abdul.azeez
    The document outlines a project planning chart for designing a high speed link buffer for an HDLC processor over 12 steps from August 2009 to May 2010. The steps include literature surveys, studying tools and simulation techniques, defining the architecture at the top and block levels, RTL coding, simulation and analysis, implementation on an FPGA, and a final software and hardware demo.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as XLSX, PDF, TXT or read online from Scribd
    Download as xlsx, pdf, or txt
    of 2

    Design of High Speed Link Buffer for HDLC Processor

    2009-10

    Appendix A- Project Planning Chart


    Legend
    survey study of tools design

    project survey and proposal

    1 28/08/09

    1M 28/09/09
    Final review and demo

    software hardware demo

    12 28/05/10
    programming language study

    1M

    1/10/2009 31/10/09
    Modifications and final testing Literature Survey

    11 16/04/10

    1M
    Implementation on FPGA

    1M

    16/05/10 10 1M 15/04/10

    1/10/2009 2/11/2009 16/03/10

    Study of Xilinx ISE tool

    Study of simulation tools

    Simulation and analysis

    1w

    1w

    15D

    10/11/2009 16/11/09

    2/11/2009 7/11/2009

    1/3/2010 15/03/10

    Top level architecture

    Block level architecture

    RTL coding

    6 18/11/09

    1M 20/12/09

    7 21/12/10

    2M 25/02/10

    1M

    21/12/2010 25/02/10

    AMC Engineering College, Bangalore

    - 69 -

    Dept. of Telecommunication Engg.

    Design of High Speed Link Buffer for HDLC Processor

    2009-10

    AMC Engineering College, Bangalore

    - 69 -

    Dept. of Telecommunication Engg.

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