AVR Dev
AVR Dev
AVR Dev
R36 180
R35 180
D1 D2 D3 D4 R34 180
1 2 1 2 1 2 1 2 R33 180
2
D5 D6 +VTG +VTG
1 R46 5K1 DIODE DIODE JP12
6 PROG_SCK JP11 R45 3
D 50K C1 1 2 RS PC2 D
2 PROG_MOSI 1 2 + 3 4
7 R47 5K1 1uF PC3 /E PC4
3 4 PA0 D0 5 6 D1 PA1
3 PROG_RESET /RESET 5 6 7 8
8 R48 5K1 PROG_MISO -2VTG PA2 D2 D3 PA3
1
PROG_SCK 7 8 PA4 D4 9 10 D5 PA5
4 PROG_MOSI PROG_MISO 9 10 11 12
9 PA6 D6 D7 PA7
13 14
5 HEADER 5X2
D7 D8 D9 15 16
DIODE DIODE DIODE PA[0:7] HEADER 8X2
DB9-FEMALE
SERIAL CONNECTOR CPU RESET CONTROL POWER JACK AND ALTERNATE LINEAR REGULATOR
1 +VTG +VEXT
6 /RESET +VEXT +VTG +AVCC
J1 U3 L1
2 R49 R50
C 7 10K 1K2 DCJACK 7805 100uH C
3 TXD1 SW5 3 2 1 3
IN OUT
2
8 + +
1
4 RXD1 D10 C14 C15
G
9 PROG_RESET Q1 C8 RESET D11 4007 100uF 100uF
1
5 U1 NPN 0.1uF POWER
2
TXD2
13 12
2
SUB-D 9 R1IN R1OUT
8 R2IN R2OUT 9 RXD2
P2 11 14
T1IN T1OUT
10 T2IN T2OUT 7
C3 0.1uF
1 2 MOUNTING HOLES AND BYPASS CAPACITORS
VCC +VTG
+
2 V+
6 +VTG
V-
B MAX232A B
-2VTG
2
A A
THIEN MINH ELECTRONICS DESIGN- www.tme.com.vn
Title
AVR Basic System - Interface
PA[0:7]
D D
PB[0:7]
+VTG U4 +AVCC U5 +VTG
PC[0:7]
B PD[0:7] B