hp StorageWorks enterprise virtual array Event Text Description File (C) Copyright 2001-2009 Hewlett-Packard Company nsaprocessed hsv450v9defaultpars

efile WARNING: Modification of this file may cause Enterprise Storage Management Software to improperly translate event information Model number string: HSV450 Software version number string: 09540000 Baselevel build string: CD1A2E Structure Format: Endian Little COUPLED CRASH CONTROL CODES: Coupled Crash Control Code: 0 Other HSV450 controller should not perform a coupled crash. Coupled Crash Control Code: 1 Other HSV450 controller should perform a coupled crash. DUMP/RESTART CONTROL CODES: Dump/Restart Control Code: 0 Perform crash dump then restart. Dump/Restart Control Code: 1 Do not perform crash dump, just restart. Dump/Restart Control Code: 2 Perform crash dump and do not restart. Dump/Restart Control Code: 3 Do not perform crash dump and do not restart. SEVERITY LEVEL CODES: Severity Level Code: 0 Normal -- informational in nature. Severity Level Code: 1 Critical -- failure or failure imminent. Severity Level Code: 2 Warning -- not failed but attention recommended or required. Severity Level Code: 3 Undetermined -- more information needed to determine severity. CORRECTIVE ACTION CODES: Corrective Action Code: 0 No action necessary. Corrective Action Code: 1 An unrecoverable hardware detected fault occurred or an unrecoverable software i

nconsistency was detected, proceed with HSV450 controller support avenues. Corrective Action Code: 2 Inconsistent/erroneous information received from the operating system. Proceed w ith operating system software support avenues. Corrective Action Code: 3 Follow the recommended corrective action shown in the termination corrective act ion code of this event's detailed information. The cause of the controller termi nation associated with this controller event can only be determined by obtaining the detailed information of the associated termination event. To obtain that in formation follow Corrective Action [[06]]. Corrective Action Code: 4 Follow the recommended corrective action described in the recursing termination event. Perform these steps to obtain that termination event's information: <UL> <LI>View the termination events of the HSV450 controller shown in this terminati on event's detailed information. NOTE: If that controller is not currently opera ting, the event of interest will not be available for viewing. <LI>Locate the te rmination event that occurred closest to the date and time shown in this termina tion event's detailed information and obtain that termination event's detailed i nformation. NOTE: The termination event of interest will show termination locati on, termination code and termination parameters that are identical to the recurs ive event termination location, recursive event termination code and recursive e vent termination parameters 0 through 28 shown in this termination event. </UL> <UL> <LI>View the termination events of the HSV450 controller shown in this terminati on event's detailed information. NOTE: If that controller is not currently opera ting, the event of interest will not be available for viewing. <LI>Locate the termination event that occurred closest to the date and time show n in this termination event's detailed information and obtain that termination e vent's detailed information. NOTE: The termination event of interest will show t ermination location, termination code and termination parameters that are identi cal to the recursive event termination location, recursive event termination cod e and recursive event termination parameters 0 through 28 shown in this terminat ion event. </UL> Corrective Action Code: 5 Follow the recommended corrective action described in the termination event repo rted by the other controller that caused this termination event to occur. Perfor m these steps to obtain that termination event's information: <UL> <LI>View the termination events of the other HSV450 controller (i.e., the controller NOT show n in this termination event's detailed information). NOTE: If that controller is not currently operating, the event of interest will not be available for viewin g. <LI>Locate the termination event that occurred closest to the date and time s hown in this termination event's detailed information and obtain that terminatio n event's detailed information. NOTE: The termination event of interest will sho w a termination location and termination code that are identical to the other co ntroller termination location and other controller termination code shown in thi s termination event. </UL> <UL> <LI>View the termination events of the other HSV450 controller (i.e., the contro ller NOT shown in this termination event's detailed information). NOTE: If that controller is not currently operating, the event of interest will not be availab le for viewing. <LI>Locate the termination event that occurred closest to the date and time show n in this termination event's detailed information and obtain that termination e vent's detailed information. NOTE: The termination event of interest will show a termination location and termination code that are identical to the other contr

oller termination location and other controller termination code shown in this t ermination event. </UL> Corrective Action Code: 6 Perform these steps to obtain the termination information associated with this c ontroller event: <UL> <LI>View the termination events of the HSV450 controller s hown in this event's detailed information. NOTE: If that controller is not curre ntly operating, the event of interest will not be available for viewing. <LI>Loc ate the termination event that occurred closest to the date and time shown in th is event's detailed information and obtain that termination event's detailed inf ormation. NOTE: The termination event of interest will show software version, ba selevel ID, and uptime information identical to that shown in this event's detai led information for the terminating controller. </UL> <UL> <LI>View the termination events of the HSV450 controller shown in this event's d etailed information. NOTE: If that controller is not currently operating, the ev ent of interest will not be available for viewing. <LI>Locate the termination event that occurred closest to the date and time show n in this event's detailed information and obtain that termination event's detai led information. NOTE: The termination event of interest will show software vers ion, baselevel ID, and uptime information identical to that shown in this event' s detailed information for the terminating controller. </UL> Corrective Action Code: 7 A significant hardware detected fault occurred or a significant software inconsi stency was detected. Accumulate information to report to HSV450 controller engin eering. Corrective Action Code: 8 A significant hardware detected fault occurred or a significant software inconsi stency was detected. Accumulate information to report to HSV450 controller engin eering. Corrective Action Code: 9 Determine power loss cause and take appropriate action to ensure power is restor ed and maintained. Corrective Action Code: a A portion of low memory is purposely set to produce an uncorrectable memory erro r in order to detect low memory access violations made by the HSV450 controller' s software (e.g., access to memory address zero through an uninitialized pointer , etc.). Unfortunately, there is no method available for immediately distinguish ing a low memory access violation from an uncorrectable memory error that occurs elsewhere in memory. However, the memory diagnostics that are executed followin g controller restart will immediately terminate HSV450 controller operation if a ny portion of memory is found defective. In that case perform corrective action [[20]]. If defective memory is not found during HSV450 controller restart and th is termination event is again reported, the most likely cause is a software indu ced low memory access violation. In that case perform corrective action [[01]]. Corrective Action Code: d User intervention is required for this HSV450 controller to continue processing. Examine the events contents in order to determine how to proceed. Corrective Action Code: 20 Replace the HSV450 controller Field Replaceable Unit (FRU). Note that the FRU mu st be a single power supply type if so indicated in this event's detailed inform ation.

Corrective Action Code: 22 Replace the '1' Battery Assembly Field Replaceable Unit (FRU)--i.e., the battery assembly closest to the cache battery door hinge. CAUTION: The information desc ribed in corrective action [[38]] must be understood before attempting a cache b attery replacement. Corrective Action Code: 23 Replace the '2' Battery Assembly Field Replaceable Unit (FRU)--i.e., the battery assembly farthest from the cache battery door hinge. CAUTION: The information d escribed in corrective action [[38]] must be understood before attempting a cach e battery replacement. Corrective Action Code: 24 Replace the '1' Blower Assembly Field Replaceable Unit (FRU)-- i.e., the blower farthest from the blower door hinge. Corrective Action Code: 25 Replace the '2' Blower Assembly Field Replaceable Unit (FRU)-- i.e., the blower closest to the blower door hinge. Corrective Action Code: 26 Replace the '1' Blower/Power Supply Assembly Field Replaceable Unit (FRU)-- i.e. , the blower/power supply closest to the cache battery door hinge. Corrective Action Code: 27 Replace the '2' Blower/Power Supply Assembly Field Replaceable Unit (FRU)-- i.e. , the blower/power supply farthest from the cache battery door hinge. Corrective Action Code: 28 Reinstall the '1' Battery Assembly Field Replaceable Unit (FRU)--i.e., the batte ry assembly closest to the cache battery door hinge. Corrective Action Code: 29 Reinstall the '2' Battery Assembly Field Replaceable Unit (FRU)--i.e., the batte ry assembly farthest from the cache battery door hinge. Corrective Action Code: 2a Reinstall the '1' Blower Assembly Field Replaceable Unit (FRU)-- i.e., the blowe r farthest from the blower door hinge. Corrective Action Code: 2b Reinstall the '2' Blower Assembly Field Replaceable Unit (FRU)-- i.e., the blowe r closest to the blower door hinge. Corrective Action Code: 2c Reinstall the '1' Blower/Power Supply Assembly Field Replaceable Unit (FRU)-- i. e., the blower/power supply closest to the cache battery door hinge, or restore AC power. Corrective Action Code: 2d Reinstall the '2' Blower/Power Supply Assembly Field Replaceable Unit (FRU)-- i. e., the blower/power supply farthest from the cache battery door hinge, or resto re AC power. Corrective Action Code: 2e Reduce the ambient temperature in the vicinity of the HSV450 controller. Corrective Action Code: 2f Ensure that both batteries in the indicated HSV450 controller are installed and

functioning normally. A cache battery failure will be indicated by the red batte ry status LED located on the OCP display. If that LED is on, open the battery co mpartment door and check for the amber status LED in the lower right corner of e ach battery assembly. If the amber status LED is ONLY on in the battery assembly closest to the battery compartment door hinge, perform corrective action [[22]] . If the amber status LED is ONLY on in the battery assembly farthest from the c ache battery door hinge, perform corrective action [[23]]. If the amber status L ED is on in BOTH battery assemblies, perform [[22]] and [[23]] simultaneously. Corrective Action Code: 30 GBIC SFF Serial ID Data check code failure. Corrective action: Try re-seating th e GBIC, if failure persists, replace the GBIC, lastly perform corrective action [[20]]. Corrective Action Code: 36 The temperature on the HSV450 controller has become critical. Proceed with corre ctive action [[2e]] and restart the controller. Corrective Action Code: 37 The temperature on the HSV450 controller could not be accurately determined poss ibly due to faulty operation of a temperature sensor or the temperature acquisit ion communication path. If the problem persists, perform Corrective Action [[20] ]. Corrective Action Code: 38 Before performing cache battery replacement the following must be understood: <U L> <LI>CAUTION: Never remove batteries from the HSV450 controller while it is po wered down. Replace a cache battery only when the controller power is on. <LI>CA UTION: If the amber status LED is on in both battery assemblies, both batteries must be removed before installing either of the new batteries. If one of the bat teries is replaced while the other failed battery is still in the enclosure, the original failure may be propagated to the newly installed battery. To ensure th ere is no propagated failure, wait a minimum of 15 seconds after the removal of both batteries before inserting the new batteries. <LI>CAUTION: Never install a battery that was previously failed by any HSV450 controller. <LI>NOTE: When inst alling a cache battery, the amber status LED will initially be on. The LED may r emain on for up to two minutes, after which time it will turn off. <LI>NOTE: It will take several hours for the HSV450 controller to recognize a new battery as fully charged. If a pair of batteries has been replaced, this period will be not iceably longer. </UL> <UL> <LI>CAUTION: Never remove batteries from the HSV450 controller while it is power ed down. Replace a cache battery only when the controller power is on. <LI>CAUTION: If the amber status LED is on in both battery assemblies, both batt eries must be removed before installing either of the new batteries. If one of t he batteries is replaced while the other failed battery is still in the enclosur e, the original failure may be propagated to the newly installed battery. To ens ure there is no propagated failure, wait a minimum of 15 seconds after the remov al of both batteries before inserting the new batteries. <LI>CAUTION: Never install a battery that was previously failed by any HSV450 co ntroller. <LI>NOTE: When installing a cache battery, the amber status LED will initially b e on. The LED may remain on for up to two minutes, after which time it will turn off. <LI>NOTE: It will take several hours for the HSV450 controller to recognize a ne w battery as fully charged. If a pair of batteries has been replaced, this perio d will be noticeably longer. </UL> Corrective Action Code: 39

If this event is an isolated occurrence, then no further action is necessary. If this event occurs more than once in a three month period, perform Corrective Ac tion [[20]]. Corrective Action Code: 3a Insert and re-seat the GBIC. If failure persists, replace the GBIC, or lastly pe rform Corrective Action [[20]]. Corrective Action Code: 3b Isolated occurrences of this event may be safely ignored. If this event occurs m ore than once in a three month period, perform Corrective Action [[20]]. Corrective Action Code: 40 Replace the indicated physical disk drive. Corrective Action Code: 41 Reinstall the indicated physical disk drive or install a drive blank. Corrective Action Code: 42 Perform these steps in an attempt to clear the error: <UL> <LI>Remove and reinst all the indicated physical disk drive. <LI>Observe the drive's status LEDs to en sure that the drive is operational. <LI>Observe the Drive Enclosure Environmenta l Monitoring Unit alphanumeric display to ensure the error no longer exists. </U L>If the error persists, perform Corrective Action [[40]]. <UL> <LI>Remove and reinstall the indicated physical disk drive. <LI>Observe the drive's status LEDs to ensure that the drive is operational. <LI>Observe the Drive Enclosure Environmental Monitoring Unit alphanumeric displ ay to ensure the error no longer exists. </UL>If the error persists, perform Corrective Action [[40]]. Corrective Action Code: 44 A Fibre Channel port has failed. This may be caused by a failure on the indicate d HSV450 controller, or the coprresponding Fibre Channel Switch. Proceed with co rrective action [[01]]. Corrective Action Code: 46 Numerous transport failures occurred while attempting to communicate with a Phys ical Disk Drive on a particular Device Port. The controller will attempt to an a lternate use Device Port to communicate with the Physical Disk Drive. If communi cation fails on the alternate Device Port, that Physical Disk Drive will be rend ered inoperable. This is a preemptive action warning, no immediate action is nec essary. Corrective Action Code: 47 Dropped frames are potential indications of an impending Fibre Channel port or p hysical disk drive failure when they occur excessively. If frame drop becomes ex cessive, the indicated Fibre Channel port or the indicated physical disk drive w ill be placed in the inoperative state. This is a preemptive action warning, no immediate action is necessary. Corrective Action Code: 48 Unexpected work from a physical disk drive is an indication of an impending driv e failure. If unexpected work becomes excessive, the indicated physical disk dri ve will be placed in the inoperative state. This is a preemptive action warning, no immediate action is necessary. Corrective Action Code: 49 Bad ALPAs are indications of an impending physical disk drive failure. If the nu mber of bad ALPAs becomes excessive, the indicated physical disk drive will be p

laced in the inoperative state. This is a preemptive action warning, no immediat e action is necessary. Corrective Action Code: 4a Unable to communicate through a Fibre Channel link to a Fibre Channel port. This may be caused by a missing Fibre connection to an HSV450 controller Host Port o r Drive Enclosure, faulty GBIC, faulty Drive Enclosure, faulty Fibre Channel Cab le, faulty Drive Enclosure I/O module, or faulty Fibre Channel Switch. This is a preemptive action warning, no immediate action is necessary. Corrective Action Code: 4c This event is probably a symptom of another problem. Check nel ports and multiple instances of this event. Also check multiple occurrences of this event pertaining to physical me rack or loop. If this is an isolated occurrence of this dicated physical disk drive and remove it from the system. for failed Fibre Chan for patterns, such as disk drives on the sa event, ungroup the in

Corrective Action Code: 4d Load the latest physical disk drive firmware superfile for the physical disk dri ve type shown in the SCSI Product ID of this event's detailed information. If no such superfile exists, the physical disk drive is unsupported, and should be un grouped and removed. Using a superfile that updates the controller approved firm ware table may be sufficient to correct the problem. Corrective Action Code: 4e This event is probably a symptom of another problem. Check for failed Fibre Chan nel ports and multiple instances of this event. Also check for patterns, such as multiple occurrences of this event pertaining to physical disk drives on the sa me rack or loop. Corrective Action Code: 4f Remove the indicated physical disk drive and install a drive blank. Corrective Action Code: 50 Delete the indicated inoperative Snapshot Storage System Virtual Disk. Corrective Action Code: 51 Evaluate previously reported Physical Device, Device Enclosure, and Storage Syst em Virtual Disk events to determine root cause and corrective action. Corrective Action Code: 52 Delete the indicated inoperative Storage System Virtual Disk, unless an instant restore operation is possible. Corrective Action Code: 5f Unable to communicate to the destination controllers, or through a specific path to the destination. Check to see if the destination controllers have malfunctio ned, and perform the repair actions indicated in event reports found for the des tination controllers. In addition, check for a malfunction that may have occurre d in the Fibre Channel fabric between the sites. Corrective Action Code: 60 Unable to communicate to the indicated source virtual disk, because the virtual disk or another member in the Data Replication Group malfunctioned. Perform the repair actions indicated in event reports found for that source virtual disk or another virtual disk member in that Data Replication Group. Corrective Action Code: 61 Unable to communicate to the indicated destination virtual disk on the remote St orage System because the virtual disk malfunctioned. Perform the repair actions

indicated in event reports found for that destination virtual disk on the remote Storage System. Corrective Action Code: 62 The Data Replication Log for the specified Data Replication Group has insufficie nt space to grow the log. A copy resynchronization will be started when data rep lication can resume. Evaluate whether sufficient disk storage has been made avai lable for the log to grow in capacity. If necessary, add new volumes to the Disk Group. Corrective Action Code: 63 The Data Replication Source Site and the Data Replication Destination Site canno t communicate because the software versions are incompatible. Communication will automatically continue when both sites are at compatible software levels. Corrective Action Code: 64 Check the Data Replication Destination Site for problems with physical disk driv es or fibre channel loops. The Data Replication Destination Site may also be tem porarily experiencing higher than usual levels of disk related activity. Corrective Action Code: 65 Check the Data Replication Destination Site for slow or no response for this Dat a Replication Group. If this is not the case then restart the Data Replication D estination Site controllers. Then restart the Data Replication Source Site contr ollers. Corrective Action Code: 66 Check both the Data Replication Source Site and the Data Replication Destination Site for slow or no response for this Data Replication Group. If this is not th e case then restart the Data Replication Source Site controllers. IF you have al ready taken this action and are receiving this event for a second time then rest art the Data Replication Destination Site controllers instead. Corrective Action Code: 67 Check link speed and quality between the Data Replication Source Site controller s and the Data Replication Destination Site controllers. Corrective Action Code: 68 Reduce the number of controller pairs on the fabric to the supported maximum. Corrective Action Code: 69 Check fabric switch settings and inter site link quality between the Data Replic ation Source Site controllers and the Data Replication Destination Site controll ers. Corrective Action Code: 6a The Data Replication Source Site and the Data Replication Destination Site canno t communicate because the software settings are incompatible. Communication will automatically continue when both sites are at compatible software settings. Corrective Action Code: 6b The Data Replication Source Site and the Data Replication Destination Site have a capacity mismatch on at least one of the their volumes. Check the source and d estination volumes to ensure that they are in agreement. Corrective Action Code: 80 Perform these steps in an attempt to clear the error: <UL> <LI>Remove and reinst all the indicated drive enclosure power supply. <LI>Observe the power supply/blo wer status LED to ensure that the power supply is operational. </UL>If the error persists, immediately (within 7 minutes) perform Corrective Action [[81]]. If t

hat action cannot be performed immediately, perform Corrective Action [[85]] imm ediately. <UL> <LI>Remove and reinstall the indicated drive enclosure power supply. <LI>Observe the power supply/blower status LED to ensure that the power supply i s operational. </UL>If the error persists, immediately (within 7 minutes) perform Corrective Ac tion [[81]]. If that action cannot be performed immediately, perform Corrective Action [[85]] immediately. Corrective Action Code: 81 Replace the indicated drive enclosure power supply. Hewlett-Packard recommends n ot removing a defective drive enclosure power supply until a replacement drive e nclosure power supply is available. Corrective Action Code: 82 Perform these steps in an attempt to clear the error: <UL> <LI>Remove and reinst all the indicated drive enclosure blower. <LI>Observe the power supply/blower st atus LED to ensure that the blower is operational. </UL>If the error persists, p erform Corrective Action [[83]]. <UL> <LI>Remove and reinstall the indicated drive enclosure blower. <LI>Observe the power supply/blower status LED to ensure that the blower is oper ational. </UL>If the error persists, perform Corrective Action [[83]]. Corrective Action Code: 83 Replace the indicated drive enclosure blower. CAUTION: Removing a blower automat ically closes flaps over the power supply blower opening. However, the air flow within the enclosure changes and can cause an over temperature condition. Hewlet t-Packard recommends not removing a defective blower until a replacement blower is available. Corrective Action Code: 85 If the problem cannot be corrected, the Enterprise Virtual Array should be shut down to: <UL> <LI>Flush data from the controllers. <LI>Shut down the drive enclo sures. <LI>Shut down the controllers. </UL>CAUTION: This is a drastic measure th at will stop all Enterprise Virtual Array operations. Hewlett-Packard recommends using this procedure only when necessary to protect a drive enclosure from over heating or to clear drive enclosure errors that cannot otherwise be cleared. <UL> <LI>Flush data from the controllers. <LI>Shut down the drive enclosures. <LI>Shut down the controllers. </UL>CAUTION: This is a drastic measure that will stop all Enterprise Virtual Ar ray operations. Hewlett-Packard recommends using this procedure only when necess ary to protect a drive enclosure from overheating or to clear drive enclosure er rors that cannot otherwise be cleared. Corrective Action Code: 86 If the indicated drive enclosure element's temperature sensor is high, follow th ese steps to correct the over temperature condition: <UL> <LI>Ensure that all el ements are properly installed to maintain proper air flow. <LI>Ensure that nothi ng is obstructing the air flow at either the front of the enclosure or the rear of the blower. <LI>Ensure that both blowers are operating properly (the LEDs are on) and neither blower is operating at high speed. If a blower appears to be de fective, perform Corrective Action [[83]]. <LI>Verify that the ambient temperatu re is within the range +10C to +35C (+50F to +95F). Adjust as necessary. </UL>If the indicated drive enclosure element's temperature sensor is low, follow this step to correct the below temperature condition: <UL> <LI>Verify that the ambien

t temperature is within the range +10C to +35C (+50F to +95F). Adjust as necessa ry. </UL> <UL> <LI>Ensure that all elements are properly installed to maintain proper air flow. <LI>Ensure that nothing is obstructing the air flow at either the front of the e nclosure or the rear of the blower. <LI>Ensure that both blowers are operating properly (the LEDs are on) and neithe r blower is operating at high speed. If a blower appears to be defective, perfor m Corrective Action [[83]]. <LI>Verify that the ambient temperature is within the range +10C to +35C (+50F t o +95F). Adjust as necessary. </UL>If the indicated drive enclosure element's temperature sensor is low, follo w this step to correct the below temperature condition: <UL> <LI>Verify that the ambient temperature is within the range +10C to +35C (+50F t o +95F). Adjust as necessary. </UL> Corrective Action Code: 87 Immediately perform Corrective Action [[86]]. If the problem persists after perf orming those actions, perform Corrective Action [[85]] immediately. Corrective Action Code: 89 Replace the indicated Drive Enclosure Environmental Monitoring Unit. Corrective Action Code: 90 Perform these steps in an attempt to clear the error: <UL> <LI>Check if one of t he HSV450 controllers has suffered a power failure. If so, perform Corrective Ac tion [[09]]. <LI>Check all the transceivers and cables to ensure they are proper ly connected. Reseat any that are not properly connected. <LI>If the problem is not corrected, check all the transceivers on the loop to ensure that they are dr ive enclosure I/O module compatible. Replace any transceivers that are found to be incompatible. <LI>If the problem is not corrected, replace the input cable co nnected to the indicated transceiver. <LI>If the problem is not corrected, repla ce both transceivers attached to the cable that is connected to the indicated tr ansceiver. </UL> <UL> <LI>Check if one of the HSV450 controllers has suffered a power failure. If so, perform Corrective Action [[09]]. <LI>Check all the transceivers and cables to ensure they are properly connected. Reseat any that are not properly connected. <LI>If the problem is not corrected, check all the transceivers on the loop to e nsure that they are drive enclosure I/O module compatible. Replace any transceiv ers that are found to be incompatible. <LI>If the problem is not corrected, replace the input cable connected to the in dicated transceiver. <LI>If the problem is not corrected, replace both transceivers attached to the c able that is connected to the indicated transceiver. </UL> Corrective Action Code: 93 Replace the indicated drive enclosure I/O module. Corrective Action Code: 95 Reset the indicated device enclosure I/O module using the following procedure: < UL> <LI>Remove the I/O module. <LI>Reinsert the I/O module. </UL>If the problem persists, perform Corrective Action [[93]]. <UL> <LI>Remove the I/O module. <LI>Reinsert the I/O module.

</UL>If the problem persists, perform Corrective Action [[93]]. Corrective Action Code: 99 Ensure that each drive enclosure I/O module is connected to the correct Fibre Ch annel port. Corrective Action Code: 9a Ensure A/C input to the rack PDU is intact, otherwise perform [[81]]. Corrective Action Code: b4 Add new volumes to the Disk Group or increase the Disk Group occupancy alarm lev el threshold. Corrective Action Code: b5 Add new volumes to the Disk Group or delete unwanted logical disks from Disk Gro up. Corrective Action Code: b6 To restore the Disk Group to a Single Point of Failure Robust Configuration add more physical disk drives or rearrange the existing Single Point of Failure Robu st Configuration to ensure the physical disk drives members are on different Fib re Channel device enclosures. Corrective Action Code: b9 Evaluate previously reported events associated with this HSV450 controller to de termine root cause and corrective action. Corrective Action Code: ba Check to see if this HSV450 controller has suffered a power failure. If so, perf orm Corrective Action [[09]]. Otherwise, perform Corrective Action [[b9]]. Corrective Action Code: bf Evaluate previously reported Device or Device Enclosure events that related to t he Physical Disk Drive that is associated with this Volume to determine root cau se and corrective action. Corrective Action Code: c3 Evaluate previously reported Device, Device Enclosure, and Host events to determ ine root cause and corrective action. If the problem persists, follow Corrective Action [[20]]. Corrective Action Code: c4 Load the latest physical disk drive firmware superfile for the physical disk dri ve type shown in the SCSI Product ID of this event's detailed information. If no such superfile exists, the physical disk drive is unsupported, and should be un grouped and removed. Using a superfile that updates the controller approved firm ware table may be sufficient to correct the problem. Corrective Action Code: dd Replace the '0' Battery Assembly Field Replaceable Unit (FRU)--i.e., the upper l eft battery assembly. CAUTION: The information described in corrective action [[ e6]] must be understood before attempting a cache battery replacement. Corrective Action Code: de Replace the '1' Battery Assembly Field Replaceable Unit (FRU)--i.e., the lower l eft battery assembly. CAUTION: The information described in corrective action [[ e6]] must be understood before attempting a cache battery replacement. Corrective Action Code: df Replace the '2' Battery Assembly Field Replaceable Unit (FRU)--i.e., the upper r

ight battery assembly. CAUTION: The information described in corrective action [ [e6]] must be understood before attempting a cache battery replacement. Corrective Action Code: e0 Replace the '3' Battery Assembly Field Replaceable Unit (FRU)--i.e., the lower r ight battery assembly. CAUTION: The information described in corrective action [ [e6]] must be understood before attempting a cache battery replacement. Corrective Action Code: e1 Reinstall the '0' Battery Assembly Field Replaceable Unit (FRU)--i.e., the upper left battery assembly. Corrective Action Code: e2 Reinstall the '1' Battery Assembly Field Replaceable Unit (FRU)--i.e., the lower left battery assembly. Corrective Action Code: e3 Reinstall the '2' Battery Assembly Field Replaceable Unit (FRU)--i.e., the upper right battery assembly. Corrective Action Code: e4 Reinstall the '3' Battery Assembly Field Replaceable Unit (FRU)--i.e., the lower right battery assembly. Corrective Action Code: e5 Ensure the required number of batteries in the indicated HSV450 controller are i nstalled and functioning normally. Each battery assembly has a green LED located to the side of a battery symbol label and an amber LED located to the side of a caution symbol label. A cache battery failure will be indicated when the amber LED is on and the green LED is off. If the upper left battery assembly is failed , perform corrective action [[dd]]. If the lower left battery assembly is failed , perform corrective action [[de]]. If the upper right battery assembly is faile d, perform corrective action [[df]]. If the lower right battery assembly is fail ed, perform corrective action [[e0]]. Corrective Action Code: e6 Before performing cache battery replacement the following must be understood: <U L> <LI>CAUTION: Never remove batteries from the controller while it is powered d own. Replace a cache battery only when the controller power is on. <LI>CAUTION: Never install a battery that was previously failed by any controller. <LI>NOTE: When installing a cache battery, the amber status LED will initially be on after insertion. It will remain on for several seconds while initial battery integrit y is checked, after which time it will turn off. <LI>NOTE: It will take several hours for the EVA controller to recognize a new battery as fully charged. </UL> <UL> <LI>CAUTION: Never remove batteries from the controller while it is powered down . Replace a cache battery only when the controller power is on. <LI>CAUTION: Never install a battery that was previously failed by any controlle r. <LI>NOTE: When installing a cache battery, the amber status LED will initially b e on after insertion. It will remain on for several seconds while initial batter y integrity is checked, after which time it will turn off. <LI>NOTE: It will take several hours for the EVA controller to recognize a new b attery as fully charged. </UL> Corrective Action Code: e7 Replace the '0' Blower Assembly Field Replaceable Unit (FRU)-- i.e., the top blo wer.

Corrective Action Code: e8 Replace the '1' Blower Assembly Field Replaceable Unit (FRU)-- i.e., the bottom blower. Corrective Action Code: e9 Reinstall the '0' Blower Assembly Field Replaceable Unit (FRU)-- i.e., the top b lower. Corrective Action Code: ea Reinstall the '1' Blower Assembly Field Replaceable Unit (FRU)-- i.e., the botto m blower. Corrective Action Code: eb Verify AC connection integrity of '0' Power Supply Assembly Field Replaceable Un it (FRU)-- i.e., the left power supply. Replace assembly if AC connection is goo d and malfunction persists. Corrective Action Code: ec Verify AC connection integrity of '1' Power Supply Assembly Field Replaceable Un it (FRU)-- i.e., the right power supply. Replace assembly if AC connection is go od and malfunction persists. Corrective Action Code: ed Reinstall the '0' Power Supply Assembly Field Replaceable Unit (FRU)-- i.e., the left power supply. Corrective Action Code: ee Reinstall the '1' Power Supply Assembly Field Replaceable Unit (FRU)-- i.e., the right power supply. Corrective Action Code: ef If this event is an isolated occurrence, then no further action is necessary. Pe rform these steps in an attempt to clear persistent occurrences: <UL> <LI>If thi s event persistently occurs for each installed battery brick in the controller, then verify the correct SDC version is installed. <LI>If this event persistently occurs for the '0' Battery Assembly, perform Corrective Action [[dd]]. <LI>If t his event persistently occurs for the '1' Battery Assembly, perform Corrective A ction [[de]]. <LI>If this event persistently occurs for the '2' Battery Assembly , perform Corrective Action [[df]]. <LI>If this event persistently occurs for th e '3' Battery Assembly, perform Corrective Action [[e0]]. <LI>If all previous st eps fail to stop event from occurring, perform Corrective Action [[01]] </UL> <UL> <LI>If this event persistently occurs for each installed battery brick in the co ntroller, then verify the correct SDC version is installed. <LI>If this event persistently occurs for the '0' Battery Assembly, perform Corr ective Action [[dd]]. <LI>If this event persistently occurs for the '1' Battery Assembly, perform Corr ective Action [[de]]. <LI>If this event persistently occurs for the '2' Battery Assembly, perform Corr ective Action [[df]]. <LI>If this event persistently occurs for the '3' Battery Assembly, perform Corr ective Action [[e0]]. <LI>If all previous steps fail to stop event from occurring, perform Corrective Action [[01]] </UL> Corrective Action Code: f0 This event indicates a SLAVE ROHS compliant HSV450 controller is being force loa ded from the MASTER with code that is inappropriate for this hardware. This will continue until this controller is made MASTER or the current master is upgraded

to the appropriate level of code that will run on both controllers. Corrective Action Code: f1 Remove the indicated enclosure. Corrective Action Code: f2 The Enterprise Virtual Array needs to be restarted to load new sprite code. Corrective Action Code: f3 Unable to communicate through a Fibre Channel link to a Fibre Channel port. This may be caused by a missing Fibre connection to an HSV450 controller Host Port o r Drive Enclosure, faulty GBIC, faulty Drive Enclosure, faulty Fibre Channel Cab le, or faulty Drive Enclosure I/O module. Examine events and clear any faults th at cause loss of redundancy. Corrective Action Code: f4 Verify AC connection integrity of the Disk Enclosure Power Supply. The Power Sup ply is located on the rear side of the Disk Enclosure. It is identified by the l abel 'PS 1' for the Left side or 'PS 2' for the Right side. Replace the Power Su pply if the AC connection is good and the malfunction persists. SOFTWARE COMPONENT ID CODES: Software Component ID Code: 1 Executive Services Software Component ID Code: 2 Cache Management Component Software Component ID Code: 3 Storage System State Services Software Component ID Code: 4 Fault Manager Software Component ID Code: 6 Fibre Channel Services Software Component ID Code: 7 Container Services Software Component ID Code: 8 Raid Services Software Component ID Code: 9 Storage System Management Interface Software Component ID Code: b System Services (DFP, XMFC, etc. processing) Software Component ID Code: c Data Replication Manager Component Software Component ID Code: d Disk Enclosure Environmental Monitoring Unit Services Software Component ID Code: e System Data Center Software Component ID Code: f

Mirroring & DMA Software Component ID Code: 42 Host Port Software Component ID Code: 83 Diagnostic Operations Generator only for XL Software Component ID Code: 84 Diagnostic Runtime Services (Scrubbing, UPS, temp/battery/voltage monitoring, et c.) only for XL EVENT CODES: Event Code: 0102000d Severity: Normal -- informational in nature. A time change occurred. Event Code: 0301400b Severity: Critical -- failure or failure imminent. A physical disk drive has bee n rendered inoperable. Event Code: 03024f0b Severity: Warning -- not failed but attention recommended or required. A physica l disk drive will not be used because the maximum number of physical disk drives already exist in the current Storage System. Event Code: 0303000a Severity: Normal -- informational in nature. An HSV450 controller has begun boot ing. Event Code: 0304000a Severity: Normal -- informational in nature. An HSV450 controller has finished t he process of bringing the Storage System online. Event Code: 0305000a Severity: Normal -- informational in nature. An HSV450 controller has been joine d into the Storage System. Event Code: 0306000a Severity: Normal -- informational in nature. An HSV450 controller has been ouste d from the Storage System. Event Code: 0307000a Severity: Normal -- informational in nature. An HSV450 controller is now the Sto rage System Master. Event Code: 0308000a Severity: Normal -- informational in nature. An HSV450 controller has been broug ht into the Storage System. Event Code: 03090018 Severity: Normal -- informational in nature. The Redundant Storage Set has start ed migrating members. Event Code: 030a0018 Severity: Normal -- informational in nature. The Redundant Storage Set has finis hed migrating members. Event Code: 030b4f0b Severity: Warning -- not failed but attention recommended or required. A physica

l disk drive has failed during Storage System realization. Event Code: 030c001e Severity: Normal -- informational in nature. The DebugFlags and/or PrintFlags ha ve changed. Event Code: 030d001e Severity: Normal -- informational in nature. Process with work during CSM reset: Event Code: 030e070b Severity: Warning -- not failed but attention recommended or required. About to write ID block to wrong physical disk drive. Event Code: 030f001e Severity: Normal -- informational in nature. RoHS Status of the HSV450 controlle r has been determined. Event Code: 0310001f Severity: Normal -- informational in nature. A Storage System Virtual Disk has c hanged controller mastership. Event Code: 03114420 Severity: Critical -- failure or failure imminent. A Fibre Channel Switch respon ded to a fabric port login. The corresponding device Fibre Channel port on the s pecified HSV450 controller has been failed. Event Code: 03120021 Severity: Normal -- informational in nature. A Storage System Virtual Disk Attac h operation has completed. Event Code: 03130021 Severity: Normal -- informational in nature. A Snapclone Storage System Virtual Disk has completed the Unsharing operation. Event Code: 03140021 Severity: Normal -- informational in nature. A Mirror Clone Storage System Virtu al Disk has completed the detach operation. Event Code: 03150021 Severity: Normal -- informational in nature. A Mirror Clone Storage System Virtu al Disk has completed the Fracture operation. Event Code: 03160021 Severity: Normal -- informational in nature. A Mirror Clone Storage System Virtu al Disk has completed the Synchronization operation. Event Code: 03170021 Severity: Normal -- informational in nature. A Storage System Virtual Disk has c ompleted the Instant Restore operation. Event Code: 03189513 Severity: Warning -- not failed but attention recommended or required. An Enclos ure Failed to initialize. Event Code: 0319000a Severity: Normal -- informational in nature. An HSV450 controller has begun disc overing devices on the backend loops. Event Code: 031a000a Severity: Normal -- informational in nature. An HSV450 controller has completed

discovering devices on the backend loops. Event Code: 031b0d23 Severity: Critical -- failure or failure imminent. The system is inoperative. Event Code: 031c4a23 Severity: Warning -- not failed but attention recommended or required. One or mo re ports has been disabled at startup. Event Code: 031d9923 Severity: Critical -- failure or failure imminent. One or more ports have been m isconfigured. Event Code: 031e0d23 Severity: Critical -- failure or failure imminent. The user is required to provi de a confirmation as to how the system should proceed. Event Code: 031f9923 Severity: Critical -- failure or failure imminent. A backend device has been mis configured. The current port states for both the master and the slave should ma tch. Event Code: 0320000a Severity: Normal -- informational in nature. The slave HSV450 controller is prev ented from joining because there are units still completing fast failover. Event Code: 0321f113 Severity: Warning -- not failed but attention recommended or required. An enclos ure will not be used because the maximum number of enclosures already exist in t he current Storage System. Event Code: 0322000f Severity: Normal -- informational in nature. The CA Port Routing value has been changed. Event Code: 0323000a Severity: Normal -- informational in nature. An HSV450 controller has successful ly completed a preserving resync after a code load operation. Event Code: 0324400b Severity: Critical -- failure or failure imminent. A physical disk drive could n ot be added to a SCELL. The device storage capacity exceeds the maximum supporte d size. Event Code: 0325000a Severity: Normal -- informational in nature. Drive reappeared with Metadata (ID buffer) Scell tag matching with deleted scell, erasing ID BLOCK. Event Code: 03260027 Severity: Normal -- informational in nature. An HSV450 controller has changed Ba ttery Cache policy Event Code: 03270129 Severity: Critical -- failure or failure imminent. A physical disk drive has exp erienced an ID block inconsistency. Event Code: 03280029 Severity: Normal -- informational in nature. A physical disk drive has experienc ed an ID block inconsistency during a periodic drive check.

Event Code: 0329002a Severity: Normal -- informational in nature. An update to the CVM data base was successfully recovered. Event Code: 032a0018 Severity: Normal -- informational in nature. The Redundant Storage Set failed to start migrating members due to insufficient capacity. Event Code: 0330000a Severity: Normal -- informational in nature. A request to scrub the Storage Syst em has been received. Event Code: 0331000a Severity: Normal -- informational in nature. The Storage System has been scrubbe d. Event Code: 0332000a Severity: Normal -- informational in nature. An invalid request to scrub the Sto rage System has been ignored. Event Code: 03400021 Severity: Normal -- informational in nature. A Storage System Virtual Disk has c ompleted the Cache Fast Failover operation. Event Code: 03410021 Severity: Normal -- informational in nature. A Storage System Virtual Disk has c ompleted the Clear Container operation. Event Code: 03420021 Severity: Normal -- informational in nature. A Storage System Virtual Disk has r emoved any sharing relationships (if any existed ) during the delete process. Event Code: 03430021 Severity: Normal -- informational in nature. A Storage System Virtual Disk has c ompleted the Set Capacity operation. Event Code: 03440021 Severity: Normal -- informational in nature. A Storage System Virtual Disk has c ompleted the Reserve Capacity operation. Event Code: 03450021 Severity: Normal -- informational in nature. A Storage System Virtual Disk has c ompleted the Cache Flush operation. Event Code: 03600021 Severity: Normal -- informational in nature. A Logical Disk operation has comple ted. Event Code: 0400031c Severity: Undetermined -- more information needed to determine severity. HSV450 controller operation was terminated due to an unrecoverable event detected by ei ther software or hardware or due to an action initiated via the Storage System M anagement Interface. Event Code: 0401031c Severity: Undetermined -- more information needed to determine severity. This HS V450 controller has received a last gasp message from another HSV450 controller prior to it terminating operation. Event Code: 04020101

Severity: Critical -- failure or failure imminent. A machine check occurred whil e a termination event was being processed. Event Code: 04030102 Severity: Critical -- failure or failure imminent. An unexpected event occurred while a termination event was being processed. Event Code: 04040003 Severity: Normal -- informational in nature. The Storage System Event Log valida tion completed successfully. Event Code: 04050003 Severity: Normal -- informational in nature. The Storage System Event Log valida tion failed. Event Code: 04060803 Severity: Normal -- informational in nature. Local event reports were lost due t o an insufficient supply of Event Log Packets on this HSV450 controller. Event Code: 04070803 Severity: Normal -- informational in nature. Remote event reports were lost due to an insufficient supply of Event Log Packets on this HSV450 controller. Event Code: 04080003 Severity: Normal -- informational in nature. The Storage System Termination Even t Log has become inaccessible. Event Code: 04090003 Severity: Normal -- informational in nature. The Storage System Termination Even t Log validation completed successfully. Event Code: 040a0003 Severity: Normal -- informational in nature. The Storage System Termination Even t Log validation failed. Event Code: 040b0003 Severity: Normal -- informational in nature. The Storage System Termination Even t Log has been updated with the termination event information obtained from the HSV450 controller that is not the Storage System Master. Event Code: 040c0803 Severity: Normal -- informational in nature. The Fault Manager on the Storage Sy stem Master received an invalid Event Information Packet from the remote Fault M anager. Event Code: 040d0003 Severity: Normal -- informational in nature. The Fault Manager operation was mad e quiescent. Event Code: 040e031c Severity: Undetermined -- more information needed to determine severity. An HSV4 50 controller sent a last gasp message prior to terminating operation with an in dication that both HSV450 controllers should terminate operation. Event Code: 040f0003 Severity: Normal -- informational in nature. This HSV450 controller sent its ter mination event information to the HSV450 controller that is the Storage System M aster. Event Code: 04100803

Severity: Normal -- informational in nature. Event reports were lost due to an i nsufficient supply of ISR Event Log Packets on the HSV450 controller that is the Storage System Master. Event Code: 04110803 Severity: Normal -- informational in nature. Event reports were lost due to an i nsufficient supply of ISR Event Log Packets on the HSV450 controller that is not the Storage System Master. Event Code: 04120003 Severity: Normal -- informational in nature. The last event reporting interval h as changed or last event reporting has been enabled or disabled. Event Code: 04130003 Severity: Normal -- informational in nature. Storage System event reporting is s till active. Event Code: 0414031d Severity: Undetermined -- more information needed to determine severity. HSV450 controller operation was terminated due to an unrecoverable event detected by ei ther software or hardware or due to an action initiated via the Storage System M anagement Interface. Event Code: 0415031d Severity: Undetermined -- more information needed to determine severity. This HS V450 controller has received a last gasp message from another HSV450 controller prior to it terminating operation. Event Code: 0416031d Severity: Undetermined -- more information needed to determine severity. An HSV4 50 controller sent a last gasp message prior to terminating operation with an in dication that both HSV450 controllers should terminate operation. Event Code: 04180003 Severity: Normal -- informational in nature. The Manufacturing Event Analysis Lo g validation completed successfully. Event Code: 04190003 Severity: Normal -- informational in nature. The Manufacturing Event Analysis Lo g validation failed. Event Code: 041a031c Severity: Undetermined -- more information needed to determine severity. An erro r condition was encountered while this HSV450 controller's Last Termination Even t information was being processed. Event Code: 041b031d Severity: Undetermined -- more information needed to determine severity. An erro r condition was encountered while this HSV450 controller's Last Termination Even t information was being processed. Event Code: 06000009 Severity: Normal -- informational in nature. A physical disk drive has reported that it has exceeded its failure prediction threshold. Event Code: 06014a08 Severity: Warning -- not failed but attention recommended or required. A Fibre C hannel port on the HSV450 controller has failed to respond. Event Code: 06020009

Severity: Normal -- informational in nature. A physical disk drive or an Enclosu re Link Module has reported a check condition error. Event Code: 06034713 Severity: Warning -- not failed but attention recommended or required. An exchan ge sent to a physical disk drive or another HSV450 controller via the mirror por t or a Fibre Channel port has timed out. Event Code: 06044812 Severity: Warning -- not failed but attention recommended or required. Work was unexpectedly sent to this HSV450 controller by a physical disk drive or another HSV450 controller. Event Code: 06054909 Severity: Warning -- not failed but attention recommended or required. Work has been sent to a physical disk drive or another HSV450 controller via the mirror p ort but it did not respond. Event Code: 06074709 Severity: Warning -- not failed but attention recommended or required. A Target Discovery Service Descriptor exchange sent to a physical disk drive has timed ou t. Event Code: 06080007 Severity: Normal -- informational in nature. An excessive number of link errors were detected on a HSV450 controller's Fibre Channel port. This informational ev ent is triggered by the occurrence of an excessive number of Tachyon chip link s tatus errors detected within a particular link status error type. Event Code: 06090013 Severity: Normal -- informational in nature. A physical disk drive has reported numerous failure prediction threshold exceeded errors. Event Code: 060a0013 Severity: Normal -- informational in nature. A physical disk drive has reported numerous check condition errors. Event Code: 060b4709 Severity: Warning -- not failed but attention recommended or required. A non-dat a exchange sent to a physical disk drive has timed out. Event Code: 060c0013 Severity: Normal -- informational in nature. A loop switch has been detected on a Fibre Channel port. Event Code: 061a0009 Severity: Normal -- informational in nature. A physical disk drive has exceeded its soft error threshold. Event Code: 061c4709 Severity: Warning -- not failed but attention recommended or required. An outbou nd frame targeted to a physical disk drive has timed out. Event Code: 061d4709 Severity: Warning -- not failed but attention recommended or required. A Fibre C hannel exchange to a physical disk drive has been retried. Event Code: 061e4c13 Severity: Critical -- failure or failure imminent. An HSV450 controller has dete cted only one port of a Fibre Channel device.

Event Code: 061f0013 Severity: Normal -- informational in nature. A previously reported Fibre Channel device with only one port has been corrected and redundancy has been restored. Event Code: 06204013 Severity: Critical -- failure or failure imminent. An unsupported Fibre Channel device has been detected. The device has been failed to prevent possible data co rruption or system instability. Event Code: 06210013 Severity: Normal -- informational in nature. A Fibre Channel device with incorre ct block size has been detected. Event Code: 06230013 Severity: Normal -- informational in nature. An HSV450 controller is about to re try a failed port. Event Code: 06280008 Severity: Normal -- informational in nature. The retry count for an OB task assi gned to a Drive Enclosure Environmental Monitoring Unit has been exhausted. Event Code: 06290009 Severity: Normal -- informational in nature. The HSV450 controller has sent a Ba sic Link Service command Abort Sequence Frame. Event Code: 062a0009 Severity: Normal -- informational in nature. The HSV450 controller has sent an E xtended Link Service command Reinstate Recovery Qualifier. Event Code: 062c0012 Severity: Normal -- informational in nature. One or more media defects were dete cted on a physical disk drive. Event Code: 062d0012 Severity: Normal -- informational in nature. An HSV450 controller issued a direc ted LIP to an arbitrated loop physical address. Event Code: 062e0012 Severity: Normal -- informational in nature. An HSV450 controller has detected l oop receiver failures. Event Code: 06304e13 Severity: Critical -- failure or failure imminent. An HSV450 controller has dete cted only one port of all Fibre Channel devices in an enclosure. Event Code: 06310013 Severity: Normal -- informational in nature. A previously reported Fibre Channel device enclosure with only one port has been corrected and redundancy has been restored. Event Code: 06324e13 Severity: Critical -- failure or failure imminent. An HSV450 controller has dete cted only one port of all Fibre Channel devices on a loop. Event Code: 06330013 Severity: Normal -- informational in nature. A previously reported Fibre Channel loop with only one port has been corrected and redundancy has been restored. Event Code: 06340013

Severity: Normal -- informational in nature. An HSV450 controller has been told to enable a device port, and that device port was not disabled during boot diagn ostics. Event Code: 06364d04 Severity: Critical -- failure or failure imminent. An unsupported Fibre Channel physical disk drive firmware revision has been detected by the physical disk dri ve firmware load process. Event Code: 0637c404 Severity: Normal -- informational in nature. A Fibre Channel physical disk drive firmware revision has been detected by the physical disk drive firmware load pr ocess that is later than the latest known supported revision. Event Code: 0638c404 Severity: Normal -- informational in nature. A Fibre Channel physical disk drive firmware revision has been detected by the physical disk drive firmware load pr ocess that has a newer supported revision available. Event Code: 06394008 Severity: Critical -- failure or failure imminent. The HSV450 controller bypasse d a device bay in an attempt to restore loop operability. Replace this drive onl y if the Loop Recovery algorithm did not abort. Event Code: 063a0008 Severity: Normal -- informational in nature. The HSV450 controller is attempting to recover devices on the indicated ports. Event Code: 063b0008 Severity: Normal -- informational in nature. The HSV450 controller has finished error recovery attempts on the indicated ports. Event Code: 063c0008 Severity: Normal -- informational in nature. The HSV450 controller been requeste d to unbypass device bays on the indicated port. Loop recovery incomplete. Event Code: 06404d04 Severity: Critical -- failure or failure imminent. A Fibre Channel physical disk drive that has new capabilities has been detected. The physical disk drive has properties that may or may not be compatible with this release of Enterprise Vir tual Array firmware -- the drive will be prevented from being used until the App roved Drive Firmware table has been updated to allow it. Event Code: 06410017 Severity: Normal -- informational in nature. The device loop configuration has c hanged on a HSV450 controller's Fibre Channel port. This informational event con tains a page of the newly genereated fibre channel loop map. Devices are listed in loop order using their ALPAs. Event Code: 06420009 Severity: Normal -- informational in nature. A user command has been sent to a p hysical disk drive. Event Code: 06440008 Severity: Normal -- informational in nature. An HSV450 controller is evaluating the next drive enclosure in the Loop Recovery Process. Event Code: 064b0008 Severity: Normal -- informational in nature. The HSV450 controller has been inst ructed to Enable or Disable Loop Recovery Operations.

Event Code: 064c0004 Severity: Normal -- informational in nature. Device Fibre Channel physical disk drive was placed on the Drive Suspect List (DSL) Look at events around this one to help determine what has happened. Fibre Channel port number used to communica te with the physical disk drive is contained in the port field. The arbitrated l oop physical address of the physical disk drive is contained in the al_pa field. Note that the content of the rack_num field will not be valid until Event Code: 064d0008 Severity: Normal -- informational in nature. The HSV450 controller has finished attempts to codeload all Drive Enclosure Environmental Monitoring Unit hardware requiring updates, and has completed staggered codeload if necessary. Event Code: 064e0009 Severity: Normal -- informational in nature. A physical disk drive has reported a non-zero RSP_CODE. in response to an I/O. This is not interesting by itself, a s the I/O will be retried if retries remain and are allowed for the particular t ype of I/O. Event Code: 064f0006 Severity: Normal -- informational in nature. An Enclosure Link Module has begun updating its code. Do not power down the Enclosure until the code update has com pleted. Event Code: 06500006 Severity: Normal -- informational in nature. An Enclosure Link Module has comple ted updating its code. It is now safe to power down the Enclosure. Event Code: 06510006 Severity: Normal -- informational in nature. A HSV450 controller has sent a SES control page to the Enclosure Link Module in the Enclosure for drive bay bypass control. Event Code: 06520006 Severity: Normal -- informational in nature. A HSV450 controller has sent a SES control page to the Enclosure Link Module in the Enclosure for drive bay power c ontrol. Event Code: 06530006 Severity: Normal -- informational in nature. A HSV450 controller has sent a SES control page to the Enclosure Link Module in the Enclosure to change the enclosu re ID number. Event Code: 06540006 Severity: Normal -- informational in nature. A HSV450 controller has discovered an Enclosure and is allocating resources for it. Event Code: 06558906 Severity: Critical -- failure or failure imminent. An Enclosure Link Module has been failed, and can no longer be used to detect drive position information, or to issue bypass/unbypass commands. Event Code: 06560006 Severity: Normal -- informational in nature. A HSV450 controller has sent a SES control page to the Enclosure Link Module in the Enclosure to shutdown the drive enclosure. Event Code: 06570006 Severity: Normal -- informational in nature. A HSV450 controller has detected an

inconsistency in the enclosure ID numbers reported by the Enclosure Link Module s in the in the Enclosure. Event Code: 06589906 Severity: Critical -- failure or failure imminent. A HSV450 controller has detec ted a potential cabling error. The Enclosure Link Module in the Enclosure is rep orting it is conencted to the wrong Fibre Channel port. Event Code: 06590006 Severity: Normal -- informational in nature. A HSV450 controller has detected a change in a physical disk drive bay condition in a Enclosure Event Code: 065a0006 Severity: Normal -- informational in nature. A HSV450 controller has detected a change in a Enclosure condition. Event Code: 065b0006 Severity: Normal -- informational in nature. A HSV450 controller has detected a change in a Enclosure power supply condition. Event Code: 065c0006 Severity: Normal -- informational in nature. A HSV450 controller has detected a change in a Enclosure fan module 1 condition. Event Code: 065d0006 Severity: Normal -- informational in nature. A HSV450 controller has detected a change in a Enclosure fan module 2 condition. Event Code: 065e0006 Severity: Normal -- informational in nature. A HSV450 controller has detected a change in the Enclosure A-side link module's condition. Event Code: 065f0006 Severity: Normal -- informational in nature. A HSV450 controller has detected a change in the Enclosure B-side link module's condition. Event Code: 06600006 Severity: Normal -- informational in nature. A HSV450 controller has detected a change in the Enclosure A-side link module's transceiver condition. Event Code: 06610006 Severity: Normal -- informational in nature. A HSV450 controller has detected a change in the Enclosure B-side link module's transceiver condition. Event Code: 06620006 Severity: Normal -- informational in nature. A HSV450 controller has detected a change in the Enclosure A-side link module alphanumeric display. Event Code: 06630006 Severity: Normal -- informational in nature. A HSV450 controller has detected a change in the Enclosure B-side link module alphanumeric display. Event Code: 06640006 Severity: Normal -- informational in nature. A HSV450 controller has detected a change in the Enclosure A-side link module temperature sensor. Event Code: 06650006 Severity: Normal -- informational in nature. A HSV450 controller has detected a change in the Enclosure B-side link module temperature sensor.

Event Code: 06660006 Severity: Normal -- informational in nature. A HSV450 controller has detected a change in the Enclosure midplane condition. Event Code: 06670006 Severity: Normal -- informational in nature. A HSV450 controller has detected a change in the Enclosure midplane temperature sensor condition. Event Code: 06684c13 Severity: Critical -- failure or failure imminent. An HSV450 controller has dete cted only one port of a Enclosure device. Event Code: 06690013 Severity: Normal -- informational in nature. A previously reported Enclosure dev ice with only one port has been corrected and redundancy has been restored. Event Code: 066a0028 Severity: Normal -- informational in nature. A Back-end Fibre Channel Port trans itioned to link up or link down. The corresponding device Fibre Channel port on the specified HSV450 controller has transitioned to a link up or link down state . Event Code: 066b0028 Severity: Normal -- informational in nature. A Back-end Fibre Channel Port is in the STO (State TimeOut) state, The corresponding device Fibre Channel port on t he specified HSV450 controller has its loop port state machine hung up for 2 sec . Event Code: 066c0008 Severity: Normal -- informational in nature. The HSV450 controller has finished codeloads to all Enclosure hardware requiring updates. Event Code: 066df308 Severity: Critical -- failure or failure imminent. The HSV450 controller cannot continue to codeload any Enclosure hardware requiring updates until backend redu ndancy is restored. Event Code: 066e0008 Severity: Normal -- informational in nature. The HSV450 controller has cleared a ny previous issues blocking codeload of any Enclosure hardware requiring updates Enclosure codeload operations will now continue Event Code: 066f0009 Severity: Normal -- informational in nature. One or more Fibre Channel devices h ave taken too long to complete the PRLI login phase in the allowed time. Event Code: 06700009 Severity: Normal -- informational in nature. One or more Fibre Channel devices h ave taken too long to complete the PLOGI login phase in the allowed time. Event Code: 0671f406 Severity: Critical -- failure or failure imminent. A HSV450 controller has detec ted a critical condition for a Disk Enclosure Power Supply. This often implies a loss in power to the Disk Enclosure Power Supply, causing a loss of redundancy in power to the Disk Enclosure. Event Code: 0700b515 Severity: Warning -- not failed but attention recommended or required. Allocatio n of a Virtual Disk has stalled due to insufficient space in the Disk Group caus ed by the failure or pulling of a physical disk drive.

Event Code: 0701b515 Severity: Warning -- not failed but attention recommended or required. Expansion of a Virtual Disk has stalled due to insufficient space in the Disk Group cause d by the failure or pulling of a physical disk drive. Event Code: 07020015 Severity: Normal -- informational in nature. Leveling of capacity in a Disk Grou p has started. Event Code: 07030015 Severity: Normal -- informational in nature. Leveling of capacity in a Disk Grou p has finished. Event Code: 07040015 Severity: Normal -- informational in nature. A member management operation has s tarted due to the appearance or disappearance of a physical disk drive. Event Code: 07050015 Severity: Normal -- informational in nature. A member management operation has f inished. Event Code: 07060015 Severity: Normal -- informational in nature. A Disk Group has started changing i ts internal structure due to the appearance or disappearance of a Volume. Event Code: 07070015 Severity: Normal -- informational in nature. A Disk Group has finished changing its internal structure due to the appearance or disappearance of a Volume. Event Code: 07080015 Severity: Normal -- informational in nature. Deallocation of a Virtual Disk has failed after three attempts due to unknown circumstances. This will more than l ikely be caused by failing physical drives. The deletion will be restarted when a resync/reboot occurs. Event Code: 0709b515 Severity: Warning -- not failed but attention recommended or required. A member management operation has stalled due to insufficient space in the Disk Group. Event Code: 070a0015 Severity: Normal -- informational in nature. A stalled member management operati on is being restarted. Event Code: 070d0015 Severity: Normal -- informational in nature. A member management operation encou nter an error while processing a Logical Disk. Processing on this logical disk will be retried again. Event Code: 070e0015 Severity: Normal -- informational in nature. An range of ebits were set or clear ed for a Logical Disk. A read of an LBA that has an ebit set will return MEDIA E RROR. A write to an LBA that has an ebit set will write the data and clear the e bit. Event Code: 070f0015 Severity: Normal -- informational in nature. A member management operation has r etried or waited too long Event Code: 07110015

Severity: Normal -- informational in nature. A Disk Group experienced an unexpec ted error during leveling or Redundant Storage Set migration and will be retried for the affected Virtual Disk. Event Code: 07120015 Severity: Normal -- informational in nature. A Virtual Disk experienced an unexp ected error during a migration operation and will be retried for the affected Di sk Group. Event Code: 07130715 Severity: Warning -- not failed but attention recommended or required. Metadata Check 0. Event Code: 07140715 Severity: Warning -- not failed but attention recommended or required. Metadata Check 1. Event Code: 07150015 Severity: Normal -- informational in nature. A Virtual Disk Expand or Shrink ope ration failed. Event Code: 09010005 Severity: Normal -- informational in nature. A physical disk drive has transitio ned to the NORMAL state. Event Code: 09020005 Severity: Normal -- informational in nature. The state of a Volume has changed. Event Code: 09040005 Severity: Normal -- informational in nature. An HSV450 controller has transition ed to the NORMAL state because the system is no longer inoperative. Event Code: 09050005 Severity: Normal -- informational in nature. The state of a battery assembly has changed. Event Code: 0906bf05 Severity: Undetermined -- more information needed to determine severity. A Volum e has transitioned to the MISSING state. Event Code: 09070005 Severity: Normal -- informational in nature. A Fibre Channel port has transition ed to the NORMAL state. Event Code: 0908b405 Severity: Warning -- not failed but attention recommended or required. A Disk Gr oup's occupancy alarm level threshold has been reached. Event Code: 09090005 Severity: Normal -- informational in nature. The resource availability state of a Volume has transitioned to the SUFFICIENT state. Event Code: 090c0005 Severity: Normal -- informational in nature. A snapclone Logical Disk has comple ted the unsharing operation. Event Code: 090d0005 Severity: Normal -- informational in nature. The state of the quorum disk flag o f a Volume has changed.

Event Code: 090e3605 Severity: Critical -- failure or failure imminent. The temperature trip point fo r a temperature sensor located within an HSV450 controller has been reached. Event Code: 090f2e05 Severity: Warning -- not failed but attention recommended or required. The tempe rature within an HSV450 controller is approaching its trip point. Event Code: 09110005 Severity: Normal -- informational in nature. An HSV450 controller's blower '1' i s now present. Event Code: 09122405 Severity: Critical -- failure or failure imminent. An HSV450 controller's blower '1' is running slower than the lowest acceptable speed. Event Code: 09132005 Severity: Critical -- failure or failure imminent. A voltage sensor has reported a voltage that is out of range. Event Code: 0914bf05 Severity: Undetermined -- more information needed to determine severity. A Volum e has transitioned to the FAILED state. Event Code: 0915b905 Severity: Undetermined -- more information needed to determine severity. An HSV4 50 controller has failed, as a result of the system becoming inoperative. Relate d events have more information. Event Code: 09160005 Severity: Normal -- informational in nature. The temperature within an HSV450 co ntroller has returned to its normal operating range. Event Code: 09172805 Severity: Critical -- failure or failure imminent. An HSV450 controller's batter y assembly '1' has been removed. Event Code: 09180005 Severity: Normal -- informational in nature. An HSV450 controller's battery asse mbly '1' is now in use. Event Code: 09190005 Severity: Normal -- informational in nature. A voltage sensor has returned to a normal range. Event Code: 091a2005 Severity: Critical -- failure or failure imminent. The battery assembly voltage regulator located within an HSV450 controller is offline. Event Code: 091b0005 Severity: Normal -- informational in nature. A Disk Group has transitioned to th e NORMAL state. Event Code: 091c0005 Severity: Normal -- informational in nature. The occupancy alarm level for a Dis k Group has returned to the normal range. Event Code: 091d2205 Severity: Critical -- failure or failure imminent. An HSV450 controller's batter y assembly '1' has malfunctioned.

Event Code: 091e0005 Severity: Normal -- informational in nature. An HSV450 controller's battery asse mbly '1' is now present. Event Code: 091f2905 Severity: Critical -- failure or failure imminent. An HSV450 controller's batter y assembly '2' has been removed. Event Code: 09200005 Severity: Normal -- informational in nature. An HSV450 controller's battery asse mbly '2' is now present. Event Code: 09210005 Severity: Normal -- informational in nature. An HSV450 controller's battery asse mbly '2' is now functioning properly. Event Code: 09222305 Severity: Critical -- failure or failure imminent. An HSV450 controller's batter y assembly has malfunctioned. Event Code: 09232b05 Severity: Critical -- failure or failure imminent. An HSV450 controller's blower '2' has been removed. Event Code: 09240005 Severity: Normal -- informational in nature. An HSV450 controller's blower assem bly '2' is now present. Event Code: 09252505 Severity: Critical -- failure or failure imminent. An HSV450 controller's blower assembly '2' is running slower than the lowest acceptable speed. Event Code: 09262c05 Severity: Critical -- failure or failure imminent. An HSV450 controller's '1' bl ower/power supply assembly has been removed or AC power has been removed from th e power supply. Event Code: 09270005 Severity: Normal -- informational in nature. An HSV450 controller's '1' blower/p ower supply assembly has been reinstalled or AC power has been restored to the p ower supply. Event Code: 09282d05 Severity: Critical -- failure or failure imminent. An HSV450 controller's '2' bl ower/power supply assembly has been removed or AC power has been removed from th e power supply. Event Code: 09290005 Severity: Normal -- informational in nature. An HSV450 controller's '2' blower/p ower supply assembly has been reinstalled or AC power has been restored to the p ower supply. Event Code: 092a2605 Severity: Critical -- failure or failure imminent. An HSV450 controller's '1' bl ower/power supply is running slower than the lowest acceptable speed. Event Code: 092b2705 Severity: Critical -- failure or failure imminent. An HSV450 controller's '2' bl ower/power supply is running slower than the lowest acceptable speed.

Event Code: 092c2f05 Severity: Warning -- not failed but attention recommended or required. An HSV450 controller's battery assembly has transitioned to the 'Battery System Hold-up T ime is zero hours' state. Event Code: 092dbf05 Severity: Undetermined -- more information needed to determine severity. The res ource availability state of a Volume has transitioned to the INSUFFICIENT state. Event Code: 092e0005 Severity: Normal -- informational in nature. An HSV450 controller has rejected a login attempt. Event Code: 092f0005 Severity: Normal -- informational in nature. An HSV450 controller has processed a Storage System Management Interface command with the result of non-success ret urn code. Event Code: 09300005 Severity: Normal -- informational in nature. An HSV450 controller has updated th e physical disk drive map for a loop pair. Event Code: 09314205 Severity: Critical -- failure or failure imminent. A physical disk drive has tra nsitioned to the DEGRADED state. Event Code: 09324005 Severity: Critical -- failure or failure imminent. A physical disk drive has tra nsitioned to the FAILED state. Event Code: 0935000e Severity: Normal -- informational in nature. A Disk Group was created. Event Code: 0936000e Severity: Normal -- informational in nature. A physical disk drive was discovere d. Event Code: 0937000e Severity: Normal -- informational in nature. A Presented Unit was created. Event Code: 0938000e Severity: Normal -- informational in nature. A Storage System Host Path was crea ted. Event Code: 0939000e Severity: Normal -- informational in nature. A Storage System Virtual Disk was c reated. Event Code: 093a000e Severity: Normal -- informational in nature. A Volume was created. Event Code: 093d000e Severity: Normal -- informational in nature. A Disk Group was deleted. Event Code: 093e420e Severity: Critical -- failure or failure imminent. A physical disk drive has dis appeared. Event Code: 093f000e

Severity: Normal -- informational in nature. A Presented Unit was deleted. Event Code: 0940000e Severity: Normal -- informational in nature. A Storage System Host Path was dele ted. Event Code: 0941000e Severity: Normal -- informational in nature. A Storage System Virtual Disk was d eleted. Event Code: 0943000e Severity: Normal -- informational in nature. An HSV450 controller has joined the Storage System. Event Code: 0944ba0e Severity: Undetermined -- more information needed to determine severity. An HSV4 50 controller has left the Storage System. Event Code: 0945000e Severity: Normal -- informational in nature. The Storage System has been deleted by an HSV450 controller. Event Code: 0946000e Severity: Normal -- informational in nature. A Data Replication Group was create d. Event Code: 0947000e Severity: Normal -- informational in nature. A Data Replication Group was delete d. Event Code: 0948000e Severity: Normal -- informational in nature. A Snapshot Storage System Virtual D isk was created. Event Code: 0949000e Severity: Normal -- informational in nature. A Clone Storage System Virtual Disk was created. Event Code: 094a000e Severity: Normal -- informational in nature. Destination Data Replication Group not deleted due to inoperative members. Event Code: 094b000e Severity: Normal -- informational in nature. A Volume was removed from a LDAD. Event Code: 094c000e Severity: Normal -- informational in nature. A new Remote Node has been discover ed. Event Code: 094d000e Severity: Normal -- informational in nature. The Remote Node object has been dis carded. Event Code: 094e000e Severity: Normal -- informational in nature. The Remote Node Storage System UUID has changed. Event Code: 094f000e Severity: Normal -- informational in nature. An Enclosure Appeared.

Event Code: 0950000e Severity: Normal -- informational in nature. An Enclosure Disappeared. Event Code: 0951000e Severity: Normal -- informational in nature. An IO Module Appeared. Event Code: 0952000e Severity: Normal -- informational in nature. An IO Module Disappeared. Event Code: 0965000f Severity: Normal -- informational in nature. A host operating system mode has ch anged. Event Code: 0966000f Severity: Normal -- informational in nature. Time was set on a Storage System. Event Code: 0967000f Severity: Normal -- informational in nature. The LUN of a Presented Unit has cha nged. Event Code: 0968000f Severity: Normal -- informational in nature. The device addition policy of a Sto rage System has changed. Event Code: 0969000f Severity: Normal -- informational in nature. The quiescent state of a Storage Sy stem Virtual Disk has changed. Event Code: 096a000f Severity: Normal -- informational in nature. The enabled/disabled state of a Sto rage System Virtual Disk has changed. Event Code: 096b000f Severity: Normal -- informational in nature. The cache policy of a Storage Syste m Virtual Disk has changed. Event Code: 096c000f Severity: Normal -- informational in nature. The usage state of a Volume changed . Event Code: 096d000f Severity: Normal -- informational in nature. The disk failure protection level o f a Disk Group has changed. Event Code: 096e000f Severity: Normal -- informational in nature. The write protected state of a Stor age System Virtual Disk has changed. Event Code: 0970460f Severity: Warning -- not failed but attention recommended or required. A HSV450 controller has declared a port on a physical disk drive unusable and will not lo g in to the device on that port due to numerous transport failures. Event Code: 0971000f Severity: Normal -- informational in nature. An HSV450 controller has received a request to shutdown. Event Code: 0972000f Severity: Normal -- informational in nature. An HSV450 controller has completed its shutdown preparations.

Event Code: 0973000f Severity: Normal -- informational in nature. The failsafe state of a Data Replic ation Group has changed. Event Code: 0974000f Severity: Normal -- informational in nature. The mode of a Data Replication Grou p has changed. Event Code: 0975000f Severity: Normal -- informational in nature. The synchronous/asynchronous operat ional state of a Data Replication Group has changed. Event Code: 0976000f Severity: Normal -- informational in nature. The read only attribute of a Data R eplication Group has changed. Event Code: 0977000f Severity: Normal -- informational in nature. A Data Replication Group failover h as occurred. Event Code: 0978000f Severity: Normal -- informational in nature. A Data Replication Group has been s uspended or resumed. Event Code: 0979000f Severity: Normal -- informational in nature. A Storage System Virtual Disk was a dded to a Data Replication Group. Event Code: 097a000f Severity: Normal -- informational in nature. A Storage System Virtual Disk was r emoved from a Data Replication Group. Event Code: 097b000f Severity: Normal -- informational in nature. The auto suspend attribute of a Dat a Replication Group has changed. Event Code: 097c000f Severity: Normal -- informational in nature. The destination presentation attrib ute of a Data Replication Group has changed. Event Code: 097d000f Severity: Normal -- informational in nature. The flags of a physical disk drive have changed because of a maintenance mode change. Event Code: 097e000f Severity: Normal -- informational in nature. The defer_copy attribute of a Data Replication Group has changed. Event Code: 097f000f Severity: Normal -- informational in nature. A Data Replication Group has been s uspended due to link down. Event Code: 0980000f Severity: Normal -- informational in nature. A Data Replication Group has been s uspended due to site failover. Event Code: 0981000f Severity: Normal -- informational in nature. A Data Replication Group has been s uspended due to defer copy.

Event Code: 0982000f Severity: Normal -- informational in nature. The split brain allow attribute of a Data Replication Group has changed. Event Code: 0983000f Severity: Normal -- informational in nature. A Data Replication Group has been s uspended due to instance restore on destination site. Event Code: 09c95105 Severity: Undetermined -- more information needed to determine severity. A Disk Group has transitioned to an INOPERATIVE state. Event Code: 09ca5105 Severity: Undetermined -- more information needed to determine severity. A Stora ge System Virtual Disk has transitioned to the FAILED state. Event Code: 09cb5005 Severity: Critical -- failure or failure imminent. A Storage System Virtual Disk has transitioned to the SNAPSHOT OVERCOMMIT state. Event Code: 09cc5105 Severity: Undetermined -- more information needed to determine severity. A Stora ge System Virtual Disk has transitioned to the DEVICE DATA LOST state. Event Code: 09cdc305 Severity: Undetermined -- more information needed to determine severity. A Fibre Channel port has transitioned to the FAILED state. Event Code: 09ce0005 Severity: Normal -- informational in nature. A Disk Group has transitioned to an INOPERATIVE MARKED state. Event Code: 09cf4105 Severity: Warning -- not failed but attention recommended or required. A physica l disk drive has transitioned to the NOT PRESENT state. Event Code: 09d00005 Severity: Normal -- informational in nature. An HSV450 controller no longer need s attention. Event Code: 09d1b905 Severity: Undetermined -- more information needed to determine severity. An HSV4 50 controller needs attention. Event Code: 09d22a05 Severity: Critical -- failure or failure imminent. An HSV450 controller's blower '1' has been removed. Event Code: 09d35105 Severity: Undetermined -- more information needed to determine severity. At leas t one Storage System Virtual Disk associated with a Data Replication Group has t ransitioned to the INOPERATIVE state. The remaining Storage System Virtual Disks associated with this Data Replication Group have been forced INOPERATIVE. Event Code: 09d40005 Severity: Normal -- informational in nature. All the Virtual Disks associated wi th a Data Replication Group have transitioned to the OPERATIVE state. Event Code: 09d50005

Severity: Normal -- informational in nature. The state of a physical disk drive has transitioned to the Single Port on Fibre state. Event Code: 09d63705 Severity: Warning -- not failed but attention recommended or required. An HSV450 controller has been powered off because the temperature sensors do not agree an d the system temperature can not be accurately determined. Event Code: 09d73705 Severity: Warning -- not failed but attention recommended or required. An HSV450 controller has been powered off because the temperature sensors can not be acce ssed and the system temperature can not be accurately determined. Event Code: 09d8b605 Severity: Undetermined -- more information needed to determine severity. A Redun dant Storage Set has two members on the same Fibre Channel device enclosure caus ing a Disk Group to lose its Single Point of Failure Robust Configuration. Event Code: 09d90005 Severity: Normal -- informational in nature. A Disk Group has attained a Single Point of Failure Robust Configuration. Event Code: 09da0005 Severity: Normal -- informational in nature. An HSV450 controller's blower '1' i s running at normal speed. Event Code: 09db0005 Severity: Normal -- informational in nature. An HSV450 controller's blower '2' i s running at normal speed. Event Code: 09dd0005 Severity: Normal -- informational in nature. An HSV450 controller receives a mai ntenance invoke call from the user Event Code: 09de5205 Severity: Critical -- failure or failure imminent. A Storage System Virtual Disk has transitioned to the INVALIDATED state. Event Code: 09e30005 Severity: Normal -- informational in nature. The state of a Storage System Virtu al Disk has changed. Event Code: 09e45105 Severity: Undetermined -- more information needed to determine severity. The dat a availability state of a Storage System Virtual Disk has transitioned to the DA TA LOST state. Event Code: 09e50005 Severity: Normal -- informational in nature. The data availability state of a St orage System Virtual Disk has transitioned to the NORMAL state. Event Code: 0b000010 Severity: Normal -- informational in nature. An HSV450 controller has begun a re synchronization operation. This is a restart of the HSV450 controller in a manne r that has little or no impact on host system connectivity. Event Code: 0b01b515 Severity: Warning -- not failed but attention recommended or required. A migrate method drive codeload has stalled due to insufficient space in the Disk Group.

Event Code: 0b040004 Severity: Normal -- informational in nature. A Fibre Channel physical disk drive firmware codeload begun. Event Code: 0b050004 Severity: Normal -- informational in nature. A Fibre Channel physical disk drive firmware codeload has finished. Event Code: 0b06001a Severity: Normal -- informational in nature. An HSV450 controller has begun/fini shed a code load, code use, or code burn operation as indicated, in a manner tha t has little or no impact on host system connectivity. Event Code: 0b09001e Severity: Normal -- informational in nature. Process with work, eg. during CSM H ang and Unit Stalled Too Long. Event Code: 0b0af21e Severity: Warning -- not failed but attention recommended or required. An HSV450 controller has a pending sprite code load. In order to use the new sprite versi on the controller needs to be restarted. Event Code: 0b0b0024 Severity: Normal -- informational in nature. The preserving resync process has b een initiated and is progressing. Event Code: 0c03000c Severity: Normal -- informational in nature. The specified Data Replication Grou p has transitioned to the Merging state, because the Data Replication Destinatio n Storage System is now accessible or resumed. Event Code: 0c045f0c Severity: Critical -- failure or failure imminent. A Data Replication Group has entered the Failsafe Locked state because the Data Replication Destination Stora ge System is inaccessible. Event Code: 0c05610c Severity: Critical -- failure or failure imminent. A Data Replication Group has entered the Failsafe Locked state due to an inaccessible Destination Virtual Dis k. Event Code: 0c06600c Severity: Critical -- failure or failure imminent. A Full Copy was terminated pr ior to completion: An unrecoverable read error occurred on the specified Source Virtual Disk during the Full Copy. Event Code: 0c075f0c Severity: Critical -- failure or failure imminent. A Full Copy terminated prior to completion: A remote copy error occurred due to an inaccessible alternate Sto rage System; The Full Copy will continue when the Data Replication Destination i s restored. Event Code: 0c08610c Severity: Critical -- failure or failure imminent. A Full Copy terminated prior to completion: A remote copy error occurred due to an inaccessible Destination V irtual Disk; The Full Copy will continue when the Destination Virtual Disk is re stored. Event Code: 0c09620c Severity: Warning -- not failed but attention recommended or required. A Data Re

plication Log has been reset due to insufficient Disk Group capacity; The Data R eplication Destination has been marked for a Full Copy. Event Code: 0c0a000c Severity: Normal -- informational in nature. A Data Replication Log has been res et due to a Data Replication Group failover. Event Code: 0c0b620c Severity: Warning -- not failed but attention recommended or required. An unreco verable read error occurred on the specified Data Replication Group Data Replica tion Log logical disk during a background read. Event Code: 0c0c000c Severity: Normal -- informational in nature. A Destination Data Replication Grou p has successfully completed a Merge. Event Code: 0c0f000c Severity: Normal -- informational in nature. A Data Replication Group is no long er in a Failsafe Locked state. Event Code: 0c10000c Severity: Normal -- informational in nature. A Destination Data Replication Grou p has been marked for a Full Copy. Event Code: 0c11000c Severity: Normal -- informational in nature. This Data Replication Group is tran sitioning from a Data Replication Source role to a Data Replication Destination role. Event Code: 0c12000c Severity: Normal -- informational in nature. This Data Replication Group is tran sitioning from a Data Replication Destination role to a Data Replication Source role. Event Code: 0c155f0c Severity: Critical -- failure or failure imminent. The Data Replication Path bet ween this Storage System and the Peer Storage System has closed, possibly due to a connection failure between the specified host port and the Peer Storage Syste m. Event Code: 0c160016 Severity: Normal -- informational in nature. An HSV450 controller has sent a tim e report message to this HSV450 controller. Event Code: 0c17630c Severity: Critical -- failure or failure imminent. The Data Replication Manager communications protocol version between the Data Replication Source Storage Syst em and a Data Replication Destination Storage System is mismatched. Event Code: 0c18640c Severity: Critical -- failure or failure imminent. Conditions on the Data Replic ation Destination Storage System are preventing acceptable replication throughpu t: Initiating temporary logging on the affected Data Replication Group that is f ailsafe mode disabled. Event Code: 0c19020c Severity: Critical -- failure or failure imminent. Overlapping concurrent host w rites to an Active/Active Peer Storage System violate a Data Replication Manager architectural requirement, resulting in a reparative resynchronization operatio n for the master Storage System and a Full Copy operation.

Event Code: 0c1a000c Severity: Normal -- informational in nature. The specified Destination Virtual D isk has successfully completed a Full Copy. Event Code: 0c1b5f0c Severity: Critical -- failure or failure imminent. A Data Replication Group has transitioned to the Logging state because the alternate Storage System is not ac cessible. Event Code: 0c1c610c Severity: Critical -- failure or failure imminent. The specified Source Data Rep lication Group has transitioned to the (not merging) Logging state because a Des tination Virtual Disk is not accessible. Event Code: 0c1d000c Severity: Normal -- informational in nature. Inconsistency was found in the grou p log: A Full Copy of the affected Data Replication Group will be initiated. Event Code: 0c1e5f0c Severity: Critical -- failure or failure imminent. The members of the specified Source Data Replication Group have not been presented to the host because the re mote Storage System is not accessible: Suspend Source Data Replication Group to override this behavior, which will present the members. Event Code: 0c1f000c Severity: Normal -- informational in nature. The members of the specified Source Data Replication Group have been presented to the host because the remote Stora ge System is now accessible or source group is now suspended. Event Code: 0c20650c Severity: Critical -- failure or failure imminent. Conditions on the Data Replic ation Destination Storage System are preventing replication processing: The spec ified Source Data Replication Group will remain in the Logging or the Failsafe L ocked state until corrective action is performed. Event Code: 0c21660c Severity: Critical -- failure or failure imminent. A replication operation on th e Data Replication Source Storage System or Data Replication Destination Storage System has stalled which will prevent replication processing for the specified Data Replication Group until corrective action is performed. Event Code: 0c22000c Severity: Normal -- informational in nature. A Data Replication Path between thi s Storage System and the Peer Storage System has been opened. Event Code: 0c23670c Severity: Warning -- not failed but attention recommended or required. Condition s on the inter site link are preventing acceptable replication throughput: Initi ating temporary logging on the affected Data Replication Group that is failsafe mode disabled. Event Code: 0c24000c Severity: Normal -- informational in nature. The specified Source Data Replicati on Group has transitioned to the (not merging) Logging state because a Destinati on Virtual Disk is momentarily inaccessible. Event Code: 0c25000c Severity: Normal -- informational in nature. A Full Copy terminated prior to com pletion: A remote copy error occurred due to a momentarily inaccessible Destinat

ion Virtual Disk; The Full Copy will continue when the Destination Virtual Disk is restored. Event Code: 0c26000c Severity: Normal -- informational in nature. The Data Replication Path between t his Storage System and the Peer Storage System has been opened due to simultaneo us requests from each Storage System Event Code: 0c27000c Severity: Normal -- informational in nature. The Data Replication Path between t his Storage System and the Peer Storage System has been opened by the Peer Stora ge System. Event Code: 0c285f0c Severity: Critical -- failure or failure imminent. A Data Replication Path to th e Peer Storage System is not currently available. Event Code: 0c29000c Severity: Normal -- informational in nature. The Data Replication Path between t his Storage System and the Peer Storage System has closed in order to force Data Replication Manager traffic to the controller's Preferred Port. Event Code: 0c2a000c Severity: Normal -- informational in nature. A Data Replication Path to a Peer S torage System has been found. Event Code: 0c2b600c Severity: Critical -- failure or failure imminent. A Merge was terminated prior to completion: An unrecoverable read error occurred on the log unit of the speci fied Data Replication Group during the Merge. Event Code: 0c2c660c Severity: Critical -- failure or failure imminent. A replication operation on th e Data Replication Source Storage System or Data Replication Destination Storage System has stalled which will prevent replication processing for the specified Data Replication Group until corrective action is performed. Event Code: 0c2d000c Severity: Normal -- informational in nature. The Peer Storage System port name t hat was incorrectly associated with a host has been deleted from the specified c lient object. Event Code: 0c2e680c Severity: Warning -- not failed but attention recommended or required. Insuffici ent resources exist to discover additional remote nodes. Event Code: 0c2f000c Severity: Normal -- informational in nature. Sufficient resources now exist to a llow discovery of additional remote nodes. Event Code: 0c30000c Severity: Normal -- informational in nature. A replication operation on the Data Replication Source Storage System or Data Replication Destination Storage Syste m has stalled which will prevent replication processing for the specified Data R eplication Group until corrective action is performed. Event Code: 0c31000c Severity: Normal -- informational in nature. A stalled Full Copy has been restar ted.

Event Code: 0c325f0c Severity: Critical -- failure or failure imminent. The Data Replication Path bet ween this Storage System and the Peer Storage System has closed, because the hos t port connection has failed. Event Code: 0c335f0c Severity: Critical -- failure or failure imminent. The Data Replication Path bet ween this Storage System and the Peer Storage System has closed, because the lin k or the Storage System has become unresponsive. Event Code: 0c345f0c Severity: Critical -- failure or failure imminent. The Data Replication Path bet ween this Storage System and the Peer Storage System has closed, due to slow res ponse on the connection between the specified host port and the Peer Storage Sys tem. Event Code: 0c35070c Severity: Warning -- not failed but attention recommended or required. The Data Replication Path between this Storage System and the Peer Storage System has clo sed, because a Data Replication Group configuration change lock was not released in a timely manner. Event Code: 0c365f0c Severity: Critical -- failure or failure imminent. The Data Replication Path bet ween this Storage System and the Peer Storage System has closed, due to thrashin g of the connection between the specified host port and the Peer Storage System. Event Code: 0c375f0c Severity: Critical -- failure or failure imminent. The Data Replication Path bet ween this Storage System and the Peer Storage System has closed, because the max imum ping retry count has been exceeded. Event Code: 0c38630c Severity: Critical -- failure or failure imminent. The Data Replication Path bet ween this Storage System and the Peer Storage System has closed, because the Dat a Replication Path protocol version is not supported by the controller firmware. Event Code: 0c39000c Severity: Normal -- informational in nature. The Data Replication Path between t his Storage System and the Peer Storage System has closed, because the Data Repl ication Path is not being used. Event Code: 0c3a5f0c Severity: Critical -- failure or failure imminent. A Data Replication Path betwe en this Storage System and the Peer Storage System could not be created, possibl y due to a connection failure between the specified host port and the Peer Stora ge System. Event Code: 0c3b000c Severity: Normal -- informational in nature. The Data Replication Path between t his Storage System and the Peer Storage System has closed, because the Peer Stor age System requested the creation of a new Data Replication Path. Event Code: 0c3c000c Severity: Normal -- informational in nature. The Data Replication Path between t his Storage System and the Peer Storage System has closed because the Peer Stora ge System tried to open a Data Replication Path to a different host port. Event Code: 0c3d5f0c Severity: Critical -- failure or failure imminent. The Data Replication Path bet

ween this Storage System and the Peer Storage System has closed because of a fra me retransmit limit was reached. Event Code: 0c3e000c Severity: Normal -- informational in nature. The Data Replication Path between t his Storage System and the Peer Storage System was closed by the Peer Storage Sy stem. Event Code: 0c3f000c Severity: Normal -- informational in nature. The Data Replication Path between t his Storage System and the Peer Storage System has closed because the NPortID of the remote port changed. Event Code: 0c40690c Severity: Warning -- not failed but attention recommended or required. The Data Replication Path between this Storage System and the Peer Storage System has clo sed because an out of order frame sequence number was detected. Event Code: 0c41000c Severity: Normal -- informational in nature. The Data Replication Path between t his Storage System and the Peer Storage System has closed to allow creation of a Data Replication Path that requires a lower protocol version. Event Code: 0c42000c Severity: Normal -- informational in nature. The Data Replication Path between t his Storage System and the Peer Storage System has closed because Peer Storage S ystem no longer exists. Event Code: 0c43000c Severity: Normal -- informational in nature. The Data Replication Path between t his Storage System and the Peer Storage System has been closed by user request. Event Code: 0c49000c Severity: Normal -- informational in nature. The Data Replication Path between t his Storage System and the Peer Storage System has closed because the correspond ing connection data was deleted. This is typically due to a change in the fabric . Event Code: 0c4a000c Severity: Normal -- informational in nature. A request to create a Data Replicat ion Path was rejected because the Storage System is re-starting. Event Code: 0c4b000c Severity: Normal -- informational in nature. A request to create a Data Replicat ion Path was rejected because the Storage System is not active. Event Code: 0c4c000c Severity: Normal -- informational in nature. A request to create a Data Replicat ion Path was rejected because the firmware has not completed Data Replication Pa th discovery. Event Code: 0c4e000c Severity: Normal -- informational in nature. A request to create a Data Replicat ion Path was rejected because the remote port is not associated with a Enterpris e Virtual Array. Event Code: 0c4f000c Severity: Normal -- informational in nature. A request to create a Data Replicat ion Path was rejected because the remote port world wide identifier is associate d with a host system.

Event Code: 0c50000c Severity: Normal -- informational in nature. A request to create a Data Replicat ion Path was rejected because the supplied UUID does not match the UUID for this Storage System. Event Code: 0c51000c Severity: Normal -- informational in nature. A request to create a Data Replicat ion Path was rejected because the requested protocol version is not compatible w ith the existing Data Replication Path. Event Code: 0c52000c Severity: Normal -- informational in nature. A request to create a Data Replicat ion Path was rejected because the requested port was disabled by the user. Event Code: 0c53000c Severity: Normal -- informational in nature. A request to create a Data Replicat ion Path was rejected because the insufficient resources exist to create the Dat a Replication Path. Event Code: 0c54000c Severity: Normal -- informational in nature. A request to create a Data Replicat ion Path was rejected to force the use of a lower protocol version on the Data R eplication Path. Event Code: 0c550016 Severity: Normal -- informational in nature. A time synchronization message has been sent to a Alternate Site. Event Code: 0c56000c Severity: Normal -- informational in nature. The DRM Forced Logging Timeout valu e has been changed. Event Code: 0c57000c Severity: Normal -- informational in nature. The DRM Forced Logging Timeout valu e has been reset to the default value. Event Code: 0c58690c Severity: Warning -- not failed but attention recommended or required. Excessive data exchange retry rate on the inter site link is preventing acceptable replic ation throughput: Reducing data exchange resources. Event Code: 0c59690c Severity: Warning -- not failed but attention recommended or required. Excessive out of order message rate on the inter site link is impacting replication throu ghput. Event Code: 0c5a670c Severity: Warning -- not failed but attention recommended or required. Excessive PING response time on the inter site link is preventing acceptable replication throughput: Reducing data exchange resources. Event Code: 0c5b670c Severity: Warning -- not failed but attention recommended or required. Replicati on data exchange write resources on the inter site link have been reduced to the minimum allowed value. Event Code: 0c5c670c Severity: Warning -- not failed but attention recommended or required. Replicati on data exchange copy resources on the inter site link have been reduced to the

minimum allowed value. Event Code: 0c5d000c Severity: Normal -- informational in nature. Quality of service on the inter sit e link has improved: Increasing data exchange resources to improve replication t hroughput. Event Code: 0c5e000c Severity: Normal -- informational in nature. A Replication Write History Log Shr ink is in progress. Event Code: 0c5f000c Severity: Normal -- informational in nature. A Replication Write History Log Shr ink has completed. Event Code: 0c60000c Severity: Normal -- informational in nature. Excessive Vdisk response time at th e Data Replication Destination has been detected: Reducing data exchange copy re sources on the inter site link to limit replication throughput. Event Code: 0c61000c Severity: Normal -- informational in nature. The Data Replication Path between t his Storage System and the Peer Storage System has closed to allow resynchroniza tion with the Peer Storage System. Event Code: 0c62000c Severity: Normal -- informational in nature. The members of the specified Source Data Replication Group have been re-presented to the host because the split bra in protection condition has been manually checked and cleared. Event Code: 0c63000c Severity: Normal -- informational in nature. The members of the specified Source Data Replication Group have not been presented to the host because the remote S torage System is not accessible: Suspend\Resume Source Data Replication Group to override this behavior, which will present the members. Event Code: 0c64000c Severity: Normal -- informational in nature. The specified Data Replication Grou p was not set on the Data Replication Destination other site since the version d oes not support the feature Event Code: 0c65000c Severity: Normal -- informational in nature. The specified Data Replication Grou p log has hit the 50 percent full mark. Event Code: 0c66000c Severity: Normal -- informational in nature. The specified Data Replication Grou p log has hit the 75 percent full mark. Event Code: 0c67000c Severity: Normal -- informational in nature. The specified Data Replication Grou p log has hit the 90 percent full mark. Event Code: 0c68000c Severity: Normal -- informational in nature. The specified Data Replication Grou p log has hit the 95 percent full mark. Event Code: 0c69000c Severity: Normal -- informational in nature. The specified Data Replication Grou p log has hit the 99 percent full mark.

Event Code: 0c6f000c Severity: Normal -- informational in nature. Excessive Vdisk response time at th e Data Replication Source has been detected: Reducing data exchange copy resourc es on the inter site link to limit replication throughput. Event Code: 0c70000c Severity: Normal -- informational in nature. The specified Destination Virtual D isk has successfully completed a Fast Resync. Event Code: 0c71000c Severity: Normal -- informational in nature. Async group removal: the Source Vir tual Disk member has been successfully removed from the Async group Data Replica tion Group. Event Code: 0c72000c Severity: Normal -- informational in nature. The removal of the Source Virtual D isk failed for the Data Replication Group. Event Code: 0c73000c Severity: Normal -- informational in nature. The removal of the Source Virtual D isk completed after a log full condition for a Data Replication Group. The desti nation member, if retained, may not have all the data. Event Code: 0c74000c Severity: Normal -- informational in nature. The Source Virtual Disk in group Da ta Replication Group has started Merge Sync. Event Code: 0c75000c Severity: Normal -- informational in nature. The Source Virtual Disk in group Da ta Replication Group has finished Merge Sync. Event Code: 0c76000c Severity: Normal -- informational in nature. The Data Replication Log of a newly created Data Replication Group has been assigned to a FATA Disk Group. Event Code: 0c77000c Severity: Normal -- informational in nature. This Data Replication Group is fail ing over during a copy operation. Event Code: 0c78000c Severity: Normal -- informational in nature. The Source Virtual Disk of a Data R eplication Group completed shrinking. Event Code: 0c79000c Severity: Normal -- informational in nature. The Source Virtual Disk of a Data R eplication Group has failed shrink. Event Code: 0c7a000c Severity: Normal -- informational in nature. The Source Virtual Disk of a Data R eplication Group will shrink immediately due to a log full condition. Event Code: 0c7b000c Severity: Normal -- informational in nature. The Data Replication Log of a newly created Data Replication Group has been assigned to a SSD Disk Group. Event Code: 0c7c000c Severity: Normal -- informational in nature. The Destination Virtual Disk of a D ata Replication Group has been assigned to a SSD Disk Group.

Event Code: 0c7d000c Severity: Normal -- informational in nature. The Source Virtual Disk of a Data R eplication Group has been assigned to a SSD Disk Group. Event Code: 0c7e5f0c Severity: Critical -- failure or failure imminent. The Data Replication Path bet ween this Storage System and the Peer Storage System has closed because the conn ection has been logged out. Event Code: 0c7f5f0c Severity: Critical -- failure or failure imminent. The number of nPortIds suppor ting the Data Replication Manager protocol exceeds the maximum supported by the firmware. Event Code: 0c806a0c Severity: Warning -- not failed but attention recommended or required. A request to create a Data Replication Path was rejected because the communication protoc ol settings are not compatible. Event Code: 0c815f0c Severity: Critical -- failure or failure imminent. The Data Replication Path bet ween this Storage System and the Peer Storage System has closed because the Data Replication Path is disabled or no longer available. Event Code: 0c826b0c Severity: Critical -- failure or failure imminent. The capacity of the Source Vi rtual Disk and its peer Destination Virtual Disk are different and must be corre cted. Event Code: 0c83000c Severity: Normal -- informational in nature. The Data Replication Group and its members have completed a failover between the master and slave controllers. Event Code: 0c84000c Severity: Normal -- informational in nature. A Replication Write History Log exp ansion has completed. Event Code: 0c86000c Severity: Normal -- informational in nature. The removal of the Source Virtual D isk failed on the DESTINATION for the Data Replication Group. Event Code: 0d024106 Severity: Warning -- not failed but attention recommended or required. A physica l disk drive is improperly installed or missing. This could affect the drive enc losure air flow and cause an over temperature condition. Event Code: 0d348006 Severity: Critical -- failure or failure imminent. A drive enclosure power suppl y is improperly installed or missing. This could affect the drive enclosure air flow and cause an over temperature condition. The operational power supply will automatically shut down after a short period of time, thereby disabling the driv e enclosure. This condition remains active until either the problem is corrected , or the operational power supply shuts down, whichever occurs first. Event Code: 0d359a06 Severity: Critical -- failure or failure imminent. A drive enclosure power suppl y component has failed. Event Code: 0d478306 Severity: Critical -- failure or failure imminent. A drive enclosure fan module

is not operating properly. This could affect the drive enclosure air flow and ca use an over temperature condition. A single fan operating at high speed can prov ide sufficient air flow to cool an enclosure. However, operating an enclosure at temperatures approaching an overheating threshold can damage elements and may r educe the mean time before failure of a specific element. Event Code: 0d4b8206 Severity: Critical -- failure or failure imminent. A drive enclosure fan module is improperly installed or missing. This affects the drive enclosure air flow an d can cause an over temperature condition. Event Code: 0d5b8606 Severity: Warning -- not failed but attention recommended or required. The tempe rature of a Enclosure Link Module temperature sensor or Midplane temperature sen sor of the disk enclosure is at warning level. The Enterprise Virtual Array syst em will automatically shut down if the average temperature of all the temperatur e sensors (IOA, IOB, and 2 Midplane temperature sensors) of the disk enclosure i s at or above 50C. Event Code: 0d5f8706 Severity: Critical -- failure or failure imminent. The temperature of a Enclosur e Link Module temperature sensor or Midplane temperature sensor of the disk encl osure is at critical level. The Enterprise Virtual Array system will automatical ly shut down if the average temperature of all the temperature sensors (IOA, IOB , and 2 Midplane temperature sensors) of the disk enclosure is at or above 50C. Event Code: 0d8d9006 Severity: Critical -- failure or failure imminent. A drive enclosure transceiver error has been detected. Event Code: 0ddd9306 Severity: Critical -- failure or failure imminent. A drive enclosure I/O module error has occurred. Event Code: 0dde0006 Severity: Normal -- informational in nature. A drive enclosure I/O module is not communicating with the other I/O module. Event Code: 0df00011 Severity: Normal -- informational in nature. The status has changed on one or mo re of the drive enclosures. This informational event is generated for the HSV el ement manager GUI and contains no user information. Event Code: 0e800019 Severity: Normal -- informational in nature. Battery subsystem boot time status. Event Code: 0e810019 Severity: Normal -- informational in nature. Battery assembly '0' is now present . Event Code: 0e82e119 Severity: Critical -- failure or failure imminent. Battery assembly '0' has been removed. Event Code: 0e830019 Severity: Normal -- informational in nature. The status of battery assembly '0' has changed. Event Code: 0e84dd19 Severity: Critical -- failure or failure imminent. Battery assembly '0' has malf

unctioned. Event Code: 0e850019 Severity: Normal -- informational in nature. Battery assembly '1' is now present . Event Code: 0e86e219 Severity: Critical -- failure or failure imminent. Battery assembly '1' has been removed. Event Code: 0e870019 Severity: Normal -- informational in nature. The status of battery assembly '1' has changed. Event Code: 0e88de19 Severity: Critical -- failure or failure imminent. Battery assembly '1' has malf unctioned. Event Code: 0e890019 Severity: Normal -- informational in nature. Battery assembly '2' is now present . Event Code: 0e8ae319 Severity: Critical -- failure or failure imminent. Battery assembly '2' has been removed. Event Code: 0e8b0019 Severity: Normal -- informational in nature. The status of battery assembly '2' has changed. Event Code: 0e8cdf19 Severity: Critical -- failure or failure imminent. Battery assembly '2' has malf unctioned. Event Code: 0e8d0019 Severity: Normal -- informational in nature. Battery assembly '3' is now present . Event Code: 0e8ee419 Severity: Critical -- failure or failure imminent. Battery assembly '3' has been removed. Event Code: 0e8f0019 Severity: Normal -- informational in nature. The status of battery assembly '3' has changed. Event Code: 0e90e019 Severity: Critical -- failure or failure imminent. Battery assembly '3' has malf unctioned. Event Code: 0e910019 Severity: Normal -- informational in nature. The battery subsystem has transitio ned to the good state. Event Code: 0e920019 Severity: Normal -- informational in nature. The battery subsystem has transitio ned to the low state. Event Code: 0e93e519 Severity: Warning -- not failed but attention recommended or required. The batte

ry subsystem has transitioned to the bad state. Event Code: 0e940019 Severity: Normal -- informational in nature. Blower subsystem boot time status. Event Code: 0e950019 Severity: Normal -- informational in nature. Blower assembly '0' is now present. Event Code: 0e96e919 Severity: Critical -- failure or failure imminent. Blower assembly '0' has been removed. Event Code: 0e970019 Severity: Normal -- informational in nature. The status of blower assembly '0' h as changed. Event Code: 0e98e719 Severity: Critical -- failure or failure imminent. Blower assembly '0' has malfu nctioned. Event Code: 0e990019 Severity: Normal -- informational in nature. Blower assembly '1' is now present. Event Code: 0e9aea19 Severity: Critical -- failure or failure imminent. Blower assembly '1' has been removed. Event Code: 0e9b0019 Severity: Normal -- informational in nature. The status of blower assembly '1' h as changed. Event Code: 0e9ce819 Severity: Critical -- failure or failure imminent. Blower assembly '1' has malfu nctioned. Event Code: 0e9def19 Severity: Warning -- not failed but attention recommended or required. Battery r ead memory failure has occurred. Event Code: 0e9e0019 Severity: Normal -- informational in nature. Temperature subsystem boot time sta tus. Event Code: 0e9f0019 Severity: Normal -- informational in nature. The temperature within an HSV450 co ntroller has returned to its normal operating range. Event Code: 0ea02e19 Severity: Warning -- not failed but attention recommended or required. The tempe rature within an HSV450 controller is approaching its trip point. Event Code: 0ea13619 Severity: Critical -- failure or failure imminent. The temperature trip point fo r a temperature sensor located within an HSV450 controller has been reached. Event Code: 0ea20019 Severity: Normal -- informational in nature. Power Supply subsystem boot time st atus. Event Code: 0ea30019

Severity: Normal -- informational in nature. Power Supply assembly '0' is now pr esent. Event Code: 0ea4ed19 Severity: Critical -- failure or failure imminent. Power Supply assembly '0' has been removed. Event Code: 0ea50019 Severity: Normal -- informational in nature. The status of power supply assembly '0' has changed. Event Code: 0ea6eb19 Severity: Critical -- failure or failure imminent. Power supply assembly '0' los t AC connection or has malfunctioned. Event Code: 0ea70019 Severity: Normal -- informational in nature. Power Supply assembly '1' is now pr esent. Event Code: 0ea8ee19 Severity: Critical -- failure or failure imminent. Power Supply assembly '1' has been removed. Event Code: 0ea90019 Severity: Normal -- informational in nature. The status of power supply assembly '1' has changed. Event Code: 0eaaec19 Severity: Critical -- failure or failure imminent. Power supply assembly '1' los t AC connection or has malfunctioned. Event Code: 0f004a08 Severity: Warning -- not failed but attention recommended or required. A Fibre C hannel port on the HSV450 controller has failed to respond. Event Code: 0f010007 Severity: Normal -- informational in nature. An excessive number of link errors were detected on a HSV450 controller's mirror Fibre Channel port. This informati onal event is triggered by the occurrence of an excessive number of Tachyon chip link status errors detected within a particular link status error type. Event Code: 0f020013 Severity: Normal -- informational in nature. An HSV450 controller has been told to enable a mirror port, and that mirror port was not disabled during boot diagn ostics. Event Code: 0f034709 Severity: Warning -- not failed but attention recommended or required. A non-dat a exchange sent to a mirror port has timed out. Event Code: 0f040009 Severity: Normal -- informational in nature. The HSV450 controller has sent an E xtended Link Service command Reinstate Recovery Qualifier. Event Code: 0f050009 Severity: Normal -- informational in nature. The HSV450 controller has sent a Ba sic Link Service command Abort Sequence Frame. Event Code: 0f060024 Severity: Normal -- informational in nature. The HSV450 controller has updated i

ts Mirror Transport Status. Event Code: 0f070724 Severity: Warning -- not failed but attention recommended or required. The HSV45 0 controller mirror transport performed an invalid status change. Event Code: 42000008 Severity: Normal -- informational in nature. A host Fibre Channel port transitio ned to the link down state. Event Code: 42010008 Severity: Normal -- informational in nature. A host Fibre Channel port transitio ned to the link failed state. Event Code: 42020008 Severity: Normal -- informational in nature. A host Fibre Channel port transitio ned to the link up state AND the in-band port is ready for SCSI. Event Code: 42030007 Severity: Normal -- informational in nature. An excessive number of link errors were detected on a host Fibre Channel port. Event Code: 42044a08 Severity: Warning -- not failed but attention recommended or required. A host Fi bre Channel port has failed to respond. Event Code: 42050008 Severity: Normal -- informational in nature. A host Fibre Channel port has trans itioned to a deadlocked state. Event Code: 4206001b Severity: Normal -- informational in nature. Indicated Virtual Disk has transiti oned to Stalled Too Long. Event Code: 42080008 Severity: Normal -- informational in nature. A host Fibre Channel port has been reissued a freeze command. Event Code: 42090008 Severity: Normal -- informational in nature. A host Fibre Channel port has been issued a soft reset. Event Code: 420a001b Severity: Normal -- informational in nature. Indicated Virtual Disk that previou sly entered into Stalled Too Long has now been unstalled and resumed. Event Code: 420b001b Severity: Normal -- informational in nature. Indicated Virtual Disk has transiti oned to ownership by the other HSV450 controller. Event Code: 420c001b Severity: Normal -- informational in nature. Indicated Virtual Disk has failed t o transition ownership to the other HSV450 controller. Event Code: 420e0024 Severity: Normal -- informational in nature. Generic frontend service informatio n events. Event Code: 420f0008 Severity: Normal -- informational in nature. A host Fibre Channel port is being

reset to clear a credit error which may result in a subsequent LINK DOWN and LIN K UP event. Event Code: 42100008 Severity: Normal -- informational in nature. A host Fibre Channel port has compl eted name server registration . Event Code: 83002014 Severity: Critical -- failure or failure imminent. A failure was detected during the execution of this HSV450 controller's on-board diagnostics. Event Code: 83013014 Severity: Critical -- failure or failure imminent. A GBIC SFF Serial ID Data che ck code failure was detected during the execution of this HSV450 controller's on -board diagnostics. Event Code: 83073a14 Severity: Critical -- failure or failure imminent. A GBIC SFF was determined to be not present during the execution of this HSV450 controller's on-board diagnos tics. Event Code: 83083b14 Severity: Warning -- not failed but attention recommended or required. A failure was detected during testing of this HSV450 controller's SRAM. Event Code: 83093b14 Severity: Warning -- not failed but attention recommended or required. A parity error was detected during testing of this HSV450 controller's SRAM. Event Code: 830b0026 Severity: Normal -- informational in nature. Cache memory ECC errors exceeded 25 0/day in this HSV450 controller's SDRAM. Event Code: 830c0026 Severity: Normal -- informational in nature. Policy memory ECC errors exceeded 2 50/day in this HSV450 controller's SDRAM. Event Code: 830d0026 Severity: Normal -- informational in nature. Cache memory ECC errors exceeded 75 0/week in this HSV450 controller's SDRAM. Event Code: 830e0026 Severity: Normal -- informational in nature. Policy memory ECC errors exceeded 7 50/week in this HSV450 controller's SDRAM. TERMINATION CODES: Termination Code: 00000000 Unknown termination code Termination Code: 0101011f Severity: Critical -- failure or failure imminent. Unknown fault type reported b y EXEC. Termination Code: 0102011f Severity: Critical -- failure or failure imminent. DLQ entry not properly linked . Termination Code: 0103011f Severity: Critical -- failure or failure imminent. Timer not expired as expected

. Termination Code: 0104011f Severity: Critical -- failure or failure imminent. Structure not a timer as expe cted. Termination Code: 0105011f Severity: Critical -- failure or failure imminent. DLQ entry doubly linked. Termination Code: 0106011f Severity: Critical -- failure or failure imminent. DLQ head not properly linked. Termination Code: 0107011f Severity: Critical -- failure or failure imminent. SQ entry doubly linked. Termination Code: 0108011f Severity: Critical -- failure or failure imminent. Structure not a BQUE as expec ted. Termination Code: 0109011f Severity: Critical -- failure or failure imminent. Structure not a SEM as expect ed. Termination Code: 010a011f Severity: Critical -- failure or failure imminent. Function not yet implemented. Termination Code: 010b011f Severity: Critical -- failure or failure imminent. ILF invocation not from SC. Termination Code: 010c011f Severity: Critical -- failure or failure imminent. Too many performance log inst ances. Termination Code: 010d011f Severity: Critical -- failure or failure imminent. Undefined performance log cal l. Termination Code: 010e011f Severity: Critical -- failure or failure imminent. Structure not AQUE as expecte d. Termination Code: 010f011f Severity: Critical -- failure or failure imminent. Waiter queue not empty as exp ected. Termination Code: 0110011f Severity: Critical -- failure or failure imminent. Structure not GATE as expecte d. Termination Code: 0111011f Severity: Critical -- failure or failure imminent. Receiver queue not empty as e xpected. Termination Code: 0112011f Severity: Critical -- failure or failure imminent. BQUE has unexpected items. Termination Code: 0113011f Severity: Critical -- failure or failure imminent. Structure not ASEM as expecte d.

Termination Code: 0114011f Severity: Critical -- failure or failure imminent. Unknown system trap routine. Termination Code: 0115011f Severity: Critical -- failure or failure imminent. Active DMA list is empty. Termination Code: 0116011f Severity: Critical -- failure or failure imminent. CDB address not as expected. Termination Code: 0117011f Severity: Critical -- failure or failure imminent. Attempt to allocate a buffer that is already in use. Termination Code: 0118011f Severity: Critical -- failure or failure imminent. Attempt to free a buffer that is already free. Termination Code: 0119011f Severity: Critical -- failure or failure imminent. Interrupts unexpectedly disab led. Termination Code: 011a011f Severity: Critical -- failure or failure imminent. Page zero corrupted. Termination Code: 011b011f Severity: Critical -- failure or failure imminent. DCBZ not cache line aligned. Termination Code: 011c0140 Severity: Critical -- failure or failure imminent. Console requested crash with dump (not coupled). Termination Code: 011d01c0 Severity: Critical -- failure or failure imminent. Console requested crash with dump (coupled). Termination Code: 011e0120 Severity: Critical -- failure or failure imminent. Console requested restart wit hout dump (not coupled). Termination Code: 011f01a0 Severity: Critical -- failure or failure imminent. Console requested restart wit hout dump (coupled). Termination Code: 01220105 Severity: Critical -- failure or failure imminent. Unknown SMI interrupt occurre d. Termination Code: 01250160 Severity: Critical -- failure or failure imminent. Console requested crash with dump (not coupled). Termination Code: 012601e0 Severity: Critical -- failure or failure imminent. Console requested crash with dump (coupled). Termination Code: 01400100 Severity: Critical -- failure or failure imminent. Expiration queue not BQUE. Termination Code: 015a0100 Severity: Critical -- failure or failure imminent. exc_do_preempt_high called wi

th empty subprocess queue Termination Code: 02000100 Severity: Critical -- failure or failure imminent. Initialization failed due to insufficient memory. Termination Code: 02010100 Severity: Critical -- failure or failure imminent. CACHE_get_data called with ba d get data. Termination Code: 02020100 Severity: Critical -- failure or failure imminent. Cannot allocate BQ. Termination Code: 0203010b Severity: Critical -- failure or failure imminent. Duplicate dirty data found in Buffer Metadata Array. Termination Code: 0204010a Severity: Critical -- failure or failure imminent. Invalid Primary Mirror Operat ion state. Invalid Unit Cache state. Termination Code: 0205010a Severity: Critical -- failure or failure imminent. Invalid Unit Cache state. Termination Code: 02070100 Severity: Critical -- failure or failure imminent. Mirror data structure inconsi stency. Termination Code: 02080100 Severity: Critical -- failure or failure imminent. Mirror UUID Changed. Termination Code: 02090100 Severity: Critical -- failure or failure imminent. Invalid call to CACHE_lock_me ta. Termination Code: 020a0104 Severity: Critical -- failure or failure imminent. Cannot align parity and user data. Termination Code: 020b0100 Severity: Critical -- failure or failure imminent. Invalid Pullover Memory Opera tion state. Termination Code: 020c0106 Severity: Critical -- failure or failure imminent. Invalid Group Cache Operation state for Data Replication Group. Termination Code: 020d0104 Severity: Critical -- failure or failure imminent. Process NV Data NCA corrupted . Termination Code: 020e0100 Severity: Critical -- failure or failure imminent. Process NV Data Freeing Diag Buffer. Termination Code: 020f0100 Severity: Critical -- failure or failure imminent. Improper MWB Recovery data se nt. Termination Code: 02100108

Severity: Critical -- failure or failure imminent. Mnode & MFC NCAE Difference. Termination Code: 02110100 Severity: Critical -- failure or failure imminent. Improper MWBF Recovery data s ent. Termination Code: 02120100 Severity: Critical -- failure or failure imminent. WRITE HOLE COLLISION IN RS_CR ITICAL.c Termination Code: 02150101 Severity: Critical -- failure or failure imminent. Unable to obtain free cache n odes. Termination Code: 02160102 Severity: Critical -- failure or failure imminent. Unable to obtain free volatil e cache buffers. Termination Code: 02180102 Severity: Critical -- failure or failure imminent. Invalid Proxy Write Mirror Op eration state. Termination Code: 02190103 Severity: Critical -- failure or failure imminent. Invalid Proxy Read Mirror Ope ration state. Termination Code: 021a0102 Severity: Critical -- failure or failure imminent. Invalid Proxy Verify Mirror O peration state. Termination Code: 021b0100 Severity: Critical -- failure or failure imminent. Not enough XDs for RSTORE flu sh Termination Code: 021c0102 Severity: Critical -- failure or failure imminent. Invalid Flush Node Detected Termination Code: 021e0100 Severity: Critical -- failure or failure imminent. Firmware was loaded with an i ncompatible Cache memory layout Termination Code: 021f0100 Severity: Critical -- failure or failure imminent. Unable to obtain free non-vol atile cache buffers Termination Code: 02200100 Severity: Critical -- failure or failure imminent. Requested address out of rang e for the Cache Moving Window Termination Code: 02210100 Severity: Critical -- failure or failure imminent. A node was inserted into a li st that already had an overlapping node Termination Code: 03010104 Severity: Critical -- failure or failure imminent. Logic inconsistency detected; one HSV450 controller is suspect. Termination Code: 03020184 Severity: Critical -- failure or failure imminent. Logic inconsistency detected; both HSV450 controllers are suspect.

Termination Code: 03030102 Severity: Critical -- failure or failure imminent. Invalid value in switch state ment. Termination Code: 03040102 Severity: Critical -- failure or failure imminent. The minimum number of quorum disks is no longer accessible. Backend hardware failure, backend configuration p roblems, or HSV450 controller hardware failure are all possible causes. Termination Code: 03060184 Severity: Critical -- failure or failure imminent. An error for which no recover y is possible occurred. Termination Code: 030a0102 Severity: Critical -- failure or failure imminent. Index out of bounds in scsscs db_get_scsdb_ds call. Termination Code: 030b0101 Severity: Critical -- failure or failure imminent. Area offset unknown in scsscs db_get_scsdb_ds call. Termination Code: 030c0100 Severity: Critical -- failure or failure imminent. All SCSDB cache pages in use. Termination Code: 030d0101 Severity: Critical -- failure or failure imminent. scsscsdb_free_scsdb_page cach e inconsistency. Termination Code: 030e0102 Severity: Critical -- failure or failure imminent. Caller believes cache page is dirty and in use, but cache does not. Termination Code: 030f0101 Severity: Critical -- failure or failure imminent. Call to commit SCSDB while ca che page dirty or in use. Termination Code: 03100102 Severity: Critical -- failure or failure imminent. Index out of bounds in scscvm db_get_cvmdb_ds call. Termination Code: 03110101 Severity: Critical -- failure or failure imminent. Area offset unknown in scscvm db_get_cvmdb_ds call. Termination Code: 03120100 Severity: Critical -- failure or failure imminent. All CVMDB cache pages in use. Termination Code: 03130101 Severity: Critical -- failure or failure imminent. scscvmdb_free_cvmdb_page cach e inconsistency. Termination Code: 03140102 Severity: Critical -- failure or failure imminent. Caller believes cache page is dirty and in use, but cache does not. Termination Code: 03150101 Severity: Critical -- failure or failure imminent. Call to commit CVMDB while ca che page dirty or in use.

Termination Code: 03160100 Severity: Critical -- failure or failure imminent. Unable to allocate login maps . Termination Code: 031f0100 Severity: Critical -- failure or failure imminent. Unable to allocate tdsd pool. Termination Code: 032a0000 Severity: Normal -- informational in nature. Both HSV450 controllers registered as Storage System Master. Termination Code: 033c0106 Severity: Critical -- failure or failure imminent. Invalid port login state in r emote port object. Termination Code: 033d0105 Severity: Critical -- failure or failure imminent. Remote port logged_in timer e xpired in inappropriate login state. Termination Code: 03500020 Severity: Normal -- informational in nature. Crash forced by maintenance invoke CRASH or SCS_DEBUG command. Termination Code: 03510141 Severity: Critical -- failure or failure imminent. Crash forced by other HSV450 controller. <UL> <LI>TP[0] contains the reason code for the kill. </UL> Termination Code: 03520144 Severity: Critical -- failure or failure imminent. This controller killed other controller and CPLD_CRASH_ALWAYS set. <UL> <LI>TP[1] contains the reason code for the kill. </UL> Termination Code: 03640021 Severity: Normal -- informational in nature. This HSV450 controller was requeste d to terminate operation and then restart. Termination Code: 03650061 Severity: Normal -- informational in nature. This HSV450 controller was requeste d to terminate operation and then not restart. Termination Code: 03660061 Severity: Normal -- informational in nature. This HSV450 controller was requeste d to terminate operation and then power off. Termination Code: 03670000 Severity: Normal -- informational in nature. This HSV450 controller was requeste d to terminate operation, perform a crash dump and then restart. Termination Code: 03680040 Severity: Normal -- informational in nature. This HSV450 controller was requeste d to terminate operation, perform a crash dump and then not restart. Termination Code: 03690080 Severity: Normal -- informational in nature. Both HSV450 controllers were reques ted to terminate operation, perform a crash dump and then restart.

Termination Code: 036a00c0 Severity: Normal -- informational in nature. Both HSV450 controllers were reques ted to terminate operation, perform a crash dump and then not restart. Termination Code: 036c01c8 Severity: Critical -- failure or failure imminent. This special termination even t is for engineering debug purpose. Termination Code: 036f0061 Severity: Normal -- informational in nature. This HSV450 controller was requeste d to terminate operation, not restart, and indicate its location. Termination Code: 03700022 Severity: Normal -- informational in nature. This HSV450 controller was requeste d to terminate operation in order to recover from a fast failover by remaining i n single controller mode until the failover data in the cache can be completely flushed. Termination Code: 03780101 Severity: Critical -- failure or failure imminent. Unable to realize the CVMDB o r SCSDB during Storage System Master failover. Backend hardware failure, backend configuration problems, or HSV450 controller hardware failure are all possible causes. Termination Code: 03790020 Severity: Normal -- informational in nature. This HSV450 controller is restartin g in order to use a new version of firmware. Termination Code: 0400011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap (i.e., SIMM operand of twi instr uction not a recognized FM_TRAP_TYPE_xxx variant or tw instruction executed). Termination Code: 0401011f Severity: Critical -- failure or failure imminent. Machine Check Interrupt Vecto r Service Routine (MCIVSR) entered; termination processing interrupted before fm _decode_machine_check could be performed. Termination Code: 0402011f Severity: Critical -- failure or failure imminent. DEBUG statement executed. Termination Code: 0403047f Severity: Undetermined -- more information needed to determine severity. Termina tion event is recursive -- i.e., the Termination Event Information contained in multiple recent Termination Events array entries is identical and the terminatio ns occurred within a short interval of time. Termination Code: 04050101 Severity: Critical -- failure or failure imminent. Out of range event data block index encountered in fm_update_scelaba_entry. Termination Code: 0406017f Severity: Critical -- failure or failure imminent. The EDC used to test the vali dity of the Last Termination Event area in nonvolatile memory was bad. Either th e EDC was not updated due to premature termination of post-termination operation s or the memory area was corrupted in an unexplained manner. A power supply inte rnal failure could cause this termination. Note: The in progress event informati on may not describe the event that caused the HSV450 controller to terminate ope ration depending on how far termination processing got before the event occurred

. Termination Code: 0407016a Severity: Critical -- failure or failure imminent. An unexpected event array ent ry indicated that post-termination operations were terminated prematurely before or during the event report block load. Termination Code: 04080582 Severity: Undetermined -- more information needed to determine severity. A last gasp message was received from the other HSV450 controller with the coupled cras h flag set. Termination Code: 040905a2 Severity: Undetermined -- more information needed to determine severity. A last gasp message was received from the other HSV450 controller with the coupled cras h flag set. Termination Code: 040a05c2 Severity: Undetermined -- more information needed to determine severity. A last gasp message was received from the other HSV450 controller with the coupled cras h flag set. Termination Code: 040b05e2 Severity: Undetermined -- more information needed to determine severity. A last gasp message was received from the other HSV450 controller with the coupled cras h flag set. Termination Code: 040c0582 Severity: Undetermined -- more information needed to determine severity. A last gasp message was received from the other HSV450 controller with the coupled cras h flag set and an unrecognized Dump/Restart code. Termination Code: 040d0101 Severity: Critical -- failure or failure imminent. Unrecognized fm_update_scelab a_entry operation code encountered. Termination Code: 040e0100 Severity: Critical -- failure or failure imminent. This HSV450 controller is not the Storage System Master when conditions dictate that it should be. Termination Code: 040f0100 Severity: Critical -- failure or failure imminent. This HSV450 controller is the Storage System Master when conditions dictate that it should not be. Termination Code: 04100182 Severity: Critical -- failure or failure imminent. The Storage System Terminatio n Event Log or Storage System Event Log is not active when conditions dictate th at it should be. Termination Code: 04110181 Severity: Critical -- failure or failure imminent. The Storage System Terminatio n Event Log or Storage System Event Log is inaccessible. Termination Code: 04120123 Severity: Critical -- failure or failure imminent. An invalid entry or an incons istency between entries was found in the Last Termination Event array following a controller resynchronization operation; all entries in the array were reset. Termination Code: 04130107 Severity: Critical -- failure or failure imminent. Structure type is not as expe

cted. Termination Code: 04140104 Severity: Critical -- failure or failure imminent. Event Information Packet type is out of range. Termination Code: 04150104 Severity: Critical -- failure or failure imminent. Event Information Packet size is too big. Termination Code: 04160103 Severity: Critical -- failure or failure imminent. Event Information Packet size is not a longword multiple. Termination Code: 04170107 Severity: Critical -- failure or failure imminent. Invalid Storage System Termin ation Event Log or Storage System Event Log I/O request, no data mapped (unalloc ated) or object is unknown. Termination Code: 04180107 Severity: Critical -- failure or failure imminent. Unrecognized status returned following a Storage System Termination Event Log or Storage System Event Log I/O request. Termination Code: 04190100 Severity: Critical -- failure or failure imminent. The restartdebug routine was invoked without a termination having been performed. Termination Code: 041a0100 Severity: Critical -- failure or failure imminent. The Fault Manager's active qu eue is unexpectedly empty. Termination Code: 041b0105 Severity: Critical -- failure or failure imminent. The Fault Manager detected th at the correct event data block was not cached. Termination Code: 041c0100 Severity: Critical -- failure or failure imminent. Calling process is not the St orage System Management Interface or Host Port SCSI as it should be. Termination Code: 041d0100 Severity: Critical -- failure or failure imminent. Calling process is not the St orage System Management Interface as it should be. Termination Code: 041e0102 Severity: Critical -- failure or failure imminent. Termination Event Information Store Packet content is not as expected. Termination Code: 041f0a1f Severity: Critical -- failure or failure imminent. Either a low memory access vi olation made by the HSV450 controller's software (e.g., access to memory address zero through an uninitialized pointer, etc.) or an uncorrectable memory error w as detected. Termination Code: 0420011f Severity: Critical -- failure or failure imminent. The HSV450 controller inactiv ity watchdog timer expired. Termination Code: 04210107 Severity: Critical -- failure or failure imminent. Drive Broken status returned

following a Storage System Termination Event Log or Storage System Event Log I/O request. Termination Code: 04220102 Severity: Critical -- failure or failure imminent. The Software Component ID spe cified in an Event Code is illegal. Termination Code: 04240960 Severity: Warning -- not failed but attention recommended or required. Power fai led. Termination Code: 043f011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 0, Reserved exception. Termination Code: 0440011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 100, System Reset exception. Termination Code: 0441011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 200, Machine Check exception. Termination Code: 0442011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 300, DSI exc eption (i.e., a data memory access cannot be performed). Termination Code: 0443011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 400, ISI exc eption (i.e., an attempt to fetch the next instruction to be executed failed). Termination Code: 0444011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 500, Externa l Interrupt exception. Termination Code: 0445011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 600, Alignme nt exception (i.e., a memory access cannot be performed because the address alig nment or mode is incompatible for the instruction that was about to be executed) . Termination Code: 0446011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 700, Program exception (i.e., execution of an illegal or privileged instruction was attempte d). Termination Code: 0447011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 800, Floatin g-Point Unavailable exception (i.e., an attempt was made to execute a floating-p oint instruction and the floating-point available bit in the MSR was cleared).

Termination Code: 0448011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 900, Decreme nter exception. Termination Code: 0449011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector A00, Reserve d exception. Termination Code: 044a011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector B00, Reserve d exception. Termination Code: 044b011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector C00, System Call exception. Termination Code: 044c011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector D00, Trace e xception. Termination Code: 044d011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector E00, Floatin g-Point Assist exception. Termination Code: 044e011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector F00, Reserve d exception. Termination Code: 044f011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 1000, Instru ction Translation Miss exception. Termination Code: 0450011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 1100, Data L oad Translation Miss exception. Termination Code: 0451011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 1200, Data S tore Translation Miss exception. Termination Code: 0452011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 1300, Instru ction Address Break exception. Termination Code: 0453011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 1400, System Management exception.

Termination Code: 04540101 Severity: Critical -- failure or failure imminent. Event data block count unexpe cted. Termination Code: 04550101 Severity: Critical -- failure or failure imminent. FM_locate_event_info received unexpected event retrieval status. Termination Code: 04560102 Severity: Critical -- failure or failure imminent. FM_activeq_read_event was una ble to satisfy an active queue event request due to an internal inconsistency. Termination Code: 04570105 Severity: Critical -- failure or failure imminent. A direct call to FM_x_termina te_ctl was made. FM_terminate_ctl_user or FM_terminate_ctl_isr must be used inst ead. Termination Code: 0458011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 1500, Reserv ed exception. Termination Code: 0459011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 1600, Altive c exception. Termination Code: 045a011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 1700, Reserv ed exception. Termination Code: 045b011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 1800, Reserv ed exception. Termination Code: 045c011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 1900, Reserv ed exception. Termination Code: 045d011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 1A00, Reserv ed exception. Termination Code: 045e011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 1B00, Reserv ed exception. Termination Code: 045f011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 1C00, Reserv ed exception. Termination Code: 0460011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 1D00, Reserv

ed exception. Termination Code: 0461011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 1E00, Reserv ed exception. Termination Code: 0462011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 1F00, Reserv ed exception. Termination Code: 0463011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 2000, Reserv ed exception. Termination Code: 0464011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 2100, Reserv ed exception. Termination Code: 0465011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 2200, Reserv ed exception. Termination Code: 0466011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 2300, Reserv ed exception. Termination Code: 0467011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 2400, Reserv ed exception. Termination Code: 0468011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 2500, Reserv ed exception. Termination Code: 0469011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 2600, Reserv ed exception. Termination Code: 046a011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 2700, Reserv ed exception. Termination Code: 046b011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 2800, Reserv ed exception. Termination Code: 046c011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 2900, Reserv

ed exception. Termination Code: 046d011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 2A00, Reserv ed exception. Termination Code: 046e011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 2B00, Reserv ed exception. Termination Code: 046f011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 2C00, Reserv ed exception. Termination Code: 0470011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 2D00, Reserv ed exception. Termination Code: 0471011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 2E00, Reserv ed exception. Termination Code: 0472011f Severity: Critical -- failure or failure imminent. Program Interrupt Vector Serv ice Routine (PIVSR) entered with unhandled trap at Exception Vector 2F00, Reserv ed exception. Termination Code: 04730167 Severity: Critical -- failure or failure imminent. Error encountered while build ing ADDRESS_MAP. Termination Code: 04740160 Severity: Critical -- failure or failure imminent. Fault Manager Event Log Packe t Management Area not allocated. Termination Code: 0476013f Severity: Critical -- failure or failure imminent. The EDC used to test the vali dity of the Last Termination Event area in nonvolatile memory was bad; terminati on processing was completed. Termination Code: 0477013f Severity: Critical -- failure or failure imminent. The EDC used to test the vali dity of the Last Termination Event area in nonvolatile memory was bad; terminati on processing was initiated but not completed. Termination Code: 0478393f Severity: Warning -- not failed but attention recommended or required. The EDC u sed to test the validity of the Last Termination Event area in nonvolatile memor y was bad; termination processing was not initiated, the HSV450 controller's Pow erPC was spontaneously reset. Termination Code: 04790020 Severity: Normal -- informational in nature. The EDC used to test the validity o f the Last Termination Event area in nonvolatile memory was bad; manufacturing f ull memory test was executed.

Termination Code: 047a013f Severity: Critical -- failure or failure imminent. The EDC used to test the vali dity of the Last Termination Event area in nonvolatile memory was bad; unexpecte d termination processing state. Termination Code: 047b0025 Severity: Normal -- informational in nature. The HSV450 controller has been requ ested to be uninitialized by the user. Termination Code: 04810111 Severity: Critical -- failure or failure imminent. The HSV450 controller inactiv ity watchdog timer expired. Termination Code: 04822070 Severity: Critical -- failure or failure imminent. Cache Memory VTT Voltage Fail ure. Termination Code: 04832070 Severity: Critical -- failure or failure imminent. Non-Volatile Cache Memory Vol tage Failure. Termination Code: 04842070 Severity: Critical -- failure or failure imminent. Volatile Cache Memory Voltage Failure. Termination Code: 04852010 Severity: Critical -- failure or failure imminent. PowerPC Bus Data Parity Error . Termination Code: 04862011 Severity: Critical -- failure or failure imminent. PowerPC Bus Address Parity Er ror. Termination Code: 0487390f Severity: Warning -- not failed but attention recommended or required. PowerPC L 1 Instruction Cache Error. Termination Code: 0488390f Severity: Warning -- not failed but attention recommended or required. PowerPC L 1 Data Cache Error. Termination Code: 0489390f Severity: Warning -- not failed but attention recommended or required. PowerPC L 2 Cache Tag Parity or L2 Cache Data Parity Error. Termination Code: 048a2016 Severity: Critical -- failure or failure imminent. Sprite PowerPC Transfer TimeO ut Error. Termination Code: 048b0031 Severity: Normal -- informational in nature. Killed by Other Controller. Termination Code: 048c0026 Severity: Normal -- informational in nature. Software Restart. Termination Code: 048d0026 Severity: Normal -- informational in nature. Button Reset. Termination Code: 048e0115

Severity: Critical -- failure or failure imminent. Atlantis CPU Address Out of R ange Error. Termination Code: 048f2016 Severity: Critical -- failure or failure imminent. Atlantis Transfer Type/Initia l Value Violation Error. Termination Code: 04900115 Severity: Critical -- failure or failure imminent. Atlantis Access to a Protecte d Region Error. Termination Code: 04913916 Severity: Warning -- not failed but attention recommended or required. Atlantis Integrated SRAM Parity Error. Termination Code: 04922016 Severity: Critical -- failure or failure imminent. Uncorrectable Policy Memory E CC Error. Termination Code: 04930113 Severity: Critical -- failure or failure imminent. Atlantis Device Burst Violati on Error. Termination Code: 04942014 Severity: Critical -- failure or failure imminent. Atlantis Device Ready Timeout Error. Termination Code: 04952014 Severity: Critical -- failure or failure imminent. Atlantis Device Address or Da ta Parity Error. Termination Code: 04960113 Severity: Critical -- failure or failure imminent. Atlantis DMA Failure to Decod e Address Error. Termination Code: 04970113 Severity: Critical -- failure or failure imminent. Atlantis DMA Access Protectio n Violation Error. Termination Code: 04980113 Severity: Critical -- failure or failure imminent. Atlantis DMA Write Protect Vi olation Error. Termination Code: 04990113 Severity: Critical -- failure or failure imminent. Atlantis DMA Attempt to Acces s the Descriptor Owned by the CPU. Termination Code: 049a0110 Severity: Critical -- failure or failure imminent. Sprite PowerPC Transfer Timeo ut on PCIX Error. Termination Code: 049b2011 Severity: Critical -- failure or failure imminent. Sprite PowerPC Last Entry Err or. Termination Code: 049c2011 Severity: Critical -- failure or failure imminent. Sprite PowerPC Alignment Erro r. Termination Code: 049d3911

Severity: Warning -- not failed but attention recommended or required. Sprite Qu eue Read Data Parity Error. Termination Code: 049e0110 Severity: Critical -- failure or failure imminent. Sprite PCIX Access Error - No t a 4-Byte Access. Termination Code: 049f2012 Severity: Critical -- failure or failure imminent. Sprite Queue Detected an Inva lid Destination Error. Termination Code: 04a0011c Severity: Critical -- failure or failure imminent. Sprite XOR-DMA - TimeOut Erro r. Termination Code: 04a1011c Severity: Critical -- failure or failure imminent. Sprite XOR-DMA - Start Frame Error. Termination Code: 04a2011c Severity: Critical -- failure or failure imminent. Sprite XOR-DMA - End Frame Er ror. Termination Code: 04a3391d Severity: Warning -- not failed but attention recommended or required. Sprite XO R-DMA - Parity Error. Termination Code: 04a4011c Severity: Critical -- failure or failure imminent. Sprite XOR-DMA - Invalid Opco de Error. Termination Code: 04a5011c Severity: Critical -- failure or failure imminent. Sprite XOR-DMA - Count Error. Termination Code: 04a62012 Severity: Critical -- failure or failure imminent. Sprite Bad Write Data Error. Termination Code: 04a73912 Severity: Warning -- not failed but attention recommended or required. Sprite Co mmand/Data Parity Error. Termination Code: 04a82012 Severity: Critical -- failure or failure imminent. Sprite New Command Bad Error. Termination Code: 04a92017 Severity: Critical -- failure or failure imminent. Uncorrectable Cache Memory EC C Error. Termination Code: 04aa2013 Severity: Critical -- failure or failure imminent. Sprite No Beginning-Of-Frame or Invalid Single Destination Error. Termination Code: 04ab2013 Severity: Critical -- failure or failure imminent. Sprite Transaction Length Mis Match Error. Termination Code: 04ac3913 Severity: Warning -- not failed but attention recommended or required. Sprite Tr ansaction Entry Read Parity Error.

Termination Code: 04ad0112 Severity: Critical -- failure or failure imminent. Sprite Bite-Count (BC) MisMat ch Error (Transaction BC != BC in FIFO). Termination Code: 04ae0112 Severity: Critical -- failure or failure imminent. Sprite Target Retry-Count Exc eeded Error. Termination Code: 04af0112 Severity: Critical -- failure or failure imminent. Sprite Initiator Retry-Count Exceeded Error. Termination Code: 04b00112 Severity: Critical -- failure or failure imminent. Sprite Split-Completion Count Exceeded Error. Termination Code: 04b10112 Severity: Critical -- failure or failure imminent. Sprite Split-Completion Error Message Received Error. Termination Code: 04b20112 Severity: Critical -- failure or failure imminent. Sprite UnExpected Split-Compl etion Error. Termination Code: 04b30112 Severity: Critical -- failure or failure imminent. Sprite Split-Completion Inval id Termination Error. Termination Code: 04b40112 Severity: Critical -- failure or failure imminent. Sprite Split-Completion Witho ut a Previous Split-Response Error. Termination Code: 04b52013 Severity: Critical -- failure or failure imminent. Sprite PCIX PERR Asserted Err or. Termination Code: 04b60113 Severity: Critical -- failure or failure imminent. Sprite performed a Master Abo rt Error. Termination Code: 04b72013 Severity: Critical -- failure or failure imminent. Sprite received a Target Abor t Error. Termination Code: 04b82014 Severity: Critical -- failure or failure imminent. Sprite asserted SERR. Termination Code: 04b92013 Severity: Critical -- failure or failure imminent. Sprite detected SERR. Termination Code: 04ba011c Severity: Critical -- failure or failure imminent. Tachyon Unsupported Byte Enab le Error. Termination Code: 04bb391c Severity: Warning -- not failed but attention recommended or required. Tachyon O utbound Parity Error. Termination Code: 04bc391c Severity: Warning -- not failed but attention recommended or required. Tachyon I

nbound Parity Error. Termination Code: 04bd201d Severity: Critical -- failure or failure imminent. Tachyon Detected Parity Error . Termination Code: 04be201d Severity: Critical -- failure or failure imminent. Tachyon Signaled System Error (SERR). Termination Code: 04bf011c Severity: Critical -- failure or failure imminent. Tachyon Received Master Abort Error. Termination Code: 04c0201d Severity: Critical -- failure or failure imminent. Tachyon Received Target Abort Error. Termination Code: 04c1201d Severity: Critical -- failure or failure imminent. Tachyon Signaled Target Abort Error. Termination Code: 04c2201d Severity: Critical -- failure or failure imminent. Tachyon Master Data Parity Er ror. Termination Code: 04c3011c Severity: Critical -- failure or failure imminent. Tachyon Unexpected Split-Comp letion Error. Termination Code: 04c4011c Severity: Critical -- failure or failure imminent. Tachyon Split-Completion Disc arded Error. Termination Code: 04c5391d Severity: Warning -- not failed but attention recommended or required. Tachyon P arity Error on Split Related Transaction. Termination Code: 04c6391d Severity: Warning -- not failed but attention recommended or required. Tachyon P arity Error on Incoming Data. Termination Code: 04c7391d Severity: Warning -- not failed but attention recommended or required. Tachyon P arity Error on Outgoing Data. Termination Code: 04c8201d Severity: Critical -- failure or failure imminent. Tachyon Attribute Parity Erro r. Termination Code: 04c9011c Severity: Critical -- failure or failure imminent. Tachyon Split-Completion Byte Count Excessive. Termination Code: 04ca011c Severity: Critical -- failure or failure imminent. Tachyon Read Byte Count Exces sive Error. Termination Code: 04cb011c Severity: Critical -- failure or failure imminent. Tachyon Read FIFO Parity Erro

r. Termination Code: 04cc011c Severity: Critical -- failure or failure imminent. Tachyon Write FIFO Parity Err or. Termination Code: 04cd011c Severity: Critical -- failure or failure imminent. Tachyon Reserved Region Acces s Error. Termination Code: 04ce010e Severity: Critical -- failure or failure imminent. Tachyon Parity Error on Split Completion Error. Termination Code: 04cf011b Severity: Critical -- failure or failure imminent. Undecoded machine check. Termination Code: 04d00180 Severity: Critical -- failure or failure imminent. Manufacturing Event Analysis Log Commit Packet unexpectedly in use. Termination Code: 04e2096a Severity: Warning -- not failed but attention recommended or required. Power fai led and was detected by the Offload PIC auxiliary processor. Termination Code: 04e3096a Severity: Warning -- not failed but attention recommended or required. The HSV45 0 controller was removed and detected by the Offload PIC auxiliary processor. Termination Code: 04e4096a Severity: Warning -- not failed but attention recommended or required. The syste m watchdog timer expired and was detected by the Offload PIC auxiliary processor . Termination Code: 04e5096a Severity: Warning -- not failed but attention recommended or required. An unknow n or unexpected event was detected and logged by the Offload PIC auxiliary proce ssor. Termination Code: 04e80100 Severity: Critical -- failure or failure imminent. The Sprite FPGA has failed ch ecksum verification. Termination Code: 04f6013f Severity: Critical -- failure or failure imminent. User termination test all par ameters. Termination Code: 04f70000 Severity: Normal -- informational in nature. Console requested restart with dump (not coupled) via CTRL-Z. Termination Code: 04f9017f Severity: Critical -- failure or failure imminent. Poweroff test. Termination Code: 04fa0100 Severity: Critical -- failure or failure imminent. User termination test no para meters. Termination Code: 04fb011f Severity: Critical -- failure or failure imminent. User termination test all par

ameters. Termination Code: 04fc0100 Severity: Critical -- failure or failure imminent. ISR termination test no param eters. Termination Code: 04fd011f Severity: Critical -- failure or failure imminent. ISR termination test all para meters. Termination Code: 04fe0100 Severity: Critical -- failure or failure imminent. Function not yet implemented. Termination Code: 04ff011f Severity: Critical -- failure or failure imminent. EXEC_BUGCHECK statement execu ted. Termination Code: 06040100 Severity: Critical -- failure or failure imminent. Failed memory allocation for SFQ. Termination Code: 06150100 Severity: Critical -- failure or failure imminent. Failed memory allocation for Fibre Channel Services Crash Dump structure. Termination Code: 061c0100 Severity: Critical -- failure or failure imminent. Failed memory allocation for IBQ. Termination Code: 06280100 Severity: Critical -- failure or failure imminent. Invalid Port Event Type. Termination Code: 06290100 Severity: Critical -- failure or failure imminent. Unknown FED type found. Termination Code: 062a0100 Severity: Critical -- failure or failure imminent. Unknown FED found during Link Down cleanup. Termination Code: 062b0100 Severity: Critical -- failure or failure imminent. Fail status returned for time r start. Termination Code: 062c0100 Severity: Critical -- failure or failure imminent. Unexpected loop state. Termination Code: 062f0100 Severity: Critical -- failure or failure imminent. SEST programming error. Termination Code: 06320100 Severity: Critical -- failure or failure imminent. Port chip failed to go Offlin e. Termination Code: 06330100 Severity: Critical -- failure or failure imminent. Out of Reserved FEDs. Termination Code: 06340100 Severity: Critical -- failure or failure imminent. Unsupported ELS requested. Termination Code: 06360100

Severity: Critical -- failure or failure imminent. Unsupported drive initializat ion sequence command. Termination Code: 063c0100 Severity: Critical -- failure or failure imminent. Command issued to an illegal LBA. Termination Code: 06480100 Severity: Critical -- failure or failure imminent. Failed memory allocation for Enclosure Management Request. Termination Code: 065a010e Severity: Critical -- failure or failure imminent. PMC-Sierra TSDK FC layer fail ed ASSERT. Termination Code: 07000100 Severity: Critical -- failure or failure imminent. Initialization failed due to insufficient memory. Termination Code: 07010100 Severity: Critical -- failure or failure imminent. LMAP allocation failed. Termination Code: 07020100 Severity: Critical -- failure or failure imminent. LMAP allocation failed. Termination Code: 07030100 Severity: Critical -- failure or failure imminent. Invalid RAID type. Termination Code: 07070100 Severity: Critical -- failure or failure imminent. Failed reading QS. Termination Code: 070a0100 Severity: Critical -- failure or failure imminent. RSD allocation failed. Termination Code: 070b0100 Severity: Critical -- failure or failure imminent. LDSB ref_count is off Termination Code: 070c0100 Severity: Critical -- failure or failure imminent. Invalid Object Class for I/O request. Termination Code: 070d0100 Severity: Critical -- failure or failure imminent. Invalid I/O range for given o bject. Termination Code: 07130100 Severity: Critical -- failure or failure imminent. Invalid RAID type. Termination Code: 07150100 Severity: Critical -- failure or failure imminent. Invalid structure - Zero proc ess. Termination Code: 07160100 Severity: Critical -- failure or failure imminent. Invalid structure - ODWORK p rocess. Termination Code: 07170100 Severity: Critical -- failure or failure imminent. Program buffer leak detected. Termination Code: 07190100

Severity: Critical -- failure or failure imminent. Code not yet implemented. Termination Code: 071a0102 Severity: Critical -- failure or failure imminent. Wrong LDSB returned to waitin g abort requester. Termination Code: 071b0100 Severity: Critical -- failure or failure imminent. Wrong LDAD returned to waitin g abort requester. Termination Code: 071c0100 Severity: Critical -- failure or failure imminent. Bad map type for read merge. Termination Code: 071d0100 Severity: Critical -- failure or failure imminent. Cache hit occurred while perf orming read merge. Termination Code: 071e0100 Severity: Critical -- failure or failure imminent. PSAR indicates invalid usage. Termination Code: 071f0100 Severity: Critical -- failure or failure imminent. Bad object class in Regen/Rep lace. Termination Code: 07200100 Severity: Critical -- failure or failure imminent. No Free CMAPs. Termination Code: 07220100 Severity: Critical -- failure or failure imminent. Invalid CS Drive Request. Termination Code: 07240100 Severity: Critical -- failure or failure imminent. No Free CS Req items. Termination Code: 07260100 Severity: Critical -- failure or failure imminent. Invalid Volnoid encountered. Termination Code: 072a0100 Severity: Critical -- failure or failure imminent. I/O Failed in CS_recover_tran sactions. Termination Code: 072b0100 Severity: Critical -- failure or failure imminent. Invalid Transaction type. Termination Code: 072d0100 Severity: Critical -- failure or failure imminent. No Transaction was found. Termination Code: 072f0100 Severity: Critical -- failure or failure imminent. Member State not supported in zero_rsdm. Termination Code: 07300100 Severity: Critical -- failure or failure imminent. Regen of Member should be com plete, but is not. Termination Code: 07340100 Severity: Critical -- failure or failure imminent. Bad CS Req Object Class in ha ndle CS Req. Termination Code: 07350100 Severity: Critical -- failure or failure imminent. Invalid CS Req Operation in h

andle CS Req. Termination Code: 07370100 Severity: Critical -- failure or failure imminent. Invalid Volnoid in Sparing Pr ocess. Termination Code: 07380100 Severity: Critical -- failure or failure imminent. No XDs available for cs_req o peration Termination Code: 07390100 Severity: Critical -- failure or failure imminent. Invalid Raid Type in Regen/Re assign. Termination Code: 073b0100 Severity: Critical -- failure or failure imminent. Unknown CS Transaction type f or Journaling. Termination Code: 073c0100 Severity: Critical -- failure or failure imminent. CS Journal Transaction incons istency. Termination Code: 073e0100 Severity: Critical -- failure or failure imminent. Invalid structure - LD Level ing process. Termination Code: 073f0100 Severity: Critical -- failure or failure imminent. Invalid structure - RStore S paring process. Termination Code: 07400100 Severity: Critical -- failure or failure imminent. Invalid structure - CS Req p rocess. Termination Code: 07410100 Severity: Critical -- failure or failure imminent. Invalid structure - PLDMC pr ocess. Termination Code: 07420100 Severity: Critical -- failure or failure imminent. No Free RLBs (RSD Lock Blocks ). Termination Code: 07430100 Severity: Critical -- failure or failure imminent. RLB List is inconsistent. Termination Code: 07440100 Severity: Critical -- failure or failure imminent. RLB state is inconsistent. Termination Code: 07450100 Severity: Critical -- failure or failure imminent. Invalid structure - CS CSLD process. Termination Code: 07460100 Severity: Critical -- failure or failure imminent. Invalid structure - CS E-bit handler. Termination Code: 07480100 Severity: Critical -- failure or failure imminent. Illegal QS I/O by Non Storage System Master.

Termination Code: 07490100 Severity: Critical -- failure or failure imminent. Illegal CSLD I/O by Non Stora ge System Master. Termination Code: 074a0100 Severity: Critical -- failure or failure imminent. Invalid structure - ACBW pro cess. Termination Code: 074b0100 Severity: Critical -- failure or failure imminent. Invalid ACBW Opcode. Termination Code: 074c0100 Severity: Critical -- failure or failure imminent. Invalid structure - Unsharing process. Termination Code: 074f0100 Severity: Critical -- failure or failure imminent. Invalid structure - RSS Migr ation process. Termination Code: 07500100 Severity: Critical -- failure or failure imminent. Invalid structure - RStore M igration process. Termination Code: 07510100 Severity: Critical -- failure or failure imminent. Member State not supported. Termination Code: 07520100 Severity: Critical -- failure or failure imminent. Metadata is inaccessible; an inoperative condition has occurred. Termination Code: 07530100 Severity: Critical -- failure or failure imminent. An invalid structure was enco untered on an ALB list. Termination Code: 07540114 Severity: Critical -- failure or failure imminent. LMAP does not point to RStore , and RStore not being allocated. Termination Code: 07550100 Severity: Critical -- failure or failure imminent. Invalid structure - LD Alloc ation work process. Termination Code: 07570100 Severity: Critical -- failure or failure imminent. Realize or realize_temp faile d. Termination Code: 07580100 Severity: Critical -- failure or failure imminent. Unrealize or unrealize_temp f ailed. Termination Code: 075a0100 Severity: Critical -- failure or failure imminent. Force a crash for testing pur poses. Termination Code: 075b0104 Severity: Critical -- failure or failure imminent. Metadata I/O failed. Termination Code: 075d0100 Severity: Critical -- failure or failure imminent. Invalid structure - CS C-bit handler.

Termination Code: 075e0100 Severity: Critical -- failure or failure imminent. Invalid structure - OD bg alo c process. Termination Code: 075f0100 Severity: Critical -- failure or failure imminent. DUB and RSS do not agree with each other. Termination Code: 07600100 Severity: Critical -- failure or failure imminent. Invalid LD type Termination Code: 07610100 Severity: Critical -- failure or failure imminent. Invalid DIP State in LD Termination Code: 07620100 Severity: Critical -- failure or failure imminent. Deallocation failed Termination Code: 07630100 Severity: Critical -- failure or failure imminent. Failure to validate reserved capacity on each rss member Termination Code: 07640100 Severity: Critical -- failure or failure imminent. Invalid structure - REBUILD PARITY MAIN Termination Code: 07650100 Severity: Critical -- failure or failure imminent. An unexpected status was retu rned to the caller Termination Code: 07680100 Severity: Critical -- failure or failure imminent. An RSS member has been remove d unexpectedly. Termination Code: 07690102 Severity: Critical -- failure or failure imminent. An unsupported member manager state has occurred. Termination Code: 076a0100 Severity: Critical -- failure or failure imminent. No Quorum Disks have been dis covered. Termination Code: 076b0100 Severity: Critical -- failure or failure imminent. Invalid/unknown pseg allocati on type Termination Code: 076c0100 Severity: Critical -- failure or failure imminent. XMFC Failure - other controll er gone during communication with it. Termination Code: 076d0100 Severity: Critical -- failure or failure imminent. Invalid XMFC operation. Termination Code: 07700105 Severity: Critical -- failure or failure imminent. CHKDSK test failed Termination Code: 07710100 Severity: Critical -- failure or failure imminent. Invalid structure - Unsharing process.

Termination Code: 07720100 Severity: Critical -- failure or failure imminent. Invalid structure - Unsharing process. Termination Code: 07730100 Severity: Critical -- failure or failure imminent. The RSD pointer should have b een NULL but wasn't Termination Code: 0775011a Severity: Critical -- failure or failure imminent. The LD should have not been r ealized but was Termination Code: 07760120 Severity: Critical -- failure or failure imminent. Force a crash for testing pur poses without an ILF dump. Termination Code: 08010100 Severity: Critical -- failure or failure imminent. Bad status from CS_SET_EBIT Termination Code: 08020100 Severity: Critical -- failure or failure imminent. An abnormal member's member_s tate is not supported Termination Code: 08030100 Severity: Critical -- failure or failure imminent. A request was made to do I/O for an undefined RAID type. Termination Code: 08040100 Severity: Critical -- failure or failure imminent. Drive rewrite function is not supported Termination Code: 08070100 Severity: Critical -- failure or failure imminent. Cannot dynamically allocate e nough memory to store waiters for ptr 9687 fix. Termination Code: 08080100 Severity: Critical -- failure or failure imminent. Unsupported structure type pa ssed into RS function Termination Code: 08110120 Severity: Critical -- failure or failure imminent. Force a crash for testing pur poses without an ILF dump. Termination Code: 09010100 Severity: Critical -- failure or failure imminent. EXEC_init_bque failed. Termination Code: 09040100 Severity: Critical -- failure or failure imminent. Storage System Management Int erface detected an internal inconsistency. Termination Code: 09060100 Severity: Critical -- failure or failure imminent. Memory allocation failed for return buffer. Termination Code: 09080100 Severity: Critical -- failure or failure imminent. Insufficient resources availa ble for SCMI Command Lock dynamic allocation. Termination Code: 09090100 Severity: Critical -- failure or failure imminent. Insufficient resources availa

ble for SCMI Command Lock initial allocation. Termination Code: 0b000100 Severity: Critical -- failure or failure imminent. Invalid XMFC Response Packet. Termination Code: 0b010100 Severity: Critical -- failure or failure imminent. Invalid MFC Vector (Index). Termination Code: 0b020100 Severity: Critical -- failure or failure imminent. Invalid System Activity Colle ction state. Termination Code: 0b040100 Severity: Critical -- failure or failure imminent. Invalid System Utility (Code Load or Resynchronization) state. Termination Code: 0b052001 Severity: Critical -- failure or failure imminent. Attempt to access EEPROM for UUID Range failed. Termination Code: 0b062001 Severity: Critical -- failure or failure imminent. UUID Range overflow. Termination Code: 0b080100 Severity: Critical -- failure or failure imminent. A resynchronization was reque sted at an inappropriate time. Termination Code: 0b092003 Severity: Critical -- failure or failure imminent. Attempt to access Operator Co ntrol Panel failed. Termination Code: 0b0a0100 Severity: Critical -- failure or failure imminent. Invalid XMFC State. Termination Code: 0b0f0122 Severity: Critical -- failure or failure imminent. File is larger than predefine d code load buffer. Termination Code: 0b100021 Severity: Normal -- informational in nature. New glue code available, attempting a force load which requires a restart after the load is successful. Termination Code: 0b110020 Severity: Normal -- informational in nature. New boot code available, attempting a force load following restart. Termination Code: 0b130021 Severity: Normal -- informational in nature. New sprite code available, attempti ng a force load which requires a restart after the load is successful. Termination Code: 0b140021 Severity: Normal -- informational in nature. New glue and sprite code available, attempting a force load which requires two back to back restarts, one for each image. One successful load flowing into the next load. Glue first then sprite. Termination Code: 0b150020 Severity: Normal -- informational in nature. Allow optional parts to be loaded d uring this resync/restart because the slave controller has not yet joined the sc ell.

Termination Code: 0b16f060 Severity: Warning -- not failed but attention recommended or required. Attempt t o load code that can not handle single rank dimms on a controller with single ra nk dimms installed. Please upgrade to code that is capable of supporting single rank dimms. Termination Code: 0c010102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger Dual State was found while processing an ACK for a dual controller managemen t command. Termination Code: 0c03010e Severity: Critical -- failure or failure imminent. Invalid state exists for dele ting a Group State Block. Termination Code: 0c040101 Severity: Critical -- failure or failure imminent. A software problem was found in processing a recovery write upon controller start or failover: The group sequ ence number node already exists. Termination Code: 0c050106 Severity: Critical -- failure or failure imminent. A software problem was found in processing a recovery write upon controller start or failover: The recovery w rite data was not in cache as expected. Termination Code: 0c060106 Severity: Critical -- failure or failure imminent. A software problem was found in processing a recovery write upon controller start or failover: The recovery w rite data found in cache was not marked dirty write-back cached data as expected . Termination Code: 0c070106 Severity: Critical -- failure or failure imminent. A software problem was found in processing a recovery write upon controller start or failover: Lookup of grou p sequence number node failed. Termination Code: 0c080106 Severity: Critical -- failure or failure imminent. A software problem was found in cleaning Data Replication Manager context in the mirror cache when the mirror was declared invalid: A recovery write was found, but its associated RIE was no t marked free as expected. Termination Code: 0c090106 Severity: Critical -- failure or failure imminent. A software problem was found in cleaning Data Replication Manager context in the mirror cache when the mirror was declared invalid: Not all group members were processed. Termination Code: 0c0a0106 Severity: Critical -- failure or failure imminent. A software problem was found in cleaning Data Replication Manager context in the primary cache when the prima ry was declared invalid: A recovery write was found, but its associated RIE was not marked free as expected. Termination Code: 0c0b0106 Severity: Critical -- failure or failure imminent. A software problem was found in cleaning Data Replication Manager context in the primary cache when the prima ry was declared invalid: Not all group members were processed. Termination Code: 0c0c0104 Severity: Critical -- failure or failure imminent. A software problem was found

when deleting the Group State Block: Transfers were not completely run down. Termination Code: 0c0d0104 Severity: Critical -- failure or failure imminent. A software problem was found when inserting a Group State Block into the active list: A Group State Block wit h this same Universal Unique Identifier is already on the active list. Termination Code: 0c0e0106 Severity: Critical -- failure or failure imminent. A group sequence number out o f order was detected in the transfer path upon remote write completion after the mirror controller was updated; A Full Copy of the affected Data Replication Gro up may be initiated upon the next controller restart. Termination Code: 0c0f0105 Severity: Critical -- failure or failure imminent. Setting the e-bit failed for a write long command on the destination unit. Termination Code: 0c110105 Severity: Critical -- failure or failure imminent. A Group Sequence Number Node was lost during mirror synchronization. Termination Code: 0c130105 Severity: Critical -- failure or failure imminent. An unexpected I/O failure occ urred: Container Services was unable to write to the PLDMC on media. Termination Code: 0c140106 Severity: Critical -- failure or failure imminent. A group sequence number out o f order was detected in the transfer path on the mirror side upon remote write c ompletion; A Full Copy of the affected Data Replication Group may be initiated u pon controller restart. Termination Code: 0c150106 Severity: Critical -- failure or failure imminent. A group sequence number out o f order was detected upon controller restart or failover when building the list of incomplete writes; A Full Copy of the affected Data Replication Group may be initiated upon controller restart. Termination Code: 0c160106 Severity: Critical -- failure or failure imminent. A group sequence number out o f order was detected upon controller restart or failover when completing previou sly incomplete writes; A Full Copy of the affected Data Replication Group may be initiated upon controller restart. Termination Code: 0c170106 Severity: Critical -- failure or failure imminent. A group sequence number out o f order with the received group sequence number was detected after a controller restarted, when synchonizing the group sequence numbers with the mirror side; A Full Copy of the affected Data Replication Group may be initiated upon controlle r restart. Termination Code: 0c180106 Severity: Critical -- failure or failure imminent. A group sequence number out o f order with the use and sent group sequence numbers was detected after a contro ller restarted, when synchronizing the group sequence numbers with the mirror si de; A Full Copy of the affected Data Replication Group may be initiated upon con troller restart. Termination Code: 0c190106 Severity: Critical -- failure or failure imminent. A group sequence number out o f order with the received group sequence number was detected after a controller

restarted, when synchronizing the group sequence numbers with the primary side; A Full Copy of the affected Data Replication Group may be initiated upon control ler restart. Termination Code: 0c1a0106 Severity: Critical -- failure or failure imminent. A group sequence number out o f order with the use and sent group sequence number was detected after a control ler restart, when synchronizing the group sequence numbers with the primary side ; A Full Copy of the affected Data Replication Group may be initiated upon contr oller restart. Termination Code: 0c1b0106 Severity: Critical -- failure or failure imminent. A group sequence number out o f order with the use group sequence number was detected after a controller resta rt, when synchronizing the group sequence numbers with the primary side; A Full Copy of the affected Data Replication Group may be initiated upon controller res tart. Termination Code: 0c1c0107 Severity: Critical -- failure or failure imminent. A group sequence number out o f order was detected after a controller restart when synchronizing the mirror wr ites with the primary side; A Full Copy of the affected Data Replication Group m ay be initiated upon controller restart. Termination Code: 0c200106 Severity: Critical -- failure or failure imminent. A group sequence number out o f order with the use group sequence number was detected after a controller resta rt, when synchronizing the group sequence numbers with the primary side; A Full Copy of the affected Data Replication Group may be initiated upon controller res tart. Termination Code: 0c210113 Severity: Critical -- failure or failure imminent. A group sequence number out o f order with the use group sequence number was detected to be too high; A Full C opy of the affected Data Replication Group may be initiated upon controller rest art. Termination Code: 0c220108 Severity: Critical -- failure or failure imminent. A group sequence number out o f order with the use group sequence number was detected to be too low; A Full Co py of the affected Data Replication Group may be initiated upon controller resta rt. Termination Code: 0c230108 Severity: Critical -- failure or failure imminent. A Data Replication Group memb er was detected to be in an unexpected cache state. Termination Code: 0c240107 Severity: Critical -- failure or failure imminent. Secondary controller selectio n failed. Termination Code: 0c270106 Severity: Critical -- failure or failure imminent. A group sequence number out o f order with the use group sequence number was detected to be too low. A Full Co py of the affected Data Replication Group may be initiated upon controller resta rt. Termination Code: 0c280106 Severity: Critical -- failure or failure imminent. A group sequence number out o f order with the use group sequence number was detected to be too low. A Full Co

py of the affected Data Replication Group may be initiated upon controller resta rt. Termination Code: 0c290105 Severity: Critical -- failure or failure imminent. Data Replication Manager Dual State was not idle for MFC communication between the dual controllers during an add member operation. Termination Code: 0c2a0106 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger Dual State was found while processing an ACK for a dual controller managemen t ADD SOURCE command. Termination Code: 0c2b0102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger Dual State was found while processing an ACK for a dual controller managemen t command when a process is waiting for the ACK. Termination Code: 0c2c0102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger Dual State was found while processing an ACK for a dual controller managemen t command when a process is waiting for a DONE response. Termination Code: 0c2d0105 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger Dual State was found while creating an ADD SOURCE dual controller management command. Termination Code: 0c2e0105 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger Dual State was found while creating an SITE FAILOVER dual controller managem ent command. Termination Code: 0c2f0106 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger Dual State was found while processing an ACK for a dual controller managemen t command requiring a DRRW response. Termination Code: 0c300105 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger Dual State was found while creating a multi-destinaton dual controller manag ement command. Termination Code: 0c310105 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger Dual State was found while creating a dual controller management command tha t has only an ACK as a response and passes a group object as a parameter. Termination Code: 0c320101 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger Dual State was found in the main dispatch function for dual controller manag ement commands. Termination Code: 0c330103 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger Dual State was found in the main processing function for dual controller man agement commands. Termination Code: 0c360102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana

ger Dual State was found while issuing a simple dual controller management comma nd. Termination Code: 0c370102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger Dual State was found while processing the response to a simple dual controll er management command. Termination Code: 0c380102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger Dual State was found while building a simple dual controller management comm and. Termination Code: 0c390102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger Dual State was found while building a dual controller management command whi ch uses an SCVD object. Termination Code: 0c3a0102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger Dual State was found while processing an ACK for a unit related dual control ler management command that does not require an additional response. Termination Code: 0c3b0102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger Dual State was found while processing an ACK for a unit related dual control ler management command that requires an additional response. Termination Code: 0c410102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger Dual State was found while initiating a site failover. Termination Code: 0c420102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger Dual State was found while processing an ACK for a dual controller managemen t synchronize buffers command. Termination Code: 0c430102 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger Dual State was found while processing an ACK for a dual controller managemen t MDW command. Termination Code: 0c450100 Severity: Critical -- failure or failure imminent. We should not have gone down this path. Termination Code: 0c460103 Severity: Critical -- failure or failure imminent. MFC frame corruption detected . Termination Code: 0c480100 Severity: Critical -- failure or failure imminent. Insufficient free memory avai lable to allocate required DDCB structures. Termination Code: 0c490100 Severity: Critical -- failure or failure imminent. Insufficient free memory avai lable to allocate required RNSB structures. Termination Code: 0c4b0100 Severity: Critical -- failure or failure imminent. Insufficient free memory avai

lable to allocate required Data Replication Manager Discovery structures. Termination Code: 0c4c0100 Severity: Critical -- failure or failure imminent. Invalid DRM MFC Vector (Index ). Termination Code: 0c4d0100 Severity: Critical -- failure or failure imminent. Invalid Data Replication Mana ger RXMFC Response Packet. Termination Code: 0c4e0106 Severity: Critical -- failure or failure imminent. Invalid RNSB pointer detected in DDCB. Termination Code: 0c4f0101 Severity: Critical -- failure or failure imminent. Insufficient free memory avai lable to allocate required Data Replication Manager communications structures. Termination Code: 0c500106 Severity: Critical -- failure or failure imminent. A group sequence number for a write command that has already completed has been received. A Full Copy of the affected Data Replication Group may be initiated upon controller restart. Termination Code: 0e000020 Severity: Normal -- informational in nature. Found invalid battery subsystem sta te. Termination Code: 0e010020 Severity: Normal -- informational in nature. Found invalid battery system hold u p time. Termination Code: 0e020020 Severity: Normal -- informational in nature. Found invalid battery brick number. Termination Code: 0e030020 Severity: Normal -- informational in nature. Found invalid battery brick state. Termination Code: 0e050020 Severity: Normal -- informational in nature. Found invalid blower number. Termination Code: 0e060020 Severity: Normal -- informational in nature. Found invalid blower state. Termination Code: 0e080020 Severity: Normal -- informational in nature. Found invalid temperature subsystem state. Termination Code: 0e090020 Severity: Normal -- informational in nature. Found invalid power supply number. Termination Code: 0e0a0020 Severity: Normal -- informational in nature. Found invalid power supply state. Termination Code: 0e0b0020 Severity: Normal -- informational in nature. A command was sent to the SDC micro controller while it was still busy processing a previous command. Termination Code: 0f000100 Severity: Critical -- failure or failure imminent. A DMA transaction completed w ith an interrupt but the DMA context queue was empty.

Termination Code: 0f010101 Severity: Critical -- failure or failure imminent. The DMA context queue is out of sync with interrupts. Termination Code: 0f020100 Severity: Critical -- failure or failure imminent. Unable to save DMA context be cause the queue is full. Termination Code: 0f100100 Severity: Critical -- failure or failure imminent. A DMA transaction followed an unsupported code path. Termination Code: 0f110100 Severity: Critical -- failure or failure imminent. A call to EXEC_allocate retur ned a NULL pointer. Termination Code: 0f150102 Severity: Critical -- failure or failure imminent. Target Read Entry header addr ess bad. Termination Code: 0f160101 Severity: Critical -- failure or failure imminent. Unknown FED type found. Termination Code: 0f170100 Severity: Critical -- failure or failure imminent. Fail status returned for time r start. Termination Code: 0f18011f Severity: Critical -- failure or failure imminent. FED for handling MFC ACK was not on the In-process Queue as expected. Termination Code: 0f190100 Severity: Critical -- failure or failure imminent. Failed memory allocation for MFC copy buffer. Termination Code: 0f1a0100 Severity: Critical -- failure or failure imminent. Failed memory allocation for SFQ. Termination Code: 0f1b0100 Severity: Critical -- failure or failure imminent. Failed memory allocation for ELSDs. Termination Code: 0f1e0100 Severity: Critical -- failure or failure imminent. Failed memory allocation for IBQ. Termination Code: 0f1f0101 Severity: Critical -- failure or failure imminent. Invalid Port Event Type. Termination Code: 0f200100 Severity: Critical -- failure or failure imminent. Out of Reserved FEDs. Termination Code: 0f210100 Severity: Critical -- failure or failure imminent. Invalid Completion Message ty pe. Termination Code: 0f220100 Severity: Critical -- failure or failure imminent. SEST programming error.

Termination Code: 0f230100 Severity: Critical -- failure or failure imminent. Class 2 Failure for outbound sequence. Termination Code: 0f24011f Severity: Critical -- failure or failure imminent. Host Programming error. Termination Code: 0f250080 Severity: Normal -- informational in nature. Remote couple crash requested. Termination Code: 0f260100 Severity: Critical -- failure or failure imminent. Unsupported ELS requested. Termination Code: 0f270100 Severity: Critical -- failure or failure imminent. Sprite returned an error that we don't know how to handle yet Termination Code: 0f280100 Severity: Critical -- failure or failure imminent. Sprite CDB memory has been co rrupted Termination Code: 0f290101 Severity: Critical -- failure or failure imminent. Unknown FED found during Link Down cleanup. Termination Code: 0f2b0100 Severity: Critical -- failure or failure imminent. Unexpected loop state. Termination Code: 0f2c0100 Severity: Critical -- failure or failure imminent. Unknown exchange type found. Termination Code: 0f2d0106 Severity: Critical -- failure or failure imminent. Invalid port login state in r emote port object. Termination Code: 0f2e0105 Severity: Critical -- failure or failure imminent. Remote port logged_in timer e xpired in inappropriate login state. Termination Code: 0f2f0dc6 Severity: Critical -- failure or failure imminent. The two controllers do not ha ve matching Cache or Policy memory configurations. Replace a controller so that both controllers match. Termination Code: 42000101 Severity: Critical -- failure or failure imminent. No memory for HP_init. Termination Code: 42050103 Severity: Critical -- failure or failure imminent. Unexpected Cache Node lock st ate for WRITE LONG. Termination Code: 42060105 Severity: Critical -- failure or failure imminent. Unexpected outstanding SCSI c ommand on unit. Termination Code: 42070123 Severity: Critical -- failure or failure imminent. DD CDB function 0X42 received .

Termination Code: 420801a3 Severity: Critical -- failure or failure imminent. DD CDB function 0X43 received . Termination Code: 420901c3 Severity: Critical -- failure or failure imminent. DD CDB function 0X86 received . Termination Code: 420c0184 Severity: Critical -- failure or failure imminent. Unknown build context receive d in remote SCSI MFC build routine. Termination Code: 420d0182 Severity: Critical -- failure or failure imminent. Unknown context received in r emote SCSI MFC receive routine. Termination Code: 420e0181 Severity: Critical -- failure or failure imminent. ICOPS could not allocate nece ssary memory. Termination Code: 420f0182 Severity: Critical -- failure or failure imminent. Unknown build context in the ICOPS build routine. Termination Code: 42100182 Severity: Critical -- failure or failure imminent. Unknown receive context in th e ICOPS receive routine. Termination Code: 42120104 Severity: Critical -- failure or failure imminent. Illegal structure on in proce ss queue. Termination Code: 42130101 Severity: Critical -- failure or failure imminent. No host port command HTBs. Termination Code: 42140102 Severity: Critical -- failure or failure imminent. Invalid Context in hp_call_ge t_scsi_data. Termination Code: 42150102 Severity: Critical -- failure or failure imminent. HP_change_host_mode ACB-- not found. Termination Code: 42160102 Severity: Critical -- failure or failure imminent. HP_present_lun-- ACB not foun d. Termination Code: 42190104 Severity: Critical -- failure or failure imminent. CCB either already in use or improperly marked not used. Termination Code: 421a0183 Severity: Critical -- failure or failure imminent. An HTB has an invalid NULL fl ow value. Termination Code: 421b0102 Severity: Critical -- failure or failure imminent. A work request has an invalid type. Termination Code: 421c0101

Severity: Critical -- failure or failure imminent. Work request resources have r un out. Termination Code: 421e0102 Severity: Critical -- failure or failure imminent. Allocated command HTB is alre ady in use. Termination Code: 42230102 Severity: Critical -- failure or failure imminent. HP_unpresent_lun ACB not foun d. Termination Code: 42250104 Severity: Critical -- failure or failure imminent. Could not delete the ACB. Termination Code: 42260104 Severity: Critical -- failure or failure imminent. Did not have a Unit Attention table and units are presented. Termination Code: 42270108 Severity: Critical -- failure or failure imminent. Port event handler had an unk nown port event. Termination Code: 42280102 Severity: Critical -- failure or failure imminent. Unknown completion message fr om the Tachyon. Termination Code: 42290103 Severity: Critical -- failure or failure imminent. Received an illegal SEST id. Termination Code: 422c0003 Severity: Normal -- informational in nature. Received an unknown error idle stat us from the Tachyon. Termination Code: 422d010a Severity: Critical -- failure or failure imminent. Received an unknown I/O error value. Termination Code: 422e0104 Severity: Critical -- failure or failure imminent. Had a LUN with write only acc ess. Termination Code: 422f0103 Severity: Critical -- failure or failure imminent. Received an unknown FCP inbou nd completion status. Termination Code: 42300103 Severity: Critical -- failure or failure imminent. Received an illegal script re sponse. Termination Code: 42310102 Severity: Critical -- failure or failure imminent. Received an illegal error sta tus in the error routine. Termination Code: 42320104 Severity: Critical -- failure or failure imminent. Requested to present a LUN th at is already in existence or is illegal Termination Code: 4233010a Severity: Critical -- failure or failure imminent. An internal request was made to return a status of Not Ready for work created in the controller.

Termination Code: 42340104 Severity: Critical -- failure or failure imminent. The state for a command with the Immed bit set in the CDB is incorrect. Termination Code: 42350104 Severity: Critical -- failure or failure imminent. A unit unquiesce was called w ithout the corresponding quiesce. Termination Code: 42360102 Severity: Critical -- failure or failure imminent. A call to notify of new ELP e ncountered an invalid CSEL state. Termination Code: 42370183 Severity: Critical -- failure or failure imminent. Gap in Sequence Numbers for E vent Logs. Termination Code: 4238011f Severity: Critical -- failure or failure imminent. The host port has detected a CSM reset after 60 minutes. Termination Code: 42390184 Severity: Critical -- failure or failure imminent. Invalid proxy io operation st ate Termination Code: 423a0102 Severity: Critical -- failure or failure imminent. Logical port number out of ra nge to access S_pcb[] Termination Code: 423b0102 Severity: Critical -- failure or failure imminent. The tachyon chip is not respo nding. The controller will be restarted so that diagnostics can be executed. Termination Code: 423e0107 Severity: Critical -- failure or failure imminent. Host Transaction Block on fre e queue is not marked free. Termination Code: 423f010c Severity: Critical -- failure or failure imminent. Host Transaction Block freed twice Termination Code: 42400104 Severity: Critical -- failure or failure imminent. HP_present_lun-- Lun, via lut _idx yielded VDSB NULL, Not yet set. Termination Code: 42410106 Severity: Critical -- failure or failure imminent. HTB incorrectly linked or mis sing from queue. Termination Code: 42420105 Severity: Critical -- failure or failure imminent. Illegal structure on connecti on pending queue. Termination Code: 83002061 Severity: Critical -- failure or failure imminent. DOG cannot branch to this rou tine. Termination Code: 83012079 Severity: Critical -- failure or failure imminent. DOG unexpected vector to erro r.

Termination Code: 8302206c Severity: Critical -- failure or failure imminent. DOG non-fault tolerant hard e rror. Termination Code: 84032069 Severity: Critical -- failure or failure imminent. Excessive correctable errors have been seen in cache memory. Termination Code: 84042065 Severity: Critical -- failure or failure imminent. Excessive correctable errors have been seen in policy memory. EVENT INFORMATION PACKETS: Event Information Packet Type: 1 EIP01 - Fault Manager Termination Processing Recursive Entry Event A machine check occurred while a termination event was being processed. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)}

<byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> union hdu Termination Event Information Header <byte 76> {lteihd (Active if Termination Event Information Header revision is greater than 3)} <byte 76> {flags (Last Termination Event flags)} <byte 76> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Termination event sequence number reset occurred tbits:1 cccc_forced Coupled crash forced tbits:1 rsvd Pad to fill byte tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 77> utiny revision Structure revision number <byte 78> ushort size Structure size {} or hdu Termination Event Information Header <byte 76> {lteihd0 (Active if Termination Event Information Header revision is less than o r equal to 3)} <byte 76> {flags (Last Termination Event flags)} <byte 76> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Termination event sequence number reset occurred tbits:1 cccc_forced Coupled crash forced tbits:1 stack_bad Stack contains pointer outside stack area tbits:1 stack_guard_bad System or process stack guard value(s) overwritten tbits:1 short_term_path Short termination path taken tbits:1 feb_saved Final Event Block saved

{} <byte 77> utiny revision Structure revision number <byte 78> ushort size Structure size {} endunion hdu Termination Event Information Header <byte 80> union ru Termination Event Reporting Information <byte 80> {lter (Active if Termination Event Information Header revision greater than 3)} <byte 80> ulong seq Sequence number assigned to the termination event <byte 84> char[8] sw_version HSV450 controller software version number string <byte 92> char[12] baselevel_id HSV450 controller baselevel build string <byte 104> char[8] ctrlr_model_id HSV450 controller model string <byte 112> scmi_obj_hnd terminating_ctrlr Storage System Management Interface Handle of HSV 450 controller that terminated operation <byte 132> scmitim termination_time Time termination event occurred <byte 140> {termination_event (Termination event information)} <byte 140> ulong termination_location Location of termination event report call <byte 144> union u Termination Code Union <byte 144> {code (Termination Code)} <byte 144> tbits:5 parc Parameter Count tbits:2 drcc Dump/Restart Control Code tbits:1 cccc Coupled Crash Control Code <byte 145> cacode cac Corrective Action Code <byte 146> utiny evnum Event Number <byte 147> utiny scid HSV450 Controller Software Component Identification {} or u Termination Code Union <byte 144> ulong value Termination Code Value endunion u Termination Code Union {} <byte 148> utiny[2] reserved Reserved <byte 150> {flags (Other Last Termination Event flags)} <byte 150> tbits:1 lg_send_sts Last Gasp send status tbits:1 stack_bad Stack contains pointer outside stack area tbits:1 stack_guard_bad System or process stack guard value(s) overwritten tbits:1 short_term_path Short termination path taken tbits:1 feb_saved Final Event Block saved tbits:3 rsvd Pad to fill byte {}

<byte 151> utiny reuea_index Termination Processing Recursive Entry Event or Unexpected nt array index <byte 152> ulonglong uptime Number of seconds HSV450 controller has run functional code {} or ru Termination Event Reporting Information <byte 80> {lter0 (Active if Termination Event Information Header revision is less than equal to 3)} <byte 80> ulong seq Sequence number assigned to the termination event <byte 84> char[4] sw_version HSV450 controller software version number string <byte 88> char[12] baselevel_id HSV450 controller baselevel build string <byte 100> char[8] ctrlr_model_id HSV450 controller model string <byte 108> scmi_obj_hnd terminating_ctrlr Storage System Management Interface Handle of 450 controller that terminated operation <byte 128> scmitim termination_time Time termination event occurred <byte 136> {termination_event (Termination event information)} <byte 136> ulong termination_location Location of termination event report call <byte 140> union u Termination Code Union <byte 140> {code (Termination Code)} <byte 140> tbits:5 parc Parameter Count tbits:2 drcc Dump/Restart Control Code tbits:1 cccc Coupled Crash Control Code <byte 141> cacode cac Corrective Action Code <byte 142> utiny evnum Event Number <byte 143> utiny scid HSV450 Controller Software Component Identification {} or u Termination Code Union <byte 140> ulong value Termination Code Value endunion u Termination Code Union {} <byte 144> utiny[2] reserved Reserved <byte 146> utiny lg_send_sts Last Gasp send status <byte 147> utiny reuea_index Termination Processing Recursive Entry Event or Unexpected nt array index <byte 148> ulonglong uptime Number of seconds HSV450 controller has run functional code {} <byte 156> do_not_display[4] union_pad Union Element Padding (DO NOT DISPLAY!) endunion ru Termination Event Reporting Information

Eve

or

HSV

Eve

<byte 160> {rei (Recursive Entry Event Information)} <byte 160> ulong tt Trap type <byte 164> ulong tc Termination code <byte 168> ulong srr0 SRR0 register <byte 172> ulong lr LR register <byte 176> ulong exception Exception code {} {} Event Information Packet Type: 2 EIP02 - Fault Manager Termination Processing Unexpected Event An unexpected event occurred while a termination event was being processed. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)}

<byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> union hdu Termination Event Information Header <byte 76> {lteihd (Active if Termination Event Information Header revision is greater than 3)} <byte 76> {flags (Last Termination Event flags)} <byte 76> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Termination event sequence number reset occurred tbits:1 cccc_forced Coupled crash forced tbits:1 rsvd Pad to fill byte tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 77> utiny revision Structure revision number <byte 78> ushort size Structure size {} or hdu Termination Event Information Header <byte 76> {lteihd0 (Active if Termination Event Information Header revision is less than o r equal to 3)} <byte 76> {flags (Last Termination Event flags)} <byte 76> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Termination event sequence number reset occurred tbits:1 cccc_forced Coupled crash forced tbits:1 stack_bad Stack contains pointer outside stack area tbits:1 stack_guard_bad System or process stack guard value(s) overwritten tbits:1 short_term_path Short termination path taken tbits:1 feb_saved Final Event Block saved

{} <byte 77> utiny revision Structure revision number <byte 78> ushort size Structure size {} endunion hdu Termination Event Information Header <byte 80> union ru Termination Event Reporting Information <byte 80> {lter (Active if Termination Event Information Header revision greater than 3)} <byte 80> ulong seq Sequence number assigned to the termination event <byte 84> char[8] sw_version HSV450 controller software version number string <byte 92> char[12] baselevel_id HSV450 controller baselevel build string <byte 104> char[8] ctrlr_model_id HSV450 controller model string <byte 112> scmi_obj_hnd terminating_ctrlr Storage System Management Interface Handle of HSV 450 controller that terminated operation <byte 132> scmitim termination_time Time termination event occurred <byte 140> {termination_event (Termination event information)} <byte 140> ulong termination_location Location of termination event report call <byte 144> union u Termination Code Union <byte 144> {code (Termination Code)} <byte 144> tbits:5 parc Parameter Count tbits:2 drcc Dump/Restart Control Code tbits:1 cccc Coupled Crash Control Code <byte 145> cacode cac Corrective Action Code <byte 146> utiny evnum Event Number <byte 147> utiny scid HSV450 Controller Software Component Identification {} or u Termination Code Union <byte 144> ulong value Termination Code Value endunion u Termination Code Union {} <byte 148> utiny[2] reserved Reserved <byte 150> {flags (Other Last Termination Event flags)} <byte 150> tbits:1 lg_send_sts Last Gasp send status tbits:1 stack_bad Stack contains pointer outside stack area tbits:1 stack_guard_bad System or process stack guard value(s) overwritten tbits:1 short_term_path Short termination path taken tbits:1 feb_saved Final Event Block saved tbits:3 rsvd Pad to fill byte {}

<byte 151> utiny reuea_index Termination Processing Recursive Entry Event or Unexpected nt array index <byte 152> ulonglong uptime Number of seconds HSV450 controller has run functional code {} or ru Termination Event Reporting Information <byte 80> {lter0 (Active if Termination Event Information Header revision is less than equal to 3)} <byte 80> ulong seq Sequence number assigned to the termination event <byte 84> char[4] sw_version HSV450 controller software version number string <byte 88> char[12] baselevel_id HSV450 controller baselevel build string <byte 100> char[8] ctrlr_model_id HSV450 controller model string <byte 108> scmi_obj_hnd terminating_ctrlr Storage System Management Interface Handle of 450 controller that terminated operation <byte 128> scmitim termination_time Time termination event occurred <byte 136> {termination_event (Termination event information)} <byte 136> ulong termination_location Location of termination event report call <byte 140> union u Termination Code Union <byte 140> {code (Termination Code)} <byte 140> tbits:5 parc Parameter Count tbits:2 drcc Dump/Restart Control Code tbits:1 cccc Coupled Crash Control Code <byte 141> cacode cac Corrective Action Code <byte 142> utiny evnum Event Number <byte 143> utiny scid HSV450 Controller Software Component Identification {} or u Termination Code Union <byte 140> ulong value Termination Code Value endunion u Termination Code Union {} <byte 144> utiny[2] reserved Reserved <byte 146> utiny lg_send_sts Last Gasp send status <byte 147> utiny reuea_index Termination Processing Recursive Entry Event or Unexpected nt array index <byte 148> ulonglong uptime Number of seconds HSV450 controller has run functional code {} <byte 156> do_not_display[4] union_pad Union Element Padding (DO NOT DISPLAY!) endunion ru Termination Event Reporting Information

Eve

or

HSV

Eve

<byte 160> {uei (Unexpected Event Information)} <byte 160> ulong type Unexpected event type <byte 164> ulong pto Post-Termination Operation Indicator <byte 168> ulong[5] param Unexpected event parameters {} {} Event Information Packet Type: 3 EIP03 - Fault Manager Management Event An event that affects Fault Manager operation occurred. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code

<byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> union ainfo Ancillary Information Union <byte 76> ulong events_not_reported Number of events not reported <byte 80> do_not_display[4] union_pad Union Element Padding (DO NOT DISPLAY!) or ainfo Ancillary Information Union <byte 76> ulong quiesce_type Quiesce type <byte 80> do_not_display[4] union_pad Union Element Padding (DO NOT DISPLAY!) or ainfo Ancillary Information Union <byte 76> {remote_event (Remote event header information)} <byte 76> union u Event Code Union <byte 76> {ec (Event Code)} <byte 76> utiny eiptype Event Information Packet Type Code <byte 77> cacode cac Corrective Action Code <byte 78> utiny evnum Event Number <byte 79> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 76> ulong value Event Code Value endunion u Event Code Union <byte 80> utiny revision Packet revision number <byte 81> utiny type Packet type <byte 82> ushort count Number of bytes in packet {} endunion ainfo Ancillary Information Union <byte 84> union cinfo Control Block Information Union <byte 84> {scelcbi (Storage System Event Log Control Block Information)} <byte 84>

ushort current_offset Current offset within event buffer <byte 86> {flags (Flags)} <byte 86> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Sequence number reset occurred tbits:1 wrapped All event data blocks in use tbits:4 rsvd Pad to fill byte {} <byte 87> utiny status Maintenance status <byte 88> ulong current_edbn Current event data block number <byte 92> ulong start_edbn Storage System State Logical Disk-Storage System Event Log star ting event data block number <byte 96> ulong end_edbn Storage System State Logical Disk-Storage System Event Log ending event data block number <byte 100> ulong seq_reset_edbn Event data block number where sequence number reset occurre d <byte 104> ulong event_count Number of events contained in Storage System State Logical Dis k-Storage System Event Log <byte 108> ulong event_count_wraps Event count overflow <byte 112> ulong sequence_number Last event sequence number used {} <byte 116> do_not_display[12] union_pad Union Element Padding (DO NOT DISPLAY!) or cinfo Control Block Information Union <byte 84> {sctelcbi (Storage System Termination Event Log Control Block Information)} <byte 84> ushort reserved Reserved for future use <byte 86> {flags (Flags)} <byte 86> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 bctrlr_wrapped All termination event data blocks in use for 'B' HSV450 c ontroller tbits:1 bctrlr_valid 'B' HSV450 controller's Storage System State Logical Disk-S torage System Termination Event Log information is valid tbits:1 actrlr_wrapped All termination event data blocks in use for 'A' HSV450 c ontroller tbits:1 actrlr_valid 'A' HSV450 controller's Storage System State Logical Disk-S torage System Termination Event Log information is valid tbits:2 rsvd Pad to fill byte {} <byte 87> utiny status Maintenance status <byte 88> uuid actrlr_id 'A' HSV450 controller's UUID <byte 104>

ulong actrlr_mru_edbn 'A' HSV450 controller's Storage System State Logical DiskStorage System Termination Event Log most recently used event data block number <byte 108> uuid bctrlr_id 'B' HSV450 controller's UUID <byte 124> ulong bctrlr_mru_edbn 'B' HSV450 controller's Storage System State Logical DiskStorage System Termination Event Log most recently used event data block number {} or cinfo Control Block Information Union <byte 84> {stats30 (Last 30 seconds activity summary)} <byte 84> {host (Host Activity,)} <byte 84> ulong rps Requests Per Second, <byte 88> ulong kbs KB/Second. {} <byte 92> {mirror (Mirror Activity,)} <byte 92> ulong rps Requests Per Second, <byte 96> ulong kbs KB/Second. {} <byte 100> {backend (Backend Activity,)} <byte 100> ulong rps Requests Per Second, <byte 104> ulong kbs KB/Second. {} <byte 108> {total (Total Activity,)} <byte 108> ulong rps Requests Per Second, <byte 112> ulong kbs KB/Second. {} <byte 116> {background (Background Activity.)} <byte 116> ulong rps Requests Per Second, <byte 120> ulong kbs KB/Second. {} {} <byte 124> do_not_display[4] union_pad Union Element Padding (DO NOT DISPLAY!) or cinfo Control Block Information Union <byte 84> {mealcbi (Manufacturing Event Analysis Log Control Block information)} <byte 84> ushort current_offset Current offset within event buffer <byte 86> {flags (Flags)} <byte 86> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System

tbits:1 seq_reset Sequence number reset occurred tbits:1 wrapped All event data blocks in use tbits:4 rsvd Pad to fill byte {} <byte 87> utiny status Maintenance status <byte 88> ulong current_edbn Current event data block number <byte 92> ulong start_edbn Manufacturing Event Analysis Log starting event data block numb er <byte 96> ulong end_edbn Manufacturing Event Analysis Log ending event data block number <byte 100> ulong seq_reset_edbn Event data block number where sequence number reset occurre d <byte 104> ulong event_count Number of events contained in Manufacturing Event Analysis Log <byte 108> ulong event_count_wraps Event count overflow <byte 112> ulong sequence_number Last event sequence number used {} <byte 116> do_not_display[12] union_pad Union Element Padding (DO NOT DISPLAY!) endunion cinfo Control Block Information Union <byte 128> union minfo Maintenance Information Union <byte 128> {scelmi (Storage System Event Log Maintenance Information)} <byte 128> ulong index Loop index <byte 132> *ptr *utp Zero test buffer pointer <byte 136> ulong current_eventp Pointer to the current event <byte 140> ulong current_edbn Current event data block number <byte 144> ulong current_seqn Current sequence number <byte 148> ushort previous_offset Previous event buffer offset <byte 150> ushort current_offset Current event buffer offset <byte 152> ulong previous_edbn Previous event data block number <byte 156> ulong previous_seqn Previous sequence number <byte 160> ulong end_found End of Storage System State Logical Disk-Storage System Event Lo g found flag <byte 164> ulong accept_new_to_old New to old transition acceptable flag <byte 168> ulong unequal_found Sequence number not as expected flag <byte 172> ulong iostatus I/O status {} or minfo Maintenance Information Union <byte 128>

{sctelmi (Storage System Termination Event Log Maintenance Information)} <byte 128> ulong index Loop index <byte 132> ulong current_edbn Current event data block number <byte 136> ulong end_edbn End event data block number <byte 140> ulong actrlr If 'A' HSV450 controller, TRUE <byte 144> ulong iostatus I/O status <byte 148> ulong hold_offset Hold buffer current offset {} <byte 152> do_not_display[24] union_pad Union Element Padding (DO NOT DISPLAY!) or minfo Maintenance Information Union <byte 128> {lerinfo (Last Event Reported Information)} <byte 128> ulong reporting_interval Last event reporting interval <byte 132> ulong sequence_number Sequence number assigned to the event <byte 136> scmitim report_time Time event was reported <byte 144> {header (Event Header)} <byte 144> union u Event Code Union <byte 144> {ec (Event Code)} <byte 144> utiny eiptype Event Information Packet Type Code <byte 145> cacode cac Corrective Action Code <byte 146> utiny evnum Event Number <byte 147> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 144> ulong value Event Code Value endunion u Event Code Union <byte 148> utiny revision Packet revision number <byte 149> utiny type Packet type <byte 150> ushort count Number of bytes in packet {} {} <byte 152> do_not_display[24] union_pad Union Element Padding (DO NOT DISPLAY!) or minfo Maintenance Information Union <byte 128> {mealmi (Manufacturing Event Analysis Log Maintenance Information)} <byte 128> ulong index Loop index <byte 132>

*ptr *utp Zero test buffer pointer <byte 136> ulong current_eventp Pointer to the current event <byte 140> ulong current_edbn Current event data block number <byte 144> ulong current_seqn Current sequence number <byte 148> ushort previous_offset Previous event buffer offset <byte 150> ushort current_offset Current event buffer offset <byte 152> ulong previous_edbn Previous event data block number <byte 156> ulong previous_seqn Previous sequence number <byte 160> ulong end_found End of Manufacturing Event Analysis Log found flag <byte 164> ulong accept_new_to_old New to old transition acceptable flag <byte 168> ulong unequal_found Sequence number not as expected flag <byte 172> ulong first_seqn First sequence number {} endunion minfo Maintenance Information Union {} Event Information Packet Type: 4 EIP04 - Fibre Channel Services Physical Disk Drive Error An error was encountered while accessing a physical disk drive. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36>

scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> tag device UUID of physical disk drive associated with the event <byte 92> char[8] cerp_id HSV450 controller enclosure rear panel Fibre Channel port attach ed to the physical disk drive or mirror port <byte 100> ulong al_pa AL_PA of the physical disk drive or mirror port <byte 104> ushort dencl_num Enclosure where the physical disk drive is located <byte 106> ushort port HSV450 controller internal Fibre Channel port number attached to the physical disk drive or mirror port <byte 108> ushort rack_num Rack where physical disk drive is located <byte 110> ushort bay Enclosure bay where the physical disk drive is located <byte 112> char[16] pid Physical disk drive product identification string <byte 128> char[4] rev Current firmware level of physical disk drive <byte 132> {enclosures[1] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} <byte 132> utiny rack_num Rack were enclosure is located <byte 133> utiny dencl_num Enclosure number {}

<byte 134> {enclosures[0] (Enclosure available on the Fibre cerp_id and port fields)} <byte 134> utiny rack_num Rack were enclosure is located <byte 135> utiny dencl_num Enclosure number {} <byte 136> {enclosures[3] (Enclosure available on the Fibre cerp_id and port fields)} <byte 136> utiny rack_num Rack were enclosure is located <byte 137> utiny dencl_num Enclosure number {} <byte 138> {enclosures[2] (Enclosure available on the Fibre cerp_id and port fields)} <byte 138> utiny rack_num Rack were enclosure is located <byte 139> utiny dencl_num Enclosure number {} <byte 140> {enclosures[5] (Enclosure available on the Fibre cerp_id and port fields)} <byte 140> utiny rack_num Rack were enclosure is located <byte 141> utiny dencl_num Enclosure number {} <byte 142> {enclosures[4] (Enclosure available on the Fibre cerp_id and port fields)} <byte 142> utiny rack_num Rack were enclosure is located <byte 143> utiny dencl_num Enclosure number {} <byte 144> {enclosures[7] (Enclosure available on the Fibre cerp_id and port fields)} <byte 144> utiny rack_num Rack were enclosure is located <byte 145> utiny dencl_num Enclosure number {} <byte 146> {enclosures[6] (Enclosure available on the Fibre cerp_id and port fields)} <byte 146> utiny rack_num Rack were enclosure is located <byte 147> utiny dencl_num Enclosure number {} <byte 148> ushort unused <byte 150> {enclosures[8] (Enclosure available on the Fibre

Channel port identified in the

Channel port identified in the

Channel port identified in the

Channel port identified in the

Channel port identified in the

Channel port identified in the

Channel port identified in the

Channel port identified in the

cerp_id and port fields)} <byte 150> utiny rack_num Rack were enclosure is located <byte 151> utiny dencl_num Enclosure number {} <byte 152> ulong bypass_reason Reason the physical disk drive at this location has been byp assed <byte 156> char[4] new_rev Latest known firmware level of physical disk drive <byte 160> ushort bypassb Mask showing bypass state for each slot in a shelf <byte 162> ushort bypassa Mask showing bypass state for each slot in a shelf {} Event Information Packet Type: 5 EIP05 - Storage System Management Interface Entity State Change The state of a Storage System Management Interface entity has changed. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union

<byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> {event_type (Entity and Event type)} <byte 76> ushort scmi_object_type Entity type <byte 78> ushort scmi_object_event_type Event Information Packet type {} <byte 80> {value (New entity state)} <byte 80> ulong ul1 Additional information longword 1 <byte 84> ulong ul2 Additional information longword 2 {} <byte 88> scmi_obj_hnd handle Storage System Management Interface Handle of affected entit y <byte 108> ulong secondary_id Alternate entity identification <byte 112> {attribute (Entity attributes)} <byte 112> ulong type Datatype used <byte 116> union value SCMI Attribute Union <byte 116> ushort[12] u16 As 16 bit words, or value SCMI Attribute Union <byte 116> ulong[6] u32 As 32 bit words, or value SCMI Attribute Union <byte 116> double_word[3] u64 As 64 bit words, or value SCMI Attribute Union <byte 116> {obj (As typed Storage System Management Interface object handle,)} <byte 116> ulong value

<byte 120> scmi_obj_hnd handle {} or value SCMI Attribute Union <byte 116> char[24] str As character string endunion value SCMI Attribute Union {} <byte 140> scmi_obj_hnd add_handle Additional entity identification (Storage System Managem ent Interface Handle) <byte 160> ulong[6] add_data Additional Data {} Event Information Packet Type: 6 EIP06 - Fibre Channel Services Enclosure or Enclosure Link Module Status Change Status of an Enclosure or Enclosure Link Module has changed. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)}

<byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> {enc_wwn (World Wide Name of Enclosure)} <byte 76> ulong hi (Bits 31:28) Network Address Authority Code, (Bits 27:4) Company ID, (B its 3:0) Type <byte 80> ulong lo (Bits 31:4) Node Number, (Bits 3:0) Port {} <byte 84> char[8] vendor_id Vendor Identification of Enclosure <byte 92> char[16] product_id Product Identification of Enclosure <byte 108> char[4] product_rev Product Revision Level of Enclosure <byte 112> char[4] enc_hw_type Hardware Type of Enclosure <byte 116> char[4] enc_hw_rev Hardware Revision of Enclosure <byte 120> char[16] enc_serial_num Serial Number of Enclosure <byte 136> char[4] fan_module_1_fw_rev Firmware Revision of Fan Module 1 <byte 140> char[4] fan_module_1_hw_rev Hardware Revision of Fan Module 1 <byte 144> char[16] fan_module_1_serial_num Serial Number of Fan Module 1 <byte 160> char[4] fan_module_2_fw_rev Firmware Revision of Fan Module 2 <byte 164> char[4] fan_module_2_hw_rev Hardware Revision of Fan Module 2 <byte 168> char[16] fan_module_2_serial_num Serial Number of Fan Module 2 <byte 184> char[4] loop_a_elmo_fw_rev Firmware Revision of Loop A Enclosure Link Module <byte 188> char[4] loop_a_elmo_hw_type Hardware Type of Loop A Enclosure Link Module <byte 192> char[4] loop_a_elmo_hw_rev Hardware Revision of Loop A Enclosure Link Module <byte 196> char[16] loop_a_elmo_serial_num Serial Number of Loop A Enclosure Link Module

<byte 212> char[4] loop_a_elmo_transceiver_1_hw_type Hardware Type of Loop A Enclosure Link Module Transceiver 1 <byte 216> char[4] loop_a_elmo_transceiver_2_hw_type Hardware Type of Loop A Enclosure Link Module Transceiver 2 <byte 220> char[4] loop_a_elmo_alphanum_disp_product_rev Product Revision of Loop A Enclosu re Link Module Alphanumeric Display <byte 224> char[16] loop_a_elmo_alphanum_disp_product_id Product Identification of Loop A E nclosure Link Module Alphanumeric Display <byte 240> char[4] loop_b_elmo_fw_rev Firmware Revision of Loop B Enclosure Link Module <byte 244> char[4] loop_b_elmo_hw_type Hardware Type of Loop B Enclosure Link Module <byte 248> char[4] loop_b_elmo_hw_rev Hardware Revision of Loop B Enclosure Link Module <byte 252> char[16] loop_b_elmo_serial_num Serial Number of Loop B Enclosure Link Module <byte 268> char[4] loop_b_elmo_transceiver_1_hw_type Hardware Type of Loop B Enclosure Link Module Transceiver 1 <byte 272> char[4] loop_b_elmo_transceiver_2_hw_type Hardware Type of Loop B Enclosure Link Module Transceiver 2 <byte 276> char[4] loop_b_elmo_alphanum_disp_product_rev Product Revision of Loop B Enclosu re Link Module Alphanumeric Display <byte 280> char[16] loop_b_elmo_alphanum_disp_product_id Product Identification of Loop B E nclosure Link Module Alphanumeric Display <byte 296> char[4] midplane_logic_fw_rev Firmware Revision of Midplane Logic <byte 300> char[4] midplane_logic_hw_type Hardware Type of Midplane Logic <byte 304> char[4] midplane_logic_hw_rev Hardware Revision of Midplane Logic <byte 308> char[16] midplane_logic_serial_num Serial Number of Midplane Logic <byte 324> char[4] backplane_hw_rev Hardware Revision of Backplane <byte 328> ulong loop_a_elmo_n_port_id Arbitrated Loop Physical Address or AL_PA acquired b y the port of Loop A Enclosure Link Module in the Enclosure <byte 332> {loop_a_elmo_n_port_name (World Wide Name of Loop A Enclosure Link Module in the Enclosure)} <byte 332> ulong hi (Bits 31:28) Network Address Authority Code, (Bits 27:4) Company ID, (B its 3:0) Type <byte 336> ulong lo (Bits 31:4) Node Number, (Bits 3:0) Port {} <byte 340> ulong loop_b_elmo_n_port_id Arbitrated Loop Physical Address or AL_PA acquired b y the port of Loop B Enclosure Link Module in the Enclosure <byte 344> {loop_b_elmo_n_port_name (World Wide Name of Loop B Enclosure Link Module in the Enclosure)}

<byte 344> ulong hi (Bits 31:28) Network Address Authority Code, (Bits 27:4) Company ID, (B its 3:0) Type <byte 348> ulong lo (Bits 31:4) Node Number, (Bits 3:0) Port {} <byte 352> ulong enc_num Enclosure Number of Enclosure <byte 356> ulong port Port Number <byte 360> ulong bypass_bay Drive bay to control bypass in Enclosure <byte 364> ulong power_bay Drive bay to control power in Enclosure <byte 368> ulong data Generic data field to be used by caller. <byte 372> ulong data2 Second field of generic data to be used by the caller {} Event Information Packet Type: 7 EIP07 - Fibre Channel Services Fibre Channel Port Link Error Excessive link errors were detected on a Fibre Channel port. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68>

{header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> char[8] cerp_id HSV450 controller enclosure rear panel Fibre Channel port <byte 84> ushort reserved Reserved <byte 86> ushort port HSV450 controller internal Fibre Channel port number <byte 88> ulong loss_of_signal Number of times a loss of signal was detected <byte 92> ulong bad_rx_char Bad received character count <byte 96> ulong loss_of_sync Loss of synchronization count <byte 100> ulong link_fail Link failure count <byte 104> ulong rx_eofa The number of frames that have been received with an EOFa delimite r <byte 108> ulong dis_frm The number of frames that have been received and then discarded <byte 112> ulong bad_crc The number of frames that have been received with a Bad_CRC and a valid EOF <byte 116> ulong proto_err The number of N_Port protocol errors detected <byte 120> ulong exp_frm The number of outbound frames that have expired and therefore were discarded. {} Event Information Packet Type: 8 EIP08 - Fibre Channel Services Fibre Channel Port Link Failure A Fibre Channel port link has failed or a Drive Enclosure Environmental Monitori ng Unit task has failed. {Event Log Packet Event Specific Information}

<byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {}

<byte 76> char[8] cerp_id HSV450 controller enclosure rear panel Fibre Channel port <byte 84> char[8] other_cerp_id HSV450 controller enclosure rear panel Fibre Channel port attached to the physical disk drive or mirror port <byte 92> {peb[0] (Fibre Channel port Event Blocks)} <byte 92> ulong type Error type code <byte 96> ulong context Error context {} <byte 100> {peb[1] (Fibre Channel port Event Blocks)} <byte 100> ulong type Error type code <byte 104> ulong context Error context {} <byte 108> {peb[2] (Fibre Channel port Event Blocks)} <byte 108> ulong type Error type code <byte 112> ulong context Error context {} <byte 116> {peb[3] (Fibre Channel port Event Blocks)} <byte 116> ulong type Error type code <byte 120> ulong context Error context {} <byte 124> {peb[4] (Fibre Channel port Event Blocks)} <byte 124> ulong type Error type code <byte 128> ulong context Error context {} <byte 132> {peb[5] (Fibre Channel port Event Blocks)} <byte 132> ulong type Error type code <byte 136> ulong context Error context {} <byte 140> {peb[6] (Fibre Channel port Event Blocks)} <byte 140> ulong type Error type code <byte 144> ulong context Error context {} <byte 148> {peb[7] (Fibre Channel port Event Blocks)} <byte 148> ulong type Error type code <byte 152> ulong context Error context

{} <byte 156> ushort peq_prod_index Producer index <byte 158> ushort peq_frz_prod_index Error idle or freeze producer index <byte 160> ushort failure_cause Code indicating path to link failure <byte 162> ushort peq_cons_index Consumer index <byte 164> ushort reserved1 Reserved <byte 166> utiny other_port HSV450 controller internal Fibre Channel port number <byte 167> utiny port HSV450 controller internal Fibre Channel port number <byte 168> ulong time Used to represent a retry time or other time based element in the eve nt. <byte 172> {recovery (Loop Recovery Operations)} <byte 172> ulong progress EWE Step for recovery process <byte 176> ulong shelf Physical Shelf being evaluated. <byte 180> ulong slot Physical Slot being evaluated. <byte 184> ulong cab Cabinet rack being evaluated. {} {} Event Information Packet Type: 9 EIP09 - Fibre Channel Services Physical Disk Drive/Mirror Port Error An error was encountered while attempting to access a physical disk drive or the mirror port. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string

<byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> tag device UUID of physical disk drive associated with the event <byte 92> char[8] cerp_id HSV450 controller enclosure rear panel Fibre Channel port attach ed to the physical disk drive or mirror port <byte 100> ushort exch_type Frame exchange type <byte 102> ushort port HSV450 controller internal Fibre Channel port number attached to the physical disk drive or mirror port <byte 104> ulong al_pa AL_PA of the physical disk drive or mirror port <byte 108> ushort dencl_num Enclosure where the physical disk drive is located <byte 110> ushort reserved Reserved <byte 112> ushort rack_num Rack where physical disk drive is located <byte 114> ushort bay Enclosure bay where the physical disk drive is located <byte 116> ulong fed_class Fibre Channel Exchange Descriptor class <byte 120>

union cmd Command Descriptor Block issued <byte 120> utiny[16] bytes CDB as bytes or cmd Command Descriptor Block issued <byte 120> ulong[4] lw CDB as longwords or cmd Command Descriptor Block issued <byte 120> {cdb10 (10 Byte CDB by field)} <byte 120> utiny lba1 Offset 3 -- Logical Block Address[1] byte 4 <byte 121> utiny lba0 Offset 2 -- Logical Block Address[0] byte 3 <byte 122> tbits:5 reserved Offset 1, Bits 0-4 -- Reserved byte 2 tbits:3 lun Offset 1, Bits 5-7 -- Logical Unit Number (obsolete method -- unused ) <byte 123> utiny opcode Offset 0 -- Operation Code byte 1 <byte 124> utiny length0 Offset 7 -- Length[0] byte 8 <byte 125> utiny reserved6 Offset 6 -- Reserved byte 7 <byte 126> utiny lba3 Offset 5 -- Logical Block Address[3] byte 6 <byte 127> utiny lba2 Offset 4 -- Logical Block Address[2] byte 5 <byte 128> ushort padding Offsets 10-11 -- Pad to longword align <byte 130> utiny control Offset 9 -- Control byte 10,11 <byte 131> utiny length1 Offset 8 -- Length[1] byte 9 {} <byte 132> do_not_display[4] union_pad Union Element Padding (DO NOT DISPLAY!) endunion cmd Command Descriptor Block issued <byte 136> union error Sense data reported by the physical disk drive <byte 136> utiny[20] bytes Sense data as bytes or error Sense data reported by the physical disk drive <byte 136> ulong[5] lw Sense data as longwords or error Sense data reported by the physical disk drive <byte 136> {sense_data (Sense data from SCSI spec)} <byte 136> utiny info_0 Byte 4 <byte 137> tbits:4 sense_key Byte 3 tbits:1 reserved_1 tbits:1 ili tbits:1 eom tbits:1 filemark <byte 138> utiny segment Byte 2 <byte 139> tbits:7 error_code Byte 1 tbits:1 valid

<byte 140> utiny add_length Byte 8-11 <byte 141> utiny info_3 Byte 7 <byte 142> utiny info_2 Byte 6 <byte 143> utiny info_1 Byte 5 <byte 144> utiny[4] cmd_specific Byte 12-13 <byte 148> tbits:3 bit_ptr Byte 16 tbits:1 bpv tbits:2 reserved tbits:1 cd tbits:1 sksv <byte 149> utiny fru_code Byte 15 <byte 150> union sns Byte 14 <byte 150> {bytes (No description available)} <byte 150> utiny asq Byte 13 <byte 151> utiny asc Byte 12 {} or sns Byte 14 <byte 150> ushort asc_asq endunion sns Byte 14 <byte 152> ushort big_endian_padding <byte 154> ushort field_ptr Byte 17 {} endunion error Sense data reported by the physical disk drive <byte 156> {enclosures[1] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} <byte 156> utiny rack_num Rack were enclosure is located <byte 157> utiny dencl_num Enclosure number {} <byte 158> {enclosures[0] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} <byte 158> utiny rack_num Rack were enclosure is located <byte 159> utiny dencl_num Enclosure number {} <byte 160> {enclosures[3] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} <byte 160> utiny rack_num Rack were enclosure is located <byte 161> utiny dencl_num Enclosure number

{} <byte 162> {enclosures[2] (Enclosure available on the Fibre Channel port identified cerp_id and port fields)} <byte 162> utiny rack_num Rack were enclosure is located <byte 163> utiny dencl_num Enclosure number {} <byte 164> {enclosures[5] (Enclosure available on the Fibre Channel port identified cerp_id and port fields)} <byte 164> utiny rack_num Rack were enclosure is located <byte 165> utiny dencl_num Enclosure number {} <byte 166> {enclosures[4] (Enclosure available on the Fibre Channel port identified cerp_id and port fields)} <byte 166> utiny rack_num Rack were enclosure is located <byte 167> utiny dencl_num Enclosure number {} <byte 168> {enclosures[7] (Enclosure available on the Fibre Channel port identified cerp_id and port fields)} <byte 168> utiny rack_num Rack were enclosure is located <byte 169> utiny dencl_num Enclosure number {} <byte 170> {enclosures[6] (Enclosure available on the Fibre Channel port identified cerp_id and port fields)} <byte 170> utiny rack_num Rack were enclosure is located <byte 171> utiny dencl_num Enclosure number {} <byte 172> ushort unused <byte 174> {enclosures[8] (Enclosure available on the Fibre Channel port identified cerp_id and port fields)} <byte 174> utiny rack_num Rack were enclosure is located <byte 175> utiny dencl_num Enclosure number {} <byte 176> ushort bypassb Mask showing bypass state for each slot in a shelf <byte 178> ushort bypassa Mask showing bypass state for each slot in a shelf <byte 180> char[8] drv_fw_rev The FW revision on the drive {} Event Information Packet Type: a

in the

in the

in the

in the

in the

in the

EIP0A - Storage System State Services State Change A Storage System state change occurred. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73>

utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> {node_name (World Wide Name of HSV450 controller)} <byte 76> ulong hi (Bits 31:28) Network Address Authority Code, (Bits 27:4) Company ID, (B its 3:0) Type <byte 80> ulong lo (Bits 31:4) Node Number, (Bits 3:0) Port {} <byte 84> tag scell_tag UUID of Storage System <byte 100> ulong dimm_size Size of this HSV450 controller's DIMM in megabytes <byte 104> ulong debug_flags DebugFlags of HSV450 controller <byte 108> ulong print_flags PrintFlags of HSV450 controller <byte 112> ulong pc Program counter <byte 116> ulong scrub_type Scrub type <byte 120> ulong reboot_flags Reboot flags of HSV450 controller <byte 124> utiny[3] reserved Reserved for future use <byte 127> utiny fm_fatal_scrub Value of fm_fatal_scrub <byte 128> ulong scrub_valid Value of scrub_valid {} Event Information Packet Type: b EIP0B - Storage System State Services Physical Disk Drive State Change A physical disk drive state change occurred. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event

<byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> uuid device UUID of physical disk drive <byte 92> char[8] cerp_id HSV450 controller enclosure rear panel Fibre Channel port attach ed to the physical disk drive <byte 100> ushort reason_code Code identifying cause of the physical disk drive being marke d inoperative or why event is being reported <byte 102> ushort port HSV450 controller internal Fibre Channel port number attached to the physical disk drive or mirror port <byte 104> ushort dencl_num Enclosure where the physical disk drive is located <byte 106> {rss_flags (Redundant Storage Set member state flags)} <byte 106> tbits:1 member_migrating Migrating tbits:1 member_missing Missing or never existed tbits:1 member_abnormal Abnormal tbits:5 reserved Reserved for future use {}

<byte 107> {flags (Information validity flags)} <byte 107> tbits:1 inq_state SCSI INQUIRY data is valid tbits:1 quorum_disk Is Storage System quorum disk tbits:6 reserved Reserved for future use {} <byte 108> ushort rack_num Rack where the physical disk drive is located <byte 110> ushort bay Enclosure bay where the physical disk drive is located <byte 112> {inq_data (Last SCSI INQUIRY data read during discovery (Note: The inquiry data is truncated after the Version Descriptor 1 field.))} <byte 112> tbits:4 response_data Response data format ( 1 = SCSI-1, 2 = SCSI-2, 3 = SCSI-3) tbits:1 hisup Hierarchical Support bit tbits:1 normaca Normal ACA bit tbits:1 obsolete Obsolete tbits:1 aerc Asynchronous Event Reporting Capability bit <byte 113> tbits:8 version Version <byte 114> tbits:7 reserved_1 Reserved tbits:1 rmb Removable Medium bit <byte 115> tbits:5 per_dev_typ Peripheral Device-type tbits:3 per_qual Peripheral Qualifier <byte 116> tbits:1 vs Vendor Specific tbits:1 cmdque Command Queuing bit tbits:1 reserved_2 Reserved tbits:1 linked Linked Command bit tbits:1 sync Synchronous Transfer bit tbits:1 wbus16 Wide Bus 16 bit tbits:1 wbus32 Wide Bus 32 bit tbits:1 reladr Relative Addressing bit <byte 117> tbits:1 addr16 Address 16 bit tbits:2 obsolete_1 Reserved tbits:1 mchngr Medium Changer bit tbits:1 multip Multiport bit tbits:1 vs_1 Vendor Specific tbits:1 encserv Enclosure Services bit tbits:1 bque Basic Queuing bit <byte 118> tbits:7 reserved_3 Reserved tbits:1 sccs SCC Supported bit <byte 119> utiny add_length Additional Length <byte 120> char[8] vendor_id Vendor Identification <byte 128> char[16] product_id Product Identification <byte 144> char[4] product_rev Product Revision Level <byte 148> ulong[5] vendor_36_55 Vendor-specific <byte 168> ushort reserved_56_57 Reserved

<byte 170> ushort vd1 Version Descriptor 1 {} <byte 172> ulong quorum_sequence Quorum Space Write Sequence (i.e., quorum disk 1, 2, or 3) <byte 176> ulong capacity LUN capacity (blocks) <byte 180> ulong supported_capacity Max supporetd LUN capacity (blocks) <byte 184> ulong member_state Redundant Storage Set member state <byte 188> uuid second_device UUID of other physical disk drive <byte 204> ulong second_fnb_ptr Address of fnb for other physical disk drive <byte 208> ushort volnoid Volume of other physical disk drive <byte 210> ushort poid NOID of other physical disk drive {} Event Information Packet Type: c EIP0C - Data Replication Manager State Change A Data Replication Manager state change occurred. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call

<byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> tag group_name_uuid Group Name UUID <byte 92> tag peer_scell_uuid Peer Storage System UUID <byte 108> tag group_uuid Data Replication Group UUID <byte 124> tag source_scvd_uuid Source Storage System Virtual Disk UUID <byte 140> tag dest_scvd_uuid If eip0c.flags.remote_adapter_wwn is set equal to 1, this fie ld contains the WWN of the remote adapter. Otherwise, this field contains the De stination Storage System Virtual Disk UUID. <byte 156> ushort blocks Number of blocks in error <byte 158> ushort status Error status value <byte 160> ulonglong vda Virtual Disk Address in error <byte 168> char[8] cerp_id HSV450 controller enclosure rear panel Fibre Channel port <byte 176> utiny extra Used for miscellaneous information <byte 177> {flags (Field use flags)} <byte 177> tbits:7 reserved Reserved for future use tbits:1 remote_adapter_wwn dest_scvd_uuid contains remote adapter WWN {} <byte 178> utiny side Remote HSV450 controller used by Data Replication Manager tunnel: 0 = > A; 1 => B <byte 179> utiny port HSV450 controller internal Fibre Channel port number <byte 180>

ulong[2] reserved1 Reserved for future use {} Event Information Packet Type: d EIP0D - Executive Services System Time Change A change in system time occurred. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value

endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> utiny[3] unused Unused <byte 79> utiny action Action code <byte 80> ulong[2] reserved Reserved <byte 88> scmitim ctime Current time value <byte 96> scmitim ptime Previous time value {} Event Information Packet Type: e EIP0E - Storage System Management Interface Entity Creation or Deletion A Storage System Management Interface entity was created or deleted. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68>

{header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> {event_type (Entity and Event type)} <byte 76> ushort scmi_object_type Entity type <byte 78> ushort scmi_object_event_type Event Information Packet type {} <byte 80> scmi_obj_hnd handle Storage System Management Interface Handle of affected entit y <byte 100> scmi_obj_hnd add_handle Additional entity identification (Storage System Managem ent Interface Handle) <byte 120> {attribute (Entity attributes)} <byte 120> ulong type Datatype used <byte 124> union value SCMI Attribute Union <byte 124> ushort[12] u16 As 16 bit words, or value SCMI Attribute Union <byte 124> ulong[6] u32 As 32 bit words, or value SCMI Attribute Union <byte 124> double_word[3] u64 As 64 bit words, or value SCMI Attribute Union <byte 124> {obj (As typed Storage System Management Interface object handle,)} <byte 124> ulong value <byte 128> scmi_obj_hnd handle {}

or value SCMI Attribute Union <byte 124> char[24] str As character string endunion value SCMI Attribute Union {} <byte 148> scmi_obj_hnd add_handle2 Additional SCMI object handle (2) <byte 168> ulong[4] add_data Additional Data {} Event Information Packet Type: f EIP0F - Storage System Management Interface Entity Attribute Change An attribute of a Storage System Management Interface entity has changed. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code

<byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> {event_type (Entity and Event type)} <byte 76> ushort scmi_object_type Entity type <byte 78> ushort scmi_object_event_type Event Information Packet type {} <byte 80> union secondary_id Secondary identification <byte 80> ulong Id Alternate entity identification or secondary_id Secondary identification <byte 80> {rss_data (Redundant Storage Set information)} <byte 80> ushort Id Redundant Storage Set identification <byte 82> ushort Index Redundant Storage Set index {} endunion secondary_id Secondary identification <byte 84> {old_attr (Old attribute information)} <byte 84> ulong type Datatype used <byte 88> union value SCMI Attribute Union <byte 88> ushort[12] u16 As 16 bit words, or value SCMI Attribute Union <byte 88> ulong[6] u32 As 32 bit words, or value SCMI Attribute Union <byte 88> double_word[3] u64 As 64 bit words, or value SCMI Attribute Union <byte 88> {obj (As typed Storage System Management Interface object handle,)} <byte 88> ulong value <byte 92> scmi_obj_hnd handle {} or value SCMI Attribute Union <byte 88>

char[24] str As character string endunion value SCMI Attribute Union {} <byte 112> {new_attr (New attribute information)} <byte 112> ulong type Datatype used <byte 116> union value SCMI Attribute Union <byte 116> ushort[12] u16 As 16 bit words, or value SCMI Attribute Union <byte 116> ulong[6] u32 As 32 bit words, or value SCMI Attribute Union <byte 116> double_word[3] u64 As 64 bit words, or value SCMI Attribute Union <byte 116> {obj (As typed Storage System Management Interface object handle,)} <byte 116> ulong value <byte 120> scmi_obj_hnd handle {} or value SCMI Attribute Union <byte 116> char[24] str As character string endunion value SCMI Attribute Union {} <byte 140> scmi_obj_hnd handle Storage System Management Interface Handle of affected entit y <byte 160> scmi_obj_hnd add_handle Additional entity identification (Storage System Managem ent Interface <byte 180> ulong reserved reserved for future use {} Event Information Packet Type: 10 EIP10 - System Services HSV450 Controller State Change A controller state change occurred. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {}

<byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> {node_name (World Wide Name of HSV450 controller)} <byte 76> ulong hi (Bits 31:28) Network Address Authority Code, (Bits 27:4) Company ID, (B its 3:0) Type <byte 80> ulong lo (Bits 31:4) Node Number, (Bits 3:0) Port {} <byte 84> {information (State change information)} <byte 84> ulong pc Program counter <byte 88> ulong flags Flags <byte 92>

ulong code Code {} {} Event Information Packet Type: 11 EIP11 - Disk Enclosure Environmental Monitoring Unit Services Status Change. Status of a disk enclosure element has changed. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68>

ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> {event_type (Entity and Event type)} <byte 76> ushort scmi_object_type Entity type <byte 78> ushort scmi_object_event_type Event Information Packet type {} <byte 80> scmi_obj_hnd handle Storage System Management Interface Handle of affected disk enclosure <byte 100> ulong rack_num Rack number <byte 104> ulong dencl_num Disk enclosure number <byte 108> union alarm_error_code Alarm code <byte 108> ulong value As longword or alarm_error_code Alarm code <byte 108> {field (By field)} <byte 108> utiny reserved Reserved for future use <byte 109> utiny ec Error code <byte 110> utiny en Element number <byte 111> utiny et Element type code {} endunion alarm_error_code Alarm code <byte 112> utiny[3] rsvd1 Reserved for future use <byte 115> utiny loop Loop number <byte 116> {enclosures[1] (Enclosure available on the Fibre Channel loop pair identified in the loop field)} <byte 116> utiny rack_num Rack were enclosure is located <byte 117> utiny dencl_num Enclosure number {} <byte 118> {enclosures[0] (Enclosure available on the Fibre Channel loop pair identified in the loop field)} <byte 118> utiny rack_num Rack were enclosure is located <byte 119> utiny dencl_num Enclosure number {}

<byte 120> {enclosures[3] (Enclosure available on the Fibre the loop field)} <byte 120> utiny rack_num Rack were enclosure is located <byte 121> utiny dencl_num Enclosure number {} <byte 122> {enclosures[2] (Enclosure available on the Fibre the loop field)} <byte 122> utiny rack_num Rack were enclosure is located <byte 123> utiny dencl_num Enclosure number {} <byte 124> {enclosures[5] (Enclosure available on the Fibre the loop field)} <byte 124> utiny rack_num Rack were enclosure is located <byte 125> utiny dencl_num Enclosure number {} <byte 126> {enclosures[4] (Enclosure available on the Fibre the loop field)} <byte 126> utiny rack_num Rack were enclosure is located <byte 127> utiny dencl_num Enclosure number {} <byte 128> {enclosures[7] (Enclosure available on the Fibre the loop field)} <byte 128> utiny rack_num Rack were enclosure is located <byte 129> utiny dencl_num Enclosure number {} <byte 130> {enclosures[6] (Enclosure available on the Fibre the loop field)} <byte 130> utiny rack_num Rack were enclosure is located <byte 131> utiny dencl_num Enclosure number {} <byte 132> ushort unused <byte 134> {enclosures[8] (Enclosure available on the Fibre the loop field)} <byte 134> utiny rack_num Rack were enclosure is located <byte 135> utiny dencl_num Enclosure number {} <byte 136> ulong[12] rsvd Reserved for future use

Channel loop pair identified in

Channel loop pair identified in

Channel loop pair identified in

Channel loop pair identified in

Channel loop pair identified in

Channel loop pair identified in

Channel loop pair identified in

{} Event Information Packet Type: 12 EIP12 - Fibre Channel Services Physical Disk Drive/Mirror Port Unexpected Work E ncountered Unexpected work was received from a physical disk drive or the mirror port. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value

endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> tag device UUID of the physical disk drive or HSV450 controller associated with the event <byte 92> char[8] cerp_id HSV450 controller enclosure rear panel Fibre Channel port attach ed to the physical disk drive or mirror port <byte 100> ulong al_pa AL_PA of the physical disk drive or the mirror port <byte 104> ushort dencl_num Enclosure where the physical disk drive is located <byte 106> ushort port HSV450 controller internal Fibre Channel port number attached to the physical disk drive or mirror port <byte 108> ushort rack_num Rack where the physical disk drive is located <byte 110> ushort bay Enclosure bay where the physical disk drive is located <byte 112> ulong[14] hdr_cdb Command Descriptor Block issued and Fibre Channel Header <byte 168> ushort bypassb Mask showing bypass state for each slot in a shelf <byte 170> ushort bypassa Mask showing bypass state for each slot in a shelf {} Event Information Packet Type: 13 EIP13 - Fibre Channel Services Physical Disk Drive/Mirror Port/Drive Enclosure E nvironmental Monitoring Unit Error summary. Summary of errors encountered while attempting to access a physical disk drive, the mirror port, or a Drive Enclosure Environmental Monitoring Unit. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4>

ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> tag device UUID of the physical disk drive, HSV450 controller, or Drive Enclosur e Environmental Monitoring Unit associated with the event <byte 92> char[8] cerp_id HSV450 controller enclosure rear panel Fibre Channel port attach ed to the physical disk drive or mirror port <byte 100> ulong al_pa AL_PA of the physical disk drive or the mirror port <byte 104> ushort dencl_num Enclosure where the physical disk drive is located <byte 106> ushort port HSV450 controller internal Fibre Channel port number attached to the physical disk drive or mirror port <byte 108> ushort rack_num Rack where the physical disk drive is located <byte 110> ushort bay Enclosure bay where the physical disk drive is located <byte 112> ulong fed_class Fibre Channel Exchange Descriptor class <byte 116>

ulong num_times Number of occurrences of the error. <byte 120> {enclosures[1] (Enclosure available on the Fibre Channel cerp_id and port fields)} <byte 120> utiny rack_num Rack were enclosure is located <byte 121> utiny dencl_num Enclosure number {} <byte 122> {enclosures[0] (Enclosure available on the Fibre Channel cerp_id and port fields)} <byte 122> utiny rack_num Rack were enclosure is located <byte 123> utiny dencl_num Enclosure number {} <byte 124> {enclosures[3] (Enclosure available on the Fibre Channel cerp_id and port fields)} <byte 124> utiny rack_num Rack were enclosure is located <byte 125> utiny dencl_num Enclosure number {} <byte 126> {enclosures[2] (Enclosure available on the Fibre Channel cerp_id and port fields)} <byte 126> utiny rack_num Rack were enclosure is located <byte 127> utiny dencl_num Enclosure number {} <byte 128> {enclosures[5] (Enclosure available on the Fibre Channel cerp_id and port fields)} <byte 128> utiny rack_num Rack were enclosure is located <byte 129> utiny dencl_num Enclosure number {} <byte 130> {enclosures[4] (Enclosure available on the Fibre Channel cerp_id and port fields)} <byte 130> utiny rack_num Rack were enclosure is located <byte 131> utiny dencl_num Enclosure number {} <byte 132> {enclosures[7] (Enclosure available on the Fibre Channel cerp_id and port fields)} <byte 132> utiny rack_num Rack were enclosure is located <byte 133> utiny dencl_num Enclosure number {} <byte 134> {enclosures[6] (Enclosure available on the Fibre Channel cerp_id and port fields)}

port identified in the

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<byte 134> utiny rack_num Rack were enclosure is located <byte 135> utiny dencl_num Enclosure number {} <byte 136> ushort bypass_reason Reason for Drive Enclosure Environmental Monitoring Unit by pass <byte 138> {enclosures[8] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)} <byte 138> utiny rack_num Rack were enclosure is located <byte 139> utiny dencl_num Enclosure number {} <byte 140> char[8] missing_cerp_id HSV450 controller enclosure rear panel Fibre Channel por t that cannot connect to physical disk drive or mirror port <byte 148> ushort bypassa Mask showing bypass state for each slot in a shelf <byte 150> ushort missing_port HSV450 controller internal Fibre Channel port number that ca nnont connect to the physical disk drive or mirror port <byte 152> ushort switch_type Used to represent the type of switch detected (SES or non-SES compliant) <byte 154> ushort bypassb Mask showing bypass state for each slot in a shelf {} Event Information Packet Type: 14 EIP14 - Diagnostic Operations Generator Detected Failure. A failure was detected during the execution of a diagnostic. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16>

char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> {eep_error (Diagnostic error EEPROM data)} <byte 76> utiny padding Pad to longword align this structure <byte 77> utiny count Duplicate error count <byte 78> utiny test_num Test number <byte 79> utiny TE_num TE number <byte 80> ulong Z_code Z's code <byte 84> ulong error_code Error code <byte 88> ulong address Address of Error <byte 92> ulong expected Expected Data <byte 96> ulong actual Actual Data <byte 100> ulonglong uptime Uptime of error {} <byte 108>

ulong dimm_size Size of this HSV450 controller's DIMM in megabytes {} Event Information Packet Type: 15 EIP15 - Container Services Management Operation has started or completed. An operation on a Disk Group has started or completed. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value

endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> tag tag1 UUID of the Virtual Disk, physical disk drive, or Disk Group associated with the event <byte 92> tag tag2 UUID of the Virtual Disk, physical disk drive, or Disk Group associated with the event <byte 108> ulong state Event-specific state value <byte 112> ulong status Event-specific operation status {} Event Information Packet Type: 16 EIP16 - Data Replication Manager Time Report. An Data Replication Manager time synchronization event has occurred. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68>

{header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> uuid sender Enterprise Virtual Array controller initiating time report message <byte 92> uuid receiver Peer controller receiving time report message <byte 108> uuid receiver_partner Other controller in sending or receiving Storage System <byte 124> scmitim sent_time Time message was sent <byte 132> scmitim received_time Time message was received {} Event Information Packet Type: 17 EIP17 - Fibre Channel Services Fibre Channel Port Loop Config A new device map has been generated on a Fibre Channel port. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2>

ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> char[8] cerp_id HSV450 controller enclosure rear panel Fibre Channel port <byte 84> ulong map_id Multi-page map identifier (all pages containing this identifier com prise this map) <byte 88> utiny entries Number of map entries (AL_PAs) in this map <byte 89> utiny total_pages Total pages containing portions of this map <byte 90> utiny page Page number of this loop map event <byte 91> utiny port HSV450 controller internal Fibre Channel port number <byte 92> utiny[92] loop_map Loop configuration information {} Event Information Packet Type: 18

EIP18 - Storage System State Services Redundant Storage Set State Change A Redundant Storage Set state change occurred. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73>

utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> tag ldad_tag Tag of the Disk Group associated with the event <byte 92> ushort target_rss Migration target <byte 94> ushort source_rss Migration source <byte 96> ushort target_migr Migration flags for target <byte 98> ushort source_migr Migration flags for source <byte 100> utiny[16] smembers Volumes in source <byte 116> utiny[16] tmembers Volumes in target {} Event Information Packet Type: 19 EIP19 - System Data Center Services Status Change Status of a System Data Center element has changed. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68>

{header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> {event_type (Entity and Event type)} <byte 76> ushort scmi_object_type Entity type <byte 78> ushort scmi_object_event_type Event Information Packet type {} <byte 80> scmi_obj_hnd handle Storage System Management Interface ------------------------------------------------------------------------- XL only - not used in LE <byte 100> {state (State of SDC monitored component)} <byte 100> ulong old Previous State <byte 104> ulong cur Current State {} <byte 108> {status_code (Status code of SDC monitored component)} <byte 108> ulong old Previous Status Code <byte 112> ulong cur Current Status Code {} <byte 116> {status_data (Status data of SDC monitored component)} <byte 116> ulong old Previous Additional Status Data <byte 120> ulong cur Current Additional Status Data {} <byte 124> ulong[4] comp_states States of SDC monitored components <byte 140> ulong[4] comp_status_codes Status codes of SDC monitored components

<byte 156> ulong[4] comp_status_data Status data of SDC monitored components <byte 172> utiny reserved3 <byte 173> utiny reserved2 <byte 174> utiny reserved1 <byte 175> utiny controller_number <byte 176> {component (Component status)} <byte 176> utiny sub_condition Component sub-condition <byte 177> utiny condition Component condition <byte 178> utiny state Component State <byte 179> utiny number Component number <byte 180> utiny[4] data Additional data <byte 184> char[8] label Component label {} <byte 192> char[16] assembly_part_number <byte 208> char[16] assembly_serial_number <byte 224> char[4] hardware_revision <byte 228> char[4] firmware_revision <byte 232> char[16] salable_product_number <byte 248> char[12] salable_serial_number <byte 260> char[16] spare_part_number <byte 276> char[8] vendor_id <byte 284> char[16] product_id <byte 300> char[64] degraded_subcomponents {} Event Information Packet Type: 1a EIP1A - System Services Code Load Operation Update A code load operation has occurred. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re

conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> char[40] state State information <byte 116> char[36] hardware Hardware information <byte 152> char[32] versions Version information <byte 184> char[32] code_version New code version.

{} Event Information Packet Type: 1b EIP1B - Host Port Event A Host Port Event Occurred {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union

<byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> tag scvd_tag Associated Storage System Virtual Disk UUID <byte 92> ulong data Event specific data New fields for revision 4 // <byte 96> tag lun_wwid Lun WWID for this vdisk <byte 112> utiny active IO on active queue <byte 113> utiny host Pending Host Quiesces <byte 114> utiny deferred Pending Deferred Quiesces <byte 115> utiny pending Pending Quiesces <byte 116> utiny presented_other Presented to other controller <byte 117> utiny presented_this Presented to reporting controller <byte 118> utiny suspended IO on suspended queue <byte 119> utiny inactive IO on inactive queue <byte 120> ulong vdsb_flags VDSB Flags <byte 124> ushort drmio DRM IO count outstanding <byte 126> ushort group DRM Unit <byte 128> ushort reserved Reserved for future use. <byte 130> utiny drmcmprefetch DRM CM Prefetch <byte 131> utiny drmcmflushing DRM CM Flushing {} Event Information Packet Type: 1c EIP1C - Fault Manager Termination Event HSV450 controller operation terminated event report. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un

til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> {lteihd (Last Termination Event Information Header)} <byte 76> {flags (Last Termination Event flags)} <byte 76> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Termination event sequence number reset occurred tbits:1 cccc_forced Coupled crash forced tbits:1 rsvd Pad to fill byte tbits:1 labcode Event reported using LAB code

tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 77> utiny revision Structure revision number <byte 78> ushort size Structure size {} <byte 80> {lter (Last Termination Event Report Block)} <byte 80> ulong seq Sequence number assigned to the termination event <byte 84> char[8] sw_version HSV450 controller software version number string <byte 92> char[12] baselevel_id HSV450 controller baselevel build string <byte 104> char[8] ctrlr_model_id HSV450 controller model string <byte 112> scmi_obj_hnd terminating_ctrlr Storage System Management Interface Handle of HSV 450 controller that terminated operation <byte 132> scmitim termination_time Time termination event occurred <byte 140> {termination_event (Termination event information)} <byte 140> ulong termination_location Location of termination event report call <byte 144> union u Termination Code Union <byte 144> {code (Termination Code)} <byte 144> tbits:5 parc Parameter Count tbits:2 drcc Dump/Restart Control Code tbits:1 cccc Coupled Crash Control Code <byte 145> cacode cac Corrective Action Code <byte 146> utiny evnum Event Number <byte 147> utiny scid HSV450 Controller Software Component Identification {} or u Termination Code Union <byte 144> ulong value Termination Code Value endunion u Termination Code Union <byte 148> {params (Termination Parameters)} <byte 148> ulong[31] param Termination Parameters {} {} <byte 272> utiny[2] reserved Reserved <byte 274> {flags (Other Last Termination Event flags)} <byte 274> tbits:1 lg_send_sts Last Gasp send status tbits:1 stack_bad Stack contains pointer outside stack area

tbits:1 stack_guard_bad System or process stack guard value(s) overwritten tbits:1 short_term_path Short termination path taken tbits:1 feb_saved Final Event Block saved tbits:3 rsvd Pad to fill byte {} <byte 275> utiny reuea_index Termination Processing Recursive Entry Event or Unexpected Eve nt array index <byte 276> ulonglong uptime Number of seconds HSV450 controller has run functional code {} {} Event Information Packet Type: 1d EIP1D - Fault Manager Termination Event (old Termination Event Information Heade r) HSV450 controller operation terminated event report. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68>

utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> {lteihd (Last Termination Event Information Header)} <byte 76> {flags (Last Termination Event flags)} <byte 76> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Termination event sequence number reset occurred tbits:1 cccc_forced Coupled crash forced tbits:1 stack_bad Stack contains pointer outside stack area tbits:1 stack_guard_bad System or process stack guard value(s) overwritten tbits:1 short_term_path Short termination path taken tbits:1 feb_saved Final Event Block saved {} <byte 77> utiny revision Structure revision number <byte 78> ushort size Structure size {} <byte 80> {lter (Nonstandard Last Termination Event Report Block)} <byte 80> ulong seq Sequence number assigned to the termination event <byte 84> char[4] sw_version HSV450 controller software version number string <byte 88> char[12] baselevel_id HSV450 controller baselevel build string <byte 100> char[8] ctrlr_model_id HSV450 controller model string <byte 108> scmi_obj_hnd terminating_ctrlr Storage System Management Interface Handle of HSV 450 controller that terminated operation <byte 128> scmitim termination_time Time termination event occurred <byte 136> {termination_event (Termination event information)} <byte 136> ulong termination_location Location of termination event report call <byte 140> union u Termination Code Union

<byte 140> {code (Termination Code)} <byte 140> tbits:5 parc Parameter Count tbits:2 drcc Dump/Restart Control Code tbits:1 cccc Coupled Crash Control Code <byte 141> cacode cac Corrective Action Code <byte 142> utiny evnum Event Number <byte 143> utiny scid HSV450 Controller Software Component Identification {} or u Termination Code Union <byte 140> ulong value Termination Code Value endunion u Termination Code Union {} <byte 144> utiny[2] reserved Reserved <byte 146> utiny lg_send_sts Last Gasp send status <byte 147> utiny reuea_index Termination Processing Recursive Entry Event or Unexpected Eve nt array index <byte 148> ulonglong uptime Number of seconds HSV450 controller has run functional code {} {} Event Information Packet Type: 1e EIP1E - General Storage System State Services State Information Event General Storage System state information to be reported. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string

<byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> char[12] info Informational String <byte 88> ulong[24] data Informational Data {} Event Information Packet Type: 1f EIP1F - A Storage System Virtual Disk has changed controller mastership. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {}

<byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> tag ld_tag Logical disk <byte 92> tag du_tag Derived unit <byte 108> tag scvd_tag Storage System Virtual Disk <byte 124> {prev_wwn (Previous Controller)} <byte 124> ulong hi (Bits 31:28) Network Address Authority Code, (Bits 27:4) Company ID, (B its 3:0) Type <byte 128> ulong lo (Bits 31:4) Node Number, (Bits 3:0) Port {} <byte 132>

{current_wwn (Current Controller)} <byte 132> ulong hi (Bits 31:28) Network Address Authority Code, (Bits 27:4) Company ID, (B its 3:0) Type <byte 136> ulong lo (Bits 31:4) Node Number, (Bits 3:0) Port {} {} Event Information Packet Type: 20 EIP20 - Storage System State Services Controller FC Port event {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71>

utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> {node_name (World Wide Name of HSV450 controller)} <byte 76> ulong hi (Bits 31:28) Network Address Authority Code, (Bits 27:4) Company ID, (B its 3:0) Type <byte 80> ulong lo (Bits 31:4) Node Number, (Bits 3:0) Port {} <byte 84> ulong port Loop port number <byte 88> ulong data Event-specific data {} Event Information Packet Type: 21 EIP21 - General purpose SCS Logical Disk synchronization event {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45

0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> tag target_tag Target Tag <byte 92> tag parent_tag Parent Tag <byte 108> ulong operation Operation <byte 112> ulong status Status <byte 116> ulong prev_state Previous State <byte 120> ulong new_state New State <byte 124> ulong redundancy Redundancy Type <byte 128> ulonglong size SCVD Size <byte 136> tag aux_tag Auxillary Tag {} Event Information Packet Type: 23 EIP23 - State configuration error events {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t

he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> {device_wwn (World Wide Name of relevant HSV450 controller or physical disk driv e)} <byte 76> ulong hi (Bits 31:28) Network Address Authority Code, (Bits 27:4) Company ID, (B

its 3:0) Type <byte 80> ulong lo (Bits 31:4) Node Number, (Bits 3:0) Port {} <byte 84> ulong scs_flags SCS flags <byte 88> ulong scs_flags2 SCS flags2 <byte 92> ulong data Generic data <byte 96> ulong data2 Generic data <byte 100> ulong[8] port_state Current port states <byte 132> ulong[8] master_port_state Current port connectivity on master. <byte 164> ulong[8] slave_port_state Current port connectivity on slave. <byte 196> ulong[8] master_prev_port_state Previous port connectivity on master. <byte 228> ulong[8] slave_prev_port_state Previous port connectivity on slave. {} Event Information Packet Type: 24 EIP24 - Host Port Event A Host Port Event Occurred {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56>

scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> ulong[5] data Event specific data {} Event Information Packet Type: 26 EIP26 - ECC error counter events {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string

<byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> {ecc_cnt (No description available)} <byte 76> ulong time_since_reset time since last reset <byte 80> ulong policy_mem_size policy memory size <byte 84> ulong cache_mem_size cache memory size <byte 88> ulong ecc_count ecc errors count <byte 92> ulong ecc_previous_count ecc errors previous count {} {} Event Information Packet Type: 27 EIP27 - Battery policy changed {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller

tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> {node_name (World Wide Name of)} <byte 76> ulong hi (Bits 31:28) Network Address Authority Code, (Bits 27:4) Company ID, (B

its 3:0) Type <byte 80> ulong lo (Bits 31:4) Node Number, (Bits 3:0) Port {} <byte 84> ulong old_battery_state_this old battery state this controller <byte 88> ulong old_battery_state_other old battery state other controller <byte 92> ulong old_battery_cache_state old battery cache state <byte 96> ulong new_battery_state_this new battery state this controller <byte 100> ulong new_battery_state_other new battery state other controller <byte 104> ulong new_battery_cache_state new battery cache state {} Event Information Packet Type: 28 EIP28 - Fibre Channel Services Fibre Channel Port Link Transition A Fibre Channel port link has come up or gone down. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68>

union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> {node_name (World Wide Name of HSV450 controller)} <byte 76> ulong hi (Bits 31:28) Network Address Authority Code, (Bits 27:4) Company ID, (B its 3:0) Type <byte 80> ulong lo (Bits 31:4) Node Number, (Bits 3:0) Port {} <byte 84> char[8] cerp_id HSV450 controller enclosure rear panel Fibre Channel port <byte 92> utiny port_count Then number of ports on the device <byte 93> utiny level The level of the link transition: 0: Low - TSDK Layer 1: High - Stat e Layer <byte 94> utiny status The status of the link transition: 0: Link went down 1: Link came u p <byte 95> utiny port HSV450 controller internal Fibre Channel port number <byte 96> ulong[8] fm_status The FM status for each Fibre Channel port on this controller Note: This can change size depending on the controller port count {} Event Information Packet Type: 29 EIP29 A physical disk drive has experienced an ID block inconsistency. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re

conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45 0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> ushort idb_write_status keeps state of the ID block write <byte 78> ushort instance 4 parts of code will trap the ID mismatch <byte 80> {cached_node_name (the cached wwn)} <byte 80> ulong hi (Bits 31:28) Network Address Authority Code, (Bits 27:4) Company ID, (B

its 3:0) Type <byte 84> ulong lo (Bits 31:4) Node Number, (Bits 3:0) Port {} <byte 88> {last_poll_node_name (the wwn as of last poll)} <byte 88> ulong hi (Bits 31:28) Network Address Authority Code, (Bits 27:4) Company ID, (B its 3:0) Type <byte 92> ulong lo (Bits 31:4) Node Number, (Bits 3:0) Port {} <byte 96> tag cached_ps_tag the cached ps tag <byte 112> tag id_ps_tag the ps tag read from disk <byte 128> tag cached_vol_tag the cached vol tag <byte 144> tag id_vol_tag the vol tab read from disk <byte 160> ushort bay drive bay <byte 162> ushort enclosure the drive shelf {} Event Information Packet Type: 2a EIP2A - Information report when CVM quorum update fails on at least one drive. {Event Log Packet Event Specific Information} <byte 0> {flags (Flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Event sequence number reset occurred tbits:1 outofsequence Event reported out of sequence due to Final Event Block re conciliation or lost host event tbits:1 requeued Event requeued following restart or resynchronization tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort count Event specific information size in bytes <byte 4> ulong sequence_number Sequence number assigned to the event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV45

0 controller that reported the event <byte 56> scmitim report_time Time event was reported <byte 64> ulong report_location Location of event report call <byte 68> {header (Header Information)} <byte 68> union u Event Code Union <byte 68> {ec (Event Code)} <byte 68> utiny eiptype Event Information Packet Type Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Event Code Union <byte 68> ulong value Event Code Value endunion u Event Code Union <byte 72> utiny revision Packet revision number <byte 73> utiny type Packet type <byte 74> ushort count Number of bytes in packet {} <byte 76> ulong io_mask quorum io mask <byte 80> ulong rss0_member_mask current state mask <byte 84> ulong success_rewrite rewritten RSS0 count <byte 88> ulong incarnation new incarnation {} TERMINATION EVENT BLOCK: {Termination Event Block} <byte 0> union u Last Termination Event Block Union <byte 0> {data (Termination Event Block Data)} <byte 0> {ltei (Last Termination Event Information)} <byte 0> {lteihd (Last Termination Event Information Header)} <byte 0> {flags (Last Termination Event flags)} <byte 0> tbits:1 time_set Time has been set on this HSV450 controller tbits:1 time_synched Time has been synchronized with all HSV450 controllers in t he Storage System tbits:1 seq_reset Termination event sequence number reset occurred tbits:1 cccc_forced Coupled crash forced

tbits:1 rsvd Pad to fill byte tbits:1 labcode Event reported using LAB code tbits:1 prictrlr Event reported by primary HSV450 controller (Note: Not valid un til Storage System primary HSV450 controller is elected) tbits:1 spsctrlr Single power supply HSV450 controller {} <byte 1> utiny revision Structure revision number <byte 2> ushort size Structure size {} <byte 4> {lter (Last Termination Event Report Block)} <byte 4> ulong seq Sequence number assigned to the termination event <byte 8> char[8] sw_version HSV450 controller software version number string <byte 16> char[12] baselevel_id HSV450 controller baselevel build string <byte 28> char[8] ctrlr_model_id HSV450 controller model string <byte 36> scmi_obj_hnd terminating_ctrlr Storage System Management Interface Handle of HSV 450 controller that terminated operation <byte 56> scmitim termination_time Time termination event occurred <byte 64> {termination_event (Termination event information)} <byte 64> ulong termination_location Location of termination event report call <byte 68> union u Termination Code Union <byte 68> {code (Termination Code)} <byte 68> tbits:5 parc Parameter Count tbits:2 drcc Dump/Restart Control Code tbits:1 cccc Coupled Crash Control Code <byte 69> cacode cac Corrective Action Code <byte 70> utiny evnum Event Number <byte 71> utiny scid HSV450 Controller Software Component Identification {} or u Termination Code Union <byte 68> ulong value Termination Code Value endunion u Termination Code Union <byte 72> {params (Termination Parameters)} <byte 72> ulong[31] param Termination Parameters {} {} <byte 196> utiny[2] reserved Reserved <byte 198> {flags (Other Last Termination Event flags)} <byte 198>

tbits:1 lg_send_sts Last Gasp send status tbits:1 stack_bad Stack contains pointer outside stack area tbits:1 stack_guard_bad System or process stack guard value(s) overwritten tbits:1 short_term_path Short termination path taken tbits:1 feb_saved Final Event Block saved tbits:3 rsvd Pad to fill byte {} <byte 199> utiny reuea_index Termination Processing Recursive Entry Event or Unexpected Eve nt array index <byte 200> ulonglong uptime Number of seconds HSV450 controller has run functional code {} <byte 208> {sa (Exception save area)} <byte 208> ulong[32] registers R0-R31 <byte 336> union int_level The level of interrupt machine, external or critical <byte 336> {standard (standard)} <byte 336> ulong srr0 SRR0 <byte 340> ulong srr1 SRR1 {} or int_level The level of interrupt machine, external or critical <byte 336> {machine (No description available)} <byte 336> ulong mcsrr0 MCSRR0 <byte 340> ulong mcsrr1 MCSRR1 {} or int_level The level of interrupt machine, external or critical <byte 336> {critical (No description available)} <byte 336> ulong csrr0 CSRR0 <byte 340> ulong csrr1 CSRR1 {} endunion int_level The level of interrupt machine, external or critical <byte 344> ulong cr CR <byte 348> ulong xer XER <byte 352> ulong esr ESR <byte 356> ulong ctr CTR <byte 360> ulong lr LR <byte 364> ulong exception Exception Code <byte 368> union optional Machine check or DSI exception values <byte 368> {mcp (Machine check values)} <byte 368>

ulong mc_count Exception Count <byte 372> ulong mcsr MCSR Register or MCSRR0 Register {} or optional Machine check or DSI exception values <byte 368> {dsi (DSI exception values)} <byte 368> ulong dsisr DSI Status Register <byte 372> ulong dear DEAR Register (440) or DAR Register (7448) {} endunion optional Machine check or DSI exception values <byte 376> ulong pid PID <byte 380> ulong usprg0 usprg0 {} <byte 384> char[8] current_process Current process name <byte 392> {stack (Stack information)} <byte 392> ulong stack_depth Total calls made <byte 396> {stack[0] (Stack entries)} <byte 396> ulong bc Back chain (old stack pointer) <byte 400> ulong slr Saved link register {} <byte 404> {stack[1] (Stack entries)} <byte 404> ulong bc Back chain (old stack pointer) <byte 408> ulong slr Saved link register {} <byte 412> {stack[2] (Stack entries)} <byte 412> ulong bc Back chain (old stack pointer) <byte 416> ulong slr Saved link register {} <byte 420> {stack[3] (Stack entries)} <byte 420> ulong bc Back chain (old stack pointer) <byte 424> ulong slr Saved link register {} <byte 428> {stack[4] (Stack entries)} <byte 428> ulong bc Back chain (old stack pointer) <byte 432> ulong slr Saved link register {} <byte 436>

{stack[5] (Stack entries)} <byte 436> ulong bc Back chain (old stack <byte 440> ulong slr Saved link register {} <byte 444> {stack[6] (Stack entries)} <byte 444> ulong bc Back chain (old stack <byte 448> ulong slr Saved link register {} <byte 452> {stack[7] (Stack entries)} <byte 452> ulong bc Back chain (old stack <byte 456> ulong slr Saved link register {} <byte 460> {stack[8] (Stack entries)} <byte 460> ulong bc Back chain (old stack <byte 464> ulong slr Saved link register {} <byte 468> {stack[9] (Stack entries)} <byte 468> ulong bc Back chain (old stack <byte 472> ulong slr Saved link register {} <byte 476> {stack[10] (Stack entries)} <byte 476> ulong bc Back chain (old stack <byte 480> ulong slr Saved link register {} <byte 484> {stack[11] (Stack entries)} <byte 484> ulong bc Back chain (old stack <byte 488> ulong slr Saved link register {} <byte 492> {stack[12] (Stack entries)} <byte 492> ulong bc Back chain (old stack <byte 496> ulong slr Saved link register {} <byte 500> {stack[13] (Stack entries)} <byte 500> ulong bc Back chain (old stack <byte 504>

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ulong slr Saved link register {} <byte 508> {stack[14] (Stack entries)} <byte 508> ulong bc Back chain (old stack <byte 512> ulong slr Saved link register {} <byte 516> {stack[15] (Stack entries)} <byte 516> ulong bc Back chain (old stack <byte 520> ulong slr Saved link register {} <byte 524> {stack[16] (Stack entries)} <byte 524> ulong bc Back chain (old stack <byte 528> ulong slr Saved link register {} <byte 532> {stack[17] (Stack entries)} <byte 532> ulong bc Back chain (old stack <byte 536> ulong slr Saved link register {} <byte 540> {stack[18] (Stack entries)} <byte 540> ulong bc Back chain (old stack <byte 544> ulong slr Saved link register {} <byte 548> {stack[19] (Stack entries)} <byte 548> ulong bc Back chain (old stack <byte 552> ulong slr Saved link register {} <byte 556> {stack[20] (Stack entries)} <byte 556> ulong bc Back chain (old stack <byte 560> ulong slr Saved link register {} <byte 564> {stack[21] (Stack entries)} <byte 564> ulong bc Back chain (old stack <byte 568> ulong slr Saved link register {} <byte 572> {stack[22] (Stack entries)}

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<byte 572> ulong bc Back chain (old stack <byte 576> ulong slr Saved link register {} <byte 580> {stack[23] (Stack entries)} <byte 580> ulong bc Back chain (old stack <byte 584> ulong slr Saved link register {} <byte 588> {stack[24] (Stack entries)} <byte 588> ulong bc Back chain (old stack <byte 592> ulong slr Saved link register {} <byte 596> {stack[25] (Stack entries)} <byte 596> ulong bc Back chain (old stack <byte 600> ulong slr Saved link register {} <byte 604> {stack[26] (Stack entries)} <byte 604> ulong bc Back chain (old stack <byte 608> ulong slr Saved link register {} <byte 612> {stack[27] (Stack entries)} <byte 612> ulong bc Back chain (old stack <byte 616> ulong slr Saved link register {} <byte 620> {stack[28] (Stack entries)} <byte 620> ulong bc Back chain (old stack <byte 624> ulong slr Saved link register {} <byte 628> {stack[29] (Stack entries)} <byte 628> ulong bc Back chain (old stack <byte 632> ulong slr Saved link register {} <byte 636> {stack[30] (Stack entries)} <byte 636> ulong bc Back chain (old stack <byte 640> ulong slr Saved link register

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{} <byte 644> {stack[31] (Stack entries)} <byte 644> ulong bc Back chain (old stack pointer) <byte 648> ulong slr Saved link register {} <byte 652> *ptr *bad_stack_ptr Bad stack address <byte 656> ulong system_stack_guard System stack guard intact flags (set to 1 if not intact ) <byte 660> ulong[16] stack_guard Process stack guard intact flags (set to 1 if not intact) {} <byte 724> {hardware (Hardware registers)} <byte 724> {flags (Hardware registers gathered flags)} <byte 724> lbits:1 uartdrd SC28L194 Quad UART d data registers gathered lbits:1 uartdrc SC28L194 Quad UART c data registers gathered lbits:1 uartdrb SC28L194 Quad UART b data registers gathered lbits:1 uartdra SC28L194 Quad UART a data registers gathered lbits:1 uartcrd SC28L194 Quad UART d control registers gathered lbits:1 uartcrc SC28L194 Quad UART c control registers gathered lbits:1 uartcrb SC28L194 Quad UART b control registers gathered lbits:1 uartcra SC28L194 Quad UART a control registers gathered lbits:1 sprite_csr Sprite Chip CSR registers gathered lbits:1 glue_csr Glue Chip CSR registers gathered lbits:1 toyclock DS1557 4MEG NV Y2KC Timekeeping RAM registers gathered lbits:1 decoder_csr Decoder lbits:1 atlantis_csr Atlantis (Crash Dump only) lbits:1 atlantis_mcs Atlantis machine check specific registers (Termination even t only) lbits:1 atlantis_a1 Atlantis Area 1 miscellaneous registers (Termination event o nly) lbits:1 aa2 Atlantis registers--Area 2 (Termination event only) lbits:1 aa3 Atlantis registers--Area 3 (Termination event only) lbits:15 rsvd Reserved {} <byte 728> {tach_flags (Tachyon registers gathered flags)} <byte 728> lbits:1 tachyon9_csr Tachyon 9 CSR registers gathered lbits:1 tachyon9_pcicfg Tachyon 9 PCI Configuration lbits:1 tachyon9_gbic Tachyon 9 GBIC Small Form Factor ID lbits:1 tachyon8_csr Tachyon 8 CSR registers gathered lbits:1 tachyon8_pcicfg Tachyon 8 PCI Configuration lbits:1 tachyon8_gbic Tachyon 8 GBIC Small Form Factor ID lbits:1 tachyon7_csr Tachyon 7 CSR registers gathered lbits:1 tachyon7_pcicfg Tachyon 7 PCI Configuration lbits:1 tachyon7_gbic Tachyon 7 GBIC Small Form Factor ID lbits:1 tachyon6_csr Tachyon 6 CSR registers gathered lbits:1 tachyon6_pcicfg Tachyon 6 PCI Configuration lbits:1 tachyon6_gbic Tachyon 6 GBIC Small Form Factor ID lbits:1 tachyon5_csr Tachyon 5 CSR registers gathered lbits:1 tachyon5_pcicfg Tachyon 5 PCI Configuration lbits:1 tachyon5_gbic Tachyon 5 GBIC Small Form Factor ID

lbits:1 tachyon4_csr Tachyon 4 CSR registers gathered lbits:1 tachyon4_pcicfg Tachyon 4 PCI Configuration lbits:1 tachyon4_gbic Tachyon 4 GBIC Small Form Factor ID lbits:1 tachyon3_csr Tachyon 3 CSR registers gathered lbits:1 tachyon3_pcicfg Tachyon 3 PCI Configuration lbits:1 tachyon3_gbic Tachyon 3 GBIC Small Form Factor ID lbits:1 tachyon2_csr Tachyon 2 CSR registers gathered lbits:1 tachyon2_pcicfg Tachyon 2 PCI Configuration lbits:1 tachyon2_gbic Tachyon 2 GBIC Small Form Factor ID lbits:1 tachyon1_csr Tachyon 1 CSR registers gathered lbits:1 tachyon1_pcicfg Tachyon 1 PCI Configuration lbits:1 tachyon1_gbic Tachyon 1 GBIC Small Form Factor ID lbits:1 tachyon0_csr Tachyon 0 CSR registers gathered lbits:1 tachyon0_pcicfg Tachyon 0 PCI Configuration lbits:1 tachyon0_gbic Tachyon 0 GBIC Small Form Factor ID lbits:2 rsvd Reserved {} <byte 732> {tach_flags2 (Tachyon registers gathered flags)} <byte 732> lbits:26 rsvd Reserved lbits:1 tachyon11_csr Tachyon 11 CSR registers gathered lbits:1 tachyon11_pcicfg Tachyon 11 PCI Configuration lbits:1 tachyon11_gbic Tachyon 11 GBIC Small Form Factor ID lbits:1 tachyon10_csr Tachyon 10 CSR registers gathered lbits:1 tachyon10_pcicfg Tachyon 10 PCI Configuration lbits:1 tachyon10_gbic Tachyon 10 GBIC Small Form Factor ID {} <byte 736> {tach_ncfg_flags (Tachyon non-configuration registers gathered flags)} <byte 736> lbits:1 tachyon9_ncfghi Tachyon 9 Non-configuration--high registers gathered lbits:1 tachyon9_ncfglo Tachyon 9 Non-configuration--low registers gathered lbits:1 tachyon8_ncfghi Tachyon 8 Non-configuration--high registers gathered lbits:1 tachyon8_ncfglo Tachyon 8 Non-configuration--low registers gathered lbits:1 tachyon7_ncfghi Tachyon 7 Non-configuration--high registers gathered lbits:1 tachyon7_ncfglo Tachyon 7 Non-configuration--low registers gathered lbits:1 tachyon6_ncfghi Tachyon 6 Non-configuration--high registers gathered lbits:1 tachyon6_ncfglo Tachyon 6 Non-configuration--low registers gathered lbits:1 tachyon5_ncfghi Tachyon 5 Non-configuration--high registers gathered lbits:1 tachyon5_ncfglo Tachyon 5 Non-configuration--low registers gathered lbits:1 tachyon4_ncfghi Tachyon 4 Non-configuration--high registers gathered lbits:1 tachyon4_ncfglo Tachyon 4 Non-configuration--low registers gathered lbits:1 tachyon3_ncfghi Tachyon 3 Non-configuration--high registers gathered lbits:1 tachyon3_ncfglo Tachyon 3 Non-configuration--low registers gathered lbits:1 tachyon2_ncfghi Tachyon 2 Non-configuration--high registers gathered lbits:1 tachyon2_ncfglo Tachyon 2 Non-configuration--low registers gathered lbits:1 tachyon1_ncfghi Tachyon 1 Non-configuration--high registers gathered lbits:1 tachyon1_ncfglo Tachyon 1 Non-configuration--low registers gathered lbits:1 tachyon0_ncfghi Tachyon 0 Non-configuration--high registers gathered lbits:1 tachyon0_ncfglo Tachyon 0 Non-configuration--low registers gathered lbits:1 tachyon10_ncfghi Tachyon 1 Non-configuration--high registers gathered lbits:1 tachyon10_ncfglo Tachyon 1 Non-configuration--low registers gathered lbits:1 tachyon11_ncfghi Tachyon 0 Non-configuration--high registers gathered lbits:1 tachyon11_ncfglo Tachyon 0 Non-configuration--low registers gathered lbits:8 rsvd Reserved {} <byte 740> {aa3 (Atlantis registers--Area3)} <byte 740>

ulong[518] reserved Reserved for future use {} <byte 2812> {aa2 (Atlantis registers--Area2)} <byte 2812> ulong[200] reserved Reserved for future use {} <byte 3612> {atlantis_a1 (Atlantis Area 1 miscellaneous registers)} <byte 3612> union cpu_configuration (Offset 0x0000) CPU Configuration <byte 3612> {field (By field)} <byte 3612> lbits:8 nomatchcnt RW CPU Address Miss Counter lbits:1 nomatchcnten RW CPU Address Miss Counter Enable lbits:1 nomatchcntext RW CPU address miss counter MSB lbits:1 reserved4 RES Reserved lbits:1 singlecpu RW 0 = Dual CPU. 1 = Single CPU lbits:1 endianess RW CPU Bus Byte Orientation. Must be 0 lbits:1 pipeline RW Pipeline Enable lbits:3 reserved3 RES Reserved lbits:1 stopretry RW Stop to retry transactions from PCI lbits:1 multigtdec RW Multi-GT Address Decode lbits:1 dpvalid RW CPU DP[0-7] Connection lbits:2 reserved2 RES Reserved lbits:1 perrprop RW Parity Error Propagation lbits:2 reserved1 RES Reserved lbits:1 aackdelay2 RW AACK# earliest assertion following TS# lbits:1 apvalid RW CPU AP[0-3] Connection lbits:1 remapwrdis RW Address Remap Registers Write Control lbits:4 reserved0 RES Reserved {} or cpu_configuration (Offset 0x0000) CPU Configuration <byte 3612> ulong value As longword endunion cpu_configuration (Offset 0x0000) CPU Configuration <byte 3616> union cs_0_base_address (Offset 0x0008) CS[0]# Base Address <byte 3616> {field (By field)} <byte 3616> lbits:20 base RW Base Address lbits:12 reserved0 RES Reserved {} or cs_0_base_address (Offset 0x0008) CS[0]# Base Address <byte 3616> ulong value As longword endunion cs_0_base_address (Offset 0x0008) CS[0]# Base Address <byte 3620> union cs_0_size (Offset 0x0010) CS[0]# Size <byte 3620> {field (By field)} <byte 3620> lbits:16 size RW Bank Size lbits:16 reserved0 RES Reserved {} or cs_0_size (Offset 0x0010) CS[0]# Size <byte 3620> ulong value As longword

endunion cs_0_size (Offset 0x0010) CS[0]# Size <byte 3624> union cs_2_base_address (Offset 0x0018) CS[2]# Base Address <byte 3624> {field (By field)} <byte 3624> lbits:20 base RW Base Address lbits:12 reserved0 RES Reserved {} or cs_2_base_address (Offset 0x0018) CS[2]# Base Address <byte 3624> ulong value As longword endunion cs_2_base_address (Offset 0x0018) CS[2]# Base Address <byte 3628> union cs_2_size (Offset 0x0020) CS[2]# Size <byte 3628> {field (By field)} <byte 3628> lbits:16 size RW Bank Size lbits:16 reserved0 RES Reserved {} or cs_2_size (Offset 0x0020) CS[2]# Size <byte 3628> ulong value As longword endunion cs_2_size (Offset 0x0020) CS[2]# Size <byte 3632> union cs_1_base_address (Offset 0x0208) CS[1]# Base Address <byte 3632> {field (By field)} <byte 3632> lbits:20 base RW Base Address lbits:12 reserved0 RES Reserved {} or cs_1_base_address (Offset 0x0208) CS[1]# Base Address <byte 3632> ulong value As longword endunion cs_1_base_address (Offset 0x0208) CS[1]# Base Address <byte 3636> union cs_1_size (Offset 0x0210) CS[1]# Size <byte 3636> {field (By field)} <byte 3636> lbits:16 size RW Bank Size lbits:16 reserved0 RES Reserved {} or cs_1_size (Offset 0x0210) CS[1]# Size <byte 3636> ulong value As longword endunion cs_1_size (Offset 0x0210) CS[1]# Size <byte 3640> union cs_3_base_address (Offset 0x0218) CS[3]# Base Address <byte 3640> {field (By field)} <byte 3640> lbits:20 base RW Base Address lbits:12 reserved0 RES Reserved {} or cs_3_base_address (Offset 0x0218) CS[3]# Base Address <byte 3640> ulong value As longword

endunion cs_3_base_address (Offset 0x0218) CS[3]# Base Address <byte 3644> union cs_3_size (Offset 0x0220) CS[3]# Size <byte 3644> {field (By field)} <byte 3644> lbits:16 size RW Bank Size lbits:16 reserved0 RES Reserved {} or cs_3_size (Offset 0x0220) CS[3]# Size <byte 3644> ulong value As longword endunion cs_3_size (Offset 0x0220) CS[3]# Size <byte 3648> union base_address_enable (Offset 0x0278) Base Address Enable <byte 3648> {field (By field)} <byte 3648> lbits:1 encs_0 RW CS[0] base address enable lbits:1 encs_1 RW CS[1] base address enable lbits:1 encs_2 RW CS[2] base address enable lbits:1 encs_3 RW CS[3] base address enable lbits:1 endevcs_0 RW DevCS[0] base address enable lbits:1 endevcs_1 RW DevCS[1] base address enable lbits:1 endevcs_2 RW DevCS[2] base address enable lbits:1 endevcs_3 RW DevCS[3] base address enable lbits:1 enbootcs RW BootCS base address enable lbits:1 enpci_0_io RW PCI_0 I/O base address enable lbits:1 enpci_0_mem0 RW PCI_0 Mem0 base address enable lbits:1 enpci_0_mem1 RW PCI_0 Mem1 base address enable lbits:1 enpci_0_mem2 RW PCI_0 Mem2 base address enable lbits:1 enpci_0_mem3 RW PCI_0 Mem3 base address enable lbits:1 enpci_1_io RW PCI_1 I/O base address enable lbits:1 enpci_1_mem0 RW PCI_1 Mem0 base address enable lbits:1 enpci_1_mem1 RW PCI_1 Mem1 base address enable lbits:1 enpci_1_mem2 RW PCI_1 Mem2 base address enable lbits:1 enpci_1_mem3 RW PCI_1 Mem3 base address enable lbits:1 enintegr_sram RW Integrated SRAM base address enable lbits:1 eninter_space RW Internal Space base address enable lbits:11 reserved0 RES Reserved {} or base_address_enable (Offset 0x0278) Base Address Enable <byte 3648> ulong value As longword endunion base_address_enable (Offset 0x0278) Base Address Enable <byte 3652> union idma_channel_0_dma_byte_count (Offset 0x0800) IDMA Channel 0 DMA Byte Coun t <byte 3652> {field (By field)} <byte 3652> lbits:24 bytecnt RW Number of bytes left for the DMA to transfer lbits:6 reserved0 RES Reserved lbits:1 bcleft RW Left Byte Count lbits:1 own RW Ownership Bit {} or idma_channel_0_dma_byte_count (Offset 0x0800) IDMA Channel 0 DMA Byte Count <byte 3652> ulong value As longword endunion idma_channel_0_dma_byte_count (Offset 0x0800) IDMA Channel 0 DMA Byte C

ount <byte 3656> union idma_channel_1_dma_byte_count (Offset 0x0804) IDMA Channel 1 DMA Byte Coun t <byte 3656> {field (By field)} <byte 3656> lbits:24 bytecnt RW Number of bytes left for the DMA to transfer lbits:6 reserved0 RES Reserved lbits:1 bcleft RW Left Byte Count lbits:1 own RW Ownership Bit {} or idma_channel_1_dma_byte_count (Offset 0x0804) IDMA Channel 1 DMA Byte Count <byte 3656> ulong value As longword endunion idma_channel_1_dma_byte_count (Offset 0x0804) IDMA Channel 1 DMA Byte C ount <byte 3660> union idma_channel_2_dma_byte_count (Offset 0x0808) IDMA Channel 2 DMA Byte Coun t <byte 3660> {field (By field)} <byte 3660> lbits:24 bytecnt RW Number of bytes left for the DMA to transfer lbits:6 reserved0 RES Reserved lbits:1 bcleft RW Left Byte Count lbits:1 own RW Ownership Bit {} or idma_channel_2_dma_byte_count (Offset 0x0808) IDMA Channel 2 DMA Byte Count <byte 3660> ulong value As longword endunion idma_channel_2_dma_byte_count (Offset 0x0808) IDMA Channel 2 DMA Byte C ount <byte 3664> union idma_channel_3_dma_byte_count (Offset 0x080C) IDMA Channel 3 DMA Byte Coun t <byte 3664> {field (By field)} <byte 3664> lbits:24 bytecnt RW Number of bytes left for the DMA to transfer lbits:6 reserved0 RES Reserved lbits:1 bcleft RW Left Byte Count lbits:1 own RW Ownership Bit {} or idma_channel_3_dma_byte_count (Offset 0x080C) IDMA Channel 3 DMA Byte Count <byte 3664> ulong value As longword endunion idma_channel_3_dma_byte_count (Offset 0x080C) IDMA Channel 3 DMA Byte C ount <byte 3668> union idma_channel_0_dma_source_address (Offset 0x0810) IDMA Channel 0 DMA Sourc e Address <byte 3668> {field (By field)} <byte 3668> lbits:32 srcadd RW Bits[31:0] of the DMA source address {} or idma_channel_0_dma_source_address (Offset 0x0810) IDMA Channel 0 DMA Source A ddress <byte 3668>

ulong value As longword endunion idma_channel_0_dma_source_address (Offset 0x0810) IDMA Channel 0 DMA So urce Address <byte 3672> union idma_channel_1_dma_source_address (Offset 0x0814) IDMA Channel 1 DMA Sourc e Address <byte 3672> {field (By field)} <byte 3672> lbits:32 srcadd RW Bits[31:0] of the DMA source address {} or idma_channel_1_dma_source_address (Offset 0x0814) IDMA Channel 1 DMA Source A ddress <byte 3672> ulong value As longword endunion idma_channel_1_dma_source_address (Offset 0x0814) IDMA Channel 1 DMA So urce Address <byte 3676> union idma_channel_2_dma_source_address (Offset 0x0818) IDMA Channel 2 DMA Sourc e Address <byte 3676> {field (By field)} <byte 3676> lbits:32 srcadd RW Bits[31:0] of the DMA source address {} or idma_channel_2_dma_source_address (Offset 0x0818) IDMA Channel 2 DMA Source A ddress <byte 3676> ulong value As longword endunion idma_channel_2_dma_source_address (Offset 0x0818) IDMA Channel 2 DMA So urce Address <byte 3680> union idma_channel_3_dma_source_address (Offset 0x081C) IDMA Channel 3 DMA Sourc e Address <byte 3680> {field (By field)} <byte 3680> lbits:32 srcadd RW Bits[31:0] of the DMA source address {} or idma_channel_3_dma_source_address (Offset 0x081C) IDMA Channel 3 DMA Source A ddress <byte 3680> ulong value As longword endunion idma_channel_3_dma_source_address (Offset 0x081C) IDMA Channel 3 DMA So urce Address <byte 3684> union idma_channel_0_dma_destination_address (Offset 0x0820) IDMA Channel 0 DMA Destination Address <byte 3684> {field (By field)} <byte 3684> lbits:32 destadd RW Bits[31:0] of the DMA destination address {} or idma_channel_0_dma_destination_address (Offset 0x0820) IDMA Channel 0 DMA Des tination Address <byte 3684> ulong value As longword endunion idma_channel_0_dma_destination_address (Offset 0x0820) IDMA Channel 0 D MA Destination Address <byte 3688>

union idma_channel_1_dma_destination_address (Offset 0x0824) IDMA Channel 1 DMA Destination Address <byte 3688> {field (By field)} <byte 3688> lbits:32 destadd RW Bits[31:0] of the DMA destination address {} or idma_channel_1_dma_destination_address (Offset 0x0824) IDMA Channel 1 DMA Des tination Address <byte 3688> ulong value As longword endunion idma_channel_1_dma_destination_address (Offset 0x0824) IDMA Channel 1 D MA Destination Address <byte 3692> union idma_channel_2_dma_destination_address (Offset 0x0828) IDMA Channel 2 DMA Destination Address <byte 3692> {field (By field)} <byte 3692> lbits:32 destadd RW Bits[31:0] of the DMA destination address {} or idma_channel_2_dma_destination_address (Offset 0x0828) IDMA Channel 2 DMA Des tination Address <byte 3692> ulong value As longword endunion idma_channel_2_dma_destination_address (Offset 0x0828) IDMA Channel 2 D MA Destination Address <byte 3696> union idma_channel_3_dma_destination_address (Offset 0x082C) IDMA Channel 3 DMA Destination Address <byte 3696> {field (By field)} <byte 3696> lbits:32 destadd RW Bits[31:0] of the DMA destination address {} or idma_channel_3_dma_destination_address (Offset 0x082C) IDMA Channel 3 DMA Des tination Address <byte 3696> ulong value As longword endunion idma_channel_3_dma_destination_address (Offset 0x082C) IDMA Channel 3 D MA Destination Address <byte 3700> union idma_channel_0_next_descriptor_pointer (Offset 0x0830) IDMA Channel 0 Next Descriptor Pointer <byte 3700> {field (By field)} <byte 3700> lbits:32 nextdescptr RW Bits[31:0] of the DMA next descriptor address {} or idma_channel_0_next_descriptor_pointer (Offset 0x0830) IDMA Channel 0 Next De scriptor Pointer <byte 3700> ulong value As longword endunion idma_channel_0_next_descriptor_pointer (Offset 0x0830) IDMA Channel 0 N ext Descriptor Pointer <byte 3704> union idma_channel_1_next_descriptor_pointer (Offset 0x0834) IDMA Channel 1 Next Descriptor Pointer <byte 3704> {field (By field)}

<byte 3704> lbits:32 nextdescptr RW Bits[31:0] of the DMA next descriptor address {} or idma_channel_1_next_descriptor_pointer (Offset 0x0834) IDMA Channel 1 Next De scriptor Pointer <byte 3704> ulong value As longword endunion idma_channel_1_next_descriptor_pointer (Offset 0x0834) IDMA Channel 1 N ext Descriptor Pointer <byte 3708> union idma_channel_2_next_descriptor_pointer (Offset 0x0838) IDMA Channel 2 Next Descriptor Pointer <byte 3708> {field (By field)} <byte 3708> lbits:32 nextdescptr RW Bits[31:0] of the DMA next descriptor address {} or idma_channel_2_next_descriptor_pointer (Offset 0x0838) IDMA Channel 2 Next De scriptor Pointer <byte 3708> ulong value As longword endunion idma_channel_2_next_descriptor_pointer (Offset 0x0838) IDMA Channel 2 N ext Descriptor Pointer <byte 3712> union idma_channel_3_next_descriptor_pointer (Offset 0x083C) IDMA Channel 3 Next Descriptor Pointer <byte 3712> {field (By field)} <byte 3712> lbits:32 nextdescptr RW Bits[31:0] of the DMA next descriptor address {} or idma_channel_3_next_descriptor_pointer (Offset 0x083C) IDMA Channel 3 Next De scriptor Pointer <byte 3712> ulong value As longword endunion idma_channel_3_next_descriptor_pointer (Offset 0x083C) IDMA Channel 3 N ext Descriptor Pointer <byte 3716> union idma_channel_0_control_low (Offset 0x0840) IDMA Channel 0 Control (Low) <byte 3716> {field (By field)} <byte 3716> lbits:3 dstburstlimit RW Destination burst limit in each DMA access lbits:1 srchold RW Source Hold lbits:1 dmaack_width RW DMA ack width lbits:1 desthold RW Destination Hold lbits:3 srcburstlimit RW Source burst limit in each DMA access lbits:1 chainmode RW Chained Mode lbits:1 intmode RW Interrupt Mode lbits:1 demandmode RW Demand Mode Enable lbits:1 chanen RW Channel Enable lbits:1 fetchnd RWC Fetch Next Descriptor lbits:1 chanact RO DMA Channel Active lbits:1 dmareqdir RW DMAReq Direction lbits:1 dmareqmode RW DMAReq# Mode lbits:1 cden RW Close Descriptor Enable lbits:1 eoten RW End Of Transfer Enable lbits:1 eotmode RW End of Transfer Affect lbits:1 abr RW Channel Abort lbits:2 saddrovr RW Override Source Address

lbits:2 daddrovr RW Override Destination Address lbits:2 naddrovr RW Override Next Descriptor Address lbits:1 dmaackmode RW DMA Acknowledge Mode lbits:1 timerreq RW Timer DMA Request Enable lbits:2 dmaackdir RW DMA Acknowledge Direction lbits:1 descmode RW Descriptor Mode {} or idma_channel_0_control_low (Offset 0x0840) IDMA Channel 0 Control (Low) <byte 3716> ulong value As longword endunion idma_channel_0_control_low (Offset 0x0840) IDMA Channel 0 Control (Low) <byte 3720> union idma_channel_1_control_low (Offset 0x0844) IDMA Channel 1 Control (Low) <byte 3720> {field (By field)} <byte 3720> lbits:3 dstburstlimit RW Destination burst limit in each DMA access lbits:1 srchold RW Source Hold lbits:1 dmaack_width RW DMA ack width lbits:1 desthold RW Destination Hold lbits:3 srcburstlimit RW Source burst limit in each DMA access lbits:1 chainmode RW Chained Mode lbits:1 intmode RW Interrupt Mode lbits:1 demandmode RW Demand Mode Enable lbits:1 chanen RW Channel Enable lbits:1 fetchnd RWC Fetch Next Descriptor lbits:1 chanact RO DMA Channel Active lbits:1 dmareqdir RW DMAReq Direction lbits:1 dmareqmode RW DMAReq# Mode lbits:1 cden RW Close Descriptor Enable lbits:1 eoten RW End Of Transfer Enable lbits:1 eotmode RW End of Transfer Affect lbits:1 abr RW Channel Abort lbits:2 saddrovr RW Override Source Address lbits:2 daddrovr RW Override Destination Address lbits:2 naddrovr RW Override Next Descriptor Address lbits:1 dmaackmode RW DMA Acknowledge Mode lbits:1 timerreq RW Timer DMA Request Enable lbits:2 dmaackdir RW DMA Acknowledge Direction lbits:1 descmode RW Descriptor Mode {} or idma_channel_1_control_low (Offset 0x0844) IDMA Channel 1 Control (Low) <byte 3720> ulong value As longword endunion idma_channel_1_control_low (Offset 0x0844) IDMA Channel 1 Control (Low) <byte 3724> union idma_channel_2_control_low (Offset 0x0848) IDMA Channel 2 Control (Low) <byte 3724> {field (By field)} <byte 3724> lbits:3 dstburstlimit RW Destination burst limit in each DMA access lbits:1 srchold RW Source Hold lbits:1 dmaack_width RW DMA ack width lbits:1 desthold RW Destination Hold lbits:3 srcburstlimit RW Source burst limit in each DMA access lbits:1 chainmode RW Chained Mode lbits:1 intmode RW Interrupt Mode lbits:1 demandmode RW Demand Mode Enable lbits:1 chanen RW Channel Enable lbits:1 fetchnd RWC Fetch Next Descriptor

lbits:1 chanact RO DMA Channel Active lbits:1 dmareqdir RW DMAReq Direction lbits:1 dmareqmode RW DMAReq# Mode lbits:1 cden RW Close Descriptor Enable lbits:1 eoten RW End Of Transfer Enable lbits:1 eotmode RW End of Transfer Affect lbits:1 abr RW Channel Abort lbits:2 saddrovr RW Override Source Address lbits:2 daddrovr RW Override Destination Address lbits:2 naddrovr RW Override Next Descriptor Address lbits:1 dmaackmode RW DMA Acknowledge Mode lbits:1 timerreq RW Timer DMA Request Enable lbits:2 dmaackdir RW DMA Acknowledge Direction lbits:1 descmode RW Descriptor Mode {} or idma_channel_2_control_low (Offset 0x0848) IDMA Channel 2 Control (Low) <byte 3724> ulong value As longword endunion idma_channel_2_control_low (Offset 0x0848) IDMA Channel 2 Control (Low) <byte 3728> union idma_channel_3_control_low (Offset 0x084C) IDMA Channel 3 Control (Low) <byte 3728> {field (By field)} <byte 3728> lbits:3 dstburstlimit RW Destination burst limit in each DMA access lbits:1 srchold RW Source Hold lbits:1 dmaack_width RW DMA ack width lbits:1 desthold RW Destination Hold lbits:3 srcburstlimit RW Source burst limit in each DMA access lbits:1 chainmode RW Chained Mode lbits:1 intmode RW Interrupt Mode lbits:1 demandmode RW Demand Mode Enable lbits:1 chanen RW Channel Enable lbits:1 fetchnd RWC Fetch Next Descriptor lbits:1 chanact RO DMA Channel Active lbits:1 dmareqdir RW DMAReq Direction lbits:1 dmareqmode RW DMAReq# Mode lbits:1 cden RW Close Descriptor Enable lbits:1 eoten RW End Of Transfer Enable lbits:1 eotmode RW End of Transfer Affect lbits:1 abr RW Channel Abort lbits:2 saddrovr RW Override Source Address lbits:2 daddrovr RW Override Destination Address lbits:2 naddrovr RW Override Next Descriptor Address lbits:1 dmaackmode RW DMA Acknowledge Mode lbits:1 timerreq RW Timer DMA Request Enable lbits:2 dmaackdir RW DMA Acknowledge Direction lbits:1 descmode RW Descriptor Mode {} or idma_channel_3_control_low (Offset 0x084C) IDMA Channel 3 Control (Low) <byte 3728> ulong value As longword endunion idma_channel_3_control_low (Offset 0x084C) IDMA Channel 3 Control (Low) <byte 3732> union idma_arbiter_control (Offset 0x0860) IDMA Arbiter Control <byte 3732> {field (By field)} <byte 3732> lbits:2 arb0 RW Slice 0 of 'pizza arbiter' lbits:2 arb1 RW Slice 1 of 'pizza arbiter'

lbits:2 arb2 RW Slice 2 of 'pizza arbiter' lbits:2 arb3 RW Slice 3 of 'pizza arbiter' lbits:2 arb4 RW Slice 4 of 'pizza arbiter' lbits:2 arb5 RW Slice 5 of 'pizza arbiter' lbits:2 arb6 RW Slice 6 of 'pizza arbiter' lbits:2 arb7 RW Slice 7 of 'pizza arbiter' lbits:2 arb8 RW Slice 8 of 'pizza arbiter' lbits:2 arb9 RW Slice 9 of 'pizza arbiter' lbits:2 arb10 RW Slice 10 of 'pizza arbiter' lbits:2 arb11 RW Slice 11 of 'pizza arbiter' lbits:2 arb12 RW Slice 12 of 'pizza arbiter' lbits:2 arb13 RW Slice 13 of 'pizza arbiter' lbits:2 arb14 RW Slice 14 of 'pizza arbiter' lbits:2 arb15 RW Slice 15 of 'pizza arbiter' {} or idma_arbiter_control (Offset 0x0860) IDMA Arbiter Control <byte 3732> ulong value As longword endunion idma_arbiter_control (Offset 0x0860) IDMA Arbiter Control <byte 3736> union idma_base_address_register_0 (Offset 0x0A00) IDMA Base Address Register 0 <byte 3736> {field (By field)} <byte 3736> lbits:4 target RW Specifies the target interface associated with this window lbits:4 reserved0 RES Reserved <byte 3736> union attr Target specific attributes <byte 3740> {dramti (DRAM Target Interface)} <byte 3740> tbits:4 bank DRAM bank select tbits:2 ccoh Cache coherency tbits:2 reserved Reserved {} or attr Target specific attributes <byte 3736> {dbti (Device Bus Target Interface)} <byte 3736> tbits:5 bank Device bank select tbits:3 reserved Reserved {} or attr Target specific attributes <byte 3736> {pci01ti (PCI0/1 Target Interface)} <byte 3736> tbits:2 swaptype Data swap type tbits:1 snoopns PCI-X No Snoop (NS) attribute tbits:1 space PCI I/O or memory space tbits:1 req64 PCI REQ64# control tbits:3 reserved Reserved {} or attr Target specific attributes <byte 3736> utiny value As byte endunion attr Target specific attributes <byte 3737> lbits:16 base RW Base Address {} or idma_base_address_register_0 (Offset 0x0A00) IDMA Base Address Register 0

<byte 3736> ulong value As longword endunion idma_base_address_register_0 (Offset 0x0A00) IDMA Base Address Register 0 <byte 3740> union idma_size_register_0 (Offset 0x0A04) IDMA Size Register 0 <byte 3740> {field (By field)} <byte 3740> lbits:16 reserved0 RO Reserved, read only lbits:16 size RW Window Size {} or idma_size_register_0 (Offset 0x0A04) IDMA Size Register 0 <byte 3740> ulong value As longword endunion idma_size_register_0 (Offset 0x0A04) IDMA Size Register 0 <byte 3744> union idma_base_address_register_1 (Offset 0x0A08) IDMA Base Address Register 1 <byte 3744> {field (By field)} <byte 3744> lbits:4 target RW Specifies the target interface associated with this window lbits:4 reserved0 RES Reserved <byte 3744> union attr Target specific attributes <byte 3748> {dramti (DRAM Target Interface)} <byte 3748> tbits:4 bank DRAM bank select tbits:2 ccoh Cache coherency tbits:2 reserved Reserved {} or attr Target specific attributes <byte 3744> {dbti (Device Bus Target Interface)} <byte 3744> tbits:5 bank Device bank select tbits:3 reserved Reserved {} or attr Target specific attributes <byte 3744> {pci01ti (PCI0/1 Target Interface)} <byte 3744> tbits:2 swaptype Data swap type tbits:1 snoopns PCI-X No Snoop (NS) attribute tbits:1 space PCI I/O or memory space tbits:1 req64 PCI REQ64# control tbits:3 reserved Reserved {} or attr Target specific attributes <byte 3744> utiny value As byte endunion attr Target specific attributes <byte 3745> lbits:16 base RW Base Address {} or idma_base_address_register_1 (Offset 0x0A08) IDMA Base Address Register 1 <byte 3744> ulong value As longword endunion idma_base_address_register_1 (Offset 0x0A08) IDMA Base Address Register

1 <byte 3748> union idma_size_register_1 (Offset 0x0A0C) IDMA Size Register 1 <byte 3748> {field (By field)} <byte 3748> lbits:16 reserved0 RO Reserved, read only lbits:16 size RW Window Size {} or idma_size_register_1 (Offset 0x0A0C) IDMA Size Register 1 <byte 3748> ulong value As longword endunion idma_size_register_1 (Offset 0x0A0C) IDMA Size Register 1 <byte 3752> union idma_base_address_register_2 (Offset 0x0A10) IDMA Base Address Register 2 <byte 3752> {field (By field)} <byte 3752> lbits:4 target RW Specifies the target interface associated with this window lbits:4 reserved0 RES Reserved <byte 3752> union attr Target specific attributes <byte 3756> {dramti (DRAM Target Interface)} <byte 3756> tbits:4 bank DRAM bank select tbits:2 ccoh Cache coherency tbits:2 reserved Reserved {} or attr Target specific attributes <byte 3752> {dbti (Device Bus Target Interface)} <byte 3752> tbits:5 bank Device bank select tbits:3 reserved Reserved {} or attr Target specific attributes <byte 3752> {pci01ti (PCI0/1 Target Interface)} <byte 3752> tbits:2 swaptype Data swap type tbits:1 snoopns PCI-X No Snoop (NS) attribute tbits:1 space PCI I/O or memory space tbits:1 req64 PCI REQ64# control tbits:3 reserved Reserved {} or attr Target specific attributes <byte 3752> utiny value As byte endunion attr Target specific attributes <byte 3753> lbits:16 base RW Base Address {} or idma_base_address_register_2 (Offset 0x0A10) IDMA Base Address Register 2 <byte 3752> ulong value As longword endunion idma_base_address_register_2 (Offset 0x0A10) IDMA Base Address Register 2 <byte 3756> union idma_size_register_2 (Offset 0x0A14) IDMA Size Register 2

<byte 3756> {field (By field)} <byte 3756> lbits:16 reserved0 RO Reserved, read only lbits:16 size RW Window Size {} or idma_size_register_2 (Offset 0x0A14) IDMA Size Register 2 <byte 3756> ulong value As longword endunion idma_size_register_2 (Offset 0x0A14) IDMA Size Register 2 <byte 3760> union idma_base_address_register_3 (Offset 0x0A18) IDMA Base Address Register 3 <byte 3760> {field (By field)} <byte 3760> lbits:4 target RW Specifies the target interface associated with this window lbits:4 reserved0 RES Reserved <byte 3760> union attr Target specific attributes <byte 3764> {dramti (DRAM Target Interface)} <byte 3764> tbits:4 bank DRAM bank select tbits:2 ccoh Cache coherency tbits:2 reserved Reserved {} or attr Target specific attributes <byte 3760> {dbti (Device Bus Target Interface)} <byte 3760> tbits:5 bank Device bank select tbits:3 reserved Reserved {} or attr Target specific attributes <byte 3760> {pci01ti (PCI0/1 Target Interface)} <byte 3760> tbits:2 swaptype Data swap type tbits:1 snoopns PCI-X No Snoop (NS) attribute tbits:1 space PCI I/O or memory space tbits:1 req64 PCI REQ64# control tbits:3 reserved Reserved {} or attr Target specific attributes <byte 3760> utiny value As byte endunion attr Target specific attributes <byte 3761> lbits:16 base RW Base Address {} or idma_base_address_register_3 (Offset 0x0A18) IDMA Base Address Register 3 <byte 3760> ulong value As longword endunion idma_base_address_register_3 (Offset 0x0A18) IDMA Base Address Register 3 <byte 3764> union idma_size_register_3 (Offset 0x0A1C) IDMA Size Register 3 <byte 3764> {field (By field)} <byte 3764>

lbits:16 reserved0 RO Reserved, read only lbits:16 size RW Window Size {} or idma_size_register_3 (Offset 0x0A1C) IDMA Size Register 3 <byte 3764> ulong value As longword endunion idma_size_register_3 (Offset 0x0A1C) IDMA Size Register 3 <byte 3768> union idma_base_address_register_4 (Offset 0x0A20) IDMA Base Address Register 4 <byte 3768> {field (By field)} <byte 3768> lbits:4 target RW Specifies the target interface associated with this window lbits:4 reserved0 RES Reserved <byte 3768> union attr Target specific attributes <byte 3772> {dramti (DRAM Target Interface)} <byte 3772> tbits:4 bank DRAM bank select tbits:2 ccoh Cache coherency tbits:2 reserved Reserved {} or attr Target specific attributes <byte 3768> {dbti (Device Bus Target Interface)} <byte 3768> tbits:5 bank Device bank select tbits:3 reserved Reserved {} or attr Target specific attributes <byte 3768> {pci01ti (PCI0/1 Target Interface)} <byte 3768> tbits:2 swaptype Data swap type tbits:1 snoopns PCI-X No Snoop (NS) attribute tbits:1 space PCI I/O or memory space tbits:1 req64 PCI REQ64# control tbits:3 reserved Reserved {} or attr Target specific attributes <byte 3768> utiny value As byte endunion attr Target specific attributes <byte 3769> lbits:16 base RW Base Address {} or idma_base_address_register_4 (Offset 0x0A20) IDMA Base Address Register 4 <byte 3768> ulong value As longword endunion idma_base_address_register_4 (Offset 0x0A20) IDMA Base Address Register 4 <byte 3772> union idma_size_register_4 (Offset 0x0A24) IDMA Size Register 4 <byte 3772> {field (By field)} <byte 3772> lbits:16 reserved0 RO Reserved, read only lbits:16 size RW Window Size {}

or idma_size_register_4 (Offset 0x0A24) IDMA Size Register 4 <byte 3772> ulong value As longword endunion idma_size_register_4 (Offset 0x0A24) IDMA Size Register 4 <byte 3776> union idma_base_address_register_5 (Offset 0x0A28) IDMA Base Address Register 5 <byte 3776> {field (By field)} <byte 3776> lbits:4 target RW Specifies the target interface associated with this window lbits:4 reserved0 RES Reserved <byte 3776> union attr Target specific attributes <byte 3780> {dramti (DRAM Target Interface)} <byte 3780> tbits:4 bank DRAM bank select tbits:2 ccoh Cache coherency tbits:2 reserved Reserved {} or attr Target specific attributes <byte 3776> {dbti (Device Bus Target Interface)} <byte 3776> tbits:5 bank Device bank select tbits:3 reserved Reserved {} or attr Target specific attributes <byte 3776> {pci01ti (PCI0/1 Target Interface)} <byte 3776> tbits:2 swaptype Data swap type tbits:1 snoopns PCI-X No Snoop (NS) attribute tbits:1 space PCI I/O or memory space tbits:1 req64 PCI REQ64# control tbits:3 reserved Reserved {} or attr Target specific attributes <byte 3776> utiny value As byte endunion attr Target specific attributes <byte 3777> lbits:16 base RW Base Address {} or idma_base_address_register_5 (Offset 0x0A28) IDMA Base Address Register 5 <byte 3776> ulong value As longword endunion idma_base_address_register_5 (Offset 0x0A28) IDMA Base Address Register 5 <byte 3780> union idma_size_register_5 (Offset 0x0A2C) IDMA Size Register 5 <byte 3780> {field (By field)} <byte 3780> lbits:16 reserved0 RO Reserved, read only lbits:16 size RW Window Size {} or idma_size_register_5 (Offset 0x0A2C) IDMA Size Register 5 <byte 3780> ulong value As longword

endunion idma_size_register_5 (Offset 0x0A2C) IDMA Size Register 5 <byte 3784> union idma_base_address_register_6 (Offset 0x0A30) IDMA Base Address Register 6 <byte 3784> {field (By field)} <byte 3784> lbits:4 target RW Specifies the target interface associated with this window lbits:4 reserved0 RES Reserved <byte 3784> union attr Target specific attributes <byte 3788> {dramti (DRAM Target Interface)} <byte 3788> tbits:4 bank DRAM bank select tbits:2 ccoh Cache coherency tbits:2 reserved Reserved {} or attr Target specific attributes <byte 3784> {dbti (Device Bus Target Interface)} <byte 3784> tbits:5 bank Device bank select tbits:3 reserved Reserved {} or attr Target specific attributes <byte 3784> {pci01ti (PCI0/1 Target Interface)} <byte 3784> tbits:2 swaptype Data swap type tbits:1 snoopns PCI-X No Snoop (NS) attribute tbits:1 space PCI I/O or memory space tbits:1 req64 PCI REQ64# control tbits:3 reserved Reserved {} or attr Target specific attributes <byte 3784> utiny value As byte endunion attr Target specific attributes <byte 3785> lbits:16 base RW Base Address {} or idma_base_address_register_6 (Offset 0x0A30) IDMA Base Address Register 6 <byte 3784> ulong value As longword endunion idma_base_address_register_6 (Offset 0x0A30) IDMA Base Address Register 6 <byte 3788> union idma_size_register_6 (Offset 0x0A34) IDMA Size Register 6 <byte 3788> {field (By field)} <byte 3788> lbits:16 reserved0 RO Reserved, read only lbits:16 size RW Window Size {} or idma_size_register_6 (Offset 0x0A34) IDMA Size Register 6 <byte 3788> ulong value As longword endunion idma_size_register_6 (Offset 0x0A34) IDMA Size Register 6 <byte 3792> union idma_base_address_register_7 (Offset 0x0A38) IDMA Base Address Register 7

<byte 3792> {field (By field)} <byte 3792> lbits:4 target RW Specifies the target interface associated with this window lbits:4 reserved0 RES Reserved <byte 3792> union attr Target specific attributes <byte 3796> {dramti (DRAM Target Interface)} <byte 3796> tbits:4 bank DRAM bank select tbits:2 ccoh Cache coherency tbits:2 reserved Reserved {} or attr Target specific attributes <byte 3792> {dbti (Device Bus Target Interface)} <byte 3792> tbits:5 bank Device bank select tbits:3 reserved Reserved {} or attr Target specific attributes <byte 3792> {pci01ti (PCI0/1 Target Interface)} <byte 3792> tbits:2 swaptype Data swap type tbits:1 snoopns PCI-X No Snoop (NS) attribute tbits:1 space PCI I/O or memory space tbits:1 req64 PCI REQ64# control tbits:3 reserved Reserved {} or attr Target specific attributes <byte 3792> utiny value As byte endunion attr Target specific attributes <byte 3793> lbits:16 base RW Base Address {} or idma_base_address_register_7 (Offset 0x0A38) IDMA Base Address Register 7 <byte 3792> ulong value As longword endunion idma_base_address_register_7 (Offset 0x0A38) IDMA Base Address Register 7 <byte 3796> union idma_size_register_7 (Offset 0x0A3C) IDMA Size Register 7 <byte 3796> {field (By field)} <byte 3796> lbits:16 reserved0 RO Reserved, read only lbits:16 size RW Window Size {} or idma_size_register_7 (Offset 0x0A3C) IDMA Size Register 7 <byte 3796> ulong value As longword endunion idma_size_register_7 (Offset 0x0A3C) IDMA Size Register 7 <byte 3800> union idma_base_address_enable (Offset 0x0A80) IDMA Base Address Enable <byte 3800> {field (By field)} <byte 3800>

lbits:1 en0 RW Address window 0 enable lbits:1 en1 RW Address window 1 enable lbits:1 en2 RW Address window 2 enable lbits:1 en3 RW Address window 3 enable lbits:1 en4 RW Address window 4 enable lbits:1 en5 RW Address window 5 enable lbits:1 en6 RW Address window 6 enable lbits:1 en7 RW Address window 7 enable lbits:24 reserved0 RO Reserved, read only {} or idma_base_address_enable (Offset 0x0A80) IDMA Base Address Enable <byte 3800> ulong value As longword endunion idma_base_address_enable (Offset 0x0A80) IDMA Base Address Enable <byte 3804> union sdram_configuration (Offset 0x1400) SDRAM Configuration <byte 3804> {field (By field)} <byte 3804> lbits:14 refresh Refresh rate of DIMM lbits:1 pinter Physical interleaving lbits:1 vinter Virtual interleaving lbits:1 reserved1 Reserved lbits:1 regdram Registered DRAM lbits:1 ecc Enable ECC lbits:1 reserved2 Reserved lbits:2 dqs # DQS pins lbits:4 reserved3 Reserved lbits:6 rdbuff Read Buffer assignment {} or sdram_configuration (Offset 0x1400) SDRAM Configuration <byte 3804> ulong value As longword endunion sdram_configuration (Offset 0x1400) SDRAM Configuration <byte 3808> union dunit_control_low (Offset 0x1404) Dunit Control (Low) <byte 3808> {field (By field)} <byte 3808> lbits:1 clksync RW Clock Domains Synchronization lbits:1 rdsyncsel RW Read Data Synchronization Select lbits:1 rdctrltdel RW Read Control Logic Delay lbits:1 rddatadel RW Read Data Delay lbits:2 ctrlpipe RW Number of pipeline stages in the Dunit control path lbits:1 ctrlpos RW Address/Control Output Timing lbits:1 rdpipe RW Number of pipeline stages in the read data path lbits:1 rdsyncen RW Read Data Path Synchronization lbits:1 rmwsyncen RW RMW Path Synchronization lbits:1 cpupriority RW CPU priority assignment lbits:1 pci_0priority RW PCI_0 priority assignment lbits:1 pci_1priority RW PCI_1 priority assignment lbits:1 mpscpriority RW MPSC priority assignment lbits:1 idmapriority RW IDMA priority assignment lbits:1 gbpriority RW Gb priority assignment lbits:4 lcnt RW Arbiter Low Priority Counter lbits:4 hcnt RW Arbiter High Priority Counter lbits:3 stburstdel RW Number of sample stages on StartBurstIn lbits:1 stburstneg RW StartBurstIn is first sampled on the falling edge of cl ock lbits:1 stburstsrc RW StartBurst source

lbits:1 rddataneg RW Read data is first sampled with falling edge of clock lbits:2 reserved0 RES Reserved {} or dunit_control_low (Offset 0x1404) Dunit Control (Low) <byte 3808> ulong value As longword endunion dunit_control_low (Offset 0x1404) Dunit Control (Low) <byte 3812> union atlantis_sdram_timing_l (Offset 0x1408) SDRAM Timing (Low) <byte 3812> {field (By field)} <byte 3812> lbits:4 Tdqss Write to DQS lbits:4 Trcd Activate to command lbits:4 Trp Precharge command period lbits:4 Twr Write command to precharge lbits:4 Twtr Write command to read command lbits:4 Tras Minimum row active time lbits:4 Trrd Activate bank A to activate bank B lbits:4 reserved Reserved {} or atlantis_sdram_timing_l (Offset 0x1408) SDRAM Timing (Low) <byte 3812> ulong value As longword endunion atlantis_sdram_timing_l (Offset 0x1408) SDRAM Timing (Low) <byte 3816> union atlantis_sdram_timing_h (Offset 0x140C) SDRAM Timing (High) <byte 3816> {field (By field)} <byte 3816> lbits:4 Trfc Refresh command period lbits:2 Trd2rd Minimum gap between DRAM read accesses lbits:2 Trd2wr Minimum gap between DRAM read and write accesses lbits:24 reserved Write command to precharge {} or atlantis_sdram_timing_h (Offset 0x140C) SDRAM Timing (High) <byte 3816> ulong value As longword endunion atlantis_sdram_timing_h (Offset 0x140C) SDRAM Timing (High) <byte 3820> union sdram_address_control (Offset 0x1410) SDRAM Address Control <byte 3820> {field (By field)} <byte 3820> lbits:4 addrsel RW SDRAM Address Select lbits:2 dcfg RW SDRAM Device Configuration lbits:26 reserved0 RES Reserved {} or sdram_address_control (Offset 0x1410) SDRAM Address Control <byte 3820> ulong value As longword endunion sdram_address_control (Offset 0x1410) SDRAM Address Control <byte 3824> union sdram_open_pages_control (Offset 0x1414) SDRAM Open Pages Control <byte 3824> {field (By field)} <byte 3824> lbits:1 ope0 RW Open Page Enable CS[0]# bank0 lbits:1 ope1 RW Open Page Enable CS[0]# bank1 lbits:1 ope2 RW Open Page Enable CS[0]# bank2

lbits:1 ope3 RW Open Page Enable CS[0]# bank3 lbits:1 ope4 RW Open Page Enable CS[1]# bank0 lbits:1 ope5 RW Open Page Enable CS[1]# bank1 lbits:1 ope6 RW Open Page Enable CS[1]# bank2 lbits:1 ope7 RW Open Page Enable CS[1]# bank3 lbits:1 ope8 RW Open Page Enable CS[2]# bank0 lbits:1 ope9 RW Open Page Enable CS[2]# bank1 lbits:1 ope10 RW Open Page Enable CS[2]# bank2 lbits:1 ope11 RW Open Page Enable CS[2]# bank3 lbits:1 ope12 RW Open Page Enable CS[3]# bank0 lbits:1 ope13 RW Open Page Enable CS[3]# bank1 lbits:1 ope14 RW Open Page Enable CS[3]# bank2 lbits:1 ope15 RW Open Page Enable CS[3]# bank3 lbits:16 reserved0 RES Reserved {} or sdram_open_pages_control (Offset 0x1414) SDRAM Open Pages Control <byte 3824> ulong value As longword endunion sdram_open_pages_control (Offset 0x1414) SDRAM Open Pages Control <byte 3828> union sdram_operation (Offset 0x1418) SDRAM Operation <byte 3828> {field (By field)} <byte 3828> lbits:3 cmd RW DRAM Mode Select lbits:29 reserved0 RES Reserved {} or sdram_operation (Offset 0x1418) SDRAM Operation <byte 3828> ulong value As longword endunion sdram_operation (Offset 0x1418) SDRAM Operation <byte 3832> union sdram_mode (Offset 0x141C) SDRAM Mode <byte 3832> {field (By field)} <byte 3832> lbits:3 bl RW Burst Length lbits:1 bt RW Burst Type/Init Val lbits:3 cl RW CAS Latency lbits:7 om RW Operation Mode lbits:18 reserved0 RES Reserved {} or sdram_mode (Offset 0x141C) SDRAM Mode <byte 3832> ulong value As longword endunion sdram_mode (Offset 0x141C) SDRAM Mode <byte 3836> union extsdram_mode (Offset 0x1420) Extended SDRAM Mode <byte 3836> {field (By field)} <byte 3836> lbits:1 dll RW DRAM DLL Enable lbits:1 ds RW DRAM Drive Strength lbits:1 qfc RW QFC Signal Enable lbits:11 om RW Operation Mode lbits:18 reserved0 RES Reserved {} or extsdram_mode (Offset 0x1420) Extended SDRAM Mode <byte 3836> ulong value As longword

endunion extsdram_mode (Offset 0x1420) Extended SDRAM Mode <byte 3840> union dunit_control_high (Offset 0x1424) Dunit Control (High) <byte 3840> {field (By field)} <byte 3840> lbits:4 wrbuff RW Reserved lbits:4 rdbuff RW Reserved lbits:4 txque RW Reserved lbits:4 wrtrig RW Reserved lbits:4 rdtrig RW Reserved lbits:4 rmwtrig RW Reserved lbits:1 snooppipe RW Snoops pipeline enable lbits:4 snoopdepth RW Reserved lbits:3 reserved0 RES Reserved {} or dunit_control_high (Offset 0x1424) Dunit Control (High) <byte 3840> ulong value As longword endunion dunit_control_high (Offset 0x1424) Dunit Control (High) <byte 3844> union sdram_interface_crossbar_control_low (Offset 0x1430) SDRAM Interface Cross bar Control (Low) <byte 3844> {field (By field)} <byte 3844> lbits:4 arb0 RW Slice 0 of the device controller 'pizza' arbiter lbits:4 arb1 RW Slice 1 of the device controller 'pizza' arbiter lbits:4 arb2 RW Slice 2 of the device controller 'pizza' arbiter lbits:4 arb3 RW Slice 3 of the device controller 'pizza' arbiter lbits:4 arb4 RW Slice 4 of the device controller 'pizza' arbiter lbits:4 arb5 RW Slice 5 of the device controller 'pizza' arbiter lbits:4 arb6 RW Slice 6 of the device controller 'pizza' arbiter lbits:4 arb7 RW Slice 7 of the device controller 'pizza' arbiter {} or sdram_interface_crossbar_control_low (Offset 0x1430) SDRAM Interface Crossbar Control (Low) <byte 3844> ulong value As longword endunion sdram_interface_crossbar_control_low (Offset 0x1430) SDRAM Interface Cr ossbar Control (Low) <byte 3848> union sdram_interface_crossbar_control_high (Offset 0x1434) SDRAM Interface Cros sbar Control (High) <byte 3848> {field (By field)} <byte 3848> lbits:4 arb8 RW Slice 8 of the device controller 'pizza' arbiter lbits:4 arb9 RW Slice 9 of the device controller 'pizza' arbiter lbits:4 arb10 RW Slice 10 of the device controller 'pizza' arbiter lbits:4 arb11 RW Slice 11 of the device controller 'pizza' arbiter lbits:4 arb12 RW Slice 12 of the device controller 'pizza' arbiter lbits:4 arb13 RW Slice 13 of the device controller 'pizza' arbiter lbits:4 arb14 RW Slice 14 of the device controller 'pizza' arbiter lbits:4 arb15 RW Slice 15 of the device controller 'pizza' arbiter {} or sdram_interface_crossbar_control_high (Offset 0x1434) SDRAM Interface Crossba r Control (High) <byte 3848> ulong value As longword

endunion sdram_interface_crossbar_control_high (Offset 0x1434) SDRAM Interface C rossbar Control (High) <byte 3852> union sdram_interface_crossbar_timeout (Offset 0x1438) SDRAM Interface Crossbar Timeout <byte 3852> {field (By field)} <byte 3852> lbits:8 timeout RW CrossBar Arbiter Timeout Preset Value lbits:8 reserved1 RES Reserved lbits:1 timeouten RW CrossBar Arbiter Timer Enable lbits:15 reserved0 RES Reserved {} or sdram_interface_crossbar_timeout (Offset 0x1438) SDRAM Interface Crossbar Tim eout <byte 3852> ulong value As longword endunion sdram_interface_crossbar_timeout (Offset 0x1438) SDRAM Interface Crossb ar Timeout <byte 3856> union dfcdl_configuration0 (Offset 0x1480) DFCDL Configuration0 <byte 3856> {field (By field)} <byte 3856> lbits:8 updwin RW The window size, after the refresh command, in which DFCDL update is allowed lbits:5 reserved1 RES Reserved lbits:1 forceupdsync RW Forces the delay line update as soon as DFCDL is sync hronized lbits:1 forceupdw RW Forces delay line update as soon as update window arrive s lbits:1 blockupd RW Disables delay line update (unless using ForceUpdSync or ForceUpdW bits) lbits:1 updnosync RW Enables dynamic update without reaching sync condition lbits:1 updnowin RW Enables dynamic update without reaching update window lbits:1 forceacc RW Forces the filter state machine to accept bad values lbits:9 maxdiff RW Maximum difference between consecutive updates Filtering i s performed on values multiplied by 4 lbits:4 reserved0 RES Reserved {} or dfcdl_configuration0 (Offset 0x1480) DFCDL Configuration0 <byte 3856> ulong value As longword endunion dfcdl_configuration0 (Offset 0x1480) DFCDL Configuration0 <byte 3860> union dfcdl_configuration1 (Offset 0x1484) DFCDL Configuration1 <byte 3860> {field (By field)} <byte 3860> lbits:6 delpval RW Delay counter preset value lbits:1 fourcell RW Delay unit selects lbits:1 isense RW Multiply by two the value found by the search machine lbits:6 phased RW Delay Counter Phase Delta lbits:1 singlephase RW Search machine only searches for first phase lbits:1 reserved1 RES Reserved lbits:1 phasemode RW Phase Mode Jump lbits:1 reserved0 RES Reserved lbits:2 avg RW Average Value Calculation for Filter Process lbits:2 goodhits RW For the sync machine to enter the previous sync state, th e number of times the good value must be received after the bad value

lbits:2 goodsync RW For the sync machine to enter sync state, the number of t imes the good value must be received after loss of sync lbits:1 forcesync RW Forces the sync machine to enter the sync state lbits:1 holdsync RW Forces the sync machine to maintain this state lbits:1 resync RW Forces the sync machine to enter a loss of sync state lbits:2 avgrd RW Average used for read address of the SRAM lbits:1 stopimid RW Forces the filter machine to enter stop state lbits:1 stopsync RW Forces it to enter stop state, if there is sync condition lbits:1 goinit RW Forces it to remain in this state {} or dfcdl_configuration1 (Offset 0x1484) DFCDL Configuration1 <byte 3860> ulong value As longword endunion dfcdl_configuration1 (Offset 0x1484) DFCDL Configuration1 <byte 3864> union sram_address (Offset 0x1490) SRAM Address <byte 3864> {field (By field)} <byte 3864> lbits:32 addr RW SRAM address {} or sram_address (Offset 0x1490) SRAM Address <byte 3864> ulong value As longword endunion sram_address (Offset 0x1490) SRAM Address <byte 3868> union sram_data0 (Offset 0x1494) SRAM Data0 <byte 3868> {field (By field)} <byte 3868> lbits:32 data RW SRAM Write Data to initialize the DFCDL SRAM {} or sram_data0 (Offset 0x1494) SRAM Data0 <byte 3868> ulong value As longword endunion sram_data0 (Offset 0x1494) SRAM Data0 <byte 3872> union dfcdl_probe (Offset 0x14A0) DFCDL Probe <byte 3872> {field (By field)} <byte 3872> lbits:4 bussel RW Select DFCDL bus to be probed lbits:1 proben RW Probe Enabled lbits:27 reserved0 RES Reserved {} or dfcdl_probe (Offset 0x14A0) DFCDL Probe <byte 3872> ulong value As longword endunion dfcdl_probe (Offset 0x14A0) DFCDL Probe <byte 3876> union sdram_address_control_pads_calibration (Offset 0x14C0) SDRAM Address/Contr ol Pads Calibration <byte 3876> {field (By field)} <byte 3876> lbits:5 drvn RW Pad Nchannel Driving Strength lbits:5 drvp RW Pad Pchannel Driving Strength lbits:6 reserved1 RES Reserved, read only lbits:1 tuneen RW Enables the dynamic tuning of pad driving strength lbits:5 lockn RO Final locked value of the Nchannel Driving Strength

lbits:5 lockp RO Final locked value of the Pchannel Driving Strength lbits:4 reserved0 RES Reserved, read only lbits:1 wren RW Write Enable CPU Pads Calibration register {} or sdram_address_control_pads_calibration (Offset 0x14C0) SDRAM Address/Control Pads Calibration <byte 3876> ulong value As longword endunion sdram_address_control_pads_calibration (Offset 0x14C0) SDRAM Address/Co ntrol Pads Calibration <byte 3880> union sdram_data_pads_calibration (Offset 0x14C4) SDRAM Data Pads Calibration <byte 3880> {field (By field)} <byte 3880> lbits:5 drvn RW Pad Nchannel Driving Strength lbits:5 drvp RW Pad Pchannel Driving Strength lbits:6 reserved1 RES Reserved, read only lbits:1 tuneen RW Enables the dynamic tuning of pad driving strength lbits:5 lockn RO Final locked value of the Nchannel Driving Strength lbits:5 lockp RO Final locked value of the Pchannel Driving Strength lbits:4 reserved0 RES Reserved, read only lbits:1 wren RW Write Enable CPU Pads Calibration register {} or sdram_data_pads_calibration (Offset 0x14C4) SDRAM Data Pads Calibration <byte 3880> ulong value As longword endunion sdram_data_pads_calibration (Offset 0x14C4) SDRAM Data Pads Calibration <byte 3884> union twsi_slave_address (Offset 0xC000) Two-Wire Serial Interface Slave Address <byte 3884> {field (By field)} <byte 3884> lbits:1 gce RW General Call Enable lbits:7 saddr RW Slave address lbits:24 reserved0 RES Reserved {} or twsi_slave_address (Offset 0xC000) Two-Wire Serial Interface Slave Address <byte 3884> ulong value As longword endunion twsi_slave_address (Offset 0xC000) Two-Wire Serial Interface Slave Addr ess <byte 3888> union twsi_data (Offset 0xC004) Two-Wire Serial Interface Data <byte 3888> {field (By field)} <byte 3888> lbits:8 data RW Data/Address byte to be transmitted by the TWSI master or sla ve, or data byte received lbits:24 reserved0 RES Reserved {} or twsi_data (Offset 0xC004) Two-Wire Serial Interface Data <byte 3888> ulong value As longword endunion twsi_data (Offset 0xC004) Two-Wire Serial Interface Data <byte 3892> union twsi_control (Offset 0xC008) Two-Wire Serial Interface Control <byte 3892> {field (By field)} <byte 3892>

lbits:2 reserved1 RES Reserved, read only lbits:1 ack RW Acknowledge lbits:1 iflg RW Interrupt Flag lbits:1 stop RW Stop lbits:1 start RW Start lbits:1 twsien RW TWSI enable lbits:1 inten RW Interrupt Enable lbits:24 reserved0 RES Reserved {} or twsi_control (Offset 0xC008) Two-Wire Serial Interface Control <byte 3892> ulong value As longword endunion twsi_control (Offset 0xC008) Two-Wire Serial Interface Control <byte 3896> union twsi_status_baud_rate (Offset 0xC00C) Two-Wire Serial Interface Status/Bau d Rate <byte 3896> {status (Status value)} <byte 3896> lbits:8 stat RO TWSI Status lbits:24 reserved0 RES Reserved {} or twsi_status_baud_rate (Offset 0xC00C) Two-Wire Serial Interface Status/Baud R ate <byte 3896> {br (Baud rate)} <byte 3896> lbits:3 n WO SCL frequency power of 2 lbits:4 m WO SCL frequency multiplier lbits:25 reserved0 RES Reserved {} or twsi_status_baud_rate (Offset 0xC00C) Two-Wire Serial Interface Status/Baud R ate <byte 3896> ulong value As longword endunion twsi_status_baud_rate (Offset 0xC00C) Two-Wire Serial Interface Status/ Baud Rate <byte 3900> union twsi_extended_slave_address (Offset 0xC010) Two-Wire Serial Interface Exte nded Slave Address <byte 3900> {field (By field)} <byte 3900> lbits:8 saddr RW Bits[7:0] of the 10-bit slave address lbits:24 reserved0 RES Reserved {} or twsi_extended_slave_address (Offset 0xC010) Two-Wire Serial Interface Extende d Slave Address <byte 3900> ulong value As longword endunion twsi_extended_slave_address (Offset 0xC010) Two-Wire Serial Interface E xtended Slave Address <byte 3904> union twsi_soft_reset (Offset 0xC01C) Two-Wire Serial Interface Soft Reset <byte 3904> {field (By field)} <byte 3904> lbits:32 rst WO Write to this register resets the TWSI logic and sets all TWS I registers to their reset values {}

or twsi_soft_reset (Offset 0xC01C) Two-Wire Serial Interface Soft Reset <byte 3904> ulong value As longword endunion twsi_soft_reset (Offset 0xC01C) Two-Wire Serial Interface Soft Reset {} <byte 3908> {atlantis_mcs (Atlantis machine check specific registers)} <byte 3908> union main_interrupt_cause_low (Offset 0x0004) Main Interrupt Cause (Low) <byte 3908> {field (By field)} <byte 3908> lbits:1 reserved2 R Reserved lbits:1 deverr R/CLL Device Bus Error lbits:1 dmaerr R/CLL DMA Error lbits:1 cpuerr R/CLL CPU Error lbits:1 idma0 R/CLL IDMA Channel0 Completion lbits:1 idma1 R/CLL IDMA Channel1 Completion lbits:1 idma2 R/CLL IDMA Channel2 Completion lbits:1 idma3 R/CLL IDMA Channel3 Completion lbits:1 timer0 R/CLL Timer0 lbits:1 timer1 R/CLL Timer1 lbits:1 timer2 R/CLL Timer2 lbits:1 timer3 R/CLL Timer3 lbits:1 pci0 R/CLL PCI0 lbits:1 sramerr R/CLL SRAM Parity Error lbits:1 gbeerr R/CLL Gb Ethernet Error lbits:1 cerr R/CLL Serial Ports Error lbits:1 pci1 R/CLL PCI1 lbits:1 dramerr R/CLL DRAM ECC Error lbits:1 wdnmi R/CLL WatchDog Reached NMI Threshold lbits:1 wde R/CLL WatchDog Reached Terminal Cnt lbits:1 pci0in R/CLL PCI0 Inbound lbits:1 pci0out R/CLL PCI0 Outbound lbits:1 pci1in R/CLL PCI1 Inbound lbits:1 pci1out R/CLL PCI1 Outbound lbits:1 p1_gpp0_7 R/CLL CPU1 GPP[7:0] Interrupt lbits:1 p1_gpp8_15 R/CLL CPU1 GPP[15:8] Interrupt lbits:1 p1_gpp16_23 R/CLL CPU1 GPP[23:16] Interrupt lbits:1 p1_gpp24_31 R/CLL CPU1 GPP[24:31] Interrupt lbits:1 p1_cpu_db R/CLL CPU1 Doorbell lbits:3 reserved1 R Reserved {} or main_interrupt_cause_low (Offset 0x0004) Main Interrupt Cause (Low) <byte 3908> ulong value As longword endunion main_interrupt_cause_low (Offset 0x0004) Main Interrupt Cause (Low) <byte 3912> union main_interrupt_cause_high (Offset 0x000C) Main Interrupt Cause (High) <byte 3912> {field (By field)} <byte 3912> lbits:1 ge0 R/CLL Gb Ethernet0 lbits:1 ge1 R/CLL Gb Ethernet1 lbits:1 ge2 R/CLL Gb Ethernet2 lbits:1 reserved3 R Reserved lbits:1 sdma0 R/CLL MPSC0 SDMA lbits:1 twsi R/CLL TWSI (I2C) lbits:1 sdma1 R/CLL MPSC1 SDMA lbits:1 brg R/CLL BRG

lbits:1 mpsc0 R/CLL MPSC0 lbits:1 mpsc1 R/CLL MPSC1 lbits:1 g0rx R/CLL Gb Ethernet0 Rx lbits:1 g0tx R/CLL Gb Ethernet0 Tx lbits:1 g0misc R/CLL Gb Ethernet0 Misc lbits:1 g1rx R/CLL Gb Ethernet1 Rx lbits:1 g1tx R/CLL Gb Ethernet1 Tx lbits:1 g1misc R/CLL Gb Ethernet1 Misc lbits:1 g2rx R/CLL Gb Ethernet2 Rx lbits:1 g2tx R/CLL Gb Ethernet2 Tx lbits:1 g2misc R/CLL Gb Ethernet2 Misc lbits:5 reserved2 R Reserved lbits:1 p0_gpp0_7 R/CLL CPU0 GPP[7:0] Interrupt lbits:1 p0_gpp8_15 R/CLL CPU0 GPP[15:8] Interrupt lbits:1 p0_gpp16_23 R/CLL CPU0 GPP[23:16] Interrupt lbits:1 p0_gpp24_31 R/CLL CPU0 GPP[24:31] Interrupt lbits:1 p0_cpu_db R/CLL CPU0 Doorbell lbits:3 reserved1 R Reserved {} or main_interrupt_cause_high (Offset 0x000C) Main Interrupt Cause (High) <byte 3912> ulong value As longword endunion main_interrupt_cause_high (Offset 0x000C) Main Interrupt Cause (High) <byte 3916> union cpuint_0_mask_low (Offset 0x0014) CPUInt[0]# Mask (Low) <byte 3916> {field (By field)} <byte 3916> lbits:1 reserved2 R Reserved lbits:1 deverr R/CLL Device Bus Error lbits:1 dmaerr R/CLL DMA Error lbits:1 cpuerr R/CLL CPU Error lbits:1 idma0 R/CLL IDMA Channel0 Completion lbits:1 idma1 R/CLL IDMA Channel1 Completion lbits:1 idma2 R/CLL IDMA Channel2 Completion lbits:1 idma3 R/CLL IDMA Channel3 Completion lbits:1 timer0 R/CLL Timer0 lbits:1 timer1 R/CLL Timer1 lbits:1 timer2 R/CLL Timer2 lbits:1 timer3 R/CLL Timer3 lbits:1 pci0 R/CLL PCI0 lbits:1 sramerr R/CLL SRAM Parity Error lbits:1 gbeerr R/CLL Gb Ethernet Error lbits:1 cerr R/CLL Serial Ports Error lbits:1 pci1 R/CLL PCI1 lbits:1 dramerr R/CLL DRAM ECC Error lbits:1 wdnmi R/CLL WatchDog Reached NMI Threshold lbits:1 wde R/CLL WatchDog Reached Terminal Cnt lbits:1 pci0in R/CLL PCI0 Inbound lbits:1 pci0out R/CLL PCI0 Outbound lbits:1 pci1in R/CLL PCI1 Inbound lbits:1 pci1out R/CLL PCI1 Outbound lbits:1 p1_gpp0_7 R/CLL CPU1 GPP[7:0] Interrupt lbits:1 p1_gpp8_15 R/CLL CPU1 GPP[15:8] Interrupt lbits:1 p1_gpp16_23 R/CLL CPU1 GPP[23:16] Interrupt lbits:1 p1_gpp24_31 R/CLL CPU1 GPP[24:31] Interrupt lbits:1 p1_cpu_db R/CLL CPU1 Doorbell lbits:3 reserved1 R Reserved {} or cpuint_0_mask_low (Offset 0x0014) CPUInt[0]# Mask (Low)

<byte 3916> ulong value As longword endunion cpuint_0_mask_low (Offset 0x0014) CPUInt[0]# Mask (Low) <byte 3920> union cpuint_0_mask_high (Offset 0x001C) CPUInt[0]# Mask (High) <byte 3920> {field (By field)} <byte 3920> lbits:1 ge0 R/CLL Gb Ethernet0 lbits:1 ge1 R/CLL Gb Ethernet1 lbits:1 ge2 R/CLL Gb Ethernet2 lbits:1 reserved3 R Reserved lbits:1 sdma0 R/CLL MPSC0 SDMA lbits:1 twsi R/CLL TWSI (I2C) lbits:1 sdma1 R/CLL MPSC1 SDMA lbits:1 brg R/CLL BRG lbits:1 mpsc0 R/CLL MPSC0 lbits:1 mpsc1 R/CLL MPSC1 lbits:1 g0rx R/CLL Gb Ethernet0 Rx lbits:1 g0tx R/CLL Gb Ethernet0 Tx lbits:1 g0misc R/CLL Gb Ethernet0 Misc lbits:1 g1rx R/CLL Gb Ethernet1 Rx lbits:1 g1tx R/CLL Gb Ethernet1 Tx lbits:1 g1misc R/CLL Gb Ethernet1 Misc lbits:1 g2rx R/CLL Gb Ethernet2 Rx lbits:1 g2tx R/CLL Gb Ethernet2 Tx lbits:1 g2misc R/CLL Gb Ethernet2 Misc lbits:5 reserved2 R Reserved lbits:1 p0_gpp0_7 R/CLL CPU0 GPP[7:0] Interrupt lbits:1 p0_gpp8_15 R/CLL CPU0 GPP[15:8] Interrupt lbits:1 p0_gpp16_23 R/CLL CPU0 GPP[23:16] Interrupt lbits:1 p0_gpp24_31 R/CLL CPU0 GPP[24:31] Interrupt lbits:1 p0_cpu_db R/CLL CPU0 Doorbell lbits:3 reserved1 R Reserved {} or cpuint_0_mask_high (Offset 0x001C) CPUInt[0]# Mask (High) <byte 3920> ulong value As longword endunion cpuint_0_mask_high (Offset 0x001C) CPUInt[0]# Mask (High) <byte 3924> union cpu_error_address_low (Offset 0x0070) CPU Error Address (Low) <byte 3924> {field (By field)} <byte 3924> lbits:32 erraddr RO Latched address bits [31:0] of a CPU transaction: illegal address (failed address decoding), access protection violation, bad data parity , bad address parity {} or cpu_error_address_low (Offset 0x0070) CPU Error Address (Low) <byte 3924> ulong value As longword endunion cpu_error_address_low (Offset 0x0070) CPU Error Address (Low) <byte 3928> union cpu_error_address_high (Offset 0x0078) CPU Error Address (High) <byte 3928> {field (By field)} <byte 3928> lbits:4 erraddr_h R Error Address bits [35:32] lbits:5 errpar R Address Parity bits lbits:1 hit R 1=HIT# asserted (cached)

lbits:22 reserved R Reserved {} or cpu_error_address_high (Offset 0x0078) CPU Error Address (High) <byte 3928> ulong value As longword endunion cpu_error_address_high (Offset 0x0078) CPU Error Address (High) <byte 3932> union cpu_error_data_low (Offset 0x0128) CPU Error Data (Low) <byte 3932> {field (By field)} <byte 3932> lbits:32 perrdata RO Latched data bits in case of bad data parity sampled on write transactions or on master read transactions on the 60x bus {} or cpu_error_data_low (Offset 0x0128) CPU Error Data (Low) <byte 3932> ulong value As longword endunion cpu_error_data_low (Offset 0x0128) CPU Error Data (Low) <byte 3936> union cpu_error_data_high (Offset 0x0130) CPU Error Data (High) <byte 3936> {field (By field)} <byte 3936> lbits:32 perrdata RO Latched data bits in case of bad data parity sampled on write transactions or on master read transactions on the 60x bus {} or cpu_error_data_high (Offset 0x0130) CPU Error Data (High) <byte 3936> ulong value As longword endunion cpu_error_data_high (Offset 0x0130) CPU Error Data (High) <byte 3940> union cpu_error_parity (Offset 0x0138) CPU Error Parity <byte 3940> {field (By field)} <byte 3940> lbits:8 perrpar RO Latched data parity bus in case of bad data parity sampled on write transactions or on master read transactions on the 60x bus lbits:2 gronk ?? Atlantis spec. error, Table 273--these bits are not defined! !! lbits:22 reserved0 RES Reserved {} or cpu_error_parity (Offset 0x0138) CPU Error Parity <byte 3940> ulong value As longword endunion cpu_error_parity (Offset 0x0138) CPU Error Parity <byte 3944> union cpu_error_cause (Offset 0x0140) CPU Error Cause <byte 3944> {field (By field)} <byte 3944> lbits:1 addrout R/W0C CPU Address Out of Range in Addr, Data, Parity Err Regs lbits:1 addrperr R/W0C Bad Address Parity Detected lbits:1 tterr R/W0C Transfer Type/Init Val Violation lbits:1 accerr R/W0C Access to a Protected Region lbits:1 wrerr R/W0C Write to a Wrt Protectd Region lbits:1 cacheerr R/W0C Cache Rd, Caching Protected lbits:1 wrdataperr R/W0C Bad Write Data Parity Detected lbits:1 rddataperr R/W0C Bad Read Data Parity Detected lbits:19 reserved R Reserved lbits:5 sel R Type of above error captured

{} or cpu_error_cause (Offset 0x0140) CPU Error Cause <byte 3944> ulong value As longword endunion cpu_error_cause (Offset 0x0140) CPU Error Cause <byte 3948> union cpu0_error_mask (Offset 0x0148) CPU0 Error Mask <byte 3948> {field (By field)} <byte 3948> lbits:1 addrout R/W0C CPU Address Out of Range in Addr, Data, Parity Err Regs lbits:1 addrperr R/W0C Bad Address Parity Detected lbits:1 tterr R/W0C Transfer Type/Init Val Violation lbits:1 accerr R/W0C Access to a Protected Region lbits:1 wrerr R/W0C Write to a Wrt Protectd Region lbits:1 cacheerr R/W0C Cache Rd, Caching Protected lbits:1 wrdataperr R/W0C Bad Write Data Parity Detected lbits:1 rddataperr R/W0C Bad Read Data Parity Detected lbits:19 reserved R Reserved lbits:5 sel R Type of above error captured {} or cpu0_error_mask (Offset 0x0148) CPU0 Error Mask <byte 3948> ulong value As longword endunion cpu0_error_mask (Offset 0x0148) CPU0 Error Mask <byte 3952> union sram_configuration (Offset 0x0380) SRAM Configuration <byte 3952> {field (By field)} <byte 3952> lbits:2 ccen R/W Cache Coherency Enable lbits:2 reserved2 R Reserved lbits:1 paren R/W Parity Enable (gen. & check) lbits:1 perrpropen R/W Parity Error Propagate Enable lbits:1 forceparen R/W Force Parity Enable (debug) lbits:1 park R/W Arbiter Park on cross bar lbits:8 forcepar R/W Forced Parity Byte Value lbits:3 rtc R Reserved by Marvell (0x6) lbits:2 wtc R Reserved by Marvell (0x2) lbits:11 reserved1 R Reserved {} or sram_configuration (Offset 0x0380) SRAM Configuration <byte 3952> ulong value As longword endunion sram_configuration (Offset 0x0380) SRAM Configuration <byte 3956> union sram_error_cause (Offset 0x0388) SRAM Error Cause <byte 3956> {field (By field)} <byte 3956> lbits:1 perr0_7 R/W0C Parity Error Byte [7:0] lbits:1 perr8_15 R/W0C Parity Error Byte [15:8] lbits:1 perr16_23 R/W0C Parity Error Byte [23:16] lbits:1 perr24_31 R/W0C Parity Error Byte [31:24] lbits:1 perr32_39 R/W0C Parity Error Byte [39:32] lbits:1 perr40_47 R/W0C Parity Error Byte [47:40] lbits:1 perr48_55 R/W0C Parity Error Byte [55:48] lbits:1 perr56_63 R/W0C Parity Error Byte [63:56] lbits:24 reserved R Reserved {}

or sram_error_cause (Offset 0x0388) SRAM Error Cause <byte 3956> ulong value As longword endunion sram_error_cause (Offset 0x0388) SRAM Error Cause <byte 3960> union sram_error_address (Offset 0x0390) SRAM Error Address <byte 3960> {field (By field)} <byte 3960> lbits:32 addr RW Error Address bits[31:0] {} or sram_error_address (Offset 0x0390) SRAM Error Address <byte 3960> ulong value As longword endunion sram_error_address (Offset 0x0390) SRAM Error Address <byte 3964> union sram_error_data_low (Offset 0x0398) SRAM Error Data (Low) <byte 3964> {field (By field)} <byte 3964> lbits:32 data RW Error data {} or sram_error_data_low (Offset 0x0398) SRAM Error Data (Low) <byte 3964> ulong value As longword endunion sram_error_data_low (Offset 0x0398) SRAM Error Data (Low) <byte 3968> union sram_error_data_high (Offset 0x03A0) SRAM Error Data (High) <byte 3968> {field (By field)} <byte 3968> lbits:32 data RW Error data {} or sram_error_data_high (Offset 0x03A0) SRAM Error Data (High) <byte 3968> ulong value As longword endunion sram_error_data_high (Offset 0x03A0) SRAM Error Data (High) <byte 3972> union sram_error_parity (Offset 0x03A8) SRAM Error Parity <byte 3972> {field (By field)} <byte 3972> lbits:8 par RW Error parity lbits:24 reserved0 RES Reserved {} or sram_error_parity (Offset 0x03A8) SRAM Error Parity <byte 3972> ulong value As longword endunion sram_error_parity (Offset 0x03A8) SRAM Error Parity <byte 3976> union sram_error_address_high (Offset 0x03F8) SRAM Error Address (High) <byte 3976> {field (By field)} <byte 3976> lbits:4 addr RW Error Address bits[35:32] Latched upon SRAM parity error dete ction lbits:28 reserved0 RES Reserved {} or sram_error_address_high (Offset 0x03F8) SRAM Error Address (High) <byte 3976>

ulong value As longword endunion sram_error_address_high (Offset 0x03F8) SRAM Error Address (High) <byte 3980> union device_interrupt_cause (Offset 0x04D0) Device Interrupt Cause <byte 3980> {field (By field)} <byte 3980> lbits:1 dbursterr R/W0C Forced ECC Byte Value in Addr, Data, Parity Err Regs lbits:1 drdyerr R/W0C Write 'forceecc' Enable (debug) lbits:1 perr0 R/W0C Parity Error 0 lbits:1 perr1 R/W0C Parity Error 1 lbits:1 perr2 R/W0C Parity Error 2 lbits:1 perr3 R/W0C Parity Error 3 lbits:21 reserved R Reserved lbits:5 sel R Type of above error captured {} or device_interrupt_cause (Offset 0x04D0) Device Interrupt Cause <byte 3980> ulong value As longword endunion device_interrupt_cause (Offset 0x04D0) Device Interrupt Cause <byte 3984> union device_interrupt_mask (Offset 0x04D4) Device Interrupt Mask <byte 3984> {field (By field)} <byte 3984> lbits:1 dbursterr R/W0C Forced ECC Byte Value in Addr, Data, Parity Err Regs lbits:1 drdyerr R/W0C Write 'forceecc' Enable (debug) lbits:1 perr0 R/W0C Parity Error 0 lbits:1 perr1 R/W0C Parity Error 1 lbits:1 perr2 R/W0C Parity Error 2 lbits:1 perr3 R/W0C Parity Error 3 lbits:21 reserved R Reserved lbits:5 sel R Type of above error captured {} or device_interrupt_mask (Offset 0x04D4) Device Interrupt Mask <byte 3984> ulong value As longword endunion device_interrupt_mask (Offset 0x04D4) Device Interrupt Mask <byte 3988> union device_error_address (Offset 0x04D8) Device Error Address <byte 3988> {field (By field)} <byte 3988> lbits:32 addr RW Latched Address Upon Device Error Condition {} or device_error_address (Offset 0x04D8) Device Error Address <byte 3988> ulong value As longword endunion device_error_address (Offset 0x04D8) Device Error Address <byte 3992> union device_error_data (Offset 0x04DC) Device Error Data <byte 3992> {field (By field)} <byte 3992> lbits:32 data RW Latched data upon parity error detection {} or device_error_data (Offset 0x04DC) Device Error Data <byte 3992> ulong value As longword endunion device_error_data (Offset 0x04DC) Device Error Data

<byte 3996> union device_error_parity (Offset 0x04E0) Device Error Parity <byte 3996> {field (By field)} <byte 3996> lbits:4 par RW Latched parity upon parity error detection lbits:28 reserved0 RES Reserved, read only {} or device_error_parity (Offset 0x04E0) Device Error Parity <byte 3996> ulong value As longword endunion device_error_parity (Offset 0x04E0) Device Error Parity <byte 4000> union idma_interrupt_cause (Offset 0x08C0) IDMA Interrupt Cause <byte 4000> {field (By field)} <byte 4000> lbits:1 dmacmplt0 R/W0C Channel 0 DMA Complete lbits:1 addrmiss0 R/W0C Channel 0 Address Miss, Failed Decode lbits:1 accprot0 R/W0C Channel 0 Access Protect Violation lbits:1 wrprot0 R/W0C Channel 0 Write Protect Violation lbits:1 own0 R/W0C Channel 0 Descriptor Ownership Violation lbits:3 reserved0 R Reserved lbits:1 dmacmplt1 R/W0C Channel 1 DMA Complete lbits:1 addrmiss1 R/W0C Channel 1 Address Miss, Failed Decode lbits:1 accprot1 R/W0C Channel 1 Access Protect Violation lbits:1 wrprot1 R/W0C Channel 1 Write Protect Violation lbits:1 own1 R/W0C Channel 1 Descriptor Ownership Violation lbits:3 reserved1 R Reserved lbits:1 dmacmplt2 R/W0C Channel 2 DMA Complete lbits:1 addrmiss2 R/W0C Channel 2 Address Miss, Failed Decode lbits:1 accprot2 R/W0C Channel 2 Access Protect Violation lbits:1 wrprot2 R/W0C Channel 2 Write Protect Violation lbits:1 own2 R/W0C Channel 2 Descriptor Ownership Violation lbits:3 reserved2 R Reserved lbits:1 dmacmplt3 R/W0C Channel 3 DMA Complete lbits:1 addrmiss3 R/W0C Channel 3 Address Miss, Failed Decode lbits:1 accprot3 R/W0C Channel 3 Access Protect Violation lbits:1 wrprot3 R/W0C Channel 3 Write Protect Violation lbits:1 own3 R/W0C Channel 3 Descriptor Ownership Violation lbits:3 reserved3 R Reserved {} or idma_interrupt_cause (Offset 0x08C0) IDMA Interrupt Cause <byte 4000> ulong value As longword endunion idma_interrupt_cause (Offset 0x08C0) IDMA Interrupt Cause <byte 4004> union idma_interrupt_mask (Offset 0x08C4) IDMA Interrupt Mask <byte 4004> {field (By field)} <byte 4004> lbits:1 dmacmplt0 R/W0C Channel 0 DMA Complete lbits:1 addrmiss0 R/W0C Channel 0 Address Miss, Failed Decode lbits:1 accprot0 R/W0C Channel 0 Access Protect Violation lbits:1 wrprot0 R/W0C Channel 0 Write Protect Violation lbits:1 own0 R/W0C Channel 0 Descriptor Ownership Violation lbits:3 reserved0 R Reserved lbits:1 dmacmplt1 R/W0C Channel 1 DMA Complete lbits:1 addrmiss1 R/W0C Channel 1 Address Miss, Failed Decode lbits:1 accprot1 R/W0C Channel 1 Access Protect Violation

lbits:1 wrprot1 R/W0C Channel 1 Write Protect Violation lbits:1 own1 R/W0C Channel 1 Descriptor Ownership Violation lbits:3 reserved1 R Reserved lbits:1 dmacmplt2 R/W0C Channel 2 DMA Complete lbits:1 addrmiss2 R/W0C Channel 2 Address Miss, Failed Decode lbits:1 accprot2 R/W0C Channel 2 Access Protect Violation lbits:1 wrprot2 R/W0C Channel 2 Write Protect Violation lbits:1 own2 R/W0C Channel 2 Descriptor Ownership Violation lbits:3 reserved2 R Reserved lbits:1 dmacmplt3 R/W0C Channel 3 DMA Complete lbits:1 addrmiss3 R/W0C Channel 3 Address Miss, Failed Decode lbits:1 accprot3 R/W0C Channel 3 Access Protect Violation lbits:1 wrprot3 R/W0C Channel 3 Write Protect Violation lbits:1 own3 R/W0C Channel 3 Descriptor Ownership Violation lbits:3 reserved3 R Reserved {} or idma_interrupt_mask (Offset 0x08C4) IDMA Interrupt Mask <byte 4004> ulong value As longword endunion idma_interrupt_mask (Offset 0x08C4) IDMA Interrupt Mask <byte 4008> union idma_error_address (Offset 0x08C8) IDMA Error Address <byte 4008> {field (By field)} <byte 4008> lbits:32 erraddr RW Bits[31:0] of Error Address {} or idma_error_address (Offset 0x08C8) IDMA Error Address <byte 4008> ulong value As longword endunion idma_error_address (Offset 0x08C8) IDMA Error Address <byte 4012> union sdram_error_data_high (Offset 0x1440) SDRAM Error Data (High) <byte 4012> {field (By field)} <byte 4012> lbits:32 eccdata RW Sampled 32 high bits of the last data with ECC error {} or sdram_error_data_high (Offset 0x1440) SDRAM Error Data (High) <byte 4012> ulong value As longword endunion sdram_error_data_high (Offset 0x1440) SDRAM Error Data (High) <byte 4016> union sdram_error_data_low (Offset 0x1444) SDRAM Error Data (Low) <byte 4016> {field (By field)} <byte 4016> lbits:32 eccdata RW Sampled 32 low bits of the last data with ECC error {} or sdram_error_data_low (Offset 0x1444) SDRAM Error Data (Low) <byte 4016> ulong value As longword endunion sdram_error_data_low (Offset 0x1444) SDRAM Error Data (Low) <byte 4020> union sdram_received_ecc (Offset 0x1448) SDRAM Received ECC <byte 4020> {field (By field)} <byte 4020> lbits:8 eccreg RW ECC code being read from SDRAM lbits:24 reserved0 RES Reserved

{} or sdram_received_ecc (Offset 0x1448) SDRAM Received ECC <byte 4020> ulong value As longword endunion sdram_received_ecc (Offset 0x1448) SDRAM Received ECC <byte 4024> union sdram_calculated_ecc (Offset 0x144C) SDRAM Calculated ECC <byte 4024> {field (By field)} <byte 4024> lbits:8 ecccalc RW ECC code calculated by Dunit lbits:24 reserved0 RES Reserved {} or sdram_calculated_ecc (Offset 0x144C) SDRAM Calculated ECC <byte 4024> ulong value As longword endunion sdram_calculated_ecc (Offset 0x144C) SDRAM Calculated ECC <byte 4028> union sdram_error_address (Offset 0x1450) SDRAM Error Address <byte 4028> {field (By field /* NOTE: WOC just clears the dramerr)} <byte 4028> lbits:1 errtype R/W0C Err Type (0=CDEs>limit, 1=UDE) lbits:2 bank R/W0C DIMM Bank (0-3) lbits:29 eccaddr R/W0C Address of Error [31:3] (NOTE: Atlantis spec. error, Tabl e 303--indicates this field is 30 bits [31:2]; changed to 29 bits [31:3]) {} or sdram_error_address (Offset 0x1450) SDRAM Error Address <byte 4028> ulong value As longword /* bit in the lower cause reg. endunion sdram_error_address (Offset 0x1450) SDRAM Error Address <byte 4032> union sdram_ecc_control (Offset 0x1454) SDRAM ECC Control <byte 4032> {field (By field)} <byte 4032> lbits:8 forceecc R/W Forced ECC Byte Value lbits:1 forceeccen R/W Write 'forceecc' Enable (debug) lbits:1 perrpropen R/W Propagate PERR to ECC mem. Err lbits:6 reserved2 R Reserved lbits:8 threcc R/W Threshold for reporting CDEs lbits:8 reserved1 R Reserved {} or sdram_ecc_control (Offset 0x1454) SDRAM ECC Control <byte 4032> ulong value As longword endunion sdram_ecc_control (Offset 0x1454) SDRAM ECC Control <byte 4036> union sdram_ecc_counter (Offset 0x1458) SDRAM ECC Counter <byte 4036> {field (By field)} <byte 4036> lbits:32 count R Number of single bit ECC errors detected {} or sdram_ecc_counter (Offset 0x1458) SDRAM ECC Counter <byte 4036> ulong value As longword endunion sdram_ecc_counter (Offset 0x1458) SDRAM ECC Counter {} <byte 4040>

{decoder (Decoder)} <byte 4040> {rsvd (03 Reserved)} <byte 4040> utiny value {} <byte 4041> union gpo_c 02 GPO C: Enet Card Reset.. <byte 4041> {field (By field)} <byte 4041> tbits:7 rsvd R Reserved tbits:1 enet_card_rst R/W Ethernet Card Reset {} or gpo_c 02 GPO C: Enet Card Reset.. <byte 4041> utiny value As utiny endunion gpo_c 02 GPO C: Enet Card Reset.. <byte 4042> union gpi 01 GPI B: Module Type.. <byte 4042> {field (By field)} <byte 4042> tbits:4 mod_type R Module Type tbits:3 rsvd R Reserved tbits:1 enet_gpi R/W Ethernet Card GPI {} or gpi 01 GPI B: Module Type.. <byte 4042> utiny value As utiny endunion gpi 01 GPI B: Module Type.. <byte 4043> union mod_rev 00 GPI A: Module Revision <byte 4043> {field (By field)} <byte 4043> tbits:3 rev R Revision tbits:5 eco_level R ECO Level {} or mod_rev 00 GPI A: Module Revision <byte 4043> utiny value As utiny endunion mod_rev 00 GPI A: Module Revision <byte 4044> {rsvd1[1] (06-FC Reserved)} <byte 4044> utiny value {} <byte 4045> {rsvd1[0] (06-FC Reserved)} <byte 4045> utiny value {} <byte 4046> union gpo_bstat1 05 GPO E: Boot Status LEDs.. <byte 4046> {field (By field)} <byte 4046> tbits:1 led8 R/W Boot Status LED 8 tbits:1 led9 R/W Boot Status LED 9

tbits:6 rsvd R Reserved {} or gpo_bstat1 05 GPO E: Boot Status LEDs.. <byte 4046> utiny value As utiny endunion gpo_bstat1 05 GPO E: Boot Status LEDs.. <byte 4047> union bstat0 04 GPO D: Boot Status LEDs <byte 4047> {field (By field)} <byte 4047> tbits:1 led0 R/W Boot Status LED 8 tbits:1 led1 R/W Boot Status LED 9 tbits:1 led2 R/W Boot Status LED 9 tbits:1 led3 R/W Boot Status LED 9 tbits:1 led4 R/W Boot Status LED 9 tbits:1 led5 R/W Boot Status LED 9 tbits:1 led6 R/W Boot Status LED 9 tbits:1 led7 R/W Boot Status LED 9 {} or bstat0 04 GPO D: Boot Status LEDs <byte 4047> utiny value As utiny endunion bstat0 04 GPO D: Boot Status LEDs <byte 4048> {rsvd1[5] (06-FC Reserved)} <byte 4048> utiny value {} <byte 4049> {rsvd1[4] (06-FC Reserved)} <byte 4049> utiny value {} <byte 4050> {rsvd1[3] (06-FC Reserved)} <byte 4050> utiny value {} <byte 4051> {rsvd1[2] (06-FC Reserved)} <byte 4051> utiny value {} <byte 4052> {rsvd1[9] (06-FC Reserved)} <byte 4052> utiny value {} <byte 4053> {rsvd1[8] (06-FC Reserved)} <byte 4053> utiny value {} <byte 4054> {rsvd1[7] (06-FC Reserved)} <byte 4054> utiny value {} <byte 4055>

{rsvd1[6] (06-FC Reserved)} <byte 4055> utiny value {} <byte 4056> {rsvd1[13] (06-FC Reserved)} <byte 4056> utiny value {} <byte 4057> {rsvd1[12] (06-FC Reserved)} <byte 4057> utiny value {} <byte 4058> {rsvd1[11] (06-FC Reserved)} <byte 4058> utiny value {} <byte 4059> {rsvd1[10] (06-FC Reserved)} <byte 4059> utiny value {} <byte 4060> {rsvd1[17] (06-FC Reserved)} <byte 4060> utiny value {} <byte 4061> {rsvd1[16] (06-FC Reserved)} <byte 4061> utiny value {} <byte 4062> {rsvd1[15] (06-FC Reserved)} <byte 4062> utiny value {} <byte 4063> {rsvd1[14] (06-FC Reserved)} <byte 4063> utiny value {} <byte 4064> {rsvd1[21] (06-FC Reserved)} <byte 4064> utiny value {} <byte 4065> {rsvd1[20] (06-FC Reserved)} <byte 4065> utiny value {} <byte 4066> {rsvd1[19] (06-FC Reserved)} <byte 4066> utiny value {} <byte 4067>

{rsvd1[18] (06-FC <byte 4067> utiny value {} <byte 4068> {rsvd1[25] (06-FC <byte 4068> utiny value {} <byte 4069> {rsvd1[24] (06-FC <byte 4069> utiny value {} <byte 4070> {rsvd1[23] (06-FC <byte 4070> utiny value {} <byte 4071> {rsvd1[22] (06-FC <byte 4071> utiny value {} <byte 4072> {rsvd1[29] (06-FC <byte 4072> utiny value {} <byte 4073> {rsvd1[28] (06-FC <byte 4073> utiny value {} <byte 4074> {rsvd1[27] (06-FC <byte 4074> utiny value {} <byte 4075> {rsvd1[26] (06-FC <byte 4075> utiny value {} <byte 4076> {rsvd1[33] (06-FC <byte 4076> utiny value {} <byte 4077> {rsvd1[32] (06-FC <byte 4077> utiny value {} <byte 4078> {rsvd1[31] (06-FC <byte 4078> utiny value {} <byte 4079>

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

{rsvd1[30] (06-FC <byte 4079> utiny value {} <byte 4080> {rsvd1[37] (06-FC <byte 4080> utiny value {} <byte 4081> {rsvd1[36] (06-FC <byte 4081> utiny value {} <byte 4082> {rsvd1[35] (06-FC <byte 4082> utiny value {} <byte 4083> {rsvd1[34] (06-FC <byte 4083> utiny value {} <byte 4084> {rsvd1[41] (06-FC <byte 4084> utiny value {} <byte 4085> {rsvd1[40] (06-FC <byte 4085> utiny value {} <byte 4086> {rsvd1[39] (06-FC <byte 4086> utiny value {} <byte 4087> {rsvd1[38] (06-FC <byte 4087> utiny value {} <byte 4088> {rsvd1[45] (06-FC <byte 4088> utiny value {} <byte 4089> {rsvd1[44] (06-FC <byte 4089> utiny value {} <byte 4090> {rsvd1[43] (06-FC <byte 4090> utiny value {} <byte 4091>

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

{rsvd1[42] (06-FC <byte 4091> utiny value {} <byte 4092> {rsvd1[49] (06-FC <byte 4092> utiny value {} <byte 4093> {rsvd1[48] (06-FC <byte 4093> utiny value {} <byte 4094> {rsvd1[47] (06-FC <byte 4094> utiny value {} <byte 4095> {rsvd1[46] (06-FC <byte 4095> utiny value {} <byte 4096> {rsvd1[53] (06-FC <byte 4096> utiny value {} <byte 4097> {rsvd1[52] (06-FC <byte 4097> utiny value {} <byte 4098> {rsvd1[51] (06-FC <byte 4098> utiny value {} <byte 4099> {rsvd1[50] (06-FC <byte 4099> utiny value {} <byte 4100> {rsvd1[57] (06-FC <byte 4100> utiny value {} <byte 4101> {rsvd1[56] (06-FC <byte 4101> utiny value {} <byte 4102> {rsvd1[55] (06-FC <byte 4102> utiny value {} <byte 4103>

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

{rsvd1[54] (06-FC <byte 4103> utiny value {} <byte 4104> {rsvd1[61] (06-FC <byte 4104> utiny value {} <byte 4105> {rsvd1[60] (06-FC <byte 4105> utiny value {} <byte 4106> {rsvd1[59] (06-FC <byte 4106> utiny value {} <byte 4107> {rsvd1[58] (06-FC <byte 4107> utiny value {} <byte 4108> {rsvd1[65] (06-FC <byte 4108> utiny value {} <byte 4109> {rsvd1[64] (06-FC <byte 4109> utiny value {} <byte 4110> {rsvd1[63] (06-FC <byte 4110> utiny value {} <byte 4111> {rsvd1[62] (06-FC <byte 4111> utiny value {} <byte 4112> {rsvd1[69] (06-FC <byte 4112> utiny value {} <byte 4113> {rsvd1[68] (06-FC <byte 4113> utiny value {} <byte 4114> {rsvd1[67] (06-FC <byte 4114> utiny value {} <byte 4115>

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

{rsvd1[66] (06-FC <byte 4115> utiny value {} <byte 4116> {rsvd1[73] (06-FC <byte 4116> utiny value {} <byte 4117> {rsvd1[72] (06-FC <byte 4117> utiny value {} <byte 4118> {rsvd1[71] (06-FC <byte 4118> utiny value {} <byte 4119> {rsvd1[70] (06-FC <byte 4119> utiny value {} <byte 4120> {rsvd1[77] (06-FC <byte 4120> utiny value {} <byte 4121> {rsvd1[76] (06-FC <byte 4121> utiny value {} <byte 4122> {rsvd1[75] (06-FC <byte 4122> utiny value {} <byte 4123> {rsvd1[74] (06-FC <byte 4123> utiny value {} <byte 4124> {rsvd1[81] (06-FC <byte 4124> utiny value {} <byte 4125> {rsvd1[80] (06-FC <byte 4125> utiny value {} <byte 4126> {rsvd1[79] (06-FC <byte 4126> utiny value {} <byte 4127>

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

{rsvd1[78] (06-FC <byte 4127> utiny value {} <byte 4128> {rsvd1[85] (06-FC <byte 4128> utiny value {} <byte 4129> {rsvd1[84] (06-FC <byte 4129> utiny value {} <byte 4130> {rsvd1[83] (06-FC <byte 4130> utiny value {} <byte 4131> {rsvd1[82] (06-FC <byte 4131> utiny value {} <byte 4132> {rsvd1[89] (06-FC <byte 4132> utiny value {} <byte 4133> {rsvd1[88] (06-FC <byte 4133> utiny value {} <byte 4134> {rsvd1[87] (06-FC <byte 4134> utiny value {} <byte 4135> {rsvd1[86] (06-FC <byte 4135> utiny value {} <byte 4136> {rsvd1[93] (06-FC <byte 4136> utiny value {} <byte 4137> {rsvd1[92] (06-FC <byte 4137> utiny value {} <byte 4138> {rsvd1[91] (06-FC <byte 4138> utiny value {} <byte 4139>

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

Reserved)}

{rsvd1[90] (06-FC Reserved)} <byte 4139> utiny value {} <byte 4140> {rsvd1[97] (06-FC Reserved)} <byte 4140> utiny value {} <byte 4141> {rsvd1[96] (06-FC Reserved)} <byte 4141> utiny value {} <byte 4142> {rsvd1[95] (06-FC Reserved)} <byte 4142> utiny value {} <byte 4143> {rsvd1[94] (06-FC Reserved)} <byte 4143> utiny value {} <byte 4144> {rsvd1[101] (06-FC Reserved)} <byte 4144> utiny value {} <byte 4145> {rsvd1[100] (06-FC Reserved)} <byte 4145> utiny value {} <byte 4146> {rsvd1[99] (06-FC Reserved)} <byte 4146> utiny value {} <byte 4147> {rsvd1[98] (06-FC Reserved)} <byte 4147> utiny value {} <byte 4148> {rsvd1[105] (06-FC Reserved)} <byte 4148> utiny value {} <byte 4149> {rsvd1[104] (06-FC Reserved)} <byte 4149> utiny value {} <byte 4150> {rsvd1[103] (06-FC Reserved)} <byte 4150> utiny value {} <byte 4151>

{rsvd1[102] <byte 4151> utiny value {} <byte 4152> {rsvd1[109] <byte 4152> utiny value {} <byte 4153> {rsvd1[108] <byte 4153> utiny value {} <byte 4154> {rsvd1[107] <byte 4154> utiny value {} <byte 4155> {rsvd1[106] <byte 4155> utiny value {} <byte 4156> {rsvd1[113] <byte 4156> utiny value {} <byte 4157> {rsvd1[112] <byte 4157> utiny value {} <byte 4158> {rsvd1[111] <byte 4158> utiny value {} <byte 4159> {rsvd1[110] <byte 4159> utiny value {} <byte 4160> {rsvd1[117] <byte 4160> utiny value {} <byte 4161> {rsvd1[116] <byte 4161> utiny value {} <byte 4162> {rsvd1[115] <byte 4162> utiny value {} <byte 4163>

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

{rsvd1[114] <byte 4163> utiny value {} <byte 4164> {rsvd1[121] <byte 4164> utiny value {} <byte 4165> {rsvd1[120] <byte 4165> utiny value {} <byte 4166> {rsvd1[119] <byte 4166> utiny value {} <byte 4167> {rsvd1[118] <byte 4167> utiny value {} <byte 4168> {rsvd1[125] <byte 4168> utiny value {} <byte 4169> {rsvd1[124] <byte 4169> utiny value {} <byte 4170> {rsvd1[123] <byte 4170> utiny value {} <byte 4171> {rsvd1[122] <byte 4171> utiny value {} <byte 4172> {rsvd1[129] <byte 4172> utiny value {} <byte 4173> {rsvd1[128] <byte 4173> utiny value {} <byte 4174> {rsvd1[127] <byte 4174> utiny value {} <byte 4175>

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

{rsvd1[126] <byte 4175> utiny value {} <byte 4176> {rsvd1[133] <byte 4176> utiny value {} <byte 4177> {rsvd1[132] <byte 4177> utiny value {} <byte 4178> {rsvd1[131] <byte 4178> utiny value {} <byte 4179> {rsvd1[130] <byte 4179> utiny value {} <byte 4180> {rsvd1[137] <byte 4180> utiny value {} <byte 4181> {rsvd1[136] <byte 4181> utiny value {} <byte 4182> {rsvd1[135] <byte 4182> utiny value {} <byte 4183> {rsvd1[134] <byte 4183> utiny value {} <byte 4184> {rsvd1[141] <byte 4184> utiny value {} <byte 4185> {rsvd1[140] <byte 4185> utiny value {} <byte 4186> {rsvd1[139] <byte 4186> utiny value {} <byte 4187>

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

{rsvd1[138] <byte 4187> utiny value {} <byte 4188> {rsvd1[145] <byte 4188> utiny value {} <byte 4189> {rsvd1[144] <byte 4189> utiny value {} <byte 4190> {rsvd1[143] <byte 4190> utiny value {} <byte 4191> {rsvd1[142] <byte 4191> utiny value {} <byte 4192> {rsvd1[149] <byte 4192> utiny value {} <byte 4193> {rsvd1[148] <byte 4193> utiny value {} <byte 4194> {rsvd1[147] <byte 4194> utiny value {} <byte 4195> {rsvd1[146] <byte 4195> utiny value {} <byte 4196> {rsvd1[153] <byte 4196> utiny value {} <byte 4197> {rsvd1[152] <byte 4197> utiny value {} <byte 4198> {rsvd1[151] <byte 4198> utiny value {} <byte 4199>

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

{rsvd1[150] <byte 4199> utiny value {} <byte 4200> {rsvd1[157] <byte 4200> utiny value {} <byte 4201> {rsvd1[156] <byte 4201> utiny value {} <byte 4202> {rsvd1[155] <byte 4202> utiny value {} <byte 4203> {rsvd1[154] <byte 4203> utiny value {} <byte 4204> {rsvd1[161] <byte 4204> utiny value {} <byte 4205> {rsvd1[160] <byte 4205> utiny value {} <byte 4206> {rsvd1[159] <byte 4206> utiny value {} <byte 4207> {rsvd1[158] <byte 4207> utiny value {} <byte 4208> {rsvd1[165] <byte 4208> utiny value {} <byte 4209> {rsvd1[164] <byte 4209> utiny value {} <byte 4210> {rsvd1[163] <byte 4210> utiny value {} <byte 4211>

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

{rsvd1[162] <byte 4211> utiny value {} <byte 4212> {rsvd1[169] <byte 4212> utiny value {} <byte 4213> {rsvd1[168] <byte 4213> utiny value {} <byte 4214> {rsvd1[167] <byte 4214> utiny value {} <byte 4215> {rsvd1[166] <byte 4215> utiny value {} <byte 4216> {rsvd1[173] <byte 4216> utiny value {} <byte 4217> {rsvd1[172] <byte 4217> utiny value {} <byte 4218> {rsvd1[171] <byte 4218> utiny value {} <byte 4219> {rsvd1[170] <byte 4219> utiny value {} <byte 4220> {rsvd1[177] <byte 4220> utiny value {} <byte 4221> {rsvd1[176] <byte 4221> utiny value {} <byte 4222> {rsvd1[175] <byte 4222> utiny value {} <byte 4223>

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

{rsvd1[174] <byte 4223> utiny value {} <byte 4224> {rsvd1[181] <byte 4224> utiny value {} <byte 4225> {rsvd1[180] <byte 4225> utiny value {} <byte 4226> {rsvd1[179] <byte 4226> utiny value {} <byte 4227> {rsvd1[178] <byte 4227> utiny value {} <byte 4228> {rsvd1[185] <byte 4228> utiny value {} <byte 4229> {rsvd1[184] <byte 4229> utiny value {} <byte 4230> {rsvd1[183] <byte 4230> utiny value {} <byte 4231> {rsvd1[182] <byte 4231> utiny value {} <byte 4232> {rsvd1[189] <byte 4232> utiny value {} <byte 4233> {rsvd1[188] <byte 4233> utiny value {} <byte 4234> {rsvd1[187] <byte 4234> utiny value {} <byte 4235>

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

{rsvd1[186] <byte 4235> utiny value {} <byte 4236> {rsvd1[193] <byte 4236> utiny value {} <byte 4237> {rsvd1[192] <byte 4237> utiny value {} <byte 4238> {rsvd1[191] <byte 4238> utiny value {} <byte 4239> {rsvd1[190] <byte 4239> utiny value {} <byte 4240> {rsvd1[197] <byte 4240> utiny value {} <byte 4241> {rsvd1[196] <byte 4241> utiny value {} <byte 4242> {rsvd1[195] <byte 4242> utiny value {} <byte 4243> {rsvd1[194] <byte 4243> utiny value {} <byte 4244> {rsvd1[201] <byte 4244> utiny value {} <byte 4245> {rsvd1[200] <byte 4245> utiny value {} <byte 4246> {rsvd1[199] <byte 4246> utiny value {} <byte 4247>

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

{rsvd1[198] <byte 4247> utiny value {} <byte 4248> {rsvd1[205] <byte 4248> utiny value {} <byte 4249> {rsvd1[204] <byte 4249> utiny value {} <byte 4250> {rsvd1[203] <byte 4250> utiny value {} <byte 4251> {rsvd1[202] <byte 4251> utiny value {} <byte 4252> {rsvd1[209] <byte 4252> utiny value {} <byte 4253> {rsvd1[208] <byte 4253> utiny value {} <byte 4254> {rsvd1[207] <byte 4254> utiny value {} <byte 4255> {rsvd1[206] <byte 4255> utiny value {} <byte 4256> {rsvd1[213] <byte 4256> utiny value {} <byte 4257> {rsvd1[212] <byte 4257> utiny value {} <byte 4258> {rsvd1[211] <byte 4258> utiny value {} <byte 4259>

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

{rsvd1[210] <byte 4259> utiny value {} <byte 4260> {rsvd1[217] <byte 4260> utiny value {} <byte 4261> {rsvd1[216] <byte 4261> utiny value {} <byte 4262> {rsvd1[215] <byte 4262> utiny value {} <byte 4263> {rsvd1[214] <byte 4263> utiny value {} <byte 4264> {rsvd1[221] <byte 4264> utiny value {} <byte 4265> {rsvd1[220] <byte 4265> utiny value {} <byte 4266> {rsvd1[219] <byte 4266> utiny value {} <byte 4267> {rsvd1[218] <byte 4267> utiny value {} <byte 4268> {rsvd1[225] <byte 4268> utiny value {} <byte 4269> {rsvd1[224] <byte 4269> utiny value {} <byte 4270> {rsvd1[223] <byte 4270> utiny value {} <byte 4271>

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

{rsvd1[222] <byte 4271> utiny value {} <byte 4272> {rsvd1[229] <byte 4272> utiny value {} <byte 4273> {rsvd1[228] <byte 4273> utiny value {} <byte 4274> {rsvd1[227] <byte 4274> utiny value {} <byte 4275> {rsvd1[226] <byte 4275> utiny value {} <byte 4276> {rsvd1[233] <byte 4276> utiny value {} <byte 4277> {rsvd1[232] <byte 4277> utiny value {} <byte 4278> {rsvd1[231] <byte 4278> utiny value {} <byte 4279> {rsvd1[230] <byte 4279> utiny value {} <byte 4280> {rsvd1[237] <byte 4280> utiny value {} <byte 4281> {rsvd1[236] <byte 4281> utiny value {} <byte 4282> {rsvd1[235] <byte 4282> utiny value {} <byte 4283>

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

(06-FC Reserved)}

{rsvd1[234] (06-FC Reserved)} <byte 4283> utiny value {} <byte 4284> {rsvd1[241] (06-FC Reserved)} <byte 4284> utiny value {} <byte 4285> {rsvd1[240] (06-FC Reserved)} <byte 4285> utiny value {} <byte 4286> {rsvd1[239] (06-FC Reserved)} <byte 4286> utiny value {} <byte 4287> {rsvd1[238] (06-FC Reserved)} <byte 4287> utiny value {} <byte 4288> {rsvd1[245] (06-FC Reserved)} <byte 4288> utiny value {} <byte 4289> {rsvd1[244] (06-FC Reserved)} <byte 4289> utiny value {} <byte 4290> {rsvd1[243] (06-FC Reserved)} <byte 4290> utiny value {} <byte 4291> {rsvd1[242] (06-FC Reserved)} <byte 4291> utiny value {} <byte 4292> {decoder_major_rev (FF Decoder Major Revision)} <byte 4292> utiny value {} <byte 4293> {decoder_minor_rev (FE Decoder Minor Revision)} <byte 4293> utiny value {} <byte 4294> {scratch (FD Scratch Register)} <byte 4294> utiny value {} <byte 4295>

{rsvd1[246] (06-FC Reserved)} <byte 4295> utiny value {} {} <byte 4296> {toyclock (DS1557 4MEG NV Y2KC Timekeeping RAM)} <byte 4296> union alarm_minutes Alarm Minutes Union <byte 4296> utiny value Alarm Minutes as byte or alarm_minutes Alarm Minutes Union <byte 4296> {bits (Alarm Minutes by field)} <byte 4296> tbits:4 minutes tbits:3 ten_minutes tbits:1 am2 {} endunion alarm_minutes Alarm Minutes Union <byte 4297> union alarm_seconds Alarm Seconds Union <byte 4297> utiny value Alarm Seconds as byte or alarm_seconds Alarm Seconds Union <byte 4297> {bits (Alarm Seconds by field)} <byte 4297> tbits:4 seconds tbits:3 ten_seconds tbits:1 am1 {} endunion alarm_seconds Alarm Seconds Union <byte 4298> utiny unused <byte 4299> union flag Alarm Enable/Status and Battery Status Flags Union <byte 4299> utiny value Alarm Enable/Status and Battery Status Flags as byte or flag Alarm Enable/Status and Battery Status Flags Union <byte 4299> {bits (Alarm Enable/Status and Battery Status Flags by field)} <byte 4299> tbits:4 unused2 tbits:1 bat_low tbits:1 unused1 tbits:1 alarm tbits:1 alarm_enable {} endunion flag Alarm Enable/Status and Battery Status Flags Union <byte 4300> union watchdog Watchdog Timer Control Flags Union <byte 4300> utiny value Watchdog Timer Control Flags as byte or watchdog Watchdog Timer Control Flags Union <byte 4300> {bits (Watchdog Timer Control Flags by field)} <byte 4300> tbits:7 multiplier tbits:1 steering_bit

{} endunion watchdog Watchdog Timer Control Flags Union <byte 4301> union interrupts Alarm Interrupt Enables Union <byte 4301> utiny value Alarm Interrupt Enables as byte or interrupts Alarm Interrupt Enables Union <byte 4301> {bits (Alarm Interrupt Enables by field)} <byte 4301> tbits:5 unused2 tbits:1 alarm_enable_in_bat tbits:1 unused1 tbits:1 alarm_enable {} endunion interrupts Alarm Interrupt Enables Union <byte 4302> union alarm_date Alarm Date Union <byte 4302> utiny value Alarm Date as byte or alarm_date Alarm Date Union <byte 4302> {bits (Alarm Date by field)} <byte 4302> tbits:4 date tbits:2 ten_date tbits:1 unused tbits:1 am4 {} endunion alarm_date Alarm Date Union <byte 4303> union alarm_hours Alarm Hours Union <byte 4303> utiny value Alarm Hours as byte or alarm_hours Alarm Hours Union <byte 4303> {alarm_hours (Alarm Hours by field)} <byte 4303> tbits:4 hours tbits:2 ten_hours tbits:1 unused tbits:1 am3 {} endunion alarm_hours Alarm Hours Union <byte 4304> union hour Hour Union <byte 4304> utiny value Hour as byte or hour Hour Union <byte 4304> {bits (Hour by field)} <byte 4304> tbits:6 hour tbits:2 unused {} endunion hour Hour Union <byte 4305> union minutes Minutes Union <byte 4305> utiny value Minutes as byte

or minutes Minutes Union <byte 4305> {bits (Minutes by field)} <byte 4305> tbits:7 minutes tbits:1 unused {} endunion minutes Minutes Union <byte 4306> union seconds Seconds/Oscillator Control Union <byte 4306> utiny value Seconds/Oscillator Control as byte or seconds Seconds/Oscillator Control Union <byte 4306> {bits (Seconds/Oscillator Control by field)} <byte 4306> tbits:7 seconds tbits:1 osc {} endunion seconds Seconds/Oscillator Control Union <byte 4307> union control TOY Control Flags/Century Union <byte 4307> utiny value TOY Control Flags/Century as byte or control TOY Control Flags/Century Union <byte 4307> {bits (TOY Control Flags/Century by field)} <byte 4307> tbits:6 century tbits:1 read_bit tbits:1 write_bit {} endunion control TOY Control Flags/Century Union <byte 4308> utiny year Year as byte <byte 4309> union month Month Union <byte 4309> utiny value Month as byte or month Month Union <byte 4309> {bits (Month by field)} <byte 4309> tbits:5 month tbits:3 unused {} endunion month Month Union <byte 4310> union date Date Union <byte 4310> utiny value Date as byte or date Date Union <byte 4310> {bits (Date by field)} <byte 4310> tbits:6 date tbits:2 unused {} endunion date Date Union <byte 4311>

union day Day Union <byte 4311> utiny value Day/Frequency Test as byte or day Day Union <byte 4311> {bits (Day/Frequency Test by field)} <byte 4311> tbits:3 day tbits:3 unused2 tbits:1 freq_test tbits:1 unused1 {} endunion day Day Union {} <byte 4312> {glue (Glue register save area)} <byte 4312> union csr Glue CSR Registers <byte 4312> ulong[256] csra Glue CSR Registers As Longwords or csr Glue CSR Registers <byte 4312> {csrfield (Glue CSR Registers By Field)} <byte 4312> {rsvd[0] (03-0F Reserved)} <byte 4312> utiny value {} <byte 4313> {self_reset (02 Self Reset (0xD1))} <byte 4313> utiny value {} <byte 4314> union reset_in 01 Reset Inputs <byte 4314> {field (By field)} <byte 4314> tbits:1 button_self R/W Button or Self Reset (Reset = 0) tbits:1 crc_reset R/W Sprite CRC Reset (Reset = 0) tbits:1 rsvd1 R Reserved tbits:1 pwr_up R/W Power Up Reset (Reset = 0) tbits:1 swd R/W SW Watchdog Reset (Reset = 0) tbits:3 rsvd R Reserved {} or reset_in 01 Reset Inputs <byte 4314> utiny value As utiny endunion reset_in 01 Reset Inputs <byte 4315> union reset_dis 00 Reset Disables <byte 4315> {field (By field)} <byte 4315> tbits:1 button_self R/W Button or Self Reset (Reset = 0) tbits:1 crc_reset R/W Sprite CRC Reset (Reset = 0) tbits:1 rsvd1 R Reserved tbits:1 pwr_up R/W Power Up Reset (Reset = 0) tbits:1 swd R/W SW Watchdog Reset (Reset = 0) tbits:3 rsvd R Reserved

{} or reset_dis 00 Reset Disables <byte 4315> utiny value As utiny endunion reset_dis 00 Reset Disables <byte 4316> {rsvd[4] (03-0F Reserved)} <byte 4316> utiny value {} <byte 4317> {rsvd[3] (03-0F Reserved)} <byte 4317> utiny value {} <byte 4318> {rsvd[2] (03-0F Reserved)} <byte 4318> utiny value {} <byte 4319> {rsvd[1] (03-0F Reserved)} <byte 4319> utiny value {} <byte 4320> {rsvd[8] (03-0F Reserved)} <byte 4320> utiny value {} <byte 4321> {rsvd[7] (03-0F Reserved)} <byte 4321> utiny value {} <byte 4322> {rsvd[6] (03-0F Reserved)} <byte 4322> utiny value {} <byte 4323> {rsvd[5] (03-0F Reserved)} <byte 4323> utiny value {} <byte 4324> {rsvd[12] (03-0F Reserved)} <byte 4324> utiny value {} <byte 4325> {rsvd[11] (03-0F Reserved)} <byte 4325> utiny value {} <byte 4326> {rsvd[10] (03-0F Reserved)} <byte 4326> utiny value {}

<byte 4327> {rsvd[9] (03-0F Reserved)} <byte 4327> utiny value {} <byte 4328> {rsvd1[0] (13-21 Reserved)} <byte 4328> utiny value {} <byte 4329> union req 12 Request <byte 4329> {field (By field)} <byte 4329> tbits:1 devA R/W PCIX0, Device A Req/Gnt Signal tbits:1 devB R/W PCIX0, Device B Req/Gnt Signal tbits:1 sprite0 R/W PCIX0, Sprite Req/Gnt Signal tbits:1 devE R/W PCIX0, Device E Req/Gnt Signal tbits:1 devC R/W PCIX1, Device C Req/Gnt Signal tbits:1 devD R/W PCIX1, Device D Req/Gnt Signal tbits:1 sprite1 R/W PCIX1, Sprite Req/Gnt Signal tbits:1 rsvd R Reserved {} or req 12 Request <byte 4329> utiny value As utiny endunion req 12 Request <byte 4330> union gnt 11 Grant <byte 4330> {field (By field)} <byte 4330> tbits:1 devA R/W PCIX0, Device A Req/Gnt Signal tbits:1 devB R/W PCIX0, Device B Req/Gnt Signal tbits:1 sprite0 R/W PCIX0, Sprite Req/Gnt Signal tbits:1 devE R/W PCIX0, Device E Req/Gnt Signal tbits:1 devC R/W PCIX1, Device C Req/Gnt Signal tbits:1 devD R/W PCIX1, Device D Req/Gnt Signal tbits:1 sprite1 R/W PCIX1, Sprite Req/Gnt Signal tbits:1 rsvd R Reserved {} or gnt 11 Grant <byte 4330> utiny value As utiny endunion gnt 11 Grant <byte 4331> union arb 10 Arbitration Control & Status <byte 4331> {field (By field)} <byte 4331> tbits:2 ctrl0 R/W PCIX0 Arb Control tbits:2 state0 R PCIX0 Arb State tbits:2 ctrl1 R/W PCIX1 Arb Control tbits:2 state1 R PCIX1 Arb State {} or arb 10 Arbitration Control & Status <byte 4331> utiny value As utiny endunion arb 10 Arbitration Control & Status

<byte 4332> {rsvd1[4] (13-21 Reserved)} <byte 4332> utiny value {} <byte 4333> {rsvd1[3] (13-21 Reserved)} <byte 4333> utiny value {} <byte 4334> {rsvd1[2] (13-21 Reserved)} <byte 4334> utiny value {} <byte 4335> {rsvd1[1] (13-21 Reserved)} <byte 4335> utiny value {} <byte 4336> {rsvd1[8] (13-21 Reserved)} <byte 4336> utiny value {} <byte 4337> {rsvd1[7] (13-21 Reserved)} <byte 4337> utiny value {} <byte 4338> {rsvd1[6] (13-21 Reserved)} <byte 4338> utiny value {} <byte 4339> {rsvd1[5] (13-21 Reserved)} <byte 4339> utiny value {} <byte 4340> {rsvd1[12] (13-21 Reserved)} <byte 4340> utiny value {} <byte 4341> {rsvd1[11] (13-21 Reserved)} <byte 4341> utiny value {} <byte 4342> {rsvd1[10] (13-21 Reserved)} <byte 4342> utiny value {} <byte 4343> {rsvd1[9] (13-21 Reserved)} <byte 4343> utiny value {}

<byte 4344> {swd_tp (23 SW Watchdog Timer Trip Pt.)} <byte 4344> utiny value {} <byte 4345> {swd_ct (22 SW Watchdog Current Time)} <byte 4345> utiny value {} <byte 4346> {rsvd1[14] (13-21 Reserved)} <byte 4346> utiny value {} <byte 4347> {rsvd1[13] (13-21 Reserved)} <byte 4347> utiny value {} <byte 4348> {rsvd2[0] (27-3F Reserved)} <byte 4348> utiny value {} <byte 4349> union timer_ctrl 26 Timer Control <byte 4349> {field (By field)} <byte 4349> tbits:1 mbd_ok R/W Driven Lo when Watchdog Expires tbits:1 rsvd1 R Reserved tbits:1 ena_swd R/W SW Watchdog Timer Enable tbits:1 ena_ppc R/W PPC Bus Snoop Timer Enable tbits:3 rsvd R Reserved tbits:1 swd_rst R/W1R SW Watchdog Reset/Restart {} or timer_ctrl 26 Timer Control <byte 4349> utiny value As utiny endunion timer_ctrl 26 Timer Control <byte 4350> {ppc_sv (25 PPC ' ' Timer Start Value)} <byte 4350> utiny value {} <byte 4351> {ppc_ct (24 PPC Bus Snoop Current Value)} <byte 4351> utiny value {} <byte 4352> {rsvd2[4] (27-3F Reserved)} <byte 4352> utiny value {} <byte 4353> {rsvd2[3] (27-3F Reserved)} <byte 4353> utiny value

{} <byte 4354> {rsvd2[2] (27-3F Reserved)} <byte 4354> utiny value {} <byte 4355> {rsvd2[1] (27-3F Reserved)} <byte 4355> utiny value {} <byte 4356> {rsvd2[8] (27-3F Reserved)} <byte 4356> utiny value {} <byte 4357> {rsvd2[7] (27-3F Reserved)} <byte 4357> utiny value {} <byte 4358> {rsvd2[6] (27-3F Reserved)} <byte 4358> utiny value {} <byte 4359> {rsvd2[5] (27-3F Reserved)} <byte 4359> utiny value {} <byte 4360> {rsvd2[12] (27-3F Reserved)} <byte 4360> utiny value {} <byte 4361> {rsvd2[11] (27-3F Reserved)} <byte 4361> utiny value {} <byte 4362> {rsvd2[10] (27-3F Reserved)} <byte 4362> utiny value {} <byte 4363> {rsvd2[9] (27-3F Reserved)} <byte 4363> utiny value {} <byte 4364> {rsvd2[16] (27-3F Reserved)} <byte 4364> utiny value {} <byte 4365> {rsvd2[15] (27-3F Reserved)} <byte 4365> utiny value

{} <byte 4366> {rsvd2[14] (27-3F Reserved)} <byte 4366> utiny value {} <byte 4367> {rsvd2[13] (27-3F Reserved)} <byte 4367> utiny value {} <byte 4368> {rsvd2[20] (27-3F Reserved)} <byte 4368> utiny value {} <byte 4369> {rsvd2[19] (27-3F Reserved)} <byte 4369> utiny value {} <byte 4370> {rsvd2[18] (27-3F Reserved)} <byte 4370> utiny value {} <byte 4371> {rsvd2[17] (27-3F Reserved)} <byte 4371> utiny value {} <byte 4372> {rsvd2[24] (27-3F Reserved)} <byte 4372> utiny value {} <byte 4373> {rsvd2[23] (27-3F Reserved)} <byte 4373> utiny value {} <byte 4374> {rsvd2[22] (27-3F Reserved)} <byte 4374> utiny value {} <byte 4375> {rsvd2[21] (27-3F Reserved)} <byte 4375> utiny value {} <byte 4376> {supply_a_off (43 Supply A Turn Off <byte 4376> utiny value {} <byte 4377> {rsvd3 (42 Reserved)} <byte 4377> utiny value

(0xA5))}

{} <byte 4378> {kill_other (41 Kill Other Controller (0x37))} <byte 4378> utiny value {} <byte 4379> union dis_ctrl 40 Disable Control <byte 4379> {field (By field)} <byte 4379> tbits:1 ena_kill_other R/W Kill Other Controller - Enable tbits:1 rsvd1 R Reserved tbits:1 ena_ps_a_off R/W Power Supply A Off - Enable tbits:1 ena_ps_b_off R/W Power Supply B Off - Enable tbits:1 amb_ps_a_led R/W Amber Power Supply A Failure LED {E1} tbits:1 amb_ps_b_led R/W Amber Power Supply B Failure LED {E2} tbits:2 rsvd R Reserved {} or dis_ctrl 40 Disable Control <byte 4379> utiny value As utiny endunion dis_ctrl 40 Disable Control <byte 4380> union iic_bus_ctrl 47 Atlantis IIC Bus Control <byte 4380> {field (By field Bus: A B C D)} <byte 4380> tbits:3 iic_sel R/W IIC Bus Select {AA9, AB9, W9, Y9} tbits:5 rsvd R Reserved {} or iic_bus_ctrl 47 Atlantis IIC Bus Control <byte 4380> utiny value As utiny endunion iic_bus_ctrl 47 Atlantis IIC Bus Control <byte 4381> {rsvdz[1] (45-46 Reserved)} <byte 4381> utiny value {} <byte 4382> {rsvdz[0] (45-46 Reserved)} <byte 4382> utiny value {} <byte 4383> {supply_b_off (44 Supply B Turn Off (0xB5))} <byte 4383> utiny value {} <byte 4384> {rsvd4[3] (48-4F Reserved)} <byte 4384> utiny value {} <byte 4385> {rsvd4[2] (48-4F Reserved)} <byte 4385> utiny value {}

<byte 4386> {rsvd4[1] (48-4F Reserved)} <byte 4386> utiny value {} <byte 4387> {rsvd4[0] (48-4F Reserved)} <byte 4387> utiny value {} <byte 4388> {rsvd4[7] (48-4F Reserved)} <byte 4388> utiny value {} <byte 4389> {rsvd4[6] (48-4F Reserved)} <byte 4389> utiny value {} <byte 4390> {rsvd4[5] (48-4F Reserved)} <byte 4390> utiny value {} <byte 4391> {rsvd4[4] (48-4F Reserved)} <byte 4391> utiny value {} <byte 4392> {rsvd5[0] (51-5F Reserved)} <byte 4392> utiny value {} <byte 4393> union ena_smi_5 52 SMI Enables 47:40 <byte 4393> {field (By field)} <byte 4393> tbits:1 atlantis_bus_req Atlantis Bus Request tbits:1 ovr_tmp_ps_off Over Temp. Power Supply Shutdown {AB4} tbits:1 ppc_addr_retry PowerPC 60x Bus Address Retry {B9} tbits:1 rsvd Reserved tbits:1 dx2f_f1_dir_rst DX2F F1 DIR RST (Int=1) {E10} tbits:1 dx2f_f0_dir_rst DX2F F0 DIR RST (Int=1) {E11} tbits:1 dx2f_intb DX2F INTB (Int=0) {F10} tbits:1 dx2f_inta DX2F INTA (Int=0) {F11} {} or ena_smi_5 52 SMI Enables 47:40 <byte 4393> utiny value As utiny endunion ena_smi_5 52 SMI Enables 47:40 <byte 4394> union int_smi_5 51 SMI Interrupt 47:40 (Int=1) <byte 4394> {field (By field)} <byte 4394> tbits:1 atlantis_bus_req Atlantis Bus Request tbits:1 ovr_tmp_ps_off Over Temp. Power Supply Shutdown {AB4}

tbits:1 ppc_addr_retry PowerPC 60x Bus Address Retry {B9} tbits:1 rsvd Reserved tbits:1 dx2f_f1_dir_rst DX2F F1 DIR RST (Int=1) {E10} tbits:1 dx2f_f0_dir_rst DX2F F0 DIR RST (Int=1) {E11} tbits:1 dx2f_intb DX2F INTB (Int=0) {F10} tbits:1 dx2f_inta DX2F INTA (Int=0) {F11} {} or int_smi_5 51 SMI Interrupt 47:40 (Int=1) <byte 4394> utiny value As utiny endunion int_smi_5 51 SMI Interrupt 47:40 (Int=1) <byte 4395> union int_out 50 Interrupt Out <byte 4395> {field (By field)} <byte 4395> tbits:1 other_l R/W Int. to Other Ctrllr (Int=0) {V12} tbits:1 rsvd1 R Reserved {U12} tbits:1 smi_l R/W System Management Int. (Int=0) {B6} tbits:1 mcp_l R/W Machine Check Interrupt (Int=0) {A6} tbits:4 rsvd R Reserved {} or int_out 50 Interrupt Out <byte 4395> utiny value As utiny endunion int_out 50 Interrupt Out <byte 4396> {rsvd5[4] (51-5F Reserved)} <byte 4396> utiny value {} <byte 4397> {rsvd5[3] (51-5F Reserved)} <byte 4397> utiny value {} <byte 4398> {rsvd5[2] (51-5F Reserved)} <byte 4398> utiny value {} <byte 4399> {rsvd5[1] (51-5F Reserved)} <byte 4399> utiny value {} <byte 4400> {rsvd5[8] (51-5F Reserved)} <byte 4400> utiny value {} <byte 4401> {rsvd5[7] (51-5F Reserved)} <byte 4401> utiny value {} <byte 4402> {rsvd5[6] (51-5F Reserved)} <byte 4402> utiny value

{} <byte 4403> {rsvd5[5] (51-5F Reserved)} <byte 4403> utiny value {} <byte 4404> {rsvd5[12] (51-5F Reserved)} <byte 4404> utiny value {} <byte 4405> {rsvd5[11] (51-5F Reserved)} <byte 4405> utiny value {} <byte 4406> {rsvd5[10] (51-5F Reserved)} <byte 4406> utiny value {} <byte 4407> {rsvd5[9] (51-5F Reserved)} <byte 4407> utiny value {} <byte 4408> union int_smi_3 63 SMI Interrupt 31:24 (Int=1) <byte 4408> {field (By field)} <byte 4408> tbits:1 dimm_dcok_3_l (NBBU) DIMM 3 DC NOT OK Int. (Int=0) {Y22} tbits:1 dimm_dcok_012_l (BBU) DIMM 0-2 DC NOT OK Int. (Int=0) {Y21} tbits:1 sdc SDC Int. (Int=0) {W20} tbits:1 other Other Controller Int. (Int=0) {AA20} tbits:1 dx2e_f1_dir_rst DX2E F1 DIR RST (Int=1) {N17} tbits:1 dx2e_f0_dir_rst DX2E F0 DIR RST (Int=1) {M17} tbits:1 dx2e_intb DX2E INTB (Int=0) {C18} tbits:1 dx2e_inta DX2E INTA (Int=0) {D18} {} or int_smi_3 63 SMI Interrupt 31:24 (Int=1) <byte 4408> utiny value As utiny endunion int_smi_3 63 SMI Interrupt 31:24 (Int=1) <byte 4409> union int_smi_2 62 SMI Interrupt 23:16 (Int=1) <byte 4409> {field (By field)} <byte 4409> tbits:1 can CAN Interrupt (Int=0) {T22} tbits:1 uart UART Interrupt (Int=0) {T21} tbits:1 sprite1 Sprite Int. 1 (Int=0) {V22} tbits:1 sprite0 Sprite Int. 0 (Int=0) {V21} tbits:1 lcd LCD Interrupt (Int=0) {V20} tbits:1 atlantis1 Atlantis CPU Int. 1 (Int=0) {V19} tbits:1 atlantis0 Atlantis CPU Int. 0 (Int=0) {W22} tbits:1 rtc Real Time Clock (Int=0) {W21} {} or int_smi_2 62 SMI Interrupt 23:16 (Int=1) <byte 4409>

utiny value As utiny endunion int_smi_2 62 SMI Interrupt 23:16 (Int=1) <byte 4410> union int_smi_1 61 SMI Interrupt 15:08 (Int=1) <byte 4410> {field (By field)} <byte 4410> tbits:1 dx2d_intb DX2D INTB (Int=0) {P20} tbits:1 dx2d_inta DX2D INTA (Int=0) {P19} tbits:1 dx2c_intb DX2C INTB (Int=0) {R22} tbits:1 dx2c_inta DX2C INTA (Int=0) {R21} tbits:1 dx2b_intb DX2B INTB (Int=0) {R20} tbits:1 dx2b_inta DX2B INTA (Int=0) {R19} tbits:1 dx2a_intb DX2A INTB (Int=0) {R18} tbits:1 dx2a_inta DX2A INTA (Int=0) {P17} {} or int_smi_1 61 SMI Interrupt 15:08 (Int=1) <byte 4410> utiny value As utiny endunion int_smi_1 61 SMI Interrupt 15:08 (Int=1) <byte 4411> union int_smi_0 60 SMI Interrupt 07:00 (Int=1) <byte 4411> {field (By field)} <byte 4411> tbits:1 dx2d_f1_dir_rst DX2D F1 DIR RST (Int=1) tbits:1 dx2d_f0_dir_rst DX2D F0 DIR RST (Int=1) tbits:1 dx2c_f1_dir_rst DX2C F1 DIR RST (Int=1) tbits:1 dx2c_f0_dir_rst DX2C F0 DIR RST (Int=1) tbits:1 dx2b_f1_dir_rst DX2B F1 DIR RST (Int=1) tbits:1 dx2b_f0_dir_rst DX2B F0 DIR RST (Int=1) tbits:1 dx2a_f1_dir_rst DX2A F1 DIR RST (Int=1) tbits:1 dx2a_f0_dir_rst DX2A F0 DIR RST (Int=1) {} or int_smi_0 60 SMI Interrupt 07:00 (Int=1) <byte 4411> utiny value As utiny endunion int_smi_0 60 SMI Interrupt 07:00 (Int=1) <byte 4412> union ena_smi_2 67 SMI Enables 23:16 <byte 4412> {field (By field)} <byte 4412> tbits:1 can CAN Interrupt (Int=0) {T22} tbits:1 uart UART Interrupt (Int=0) {T21} tbits:1 sprite1 Sprite Int. 1 (Int=0) {V22} tbits:1 sprite0 Sprite Int. 0 (Int=0) {V21} tbits:1 lcd LCD Interrupt (Int=0) {V20} tbits:1 atlantis1 Atlantis CPU Int. 1 (Int=0) {V19} tbits:1 atlantis0 Atlantis CPU Int. 0 (Int=0) {W22} tbits:1 rtc Real Time Clock (Int=0) {W21} {} or ena_smi_2 67 SMI Enables 23:16 <byte 4412> utiny value As utiny endunion ena_smi_2 67 SMI Enables 23:16 <byte 4413> union ena_smi_1 66 SMI Enables 15:08 <byte 4413> {field (By field)}

{N22} {N21} {N20} {N19} {N18} {P18} {P22} {P21}

<byte 4413> tbits:1 dx2d_intb DX2D INTB (Int=0) {P20} tbits:1 dx2d_inta DX2D INTA (Int=0) {P19} tbits:1 dx2c_intb DX2C INTB (Int=0) {R22} tbits:1 dx2c_inta DX2C INTA (Int=0) {R21} tbits:1 dx2b_intb DX2B INTB (Int=0) {R20} tbits:1 dx2b_inta DX2B INTA (Int=0) {R19} tbits:1 dx2a_intb DX2A INTB (Int=0) {R18} tbits:1 dx2a_inta DX2A INTA (Int=0) {P17} {} or ena_smi_1 66 SMI Enables 15:08 <byte 4413> utiny value As utiny endunion ena_smi_1 66 SMI Enables 15:08 <byte 4414> union ena_smi_0 65 SMI Enables 07:00 <byte 4414> {field (By field)} <byte 4414> tbits:1 dx2d_f1_dir_rst DX2D F1 DIR RST (Int=1) {N22} tbits:1 dx2d_f0_dir_rst DX2D F0 DIR RST (Int=1) {N21} tbits:1 dx2c_f1_dir_rst DX2C F1 DIR RST (Int=1) {N20} tbits:1 dx2c_f0_dir_rst DX2C F0 DIR RST (Int=1) {N19} tbits:1 dx2b_f1_dir_rst DX2B F1 DIR RST (Int=1) {N18} tbits:1 dx2b_f0_dir_rst DX2B F0 DIR RST (Int=1) {P18} tbits:1 dx2a_f1_dir_rst DX2A F1 DIR RST (Int=1) {P22} tbits:1 dx2a_f0_dir_rst DX2A F0 DIR RST (Int=1) {P21} {} or ena_smi_0 65 SMI Enables 07:00 <byte 4414> utiny value As utiny endunion ena_smi_0 65 SMI Enables 07:00 <byte 4415> union int_smi_4 64 SMI Interrupt 39:32 (Int=1) <byte 4415> {field (By field)} <byte 4415> tbits:1 atlantis_pcix0 Atlantis PCIX0 Int. (Int=0) {A19} tbits:1 cache_vtt_fail Cache VTT Fail Int. (Int=0) {C12} tbits:1 enet_dcard0 Ethernet Daughter Card Int.0 {H3} tbits:1 ac_fail_ups1 AC fail UPS 1 (Int=0) {W12} tbits:1 enet_dcard1 Ethernet Daughter Card Int.1 {H4} tbits:1 reset Reset tbits:1 sdc_wdto SDC Watchdog Timeout tbits:1 ppc_to PowerPC Bus Timeout {} or int_smi_4 64 SMI Interrupt 39:32 (Int=1) <byte 4415> utiny value As utiny endunion int_smi_4 64 SMI Interrupt 39:32 (Int=1) <byte 4416> union int_mcp_1 6B MCP Interrupt 15:08 (Int=1) <byte 4416> {field (By field)} <byte 4416> tbits:1 dx2d_intb DX2D INTB (Int=0) {P20} tbits:1 dx2d_inta DX2D INTA (Int=0) {P19} tbits:1 dx2c_intb DX2C INTB (Int=0) {R22} tbits:1 dx2c_inta DX2C INTA (Int=0) {R21} tbits:1 dx2b_intb DX2B INTB (Int=0) {R20}

tbits:1 dx2b_inta DX2B INTA (Int=0) {R19} tbits:1 dx2a_intb DX2A INTB (Int=0) {R18} tbits:1 dx2a_inta DX2A INTA (Int=0) {P17} {} or int_mcp_1 6B MCP Interrupt 15:08 (Int=1) <byte 4416> utiny value As utiny endunion int_mcp_1 6B MCP Interrupt 15:08 (Int=1) <byte 4417> union int_mcp_0 6A MCP Interrupt 07:00 (Int=1) <byte 4417> {field (By field)} <byte 4417> tbits:1 dx2d_f1_dir_rst DX2D F1 DIR RST (Int=1) {N22} tbits:1 dx2d_f0_dir_rst DX2D F0 DIR RST (Int=1) {N21} tbits:1 dx2c_f1_dir_rst DX2C F1 DIR RST (Int=1) {N20} tbits:1 dx2c_f0_dir_rst DX2C F0 DIR RST (Int=1) {N19} tbits:1 dx2b_f1_dir_rst DX2B F1 DIR RST (Int=1) {N18} tbits:1 dx2b_f0_dir_rst DX2B F0 DIR RST (Int=1) {P18} tbits:1 dx2a_f1_dir_rst DX2A F1 DIR RST (Int=1) {P22} tbits:1 dx2a_f0_dir_rst DX2A F0 DIR RST (Int=1) {P21} {} or int_mcp_0 6A MCP Interrupt 07:00 (Int=1) <byte 4417> utiny value As utiny endunion int_mcp_0 6A MCP Interrupt 07:00 (Int=1) <byte 4418> union ena_smi_4 69 SMI Enables 39:32 <byte 4418> {field (By field)} <byte 4418> tbits:1 atlantis_pcix0 Atlantis PCIX0 Int. (Int=0) {A19} tbits:1 cache_vtt_fail Cache VTT Fail Int. (Int=0) {C12} tbits:1 enet_dcard0 Ethernet Daughter Card Int.0 {H3} tbits:1 ac_fail_ups1 AC fail UPS 1 (Int=0) {W12} tbits:1 enet_dcard1 Ethernet Daughter Card Int.1 {H4} tbits:1 reset Reset tbits:1 sdc_wdto SDC Watchdog Timeout tbits:1 ppc_to PowerPC Bus Timeout {} or ena_smi_4 69 SMI Enables 39:32 <byte 4418> utiny value As utiny endunion ena_smi_4 69 SMI Enables 39:32 <byte 4419> union ena_smi_3 68 SMI Enables 31:24 <byte 4419> {field (By field)} <byte 4419> tbits:1 dimm_dcok_3_l (NBBU) DIMM 3 DC NOT OK Int. (Int=0) {Y22} tbits:1 dimm_dcok_012_l (BBU) DIMM 0-2 DC NOT OK Int. (Int=0) {Y21} tbits:1 sdc SDC Int. (Int=0) {W20} tbits:1 other Other Controller Int. (Int=0) {AA20} tbits:1 dx2e_f1_dir_rst DX2E F1 DIR RST (Int=1) {N17} tbits:1 dx2e_f0_dir_rst DX2E F0 DIR RST (Int=1) {M17} tbits:1 dx2e_intb DX2E INTB (Int=0) {C18} tbits:1 dx2e_inta DX2E INTA (Int=0) {D18} {} or ena_smi_3 68 SMI Enables 31:24 <byte 4419>

utiny value As utiny endunion ena_smi_3 68 SMI Enables 31:24 <byte 4420> union ena_mcp_0 6F MCP Enables 07:00 <byte 4420> {field (By field)} <byte 4420> tbits:1 dx2d_f1_dir_rst DX2D F1 DIR RST (Int=1) {N22} tbits:1 dx2d_f0_dir_rst DX2D F0 DIR RST (Int=1) {N21} tbits:1 dx2c_f1_dir_rst DX2C F1 DIR RST (Int=1) {N20} tbits:1 dx2c_f0_dir_rst DX2C F0 DIR RST (Int=1) {N19} tbits:1 dx2b_f1_dir_rst DX2B F1 DIR RST (Int=1) {N18} tbits:1 dx2b_f0_dir_rst DX2B F0 DIR RST (Int=1) {P18} tbits:1 dx2a_f1_dir_rst DX2A F1 DIR RST (Int=1) {P22} tbits:1 dx2a_f0_dir_rst DX2A F0 DIR RST (Int=1) {P21} {} or ena_mcp_0 6F MCP Enables 07:00 <byte 4420> utiny value As utiny endunion ena_mcp_0 6F MCP Enables 07:00 <byte 4421> union int_mcp_4 6E MCP Interrupt 39:32 (Int=1) <byte 4421> {field (By field)} <byte 4421> tbits:1 atlantis_pcix0 Atlantis PCIX0 Int. (Int=0) {A19} tbits:1 cache_vtt_fail Cache VTT Fail Int. (Int=0) {C12} tbits:1 enet_dcard0 Ethernet Daughter Card Int.0 {H3} tbits:1 ac_fail_ups1 AC fail UPS 1 (Int=0) {W12} tbits:1 enet_dcard1 Ethernet Daughter Card Int.1 {H4} tbits:1 reset Reset tbits:1 sdc_wdto SDC Watchdog Timeout tbits:1 ppc_to PowerPC Bus Timeout {} or int_mcp_4 6E MCP Interrupt 39:32 (Int=1) <byte 4421> utiny value As utiny endunion int_mcp_4 6E MCP Interrupt 39:32 (Int=1) <byte 4422> union int_mcp_3 6D MCP Interrupt 31:24 (Int=1) <byte 4422> {field (By field)} <byte 4422> tbits:1 dimm_dcok_3_l (NBBU) DIMM 3 DC NOT OK Int. (Int=0) {Y22} tbits:1 dimm_dcok_012_l (BBU) DIMM 0-2 DC NOT OK Int. (Int=0) {Y21} tbits:1 sdc SDC Int. (Int=0) {W20} tbits:1 other Other Controller Int. (Int=0) {AA20} tbits:1 dx2e_f1_dir_rst DX2E F1 DIR RST (Int=1) {N17} tbits:1 dx2e_f0_dir_rst DX2E F0 DIR RST (Int=1) {M17} tbits:1 dx2e_intb DX2E INTB (Int=0) {C18} tbits:1 dx2e_inta DX2E INTA (Int=0) {D18} {} or int_mcp_3 6D MCP Interrupt 31:24 (Int=1) <byte 4422> utiny value As utiny endunion int_mcp_3 6D MCP Interrupt 31:24 (Int=1) <byte 4423> union int_mcp_2 6C MCP Interrupt 23:16 (Int=1) <byte 4423> {field (By field)}

<byte 4423> tbits:1 can CAN Interrupt (Int=0) {T22} tbits:1 uart UART Interrupt (Int=0) {T21} tbits:1 sprite1 Sprite Int. 1 (Int=0) {V22} tbits:1 sprite0 Sprite Int. 0 (Int=0) {V21} tbits:1 lcd LCD Interrupt (Int=0) {V20} tbits:1 atlantis1 Atlantis CPU Int. 1 (Int=0) {V19} tbits:1 atlantis0 Atlantis CPU Int. 0 (Int=0) {W22} tbits:1 rtc Real Time Clock (Int=0) {W21} {} or int_mcp_2 6C MCP Interrupt 23:16 (Int=1) <byte 4423> utiny value As utiny endunion int_mcp_2 6C MCP Interrupt 23:16 (Int=1) <byte 4424> union ena_mcp_4 73 MCP Enables 39:32 <byte 4424> {field (By field)} <byte 4424> tbits:1 atlantis_pcix0 Atlantis PCIX0 Int. (Int=0) {A19} tbits:1 cache_vtt_fail Cache VTT Fail Int. (Int=0) {C12} tbits:1 enet_dcard0 Ethernet Daughter Card Int.0 {H3} tbits:1 ac_fail_ups1 AC fail UPS 1 (Int=0) {W12} tbits:1 enet_dcard1 Ethernet Daughter Card Int.1 {H4} tbits:1 reset Reset tbits:1 sdc_wdto SDC Watchdog Timeout tbits:1 ppc_to PowerPC Bus Timeout {} or ena_mcp_4 73 MCP Enables 39:32 <byte 4424> utiny value As utiny endunion ena_mcp_4 73 MCP Enables 39:32 <byte 4425> union ena_mcp_3 72 MCP Enables 31:24 <byte 4425> {field (By field)} <byte 4425> tbits:1 dimm_dcok_3_l (NBBU) DIMM 3 DC NOT OK Int. (Int=0) {Y22} tbits:1 dimm_dcok_012_l (BBU) DIMM 0-2 DC NOT OK Int. (Int=0) {Y21} tbits:1 sdc SDC Int. (Int=0) {W20} tbits:1 other Other Controller Int. (Int=0) {AA20} tbits:1 dx2e_f1_dir_rst DX2E F1 DIR RST (Int=1) {N17} tbits:1 dx2e_f0_dir_rst DX2E F0 DIR RST (Int=1) {M17} tbits:1 dx2e_intb DX2E INTB (Int=0) {C18} tbits:1 dx2e_inta DX2E INTA (Int=0) {D18} {} or ena_mcp_3 72 MCP Enables 31:24 <byte 4425> utiny value As utiny endunion ena_mcp_3 72 MCP Enables 31:24 <byte 4426> union ena_mcp_2 71 MCP Enables 23:16 <byte 4426> {field (By field)} <byte 4426> tbits:1 can CAN Interrupt (Int=0) {T22} tbits:1 uart UART Interrupt (Int=0) {T21} tbits:1 sprite1 Sprite Int. 1 (Int=0) {V22} tbits:1 sprite0 Sprite Int. 0 (Int=0) {V21} tbits:1 lcd LCD Interrupt (Int=0) {V20}

tbits:1 atlantis1 Atlantis CPU Int. 1 (Int=0) {V19} tbits:1 atlantis0 Atlantis CPU Int. 0 (Int=0) {W22} tbits:1 rtc Real Time Clock (Int=0) {W21} {} or ena_mcp_2 71 MCP Enables 23:16 <byte 4426> utiny value As utiny endunion ena_mcp_2 71 MCP Enables 23:16 <byte 4427> union ena_mcp_1 70 MCP Enables 15:08 <byte 4427> {field (By field)} <byte 4427> tbits:1 dx2d_intb DX2D INTB (Int=0) {P20} tbits:1 dx2d_inta DX2D INTA (Int=0) {P19} tbits:1 dx2c_intb DX2C INTB (Int=0) {R22} tbits:1 dx2c_inta DX2C INTA (Int=0) {R21} tbits:1 dx2b_intb DX2B INTB (Int=0) {R20} tbits:1 dx2b_inta DX2B INTA (Int=0) {R19} tbits:1 dx2a_intb DX2A INTB (Int=0) {R18} tbits:1 dx2a_inta DX2A INTA (Int=0) {P17} {} or ena_mcp_1 70 MCP Enables 15:08 <byte 4427> utiny value As utiny endunion ena_mcp_1 70 MCP Enables 15:08 <byte 4428> union int_in_3 77 Interrupt Inputs 31:24 <byte 4428> {field (By field)} <byte 4428> tbits:1 dimm_dcok_3_l (NBBU) DIMM 3 DC NOT OK Int. (Int=0) {Y22} tbits:1 dimm_dcok_012_l (BBU) DIMM 0-2 DC NOT OK Int. (Int=0) {Y21} tbits:1 sdc SDC Int. (Int=0) {W20} tbits:1 other Other Controller Int. (Int=0) {AA20} tbits:1 dx2e_f1_dir_rst DX2E F1 DIR RST (Int=1) {N17} tbits:1 dx2e_f0_dir_rst DX2E F0 DIR RST (Int=1) {M17} tbits:1 dx2e_intb DX2E INTB (Int=0) {C18} tbits:1 dx2e_inta DX2E INTA (Int=0) {D18} {} or int_in_3 77 Interrupt Inputs 31:24 <byte 4428> utiny value As utiny endunion int_in_3 77 Interrupt Inputs 31:24 <byte 4429> union int_in_2 76 Interrupt Inputs 23:16 <byte 4429> {field (By field)} <byte 4429> tbits:1 can CAN Interrupt (Int=0) {T22} tbits:1 uart UART Interrupt (Int=0) {T21} tbits:1 sprite1 Sprite Int. 1 (Int=0) {V22} tbits:1 sprite0 Sprite Int. 0 (Int=0) {V21} tbits:1 lcd LCD Interrupt (Int=0) {V20} tbits:1 atlantis1 Atlantis CPU Int. 1 (Int=0) {V19} tbits:1 atlantis0 Atlantis CPU Int. 0 (Int=0) {W22} tbits:1 rtc Real Time Clock (Int=0) {W21} {} or int_in_2 76 Interrupt Inputs 23:16 <byte 4429>

utiny value As utiny endunion int_in_2 76 Interrupt Inputs 23:16 <byte 4430> union int_in_1 75 Interrupt Inputs 15:08 <byte 4430> {field (By field)} <byte 4430> tbits:1 dx2d_intb DX2D INTB (Int=0) {P20} tbits:1 dx2d_inta DX2D INTA (Int=0) {P19} tbits:1 dx2c_intb DX2C INTB (Int=0) {R22} tbits:1 dx2c_inta DX2C INTA (Int=0) {R21} tbits:1 dx2b_intb DX2B INTB (Int=0) {R20} tbits:1 dx2b_inta DX2B INTA (Int=0) {R19} tbits:1 dx2a_intb DX2A INTB (Int=0) {R18} tbits:1 dx2a_inta DX2A INTA (Int=0) {P17} {} or int_in_1 75 Interrupt Inputs 15:08 <byte 4430> utiny value As utiny endunion int_in_1 75 Interrupt Inputs 15:08 <byte 4431> union int_in_0 74 Interrupt Inputs 07:00 <byte 4431> {field (By field)} <byte 4431> tbits:1 dx2d_f1_dir_rst DX2D F1 DIR RST (Int=1) {N22} tbits:1 dx2d_f0_dir_rst DX2D F0 DIR RST (Int=1) {N21} tbits:1 dx2c_f1_dir_rst DX2C F1 DIR RST (Int=1) {N20} tbits:1 dx2c_f0_dir_rst DX2C F0 DIR RST (Int=1) {N19} tbits:1 dx2b_f1_dir_rst DX2B F1 DIR RST (Int=1) {N18} tbits:1 dx2b_f0_dir_rst DX2B F0 DIR RST (Int=1) {P18} tbits:1 dx2a_f1_dir_rst DX2A F1 DIR RST (Int=1) {P22} tbits:1 dx2a_f0_dir_rst DX2A F0 DIR RST (Int=1) {P21} {} or int_in_0 74 Interrupt Inputs 07:00 <byte 4431> utiny value As utiny endunion int_in_0 74 Interrupt Inputs 07:00 <byte 4432> union int_mcp_5 7B MCP Interrupt 47:40 <byte 4432> {field (By field)} <byte 4432> tbits:1 atlantis_bus_req Atlantis Bus Request tbits:1 ovr_tmp_ps_off Over Temp. Power Supply Shutdown {AB4} tbits:1 ppc_addr_retry PowerPC 60x Bus Address Retry {B9} tbits:1 rsvd Reserved tbits:1 dx2f_f1_dir_rst DX2F F1 DIR RST (Int=1) {E10} tbits:1 dx2f_f0_dir_rst DX2F F0 DIR RST (Int=1) {E11} tbits:1 dx2f_intb DX2F INTB (Int=0) {F10} tbits:1 dx2f_inta DX2F INTA (Int=0) {F11} {} or int_mcp_5 7B MCP Interrupt 47:40 <byte 4432> utiny value As utiny endunion int_mcp_5 7B MCP Interrupt 47:40 <byte 4433> union int_in_5 7A Interrupt Inputs 47:40 <byte 4433> {field (By field)}

<byte 4433> tbits:1 atlantis_bus_req Atlantis Bus Request tbits:1 ovr_tmp_ps_off Over Temp. Power Supply Shutdown {AB4} tbits:1 ppc_addr_retry PowerPC 60x Bus Address Retry {B9} tbits:1 rsvd Reserved tbits:1 dx2f_f1_dir_rst DX2F F1 DIR RST (Int=1) {E10} tbits:1 dx2f_f0_dir_rst DX2F F0 DIR RST (Int=1) {E11} tbits:1 dx2f_intb DX2F INTB (Int=0) {F10} tbits:1 dx2f_inta DX2F INTA (Int=0) {F11} {} or int_in_5 7A Interrupt Inputs 47:40 <byte 4433> utiny value As utiny endunion int_in_5 7A Interrupt Inputs 47:40 <byte 4434> union int_smi_pulsed 79 SMI Latched Pulse Interrupts <byte 4434> {field (By field)} <byte 4434> tbits:2 rsvd2 Reserved tbits:1 sdc_int SDC Latched Int. (Int=1) tbits:1 rsvd1 Reserved tbits:1 lcd_int LCD Latched Int. (Int=1) tbits:3 rsvd Reserved {} or int_smi_pulsed 79 SMI Latched Pulse Interrupts <byte 4434> utiny value As utiny endunion int_smi_pulsed 79 SMI Latched Pulse Interrupts <byte 4435> union int_in_4 78 Interrupt Inputs 39:32 <byte 4435> {field (By field)} <byte 4435> tbits:1 atlantis_pcix0 Atlantis PCIX0 Int. (Int=0) {A19} tbits:1 cache_vtt_fail Cache VTT Fail Int. (Int=0) {C12} tbits:1 enet_dcard0 Ethernet Daughter Card Int.0 {H3} tbits:1 ac_fail_ups1 AC fail UPS 1 (Int=0) {W12} tbits:1 enet_dcard1 Ethernet Daughter Card Int.1 {H4} tbits:1 reset Reset tbits:1 sdc_wdto SDC Watchdog Timeout tbits:1 ppc_to PowerPC Bus Timeout {} or int_in_4 78 Interrupt Inputs 39:32 <byte 4435> utiny value As utiny endunion int_in_4 78 Interrupt Inputs 39:32 <byte 4436> {rsvda[2] (7D-7F Reserved)} <byte 4436> utiny value {} <byte 4437> {rsvda[1] (7D-7F Reserved)} <byte 4437> utiny value {} <byte 4438> {rsvda[0] (7D-7F Reserved)} <byte 4438>

utiny value {} <byte 4439> union ena_mcp_5 7C MCP Enables 47:40 <byte 4439> {field (By field)} <byte 4439> tbits:1 atlantis_bus_req Atlantis Bus Request tbits:1 ovr_tmp_ps_off Over Temp. Power Supply Shutdown {AB4} tbits:1 ppc_addr_retry PowerPC 60x Bus Address Retry {B9} tbits:1 rsvd Reserved tbits:1 dx2f_f1_dir_rst DX2F F1 DIR RST (Int=1) {E10} tbits:1 dx2f_f0_dir_rst DX2F F0 DIR RST (Int=1) {E11} tbits:1 dx2f_intb DX2F INTB (Int=0) {F10} tbits:1 dx2f_inta DX2F INTA (Int=0) {F11} {} or ena_mcp_5 7C MCP Enables 47:40 <byte 4439> utiny value As utiny endunion ena_mcp_5 7C MCP Enables 47:40 <byte 4440> {int_sci_3 (83 State Change Interrupt 31:24)} <byte 4440> utiny value {} <byte 4441> union int_sci_2 82 State Change Interrupt 23:16 <byte 4441> {field (By field)} <byte 4441> tbits:1 sfp3_l SFP 3 Present Lo {R1} tbits:1 sfp2_l SFP 2 Present Lo {R2} tbits:1 sfp1_l SFP 1 Present Lo {R3} tbits:1 sfp0_l SFP 0 Present Lo {R4} tbits:1 agent_pres_l Agent Present Lo {T1} tbits:1 ups1_pres_l UPS 1 Present Lo {T2} tbits:1 ps_a_dcok_l Power Supply A DC OK Lo {U3} tbits:1 ps_b_dcok_l Power Supply B DC OK Lo {U4} {} or int_sci_2 82 State Change Interrupt 23:16 <byte 4441> utiny value As utiny endunion int_sci_2 82 State Change Interrupt 23:16 <byte 4442> union int_sci_1 81 State Change Interrupt 15:08 <byte 4442> {field (By field)} <byte 4442> tbits:1 sfp9_l SFP 9 Present Lo {N5} tbits:1 sfp8_l SFP 8 Present Lo {N6} tbits:1 sprite_hw_rdy_l Sprite HW ready Lo {P1} tbits:1 lcd_l LCD Present Lo {P2} tbits:1 sfp7_l SFP 7 Present Lo {P3} tbits:1 sfp6_l SFP 6 Present Lo {P4} tbits:1 sfp5_l SFP 5 Present Lo {P5} tbits:1 sfp4_l SFP 4 Present Lo {P6} {} or int_sci_1 81 State Change Interrupt 15:08 <byte 4442> utiny value As utiny

endunion int_sci_1 81 State Change Interrupt 15:08 <byte 4443> union int_sci_0 80 State Change Interrupt 07:00 <byte 4443> {field (By field)} <byte 4443> tbits:1 ps_b_pres_l Power Supply B Present (Int=1) {M3} tbits:1 ps_a_pres_l Power Supply A Present (Int=1) {M4} tbits:1 sfp11_l SFP 11 Present Lo {M5} tbits:1 sfp10_l SFP 10 Present Lo {M6} tbits:1 bhm_pres_l Bulkhead Modules (Int=1) {N1} Present tbits:1 mpi_pres_l Mid Plane Interconnect (Int=1) {N2} Present tbits:1 clf_pres_l Flash Card Present Lo {N3} tbits:1 other_ok_l Other Controller OK Lo (Int=1) {N4} {} or int_sci_0 80 State Change Interrupt 07:00 <byte 4443> utiny value As utiny endunion int_sci_0 80 State Change Interrupt 07:00 <byte 4444> union ena_sci_1 87 State Change Int Enable 15:08 <byte 4444> {field (By field)} <byte 4444> tbits:1 sfp9_l SFP 9 Present Lo {N5} tbits:1 sfp8_l SFP 8 Present Lo {N6} tbits:1 sprite_hw_rdy_l Sprite HW ready Lo {P1} tbits:1 lcd_l LCD Present Lo {P2} tbits:1 sfp7_l SFP 7 Present Lo {P3} tbits:1 sfp6_l SFP 6 Present Lo {P4} tbits:1 sfp5_l SFP 5 Present Lo {P5} tbits:1 sfp4_l SFP 4 Present Lo {P6} {} or ena_sci_1 87 State Change Int Enable 15:08 <byte 4444> utiny value As utiny endunion ena_sci_1 87 State Change Int Enable 15:08 <byte 4445> union ena_sci_0 86 State Change Int Enable 07:00 <byte 4445> {field (By field)} <byte 4445> tbits:1 ps_b_pres_l Power Supply B Present (Int=1) {M3} tbits:1 ps_a_pres_l Power Supply A Present (Int=1) {M4} tbits:1 sfp11_l SFP 11 Present Lo {M5} tbits:1 sfp10_l SFP 10 Present Lo {M6} tbits:1 bhm_pres_l Bulkhead Modules (Int=1) {N1} Present tbits:1 mpi_pres_l Mid Plane Interconnect (Int=1) {N2} Present tbits:1 clf_pres_l Flash Card Present Lo {N3} tbits:1 other_ok_l Other Controller OK Lo (Int=1) {N4} {} or ena_sci_0 86 State Change Int Enable 07:00 <byte 4445> utiny value As utiny endunion ena_sci_0 86 State Change Int Enable 07:00 <byte 4446> {rsvdb (85 Reserved)} <byte 4446> utiny value {}

Lo Lo

Lo Lo

<byte 4447> union int_sci_4 84 State Change Interrupt 39:32 <byte 4447> {field (By field)} <byte 4447> tbits:1 batt_det Battery Detect tbits:1 blower_det Blower Detect tbits:1 meltdown_temp_minus_4C_det Meltdown Temp minus 4 degrees C detect tbits:1 meltdown_temp_det Meltdown Temperature detect tbits:4 rsvd Reserved {} or int_sci_4 84 State Change Interrupt 39:32 <byte 4447> utiny value As utiny endunion int_sci_4 84 State Change Interrupt 39:32 <byte 4448> {rsvdc (8B Reserved)} <byte 4448> utiny value {} <byte 4449> union ena_sci_4 8A State Change Int Enable 39:32 <byte 4449> {field (By field)} <byte 4449> tbits:1 batt_det Battery Detect tbits:1 blower_det Blower Detect tbits:1 meltdown_temp_minus_4C_det Meltdown Temp minus 4 degrees C detect tbits:1 meltdown_temp_det Meltdown Temperature detect tbits:4 rsvd Reserved {} or ena_sci_4 8A State Change Int Enable 39:32 <byte 4449> utiny value As utiny endunion ena_sci_4 8A State Change Int Enable 39:32 <byte 4450> {ena_sci_3 (89 State Change Int Enable 31:24)} <byte 4450> utiny value {} <byte 4451> union ena_sci_2 88 State Change Int Enable 23:16 <byte 4451> {field (By field)} <byte 4451> tbits:1 sfp3_l SFP 3 Present Lo {R1} tbits:1 sfp2_l SFP 2 Present Lo {R2} tbits:1 sfp1_l SFP 1 Present Lo {R3} tbits:1 sfp0_l SFP 0 Present Lo {R4} tbits:1 agent_pres_l Agent Present Lo {T1} tbits:1 ups1_pres_l UPS 1 Present Lo {T2} tbits:1 ps_a_dcok_l Power Supply A DC OK Lo {U3} tbits:1 ps_b_dcok_l Power Supply B DC OK Lo {U4} {} or ena_sci_2 88 State Change Int Enable 23:16 <byte 4451> utiny value As utiny endunion ena_sci_2 88 State Change Int Enable 23:16 <byte 4452> {sc_in_3 (8F State Change Inputs 31:24)}

<byte 4452> utiny value {} <byte 4453> union sc_in_2 8E State Change Inputs 23:16 <byte 4453> {field (By field)} <byte 4453> tbits:1 sfp3_l SFP 3 Present Lo {R1} tbits:1 sfp2_l SFP 2 Present Lo {R2} tbits:1 sfp1_l SFP 1 Present Lo {R3} tbits:1 sfp0_l SFP 0 Present Lo {R4} tbits:1 agent_pres_l Agent Present Lo {T1} tbits:1 ups1_pres_l UPS 1 Present Lo {T2} tbits:1 ps_a_dcok_l Power Supply A DC OK Lo {U3} tbits:1 ps_b_dcok_l Power Supply B DC OK Lo {U4} {} or sc_in_2 8E State Change Inputs 23:16 <byte 4453> utiny value As utiny endunion sc_in_2 8E State Change Inputs 23:16 <byte 4454> union sc_in_1 8D State Change Inputs 15:08 <byte 4454> {field (By field)} <byte 4454> tbits:1 sfp9_l SFP 9 Present Lo {N5} tbits:1 sfp8_l SFP 8 Present Lo {N6} tbits:1 sprite_hw_rdy_l Sprite HW ready Lo {P1} tbits:1 lcd_l LCD Present Lo {P2} tbits:1 sfp7_l SFP 7 Present Lo {P3} tbits:1 sfp6_l SFP 6 Present Lo {P4} tbits:1 sfp5_l SFP 5 Present Lo {P5} tbits:1 sfp4_l SFP 4 Present Lo {P6} {} or sc_in_1 8D State Change Inputs 15:08 <byte 4454> utiny value As utiny endunion sc_in_1 8D State Change Inputs 15:08 <byte 4455> union sc_in_0 8C State Change Inputs 07:00 <byte 4455> {field (By field)} <byte 4455> tbits:1 ps_b_pres_l Power Supply B Present (Int=1) {M3} tbits:1 ps_a_pres_l Power Supply A Present (Int=1) {M4} tbits:1 sfp11_l SFP 11 Present Lo {M5} tbits:1 sfp10_l SFP 10 Present Lo {M6} tbits:1 bhm_pres_l Bulkhead Modules (Int=1) {N1} Present Lo tbits:1 mpi_pres_l Mid Plane Interconnect (Int=1) {N2} Present Lo tbits:1 clf_pres_l Flash Card Present Lo {N3} tbits:1 other_ok_l Other Controller OK Lo (Int=1) {N4} {} or sc_in_0 8C State Change Inputs 07:00 <byte 4455> utiny value As utiny endunion sc_in_0 8C State Change Inputs 07:00 <byte 4456> {rsvdd[0] (93-9F Reserved)} <byte 4456>

utiny value {} <byte 4457> {batt_good_tp (92 Battery Good Trip Point)} <byte 4457> utiny value {} <byte 4458> {batt_lo_tp (91 Battery Low Trip Point)} <byte 4458> utiny value {} <byte 4459> {melt_down (90 Meltdown Temp.)} <byte 4459> utiny value {} <byte 4460> {rsvdd[4] (93-9F Reserved)} <byte 4460> utiny value {} <byte 4461> {rsvdd[3] (93-9F Reserved)} <byte 4461> utiny value {} <byte 4462> {rsvdd[2] (93-9F Reserved)} <byte 4462> utiny value {} <byte 4463> {rsvdd[1] (93-9F Reserved)} <byte 4463> utiny value {} <byte 4464> {rsvdd[8] (93-9F Reserved)} <byte 4464> utiny value {} <byte 4465> {rsvdd[7] (93-9F Reserved)} <byte 4465> utiny value {} <byte 4466> {rsvdd[6] (93-9F Reserved)} <byte 4466> utiny value {} <byte 4467> {rsvdd[5] (93-9F Reserved)} <byte 4467> utiny value {} <byte 4468> {rsvdd[12] (93-9F Reserved)} <byte 4468>

utiny value {} <byte 4469> {rsvdd[11] (93-9F Reserved)} <byte 4469> utiny value {} <byte 4470> {rsvdd[10] (93-9F Reserved)} <byte 4470> utiny value {} <byte 4471> {rsvdd[9] (93-9F Reserved)} <byte 4471> utiny value {} <byte 4472> union reset_dev_0 A3 GPO D: Reset Devices Ctrl 0 <byte 4472> {field (By field)} <byte 4472> tbits:1 dx2_a_l DX2 A Reset Lo {M21} tbits:1 dx2_b_l DX2 B Reset Lo {M20} tbits:1 dx2_c_l DX2 C Reset Lo {M19} tbits:1 dx2_d_l DX2 D Reset Lo {M18} tbits:1 sprite_l SPRITE Reset Lo {D1} tbits:1 uart_l UART Reset Lo {W17} tbits:1 enet1_l Ethernet 1 Reset Lo {Y17} tbits:1 enet2_l Ethernet 2 Reset Lo {AA18} {} or reset_dev_0 A3 GPO D: Reset Devices Ctrl 0 <byte 4472> utiny value As utiny endunion reset_dev_0 A3 GPO D: Reset Devices Ctrl 0 <byte 4473> union reprog_misc A2 GPO C: Reprog. & Misc. Ctrl <byte 4473> {field (By field)} <byte 4473> tbits:1 prog_sdc SDC reprogram mode (prog=1) {Y13} tbits:1 prog_can CAN reprogram mode (prog=1) {W13} tbits:1 prog_lcd LCD reprogram mode (prog=1) {V13} tbits:1 rpgm_clk Shared PIC reprogram clock {U13} tbits:1 rpgm_data Shared PIC reprogram data {W18} tbits:1 dx2_e_l DX2 E Reset L {V7} tbits:1 sdc_wdt SDC watchdog enable {Y5} tbits:1 dx2_f_l DX2 F Reset L {Y12} {} or reprog_misc A2 GPO C: Reprog. & Misc. Ctrl <byte 4473> utiny value As utiny endunion reprog_misc A2 GPO C: Reprog. & Misc. Ctrl <byte 4474> union sfp_laser A1 GPO B: SFP Laser Disable Ctrl <byte 4474> {field (By field)} <byte 4474> tbits:1 disable_0 SFP Laser 0 Disable (dis=1) {E18} tbits:1 disable_1 SFP Laser 1 Disable (dis=1) {F18}

tbits:1 disable_2 SFP Laser 2 Disable (dis=1) {G22} tbits:1 disable_3 SFP Laser 3 Disable (dis=1) {G21} tbits:1 disable_4 SFP Laser 4 Disable (dis=1) {H22} tbits:1 disable_5 SFP Laser 5 Disable (dis=1) {H21} tbits:1 disable_6 SFP Laser 6 Disable (dis=1) {H20} tbits:1 disable_7 SFP Laser 7 Disable (dis=1) {H19} {} or sfp_laser A1 GPO B: SFP Laser Disable Ctrl <byte 4474> utiny value As utiny endunion sfp_laser A1 GPO B: SFP Laser Disable Ctrl <byte 4475> union pcix01 A0 GPO A: PCIX 0 & 1 Bus Signals <byte 4475> {field (By field)} <byte 4475> tbits:1 bus0_stop_l Bus 0 STOP Lo {C22} tbits:1 bus0_trdy_l Bus 0 TRDY Lo {C21} tbits:1 bus0_devsel_l Bus 0 DEVSEL0 Lo {D22} tbits:1 bus0_req64_l Bus 0 REQ64 Lo {D21} tbits:2 rsvd1 Reserved tbits:1 pcix1_cfg_en PCIX1 Configuration Enable {E20} tbits:1 rsvd Reserved {} or pcix01 A0 GPO A: PCIX 0 & 1 Bus Signals <byte 4475> utiny value As utiny endunion pcix01 A0 GPO A: PCIX 0 & 1 Bus Signals <byte 4476> union gbic_act A7 GPI I: GBIC active <byte 4476> {field (By field)} <byte 4476> tbits:1 dx2a_f0 DX2A F0 ACTIVE {W1} tbits:1 dx2b_f0 DX2B F0 ACTIVE {W2} tbits:1 dx2c_f0 DX2C F0 ACTIVE {V3} tbits:1 dx2d_f0 DX2D F0 ACTIVE {V4} tbits:1 dx2e_f0 DX2E F0 ACTIVE {H2} tbits:1 temp0_ovr_thresh Temp Sensor 0 Over Threshold {AB19} tbits:1 temp1_ovr_thresh Temp Sensor 1 Over Threshold {AA17} tbits:1 temp2_ovr_thresh Temp Sensor 2 Over Threshold {Y18} {} or gbic_act A7 GPI I: GBIC active <byte 4476> utiny value As utiny endunion gbic_act A7 GPI I: GBIC active <byte 4477> union gbic_led A6 GPO G: GBIC LED Control <byte 4477> {field (By field)} <byte 4477> tbits:1 amb0_l R/W Amber 0 LED FLASH OFF Lo {E16} tbits:1 amb1_l R/W Amber 1 LED FLASH OFF Lo {E17} tbits:1 amb2_l R/W Amber 2 LED FLASH OFF Lo {A17} tbits:1 amb3_l R/W Amber 3 LED FLASH OFF Lo {B17} tbits:1 amb4_l R/W Amber 4 LED FLASH OFF Lo {C17} tbits:1 amb5_l R/W Amber 5 LED FLASH OFF Lo {D17} tbits:1 amb6_l R/W Amber 6 LED FLASH OFF Lo {A18} tbits:1 amb7_l R/W Amber 7 LED FLASH OFF Lo {B18} {}

or gbic_led A6 GPO G: GBIC LED Control <byte 4477> utiny value As utiny endunion gbic_led A6 GPO G: GBIC LED Control <byte 4478> union gp_in A5 GPI F: Kills, msref_req, etc. <byte 4478> {field (By field)} <byte 4478> tbits:1 dx2f_f0 DX2F F0 ACTIVE {AB17} tbits:1 rsvd Reserved {AA13} tbits:1 enet_card_gpi_1 Ethernet Card GPI_1 {V5} tbits:1 spr_debug2 Sprite Debug Bit2 {B4} tbits:1 msref_req_l MSREF_REQ Sense Line (0=SelfRef) {Y2} tbits:1 lcd_ready LCD Ready {L22} tbits:1 spr_debug3 Sprite Debug Bit3 {A4} tbits:1 rpgm_data_in Shared PIC reprogram data in {AA4} {} or gp_in A5 GPI F: Kills, msref_req, etc. <byte 4478> utiny value As utiny endunion gp_in A5 GPI F: Kills, msref_req, etc. <byte 4479> union reset_dev_1 A4 GPO E: Reset Devices Ctrl 1 <byte 4479> {field (By field)} <byte 4479> tbits:1 bezel_hb_led Bezel heart beat LED (Default=Off=1){AB5} tbits:1 sdc_l SDC Reset Lo {AA5} tbits:1 can_l CAN Reset Lo {Y6} tbits:1 lcd_l LCD Reset Lo {W6} tbits:1 toy_l TOY Reset Lo {V6} tbits:1 bezel_flt_led Bezel fault LED (Default=On=0) {W5} tbits:1 dpm_rdy PPC not accessing DPM {X} tbits:1 sdc_int_l glue to sdc interrupt (Int=0) {AB18} {} or reset_dev_1 A4 GPO E: Reset Devices Ctrl 1 <byte 4479> utiny value As utiny endunion reset_dev_1 A4 GPO E: Reset Devices Ctrl 1 <byte 4480> {rsvde[2] (A9-AE Reserved)} <byte 4480> utiny value {} <byte 4481> {rsvde[1] (A9-AE Reserved)} <byte 4481> utiny value {} <byte 4482> {rsvde[0] (A9-AE Reserved)} <byte 4482> utiny value {} <byte 4483> union gbic_led8 A8 GPO H: GBIC LED Control <byte 4483> {field (By field)} <byte 4483>

tbits:1 amb8_l R/W Amber 8 LED FLASH OFF Lo {Y2} tbits:1 amb9_l R/W Amber 9 LED FLASH OFF Lo {Y1} tbits:1 disable_8 SFP Laser 8 Disable (dis=1) {U5} tbits:1 disable_9 SFP Laser 9 Disable (dis=1) {V5} tbits:4 unused unused {} or gbic_led8 A8 GPO H: GBIC LED Control <byte 4483> utiny value As utiny endunion gbic_led8 A8 GPO H: GBIC LED Control <byte 4484> union cache_ctrl AF Cache DIMM Control <byte 4484> {field (By field)} <byte 4484> tbits:1 msref_req_l R/W MSREF_REQ (0=Self-Refresh) {AB8} tbits:1 dimm0_rst_l R/W DIMM 0 Reset Lo {D10} tbits:1 dimm1_rst_l R/W DIMM 1 Reset Lo {C10} tbits:1 dimm2_rst_l R/W DIMM 2 Reset Lo {B10} tbits:1 dimm3_rst_l R/W DIMM 3 Reset Lo {A10} tbits:1 bbu_dcok_clear R/W BBU DIMM DC OK LATCH CLEAR {AA8} tbits:1 batt_on_l R/W Battery Turn ON Lo (to preset) {Y8} tbits:1 batt_off_l R/W Battery Turn OFF Lo (to clear) {W8} {} or cache_ctrl AF Cache DIMM Control <byte 4484> utiny value As utiny endunion cache_ctrl AF Cache DIMM Control <byte 4485> {rsvde[5] (A9-AE Reserved)} <byte 4485> utiny value {} <byte 4486> {rsvde[4] (A9-AE Reserved)} <byte 4486> utiny value {} <byte 4487> {rsvde[3] (A9-AE Reserved)} <byte 4487> utiny value {} <byte 4488> {ppc_data[2] (B1-B4 PPC command data)} <byte 4488> utiny value {} <byte 4489> {ppc_data[1] (B1-B4 PPC command data)} <byte 4489> utiny value {} <byte 4490> {ppc_data[0] (B1-B4 PPC command data)} <byte 4490> utiny value {} <byte 4491> {ppc_cmd (B0 PPC command to SDC)}

<byte 4491> utiny value {} <byte 4492> {sdc_toy[1] (B6-BC sdc toy data)} <byte 4492> utiny value {} <byte 4493> {sdc_toy[0] (B6-BC sdc toy data)} <byte 4493> utiny value {} <byte 4494> {rsvb5 (B5 Reserved)} <byte 4494> utiny value {} <byte 4495> {ppc_data[3] (B1-B4 PPC command data)} <byte 4495> utiny value {} <byte 4496> {sdc_toy[5] (B6-BC sdc toy data)} <byte 4496> utiny value {} <byte 4497> {sdc_toy[4] (B6-BC sdc toy data)} <byte 4497> utiny value {} <byte 4498> {sdc_toy[3] (B6-BC sdc toy data)} <byte 4498> utiny value {} <byte 4499> {sdc_toy[2] (B6-BC sdc toy data)} <byte 4499> utiny value {} <byte 4500> union blower_led BF Blower LED Override Control <byte 4500> {field (By field)} <byte 4500> tbits:1 grn_blwr_a R/W Green Blower A LED tbits:1 amb_blwr_a R/W Amber Blower A LED tbits:1 grn_blwr_b R/W Green Blower B LED tbits:1 amb_blwr_b R/W Amber Blower B LED tbits:4 rsvd R Reserved {} or blower_led BF Blower LED Override Control <byte 4500> utiny value As utiny endunion blower_led BF Blower LED Override Control <byte 4501> union batt_led BE Battery LED Override Control

<byte 4501> {field (By field)} <byte 4501> tbits:1 grn_brk0 R/W Green Brick 0 LED tbits:1 amb_brk0 R/W Amber Brick 0 LED tbits:1 grn_brk1 R/W Green Brick 1 LED tbits:1 amb_brk1 R/W Amber Brick 1 LED tbits:1 grn_brk2 R/W Green Brick 2 LED tbits:1 amb_brk2 R/W Amber Brick 2 LED tbits:1 grn_brk3 R/W Green Brick 3 LED tbits:1 amb_brk3 R/W Amber Brick 3 LED {} or batt_led BE Battery LED Override Control <byte 4501> utiny value As utiny endunion batt_led BE Battery LED Override Control <byte 4502> {rsvbd (BD Reserved)} <byte 4502> utiny value {} <byte 4503> {sdc_toy[6] (B6-BC sdc toy data)} <byte 4503> utiny value {} <byte 4504> {batt_mod_rev[3] (C0-C3 Battery Mod. Rev.)} <byte 4504> utiny value {} <byte 4505> {batt_mod_rev[2] (C0-C3 Battery Mod. Rev.)} <byte 4505> utiny value {} <byte 4506> {batt_mod_rev[1] (C0-C3 Battery Mod. Rev.)} <byte 4506> utiny value {} <byte 4507> {batt_mod_rev[0] (C0-C3 Battery Mod. Rev.)} <byte 4507> utiny value {} <byte 4508> {avg_temp (C7 Average Temperature)} <byte 4508> utiny value {} <byte 4509> {temp_sensor[2] (C4-C6 Temp. Sensors 1, 2, & 3)} <byte 4509> utiny value {} <byte 4510> {temp_sensor[1] (C4-C6 Temp. Sensors 1, 2, & 3)} <byte 4510> utiny value

{} <byte 4511> {temp_sensor[0] (C4-C6 Temp. Sensors 1, 2, & 3)} <byte 4511> utiny value {} <byte 4512> {backup_time[1] (CA-CB backup time in x Watt-Sec)} <byte 4512> utiny value {} <byte 4513> {backup_time[0] (CA-CB backup time in x Watt-Sec)} <byte 4513> utiny value {} <byte 4514> {blower_rpm[1] (C8-C9 RPMs, Blowers 0 & 1)} <byte 4514> utiny value {} <byte 4515> {blower_rpm[0] (C8-C9 RPMs, Blowers 0 & 1)} <byte 4515> utiny value {} <byte 4516> {rsvcf (CF Spare Read Registers)} <byte 4516> utiny value {} <byte 4517> {volts_12v (CE 12V Level)} <byte 4517> utiny value {} <byte 4518> {sdc_major_rev (CD SDC Major Revision)} <byte 4518> utiny value {} <byte 4519> {sdc_minor_rev (CC SDC Minor Revision)} <byte 4519> utiny value {} <byte 4520> {brick_status[1] (D2-D5 brick interrupt status)} <byte 4520> utiny value {} <byte 4521> {brick_status[0] (D2-D5 brick interrupt status)} <byte 4521> utiny value {} <byte 4522> union sdc_int_cause1 D1 SDC interrupt cause1 <byte 4522> {field (By field)}

<byte 4522> tbits:1 rsvd R/WA0 Reserved tbits:1 cmd_processed R/WA0 PPC command has been processed tbits:2 rsvd1 R/WA0 Reserved tbits:1 hut_changed R/WA0 Hold up time changed tbits:2 rsvd2 R/WA0 Reserved tbits:1 time_req R/WA0 SDC time request {} or sdc_int_cause1 D1 SDC interrupt cause1 <byte 4522> utiny value As utiny endunion sdc_int_cause1 D1 SDC interrupt cause1 <byte 4523> union sdc_int_cause0 D0 SDC interrupt cause0 <byte 4523> {field (By field)} <byte 4523> tbits:1 brick0 R/WA0 Brick 0 tbits:1 brick1 R/WA0 Brick 1 tbits:1 brick2 R/WA0 Brick 2 tbits:1 brick3 R/WA0 Brick 3 tbits:1 blower0 R/WA0 Blower 0 tbits:1 blower1 R/WA0 Blower 1 tbits:1 temperature R/WA0 Temperature tbits:1 rsvd R/WA0 Reserved {} or sdc_int_cause0 D0 SDC interrupt cause0 <byte 4523> utiny value As utiny endunion sdc_int_cause0 D0 SDC interrupt cause0 <byte 4524> {blower_status[1] (D6-D7 blower interrupt status)} <byte 4524> utiny value {} <byte 4525> {blower_status[0] (D6-D7 blower interrupt status)} <byte 4525> utiny value {} <byte 4526> {brick_status[3] (D2-D5 brick interrupt status)} <byte 4526> utiny value {} <byte 4527> {brick_status[2] (D2-D5 brick interrupt status)} <byte 4527> utiny value {} <byte 4528> {sdc_cmd_status (DB Battery Hold Up Time)} <byte 4528> utiny value {} <byte 4529> union fru_detect DA fru detect bits <byte 4529> {field (By field)} <byte 4529>

tbits:1 brick0_present R tbits:1 brick1_present R tbits:1 brick2_present R tbits:1 brick3_present R tbits:1 blower0_present R tbits:1 blower1_present R tbits:2 rsvd R {} or fru_detect DA fru detect bits <byte 4529> utiny value As utiny endunion fru_detect DA fru detect bits <byte 4530> {sdc_status (D9 SDC codeload and brick test results)} <byte 4530> utiny value {} <byte 4531> {tmp_status (D8 temperature interrupt status)} <byte 4531> utiny value {} <byte 4532> {sdc_cmd_data[3] (DC-DF Reserved)} <byte 4532> utiny value {} <byte 4533> {sdc_cmd_data[2] (DC-DF Reserved)} <byte 4533> utiny value {} <byte 4534> {sdc_cmd_data[1] (DC-DF Reserved)} <byte 4534> utiny value {} <byte 4535> {sdc_cmd_data[0] (DC-DF Reserved)} <byte 4535> utiny value {} <byte 4536> {scratch[3] (E0-EF R/W Scratch Registers: Hardware team maintains right to res erve higher bytes if future Glue features need the space.)} <byte 4536> utiny value {} <byte 4537> {scratch[2] (E0-EF R/W Scratch Registers: Hardware team maintains right to res erve higher bytes if future Glue features need the space.)} <byte 4537> utiny value {} <byte 4538> {scratch[1] (E0-EF R/W Scratch Registers: Hardware team maintains right to res erve higher bytes if future Glue features need the space.)} <byte 4538> utiny value {}

<byte 4539> {scratch[0] (E0-EF R/W Scratch Registers: Hardware team maintains right to res erve higher bytes if future Glue features need the space.)} <byte 4539> utiny value {} <byte 4540> {scratch[7] (E0-EF R/W Scratch Registers: Hardware team maintains right to res erve higher bytes if future Glue features need the space.)} <byte 4540> utiny value {} <byte 4541> {scratch[6] (E0-EF R/W Scratch Registers: Hardware team maintains right to res erve higher bytes if future Glue features need the space.)} <byte 4541> utiny value {} <byte 4542> {scratch[5] (E0-EF R/W Scratch Registers: Hardware team maintains right to res erve higher bytes if future Glue features need the space.)} <byte 4542> utiny value {} <byte 4543> {scratch[4] (E0-EF R/W Scratch Registers: Hardware team maintains right to res erve higher bytes if future Glue features need the space.)} <byte 4543> utiny value {} <byte 4544> {scratch[11] (E0-EF R/W Scratch Registers: Hardware team maintains right to re serve higher bytes if future Glue features need the space.)} <byte 4544> utiny value {} <byte 4545> {scratch[10] (E0-EF R/W Scratch Registers: Hardware team maintains right to re serve higher bytes if future Glue features need the space.)} <byte 4545> utiny value {} <byte 4546> {scratch[9] (E0-EF R/W Scratch Registers: Hardware team maintains right to res erve higher bytes if future Glue features need the space.)} <byte 4546> utiny value {} <byte 4547> {scratch[8] (E0-EF R/W Scratch Registers: Hardware team maintains right to res erve higher bytes if future Glue features need the space.)} <byte 4547> utiny value {} <byte 4548> {scratch[15] (E0-EF R/W Scratch Registers: Hardware team maintains right to re serve higher bytes if future Glue features need the space.)} <byte 4548> utiny value {}

<byte 4549> {scratch[14] (E0-EF R/W Scratch serve higher bytes if future Glue <byte 4549> utiny value {} <byte 4550> {scratch[13] (E0-EF R/W Scratch serve higher bytes if future Glue <byte 4550> utiny value {} <byte 4551> {scratch[12] (E0-EF R/W Scratch serve higher bytes if future Glue <byte 4551> utiny value {} <byte 4552> {rsvd12[3] (F0-FD Reserved)} <byte 4552> utiny value {} <byte 4553> {rsvd12[2] (F0-FD Reserved)} <byte 4553> utiny value {} <byte 4554> {rsvd12[1] (F0-FD Reserved)} <byte 4554> utiny value {} <byte 4555> {rsvd12[0] (F0-FD Reserved)} <byte 4555> utiny value {} <byte 4556> {rsvd12[7] (F0-FD Reserved)} <byte 4556> utiny value {} <byte 4557> {rsvd12[6] (F0-FD Reserved)} <byte 4557> utiny value {} <byte 4558> {rsvd12[5] (F0-FD Reserved)} <byte 4558> utiny value {} <byte 4559> {rsvd12[4] (F0-FD Reserved)} <byte 4559> utiny value {} <byte 4560> {rsvd12[11] (F0-FD Reserved)}

Registers: Hardware team maintains right to re features need the space.)}

Registers: Hardware team maintains right to re features need the space.)}

Registers: Hardware team maintains right to re features need the space.)}

<byte 4560> utiny value {} <byte 4561> {rsvd12[10] (F0-FD Reserved)} <byte 4561> utiny value {} <byte 4562> {rsvd12[9] (F0-FD Reserved)} <byte 4562> utiny value {} <byte 4563> {rsvd12[8] (F0-FD Reserved)} <byte 4563> utiny value {} <byte 4564> {glue_major_rev (FF Glue Major Revision)} <byte 4564> utiny value {} <byte 4565> {glue_minor_rev (FE Glue Minor Revision)} <byte 4565> utiny value {} <byte 4566> {rsvd12[13] (F0-FD Reserved)} <byte 4566> utiny value {} <byte 4567> {rsvd12[12] (F0-FD Reserved)} <byte 4567> utiny value {} {} <byte 4568> do_not_display[768] union_pad Union Element Padding (DO NOT DISPLAY!) endunion csr Glue CSR Registers {} <byte 5336> {sprite (Sprite register save area)} <byte 5336> union csr Sprite CSR Registers <byte 5336> ulong[256] csra Sprite CSR Registers As Longwords or csr Sprite CSR Registers <byte 5336> {csrfield (Sprite CSR Registers By Field)} <byte 5336> union pc_cba 000 ppc chip base address <byte 5336> {field (By field)} <byte 5336> lbits:4 rev R Revision of Sprite lbits:4 rsvd R Reserved lbits:1 dimm_swap_cs R/W Swap DIMM Chip Select Signals

lbits:23 reg_base_addr R/W Register Base Address {} or pc_cba 000 ppc chip base address <byte 5336> ulong value As longword endunion pc_cba 000 ppc chip base address <byte 5340> union pc_m0_a 004 ppc to DDR memory window 0 description <byte 5340> {field (By field)} <byte 5340> lbits:12 ddr_addr R/W DDR base address, bits 35:xx lbits:2 rsvd R Reserved lbits:2 byte_swap R/W No swap, Quasar Emulation, or 32-bit lbits:8 size R/W Window size, 16MB -> 2GB lbits:8 base_addr R/W Sets bits 31:24 of base address {} or pc_m0_a 004 ppc to DDR memory window 0 description <byte 5340> ulong value As longword endunion pc_m0_a 004 ppc to DDR memory window 0 description <byte 5344> union pc_m1_a 008 ppc to DDR memory window 1 description <byte 5344> {field (By field)} <byte 5344> lbits:12 ddr_addr R/W DDR base address, bits 35:xx lbits:2 rsvd R Reserved lbits:2 byte_swap R/W No swap, Quasar Emulation, or 32-bit lbits:8 size R/W Window size, 16MB -> 2GB lbits:8 base_addr R/W Sets bits 31:24 of base address {} or pc_m1_a 008 ppc to DDR memory window 1 description <byte 5344> ulong value As longword endunion pc_m1_a 008 ppc to DDR memory window 1 description <byte 5348> union pc_m2_a 00c ppc to DDR memory window 2 description <byte 5348> {field (By field)} <byte 5348> lbits:12 ddr_addr R/W DDR base address, bits 35:xx lbits:2 rsvd R Reserved lbits:2 byte_swap R/W No swap, Quasar Emulation, or 32-bit lbits:8 size R/W Window size, 16MB -> 2GB lbits:8 base_addr R/W Sets bits 31:24 of base address {} or pc_m2_a 00c ppc to DDR memory window 2 description <byte 5348> ulong value As longword endunion pc_m2_a 00c ppc to DDR memory window 2 description <byte 5352> union pc_m3_a 010 ppc to DDR memory window 3 description <byte 5352> {field (By field)} <byte 5352> lbits:12 ddr_addr R/W DDR base address, bits 35:xx lbits:2 rsvd R Reserved lbits:2 byte_swap R/W No swap, Quasar Emulation, or 32-bit lbits:8 size R/W Window size, 16MB -> 2GB

Value Preserved

Value Preserved

Value Preserved

Value Preserved

lbits:8 base_addr R/W Sets bits 31:24 of base address {} or pc_m3_a 010 ppc to DDR memory window 3 description <byte 5352> ulong value As longword endunion pc_m3_a 010 ppc to DDR memory window 3 description <byte 5356> union pc_p0_a 014 ppc to PCIX0 memory space window description <byte 5356> {field (By field)} <byte 5356> lbits:2 byte_swap R/W No swap, Quasar Emulation, or 32-bit Value Preserved lbits:2 rsvd1 R Reserved lbits:12 size R/W Window size, 1MB -> 2GB lbits:4 rsvd R Reserved lbits:12 base_addr R/W Sets bits 31:20 of base address {} or pc_p0_a 014 ppc to PCIX0 memory space window description <byte 5356> ulong value As longword endunion pc_p0_a 014 ppc to PCIX0 memory space window description <byte 5360> {pc_p0_ua (018 ppc to PCIX0 upper address)} <byte 5360> ulong value {} <byte 5364> union pc_p1_a 01c ppc to PCIX1 memory space window description <byte 5364> {field (By field)} <byte 5364> lbits:2 byte_swap R/W No swap, Quasar Emulation, or 32-bit Value Preserved lbits:2 rsvd1 R Reserved lbits:12 size R/W Window size, 1MB -> 2GB lbits:4 rsvd R Reserved lbits:12 base_addr R/W Sets bits 31:20 of base address {} or pc_p1_a 01c ppc to PCIX1 memory space window description <byte 5364> ulong value As longword endunion pc_p1_a 01c ppc to PCIX1 memory space window description <byte 5368> {pc_p1_ua (020 ppc to PCIX1 upper address)} <byte 5368> ulong value {} <byte 5372> union pc_io_a 024 ppc lower IO address description <byte 5372> {field (By field)} <byte 5372> lbits:1 pcix_bus R/W 0 = PCIX0, 1 = PCIX1 lbits:1 rsvd R Reserved lbits:30 base_addr R/W Sets bits 31:02 of base address {} or pc_io_a 024 ppc lower IO address description <byte 5372> ulong value As longword endunion pc_io_a 024 ppc lower IO address description <byte 5376>

union pc_dls 028 mirror data has left sprite counter <byte 5376> {field (By field)} <byte 5376> lbits:16 count R/WTI Count of writes to this reg. lbits:16 rsvd R Reserved {} or pc_dls 028 mirror data has left sprite counter <byte 5376> ulong value As longword endunion pc_dls 028 mirror data has left sprite counter <byte 5380> union pc_cfg_add 02c ppc configuration address phase description <byte 5380> {field (By field)} <byte 5380> lbits:1 pcix_bus R/W 0 = PCIX0, 1 = PCIX1 lbits:1 rsvd1 R Reserved lbits:6 Register R/W Register Number lbits:3 Function R/W Function Number lbits:5 device R/W Device Number lbits:8 bus R/W Bus Number lbits:8 rsvd R Reserved {} or pc_cfg_add 02c ppc configuration address phase description <byte 5380> ulong value As longword endunion pc_cfg_add 02c ppc configuration address phase description <byte 5384> union pc_wtt 030 ppc watchdog transfer timeout <byte 5384> {field (By field)} <byte 5384> lbits:19 wd_lo R Lower Bits of Count Value lbits:8 wd_hi R/W Programmable Extra Count Value lbits:4 rsvd R Reserved lbits:1 wd_ena R/W Watchdog Enable {} or pc_wtt 030 ppc watchdog transfer timeout <byte 5384> ulong value As longword endunion pc_wtt 030 ppc watchdog transfer timeout <byte 5388> union pc_tt 034 ppc transfer timeout <byte 5388> {field (By field)} <byte 5388> lbits:16 ttcounter R/W Transfer Timeout Counter lbits:16 rsvd R Reserved {} or pc_tt 034 ppc transfer timeout <byte 5388> ulong value As longword endunion pc_tt 034 ppc transfer timeout <byte 5392> union pc_csr 038 ppc control and status <byte 5392> {field (By field)} <byte 5392> lbits:1 esum_ddr_me R/CLL DDR Memory Error Summary

lbits:1 esum_mir_me R/CLL Mirror Memory Error Summary lbits:1 esum_xor_dma R/CLL XOR-DMA Error Summary lbits:1 esum_que R/CLL Queue Error Summary lbits:1 esum_pcix1 R/CLL PCIX1 Error Summary lbits:1 esum_pcix0 R/CLL PCIX0 Error Summary lbits:1 err_pcixae R/W1C PCIX Access Error lbits:1 err_qrdpe R/W1C Queue Read Data Parity Error lbits:1 err_ppcttoe R/W1C PowerPC Transfer TimeOut Error lbits:1 err_ppcae R/W1C PowerPC Alignment Error lbits:1 err_ppcwdpe R/W1C PowerPC Write Data Parity Err lbits:1 err_ppcape R/W1C PowerPC Address Parity Error lbits:1 err_ppclee R/W1C PowerPC Last Entry Error lbits:1 err_ppc2pcixtoe R/W1C PowerPC-PCIX Transfer Timeout lbits:1 ena_pcixae R/W Enable PCIX Access Error lbits:1 ena_qrdpe R/W Enable Queue Rd Data Parity Er lbits:1 ena_ppcttoe R/W Enable PPC Transfer T.O. Error lbits:1 ena_ppcae R/W Enable PPC Alignment Error lbits:1 ena_ppcwdpe R/W Enable PPC Wrt Data Parity Err lbits:1 ena_ppcape R/W Enable PPC Address Parity Err lbits:1 ena_ppclee R/W Enable PPC Last Entry Error lbits:1 ena_ppc2pcixtoe R/W Enable PPC-PCIX Transfer T.O. lbits:1 ena_p_int1 R/W Ena PPC errs on INT1_L to Glue lbits:1 ena_p_int0 R/W Ena PPC errs on INT0_L to Glue lbits:1 sel_pcixae R/W Select P_INT(0/1)_L for pcixae lbits:1 sel_qrddpe R/W Select P_INT(0/1)_L for qrddpe lbits:1 sel_ppcttoe R/W Select P_INT(0/1)_L for ppcttoe lbits:1 sel_ppcae R/W Select P_INT(0/1)_L for ppcae lbits:1 sel_ppcwdpe R/W Select P_INT(0/1)_L for ppcwdpe lbits:1 sel_ppcape R/W Select P_INT(0/1)_L for ppcape lbits:1 sel_ppclee R/W Select P_INT(0/1)_L for ppclee lbits:1 sel_ppc2pcixtoe R/W Sel P_INT(0/1)_L 4 ppc2pcixtoe {} or pc_csr 038 ppc control and status <byte 5392> ulong value As longword endunion pc_csr 038 ppc control and status <byte 5396> union pc_err 03c ppc error status <byte 5396> {field (By field)} <byte 5396> lbits:1 hlt_mirror R/W Halt Mirror Block lbits:1 hlt_pcix1 R/W Halt PCIX 1 Block lbits:1 hlt_pcix0 R/W Halt PCIX 0 Block lbits:1 hlt_queue R/W Halt Queue Block lbits:1 hlt_ddrm R/W Halt DDR Memory Block lbits:1 hlt_dma R/W Halt DMA Block lbits:1 ena_tea R/W Enable Transfer Err Ack (TEA) lbits:1 rsvd1 R Reserved lbits:1 chk_even_ap R/W Set to Check Even Addr Parity lbits:1 chk_even_wrp R/W Set to Check Even WR Parity lbits:1 chk_even_rdp R/W Set to Check Even RD Parity lbits:1 gen_even_wrp R/W Set to Generate Even WR Parity lbits:1 gen_even_rdp R/W Set to Generate Even RD Parity lbits:1 ppc_mode R/W PowerPC Mode (1=7450 / 0=other) lbits:1 clr_hltd_mirror R/W Clear Mirror Halted Condition lbits:1 clr_hltd_pcix1 R/W Clear PCIX 1 Halted Condition lbits:1 clr_hltd_pcix0 R/W Clear PCIX 0 Halted Condition lbits:1 clr_hltd_ddq R/W Clear dma,ddrm,queue Halt Cond. lbits:8 rsvd R Reserved

lbits:1 hltd_mirror R Mirror Halted lbits:1 hltd_pcix1 R PCIX 1 Halted lbits:1 hltd_pcix0 R PCIX 0 Halted lbits:1 hltd_queue R Queue Halted lbits:1 hltd_ddrm R DDR Memory Halted lbits:1 hltd_dma R DMA Halted {} or pc_err 03c ppc error status <byte 5396> ulong value As longword endunion pc_err 03c ppc error status <byte 5400> {pc_io_data (040 ppc IO data (not configured; do not read))} <byte 5400> ulong value {} <byte 5404> {pc_cfg_data (044 ppc configuration data)} <byte 5404> ulong value {} <byte 5408> {pc_addr (048 ppc error address)} <byte 5408> ulong value {} <byte 5412> {pc_rev (04c sprite3 hardware build revision)} <byte 5412> ulong value {} <byte 5416> union pc_gen 050 sprite3 gpio control <byte 5416> {field (By field)} <byte 5416> lbits:1 gbic_amb0_l R/W GBIC Amber LED0 (flashing=1) lbits:1 gbic_amb1_l R/W GBIC Amber LED1 (flashing=1) lbits:1 gbic_amb2_l R/W GBIC Amber LED2 (flashing=1) lbits:1 gbic_amb3_l R/W GBIC Amber LED3 (flashing=1) lbits:1 gbic_amb4_l R/W GBIC Amber LED4 (flashing=1) lbits:1 gbic_amb5_l R/W GBIC Amber LED5 (flashing=1) lbits:1 gbic_amb6_l R/W GBIC Amber LED6 (flashing=1) lbits:1 gbic_amb7_l R/W GBIC Amber LED7 (flashing=1) lbits:1 gbic_amb8_l R/W GBIC Amber LED8 (flashing=1) lbits:1 gbic_amb9_l R/W GBIC Amber LED9 (flashing=1) lbits:1 sfp_dis_0 R/W SFP Laser 0 Disable (dis=1) lbits:1 sfp_dis_1 R/W SFP Laser 1 Disable (dis=1) lbits:1 sfp_dis_2 R/W SFP Laser 2 Disable (dis=1) lbits:1 sfp_dis_3 R/W SFP Laser 3 Disable (dis=1) lbits:1 sfp_dis_4 R/W SFP Laser 4 Disable (dis=1) lbits:1 sfp_dis_5 R/W SFP Laser 5 Disable (dis=1) lbits:1 sfp_dis_6 R/W SFP Laser 6 Disable (dis=1) lbits:1 sfp_dis_7 R/W SFP Laser 7 Disable (dis=1) lbits:1 sfp_dis_8 R/W SFP Laser 8 Disable (dis=1) lbits:1 sfp_dis_9 R/W SFP Laser 9 Disable (dis=1) lbits:1 sfp_dis_10 R/W SFP Laser 10 Disable (dis=1) lbits:1 sfp_dis_11 R/W SFP Laser 11 Disable (dis=1) lbits:1 gbic_amb10_l R/W GBIC Amber LED10 (flashing=1) lbits:1 gbic_amb11_l R/W GBIC Amber LED11 (flashing=1)

lbits:2 rsvd1 R/W Reserved 3.3V LVTTL lbits:6 rsvd R/W Reserved 2.5V CMOS {} or pc_gen 050 sprite3 gpio control <byte 5416> ulong value As longword endunion pc_gen 050 sprite3 gpio control <byte 5420> union pc_pll 054 sprite3 pll config <byte 5420> {field (By field)} <byte 5420> lbits:2 pll_phase_m_cnt R/W PLL phase shift for m counter lbits:2 pll_phase_c0 R/W PLL phase shift for clock C0 lbits:2 pll_phase_c1 R/W PLL phase shift for clock C1 lbits:2 pll_phase_c2 R/W PLL phase shift for clock C2 lbits:2 pll_phase_c3 R/W PLL phase shift for clock C3 lbits:2 pll_phase_c4 R/W PLL phase shift for clock C4 lbits:2 pll_phase_c5 R/W PLL phase shift for clock C5 lbits:1 rsvd1 R/W Reserved lbits:1 e_scan_done_ck R/W Enable scan done check lbits:7 pll_delay_parms R/W PLL delay parameters lbits:8 rsvd R/W Reserved lbits:1 pll_recon_w_e R/W PLL reconfig write enable {} or pc_pll 054 sprite3 pll config <byte 5420> ulong value As longword endunion pc_pll 054 sprite3 pll config <byte 5424> {ep_data (058 sprite3+ and sprite4 EEPROM reload data register)} <byte 5424> ulong value R/W EEPROM DATA {} <byte 5428> union ep_ctl 05c sprite3+ and sprite4 EEPROM reload control register <byte 5428> {field (By field)} <byte 5428> lbits:1 start_write R/W 1 = EEPROM Being written 0 = EEPROM was written lbits:1 start_read R/W 1 = EEPROM Being read 0 = EEPROM was read lbits:1 bulk_erase R/W 1 = EEPROM Being erased 0 = EEPROM was erased lbits:1 silicon_id_read R/W 1 = EEPROM ID Being read 0 = EEPROM ID read lbits:1 write_data_ready R 1 = EPA_DATA ready to be written 0 = EPA_DATA no new value lbits:1 read_data_ready R 1 = EPA_DATA ready to be read 0 = EPA_DATA now new v alue lbits:1 silicon_id_ready R Silicon ID placed in the lower bits of the EPA_DATA register lbits:1 reserved R Reserved lbits:24 eeprom_addr R Default value is 0 {} or ep_ctl 05c sprite3+ and sprite4 EEPROM reload control register <byte 5428> ulong value As longword endunion ep_ctl 05c sprite3+ and sprite4 EEPROM reload control register <byte 5432> union p0_mem_0 060 pcix0 to DDR window 0 description <byte 5432> {field (By field)}

<byte 5432> lbits:12 size R/W Window size, 32MB -> 32GB lbits:20 base_addr R/W Sets bits 45:25 of base address {} or p0_mem_0 060 pcix0 to DDR window 0 description <byte 5432> ulong value As longword endunion p0_mem_0 060 pcix0 to DDR window 0 description <byte 5436> union p0_sel_tra_0 064 pcix0 to DDR window 0 select address translation bits <byte 5436> {field (By field)} <byte 5436> lbits:12 rsvd R Reserved lbits:20 trans_sel R/W Selects Translation bits 45:25 {} or p0_sel_tra_0 064 pcix0 to DDR window 0 select address translation bits <byte 5436> ulong value As longword endunion p0_sel_tra_0 064 pcix0 to DDR window 0 select address translation bits <byte 5440> union p0_tra_0 068 pcix0 to DDR window 0 address translation value <byte 5440> {field (By field)} <byte 5440> lbits:12 rsvd R Reserved lbits:20 trans_val R/W Translation Value, bits 45:25 {} or p0_tra_0 068 pcix0 to DDR window 0 address translation value <byte 5440> ulong value As longword endunion p0_tra_0 068 pcix0 to DDR window 0 address translation value <byte 5444> union p0_mem_1 06c pcix0 to DDR window 1 description <byte 5444> {field (By field)} <byte 5444> lbits:12 size R/W Window size, 32MB -> 32GB lbits:20 base_addr R/W Sets bits 45:25 of base address {} or p0_mem_1 06c pcix0 to DDR window 1 description <byte 5444> ulong value As longword endunion p0_mem_1 06c pcix0 to DDR window 1 description <byte 5448> union p0_sel_tra_1 070 pcix0 to DDR window 1 select address translation bits <byte 5448> {field (By field)} <byte 5448> lbits:12 rsvd R Reserved lbits:20 trans_sel R/W Selects Translation bits 45:25 {} or p0_sel_tra_1 070 pcix0 to DDR window 1 select address translation bits <byte 5448> ulong value As longword endunion p0_sel_tra_1 070 pcix0 to DDR window 1 select address translation bits <byte 5452> union p0_tra_1 074 pcix0 to DDR window 1 address translation value <byte 5452> {field (By field)}

<byte 5452> lbits:12 rsvd R Reserved lbits:20 trans_val R/W Translation Value, bits 45:25 {} or p0_tra_1 074 pcix0 to DDR window 1 address translation value <byte 5452> ulong value As longword endunion p0_tra_1 074 pcix0 to DDR window 1 address translation value <byte 5456> union p0_csr 078 pcix0 control and status <byte 5456> {field (By field)} <byte 5456> lbits:1 err_mabort R/W1C Sprite performed a Master Abort lbits:1 err_tabort R/W1C Sprite received a Target Abort lbits:1 err_sa_serr R/W1C Sprite asserted SERR lbits:1 err_sd_serr R/W1C Sprite detected SERR lbits:1 err_perr R/W1C PERR asserted lbits:1 err_scit R/W1C SC Invalid Termination PCIX Errors: lbits:1 err_uesc R/W1C UnExpected SC lbits:1 err_scemr R/W1C SC Error Message or SC Received lbits:1 err_irce R/W1C Initiator Retry-Count Exceeded Split-Completion (SC) Erro rs: lbits:1 err_trce R/W1C Target Retry-Count Exceeded lbits:1 err_bcmm R/W1C Bite-Count (BC) MisMatch (Transaction BC != BC in FIFO) S prite Retry-Counts Exceeded: lbits:1 err_terpe R/W1C Transaction Entry RD Parity Err lbits:1 err_tlmm R/W1C Transaction Length MisMatch lbits:1 err_scce R/W1C Split-Completion Count Exceeded lbits:1 rsvd R Reserved lbits:1 err_nbofisd R/W1C No Beginning-Of-Frame or Invalid Single Destination lbits:1 sel_mabort R/W Select P_INT(0/1)_L for mabort lbits:1 sel_tabort R/W Select P_INT(0/1)_L for tabort lbits:1 sel_sa_serr R/W Select P_INT(0/1)_L for sa_serr lbits:1 sel_sd_serr R/W Select P_INT(0/1)_L for sd_serr lbits:1 sel_perr R/W Select P_INT(0/1)_L for perr lbits:1 sel_scit R/W Select P_INT(0/1)_L for scit lbits:1 sel_uesc R/W Select P_INT(0/1)_L for uesc lbits:1 sel_scemr R/W Select P_INT(0/1)_L for scemr lbits:1 sel_irce R/W Select P_INT(0/1)_L for irce lbits:1 sel_trce R/W Select P_INT(0/1)_L for trce lbits:1 sel_bcmm R/W Select P_INT(0/1)_L for bcmm lbits:1 sel_terpe R/W Select P_INT(0/1)_L for terpe lbits:1 sel_tlmm R/W Select P_INT(0/1)_L for tlmm lbits:1 sel_scce R/W Select P_INT(0/1)_L for scce lbits:1 sel_bt32bm R/W Select P_INT(0/1)_L for bt32bm lbits:1 sel_nbofisd R/W Select P_INT(0/1)_L for nbofisd {} or p0_csr 078 pcix0 control and status <byte 5456> ulong value As longword endunion p0_csr 078 pcix0 control and status <byte 5460> union p0_ecr 07c pcix0 error counters <byte 5460> {field (By field)} <byte 5460> lbits:12 sc_delay R/W Split-Completion Delay lbits:10 i_retries R/W Initiator Retry Count lbits:10 t_retries R/W Target Retry Count (N/A Mirror)

{} or p0_ecr 07c pcix0 error counters <byte 5460> ulong value As longword endunion p0_ecr 07c pcix0 error counters <byte 5464> union p0_edr 080 pcix0 error disables <byte 5464> {field (By field)} <byte 5464> lbits:1 dis_mabort R/W Sprite performed a Master Abort lbits:1 dis_tabort R/W Sprite received a Target Abort lbits:1 dis_sa_serr R/W Sprite asserted SERR lbits:1 dis_sd_serr R/W Sprite detected SERR lbits:1 dis_perr R/W PERR asserted lbits:1 dis_scit R/W SC Invalid Termination PCIX Errors: lbits:1 dis_uesc R/W UnExpected SC lbits:1 dis_scemr R/W SC Error Message or SC Received lbits:1 dis_irce R/W Initiator Retry-Count Exceeded Split-Completion (SC) Erro rs: lbits:1 dis_trce R/W Target Retry-Count Exceeded lbits:1 dis_bcmm R/W Bite-Count (BC) MisMatch (Transaction BC != BC in FIFO) S prite Retry-Counts Exceeded: lbits:1 dis_terpe R/W Transaction Entry RD Parity Err lbits:1 dis_tlmm R/W Transaction Length MisMatch lbits:1 dis_scce R/W Split-Completion Count Exceeded lbits:1 rsvd1 R Reserved lbits:1 dis_nbofisd R/W No Beginning-Of-Frame or Invalid Single Destination lbits:1 dis_scwopsr R/W Split-Completion without a previous Split-Response lbits:13 rsvd R Reserved DISABLE interrupts from: lbits:1 ignore_mir_bad R/W Sprite ignores err_mir_bad bit (rsvd in p0_csr & p1 _csr) lbits:1 ena_perr_serr R/W Enable PERR and SERR {} or p0_edr 080 pcix0 error disables <byte 5464> ulong value As longword endunion p0_edr 080 pcix0 error disables <byte 5468> union p0_pcix_atr 084 pcix0 attributes <byte 5468> {field (By field)} <byte 5468> lbits:8 rsvd1 R Reserved lbits:3 function R/W Transaction Function Number lbits:5 device R/W Transaction Device Number lbits:8 bus R/W Transaction Bus Number lbits:5 tag R/W Transaction Tag Number lbits:3 rsvd R Reserved {} or p0_pcix_atr 084 pcix0 attributes <byte 5468> ulong value As longword endunion p0_pcix_atr 084 pcix0 attributes <byte 5472> union p0_csr2 088 pcix0 control and status continued <byte 5472> {field (By field previous Split-Response)} <byte 5472> lbits:1 err_scwopsr R/W1C Split-Completion without a

lbits:14 rsvd1 R Reserved lbits:1 err_mir_bad R/W1C Mirror Not Present or Not OK (rsvd in p0_csr & p1_csr) lbits:1 sel_scwopsr R/W Select P_INT(0/1)_L for scnosr lbits:14 rsvd R Reserved lbits:1 sel_mir_bad R/W Sprite P_INT(0/1)_L for scnosr (rsvd in p0_csr & p1_cs r) {} or p0_csr2 088 pcix0 control and status continued <byte 5472> ulong value As longword endunion p0_csr2 088 pcix0 control and status continued <byte 5476> {rsvd3[0] (08c - 09c unused)} <byte 5476> ulong value {} <byte 5480> {rsvd3[1] (08c - 09c unused)} <byte 5480> ulong value {} <byte 5484> {rsvd3[2] (08c - 09c unused)} <byte 5484> ulong value {} <byte 5488> {rsvd3[3] (08c - 09c unused)} <byte 5488> ulong value {} <byte 5492> {rsvd3[4] (08c - 09c unused)} <byte 5492> ulong value {} <byte 5496> union p1_mem_0 0a0 pcix1 to DDR window 0 description <byte 5496> {field (By field)} <byte 5496> lbits:12 size R/W Window size, 32MB -> 32GB lbits:20 base_addr R/W Sets bits 45:25 of base address {} or p1_mem_0 0a0 pcix1 to DDR window 0 description <byte 5496> ulong value As longword endunion p1_mem_0 0a0 pcix1 to DDR window 0 description <byte 5500> union p1_sel_tra_0 0a4 pcix1 to DDR window 0 select address translation bits <byte 5500> {field (By field)} <byte 5500> lbits:12 rsvd R Reserved lbits:20 trans_sel R/W Selects Translation bits 45:25 {} or p1_sel_tra_0 0a4 pcix1 to DDR window 0 select address translation bits <byte 5500> ulong value As longword endunion p1_sel_tra_0 0a4 pcix1 to DDR window 0 select address translation bits

<byte 5504> union p1_tra_0 0a8 pcix1 to DDR window 0 address translation value <byte 5504> {field (By field)} <byte 5504> lbits:12 rsvd R Reserved lbits:20 trans_val R/W Translation Value, bits 45:25 {} or p1_tra_0 0a8 pcix1 to DDR window 0 address translation value <byte 5504> ulong value As longword endunion p1_tra_0 0a8 pcix1 to DDR window 0 address translation value <byte 5508> union p1_mem_1 0ac pcix1 to DDR window 1 description <byte 5508> {field (By field)} <byte 5508> lbits:12 size R/W Window size, 32MB -> 32GB lbits:20 base_addr R/W Sets bits 45:25 of base address {} or p1_mem_1 0ac pcix1 to DDR window 1 description <byte 5508> ulong value As longword endunion p1_mem_1 0ac pcix1 to DDR window 1 description <byte 5512> union p1_sel_tra_1 0b0 pcix1 to DDR window 1 select address translation bits <byte 5512> {field (By field)} <byte 5512> lbits:12 rsvd R Reserved lbits:20 trans_sel R/W Selects Translation bits 45:25 {} or p1_sel_tra_1 0b0 pcix1 to DDR window 1 select address translation bits <byte 5512> ulong value As longword endunion p1_sel_tra_1 0b0 pcix1 to DDR window 1 select address translation bits <byte 5516> union p1_tra_1 0b4 pcix1 to DDR window 1 address translation value <byte 5516> {field (By field)} <byte 5516> lbits:12 rsvd R Reserved lbits:20 trans_val R/W Translation Value, bits 45:25 {} or p1_tra_1 0b4 pcix1 to DDR window 1 address translation value <byte 5516> ulong value As longword endunion p1_tra_1 0b4 pcix1 to DDR window 1 address translation value <byte 5520> union p1_csr 0b8 pcix1 control and status <byte 5520> {field (By field)} <byte 5520> lbits:1 err_mabort R/W1C Sprite performed a Master Abort lbits:1 err_tabort R/W1C Sprite received a Target Abort lbits:1 err_sa_serr R/W1C Sprite asserted SERR lbits:1 err_sd_serr R/W1C Sprite detected SERR lbits:1 err_perr R/W1C PERR asserted lbits:1 err_scit R/W1C SC Invalid Termination PCIX Errors: lbits:1 err_uesc R/W1C UnExpected SC

lbits:1 err_scemr R/W1C SC Error Message or SC Received lbits:1 err_irce R/W1C Initiator Retry-Count Exceeded Split-Completion (SC) Erro rs: lbits:1 err_trce R/W1C Target Retry-Count Exceeded lbits:1 err_bcmm R/W1C Bite-Count (BC) MisMatch (Transaction BC != BC in FIFO) S prite Retry-Counts Exceeded: lbits:1 err_terpe R/W1C Transaction Entry RD Parity Err lbits:1 err_tlmm R/W1C Transaction Length MisMatch lbits:1 err_scce R/W1C Split-Completion Count Exceeded lbits:1 rsvd R Reserved lbits:1 err_nbofisd R/W1C No Beginning-Of-Frame or Invalid Single Destination lbits:1 sel_mabort R/W Select P_INT(0/1)_L for mabort lbits:1 sel_tabort R/W Select P_INT(0/1)_L for tabort lbits:1 sel_sa_serr R/W Select P_INT(0/1)_L for sa_serr lbits:1 sel_sd_serr R/W Select P_INT(0/1)_L for sd_serr lbits:1 sel_perr R/W Select P_INT(0/1)_L for perr lbits:1 sel_scit R/W Select P_INT(0/1)_L for scit lbits:1 sel_uesc R/W Select P_INT(0/1)_L for uesc lbits:1 sel_scemr R/W Select P_INT(0/1)_L for scemr lbits:1 sel_irce R/W Select P_INT(0/1)_L for irce lbits:1 sel_trce R/W Select P_INT(0/1)_L for trce lbits:1 sel_bcmm R/W Select P_INT(0/1)_L for bcmm lbits:1 sel_terpe R/W Select P_INT(0/1)_L for terpe lbits:1 sel_tlmm R/W Select P_INT(0/1)_L for tlmm lbits:1 sel_scce R/W Select P_INT(0/1)_L for scce lbits:1 sel_bt32bm R/W Select P_INT(0/1)_L for bt32bm lbits:1 sel_nbofisd R/W Select P_INT(0/1)_L for nbofisd {} or p1_csr 0b8 pcix1 control and status <byte 5520> ulong value As longword endunion p1_csr 0b8 pcix1 control and status <byte 5524> union p1_ecr 0bc pcix1 error counters <byte 5524> {field (By field)} <byte 5524> lbits:12 sc_delay R/W Split-Completion Delay lbits:10 i_retries R/W Initiator Retry Count lbits:10 t_retries R/W Target Retry Count (N/A Mirror) {} or p1_ecr 0bc pcix1 error counters <byte 5524> ulong value As longword endunion p1_ecr 0bc pcix1 error counters <byte 5528> union p1_edr 0c0 pcix1 error disables <byte 5528> {field (By field)} <byte 5528> lbits:1 dis_mabort R/W Sprite performed a Master Abort lbits:1 dis_tabort R/W Sprite received a Target Abort lbits:1 dis_sa_serr R/W Sprite asserted SERR lbits:1 dis_sd_serr R/W Sprite detected SERR lbits:1 dis_perr R/W PERR asserted lbits:1 dis_scit R/W SC Invalid Termination PCIX Errors: lbits:1 dis_uesc R/W UnExpected SC lbits:1 dis_scemr R/W SC Error Message or SC Received lbits:1 dis_irce R/W Initiator Retry-Count Exceeded Split-Completion (SC) Erro rs:

lbits:1 dis_trce R/W Target Retry-Count Exceeded lbits:1 dis_bcmm R/W Bite-Count (BC) MisMatch (Transaction BC != BC in FIFO) S prite Retry-Counts Exceeded: lbits:1 dis_terpe R/W Transaction Entry RD Parity Err lbits:1 dis_tlmm R/W Transaction Length MisMatch lbits:1 dis_scce R/W Split-Completion Count Exceeded lbits:1 rsvd1 R Reserved lbits:1 dis_nbofisd R/W No Beginning-Of-Frame or Invalid Single Destination lbits:1 dis_scwopsr R/W Split-Completion without a previous Split-Response lbits:13 rsvd R Reserved DISABLE interrupts from: lbits:1 ignore_mir_bad R/W Sprite ignores err_mir_bad bit (rsvd in p0_csr & p1 _csr) lbits:1 ena_perr_serr R/W Enable PERR and SERR {} or p1_edr 0c0 pcix1 error disables <byte 5528> ulong value As longword endunion p1_edr 0c0 pcix1 error disables <byte 5532> union p1_pcix_atr 0c4 pcix1 attributes <byte 5532> {field (By field)} <byte 5532> lbits:8 rsvd1 R Reserved lbits:3 function R/W Transaction Function Number lbits:5 device R/W Transaction Device Number lbits:8 bus R/W Transaction Bus Number lbits:5 tag R/W Transaction Tag Number lbits:3 rsvd R Reserved {} or p1_pcix_atr 0c4 pcix1 attributes <byte 5532> ulong value As longword endunion p1_pcix_atr 0c4 pcix1 attributes <byte 5536> union p1_csr2 0c8 pcix1 control and status continued <byte 5536> {field (By field previous Split-Response)} <byte 5536> lbits:1 err_scwopsr R/W1C Split-Completion without a lbits:14 rsvd1 R Reserved lbits:1 err_mir_bad R/W1C Mirror Not Present or Not OK (rsvd in p0_csr & p1_csr) lbits:1 sel_scwopsr R/W Select P_INT(0/1)_L for scnosr lbits:14 rsvd R Reserved lbits:1 sel_mir_bad R/W Sprite P_INT(0/1)_L for scnosr (rsvd in p0_csr & p1_cs r) {} or p1_csr2 0c8 pcix1 control and status continued <byte 5536> ulong value As longword endunion p1_csr2 0c8 pcix1 control and status continued <byte 5540> {rsvd4[0] (0cc - 0dc unused)} <byte 5540> ulong value {} <byte 5544> {rsvd4[1] (0cc - 0dc unused)} <byte 5544> ulong value

{} <byte 5548> {rsvd4[2] (0cc - 0dc unused)} <byte 5548> ulong value {} <byte 5552> {rsvd4[3] (0cc - 0dc unused)} <byte 5552> ulong value {} <byte 5556> {rsvd4[4] (0cc - 0dc unused)} <byte 5556> ulong value {} <byte 5560> union q_mir 0e0 mirror window description <byte 5560> {field (By field)} <byte 5560> lbits:12 size R/W Window size, 32MB -> 32GB lbits:9 rsvd R Reserved lbits:11 base_addr R/W Sets bits 35:25 of base address {} or q_mir 0e0 mirror window description <byte 5560> ulong value As longword endunion q_mir 0e0 mirror window description <byte 5564> union q_wsb 0e4 write sensitive base <byte 5564> {field (By field)} <byte 5564> lbits:1 ena_perf_int R/W Enable Performance Interrupt lbits:31 base_addr R/W Sets bits 35:5 of base address {} or q_wsb 0e4 write sensitive base <byte 5564> ulong value As longword endunion q_wsb 0e4 write sensitive base <byte 5568> union q_pint 0e8 performance interrupt <byte 5568> {field (By field)} <byte 5568> lbits:1 wsa000 R/W1C Write Sensitive Area 0x000 lbits:1 wsa020 R/W1C Write Sensitive Area 0x020 lbits:1 wsa040 R/W1C Write Sensitive Area 0x040 lbits:1 wsa060 R/W1C Write Sensitive Area 0x060 lbits:1 wsa080 R/W1C Write Sensitive Area 0x080 lbits:1 wsa0A0 R/W1C Write Sensitive Area 0x0A0 lbits:1 wsa0C0 R/W1C Write Sensitive Area 0x0C0 lbits:1 wsa0E0 R/W1C Write Sensitive Area 0x0E0 lbits:1 wsa100 R/W1C Write Sensitive Area 0x100 lbits:1 wsa120 R/W1C Write Sensitive Area 0x120 lbits:1 wsa140 R/W1C Write Sensitive Area 0x140 lbits:1 wsa160 R/W1C Write Sensitive Area 0x160 lbits:1 wsa180 R/W1C Write Sensitive Area 0x180 lbits:1 wsa1A0 R/W1C Write Sensitive Area 0x1A0

lbits:1 wsa1C0 R/W1C Write Sensitive Area 0x1C0 lbits:1 wsa1E0 R/W1C Write Sensitive Area 0x1E0 lbits:1 wsa200 R/W1C Write Sensitive Area 0x200 lbits:1 wsa220 R/W1C Write Sensitive Area 0x220 lbits:1 wsa240 R/W1C Write Sensitive Area 0x240 lbits:1 wsa260 R/W1C Write Sensitive Area 0x260 lbits:1 wsa280 R/W1C Write Sensitive Area 0x280 lbits:1 wsa2A0 R/W1C Write Sensitive Area 0x2A0 lbits:1 wsa2C0 R/W1C Write Sensitive Area 0x2C0 lbits:1 wsa2E0 R/W1C Write Sensitive Area 0x2E0 lbits:1 wsa300 R/W1C Write Sensitive Area 0x300 lbits:1 wsa320 R/W1C Write Sensitive Area 0x320 lbits:1 wsa340 R/W1C Write Sensitive Area 0x340 lbits:1 wrt_mir_dls R/W1C Write to Mirror Data has Left Sprite register lbits:1 dma_cmp_err R/W1C XOR-DMA Compare Error lbits:1 dma_complete R/W1C XOR-DMA Operation Completed lbits:1 int1 R/W1C INT_IN_1_L is asserted lbits:1 int0 R/W1C INT_IN_0_L is asserted {} or q_pint 0e8 performance interrupt <byte 5568> ulong value As longword endunion q_pint 0e8 performance interrupt <byte 5572> union q_csr 0ec queue control and status <byte 5572> {field (By field)} <byte 5572> lbits:1 err_mir_bad R/W1C Mirror Not Present or Not OK lbits:1 err_qdid R/W1C Queue Detected an Invalid Destination lbits:6 rsvd2 R Reserved lbits:1 ena_mir_bad R/W Enable mir_bad to error & halt lbits:1 ena_qdid R/W Enable qdid to error & halt lbits:6 rsvd1 R Reserved lbits:1 sel_mir_bad R/W Select P_INT(0/1)_L for mir_bad lbits:1 sel_qdid R/W Select P_INT(0/1)_L for qdid lbits:12 rsvd R Reserved lbits:1 gp2ppc_rd R/W Give priority to PowerPC Read transactions lbits:1 max_xfer_len R/W Max. Xfer Length 0=1K, 1=2K {} or q_csr 0ec queue control and status <byte 5572> ulong value As longword endunion q_csr 0ec queue control and status <byte 5576> union q_egen 0f0 error generation <byte 5576> {field (By field)} <byte 5576> lbits:3 pdf R/W Port Detector Field lbits:1 qrice R/W Queue Received an Invalid Command Entry lbits:1 tmpdb R/W Transaction Missing Proper Destination Bit lbits:1 twalanob R/W Transaction With a Low Actual Number of Bytes lbits:1 peifte R/W Parity Error in First Transaction Entry lbits:1 twnleb R/W Transaction With No Last-Entry Bit lbits:1 twnfeb R/W Transaction With No First-Entry Bit lbits:23 rsvd R Reserved {} or q_egen 0f0 error generation <byte 5576>

ulong value As longword endunion q_egen 0f0 error generation <byte 5580> union q_pcix 0f4 pci-x arbitration and bootstrapping - new for sprite3 <byte 5580> {field (By field)} <byte 5580> lbits:2 ctrl1 R/W PCIX0 Arb Control lbits:2 state1 R PCIX0 Arb State lbits:2 ctrl0 R/W PCIX1 Arb Control lbits:2 state0 R PCIX1 Arb State lbits:16 rsvd2 R Reserved lbits:1 pcix1_init_stop_l R/W PCIX1 Initialization value for Stop_l lbits:1 pcix1_init_trdy_l R/W PCIX1 Initialization value for Trdy_l lbits:1 rsvd1 R Reserved lbits:1 pcix1_init_req64_l R/W PCIX1 Initialization value for Req64_l lbits:1 pcix0_init_stop_l R/W PCIX0 Initialization value for Stop_l lbits:1 pcix0_init_trdy_l R/W PCIX0 Initialization value for Trdy_l lbits:1 rsvd R Reserved lbits:1 pcix0_init_req64_l R/W PCIX0 Initialization value for Req64_l {} or q_pcix 0f4 pci-x arbitration and bootstrapping - new for sprite3 <byte 5580> ulong value As longword endunion q_pcix 0f4 pci-x arbitration and bootstrapping - new for sprite3 <byte 5584> {rsvd5[0] (0f8 - 0fc unused)} <byte 5584> ulong value {} <byte 5588> {rsvd5[1] (0f8 - 0fc unused)} <byte 5588> ulong value {} <byte 5592> union mir_csr 100 mirror control and status <byte 5592> {field (By field)} <byte 5592> lbits:1 err_mabort R/W1C Sprite performed a Master Abort lbits:1 err_tabort R/W1C Sprite received a Target Abort lbits:1 err_sa_serr R/W1C Sprite asserted SERR lbits:1 err_sd_serr R/W1C Sprite detected SERR lbits:1 err_perr R/W1C PERR asserted lbits:1 err_scit R/W1C SC Invalid Termination PCIX Errors: lbits:1 err_uesc R/W1C UnExpected SC lbits:1 err_scemr R/W1C SC Error Message or SC Received lbits:1 err_irce R/W1C Initiator Retry-Count Exceeded Split-Completion (SC) Erro rs: lbits:1 err_trce R/W1C Target Retry-Count Exceeded lbits:1 err_bcmm R/W1C Bite-Count (BC) MisMatch (Transaction BC != BC in FIFO) S prite Retry-Counts Exceeded: lbits:1 err_terpe R/W1C Transaction Entry RD Parity Err lbits:1 err_tlmm R/W1C Transaction Length MisMatch lbits:1 err_scce R/W1C Split-Completion Count Exceeded lbits:1 rsvd R Reserved lbits:1 err_nbofisd R/W1C No Beginning-Of-Frame or Invalid Single Destination lbits:1 sel_mabort R/W Select P_INT(0/1)_L for mabort lbits:1 sel_tabort R/W Select P_INT(0/1)_L for tabort

lbits:1 sel_sa_serr R/W Select P_INT(0/1)_L for sa_serr lbits:1 sel_sd_serr R/W Select P_INT(0/1)_L for sd_serr lbits:1 sel_perr R/W Select P_INT(0/1)_L for perr lbits:1 sel_scit R/W Select P_INT(0/1)_L for scit lbits:1 sel_uesc R/W Select P_INT(0/1)_L for uesc lbits:1 sel_scemr R/W Select P_INT(0/1)_L for scemr lbits:1 sel_irce R/W Select P_INT(0/1)_L for irce lbits:1 sel_trce R/W Select P_INT(0/1)_L for trce lbits:1 sel_bcmm R/W Select P_INT(0/1)_L for bcmm lbits:1 sel_terpe R/W Select P_INT(0/1)_L for terpe lbits:1 sel_tlmm R/W Select P_INT(0/1)_L for tlmm lbits:1 sel_scce R/W Select P_INT(0/1)_L for scce lbits:1 sel_bt32bm R/W Select P_INT(0/1)_L for bt32bm lbits:1 sel_nbofisd R/W Select P_INT(0/1)_L for nbofisd {} or mir_csr 100 mirror control and status <byte 5592> ulong value As longword endunion mir_csr 100 mirror control and status <byte 5596> union mir_ecr 104 mirror error counters <byte 5596> {field (By field)} <byte 5596> lbits:12 sc_delay R/W Split-Completion Delay lbits:10 i_retries R/W Initiator Retry Count lbits:10 t_retries R/W Target Retry Count (N/A Mirror) {} or mir_ecr 104 mirror error counters <byte 5596> ulong value As longword endunion mir_ecr 104 mirror error counters <byte 5600> union mir_edr 108 mirror error disables <byte 5600> {field (By field)} <byte 5600> lbits:1 dis_mabort R/W Sprite performed a Master Abort lbits:1 dis_tabort R/W Sprite received a Target Abort lbits:1 dis_sa_serr R/W Sprite asserted SERR lbits:1 dis_sd_serr R/W Sprite detected SERR lbits:1 dis_perr R/W PERR asserted lbits:1 dis_scit R/W SC Invalid Termination PCIX Errors: lbits:1 dis_uesc R/W UnExpected SC lbits:1 dis_scemr R/W SC Error Message or SC Received lbits:1 dis_irce R/W Initiator Retry-Count Exceeded Split-Completion (SC) Erro rs: lbits:1 dis_trce R/W Target Retry-Count Exceeded lbits:1 dis_bcmm R/W Bite-Count (BC) MisMatch (Transaction BC != BC in FIFO) S prite Retry-Counts Exceeded: lbits:1 dis_terpe R/W Transaction Entry RD Parity Err lbits:1 dis_tlmm R/W Transaction Length MisMatch lbits:1 dis_scce R/W Split-Completion Count Exceeded lbits:1 rsvd1 R Reserved lbits:1 dis_nbofisd R/W No Beginning-Of-Frame or Invalid Single Destination lbits:1 dis_scwopsr R/W Split-Completion without a previous Split-Response lbits:13 rsvd R Reserved DISABLE interrupts from: lbits:1 ignore_mir_bad R/W Sprite ignores err_mir_bad bit (rsvd in p0_csr & p1 _csr) lbits:1 ena_perr_serr R/W Enable PERR and SERR

{} or mir_edr 108 mirror error disables <byte 5600> ulong value As longword endunion mir_edr 108 mirror error disables <byte 5604> union mir_pcix_atr 10c mirror pcix attributes <byte 5604> {field (By field)} <byte 5604> lbits:8 rsvd1 R Reserved lbits:3 function R/W Transaction Function Number lbits:5 device R/W Transaction Device Number lbits:8 bus R/W Transaction Bus Number lbits:5 tag R/W Transaction Tag Number lbits:3 rsvd R Reserved {} or mir_pcix_atr 10c mirror pcix attributes <byte 5604> ulong value As longword endunion mir_pcix_atr 10c mirror pcix attributes <byte 5608> union mir_dls 110 mirror data has left sprite counter <byte 5608> {field (By field)} <byte 5608> lbits:16 count R/WTI Count of writes to this reg. lbits:16 rsvd R Reserved {} or mir_dls 110 mirror data has left sprite counter <byte 5608> ulong value As longword endunion mir_dls 110 mirror data has left sprite counter <byte 5612> union mir_csr2 114 mirror control and status continued <byte 5612> {field (By field previous Split-Response)} <byte 5612> lbits:1 err_scwopsr R/W1C Split-Completion without a lbits:14 rsvd1 R Reserved lbits:1 err_mir_bad R/W1C Mirror Not Present or Not OK (rsvd in p0_csr & p1_csr) lbits:1 sel_scwopsr R/W Select P_INT(0/1)_L for scnosr lbits:14 rsvd R Reserved lbits:1 sel_mir_bad R/W Sprite P_INT(0/1)_L for scnosr (rsvd in p0_csr & p1_cs r) {} or mir_csr2 114 mirror control and status continued <byte 5612> ulong value As longword endunion mir_csr2 114 mirror control and status continued <byte 5616> {rsvd6[0] (118 - 11c unused)} <byte 5616> ulong value {} <byte 5620> {rsvd6[1] (118 - 11c unused)} <byte 5620> ulong value {}

<byte 5624> union x_cb 120 xor-dma command block base address <byte 5624> {field (By field)} <byte 5624> lbits:19 base_addr R/W Base Address of XOR-DMA SCDBs lbits:13 rsvd R Reserved {} or x_cb 120 xor-dma command block base address <byte 5624> ulong value As longword endunion x_cb 120 xor-dma command block base address <byte 5628> union x_pi 124 xor-dma producer index <byte 5628> {field (By field)} <byte 5628> lbits:11 index R/W SCDB index lbits:21 rsvd R Reserved {} or x_pi 124 xor-dma producer index <byte 5628> ulong value As longword endunion x_pi 124 xor-dma producer index <byte 5632> union x_ci 128 xor-dma consumer index <byte 5632> {field (By field)} <byte 5632> lbits:11 index R/W SCDB index lbits:21 rsvd R Reserved {} or x_ci 128 xor-dma consumer index <byte 5632> ulong value As longword endunion x_ci 128 xor-dma consumer index <byte 5636> union x_cc 12c xor-dma current command <byte 5636> {field (By field)} <byte 5636> lbits:4 rsvd R Reserved lbits:20 qword_cnt R Transfer Size in Qwords lbits:7 opcode R DMA Operation lbits:1 I R Interrupt on command completion {} or x_cc 12c xor-dma current command <byte 5636> ulong value As longword endunion x_cc 12c xor-dma current command <byte 5640> union x_usa 130 xor-dma upper source address <byte 5640> {field (By field)} <byte 5640> lbits:8 x_sa3 R Upper Source Address for x_sa3 lbits:8 x_sa2 R Upper Source Address for x_sa2 lbits:8 x_sa1 R Upper Source Address for x_sa1 lbits:8 x_sa0 R Upper Source Address for x_sa0 {}

or x_usa 130 xor-dma upper source address <byte 5640> ulong value As longword endunion x_usa 130 xor-dma upper source address <byte 5644> union x_sa[0] 134 - 140 xor-dma source addresses 0-3 <byte 5644> {field (By field)} <byte 5644> lbits:4 mrwc R Mirror R/W Control lbits:28 addr R Source Address, (Lower) {} or x_sa[0] 134 - 140 xor-dma source addresses 0-3 <byte 5644> ulong value As longword endunion x_sa[0] 134 - 140 xor-dma source addresses 0-3 <byte 5648> union x_sa[1] 134 - 140 xor-dma source addresses 0-3 <byte 5648> {field (By field)} <byte 5648> lbits:4 mrwc R Mirror R/W Control lbits:28 addr R Source Address, (Lower) {} or x_sa[1] 134 - 140 xor-dma source addresses 0-3 <byte 5648> ulong value As longword endunion x_sa[1] 134 - 140 xor-dma source addresses 0-3 <byte 5652> union x_sa[2] 134 - 140 xor-dma source addresses 0-3 <byte 5652> {field (By field)} <byte 5652> lbits:4 mrwc R Mirror R/W Control lbits:28 addr R Source Address, (Lower) {} or x_sa[2] 134 - 140 xor-dma source addresses 0-3 <byte 5652> ulong value As longword endunion x_sa[2] 134 - 140 xor-dma source addresses 0-3 <byte 5656> union x_sa[3] 134 - 140 xor-dma source addresses 0-3 <byte 5656> {field (By field)} <byte 5656> lbits:4 mrwc R Mirror R/W Control lbits:28 addr R Source Address, (Lower) {} or x_sa[3] 134 - 140 xor-dma source addresses 0-3 <byte 5656> ulong value As longword endunion x_sa[3] 134 - 140 xor-dma source addresses 0-3 <byte 5660> union x_da 144 xor-dma destination address <byte 5660> {field (By field)} <byte 5660> lbits:4 mrwc R Mirror R/W Control lbits:28 addr R Source Address, (Lower) {}

or x_da 144 xor-dma destination address <byte 5660> ulong value As longword endunion x_da 144 xor-dma destination address <byte 5664> union x_uda 148 xor-dma upper destination address <byte 5664> {field (By field)} <byte 5664> lbits:24 rsvd R Reserved lbits:8 x_da R Upper Destination Addr for x_da {} or x_uda 148 xor-dma upper destination address <byte 5664> ulong value As longword endunion x_uda 148 xor-dma upper destination address <byte 5668> {x_spare (14c xor-dma spare)} <byte 5668> ulong value {} <byte 5672> {x_tmo (150 xor-dma transfer time out)} <byte 5672> ulong value {} <byte 5676> union x_csr 154 xor-dma control and status <byte 5676> {field (By field ** in q_pint and W1C in q_pint))} <byte 5676> lbits:1 cmp_err R Compare Error -- (duplicated lbits:1 err_count R/W1C Error, Count lbits:1 err_invop R/W1C Error, Invalid Opcode lbits:1 err_parity R/W1C Error, Parity lbits:1 err_efe R/W1C Error, End Frame Error lbits:1 err_sfe R/W1C Error, Start Frame Error lbits:1 err_toe R/W1C Error, TimeOut Error lbits:2 rsvd2 R Reserved lbits:1 sel_count R/W Select P_INT(0/1)_L for count lbits:1 sel_invop R/W Select P_INT(0/1)_L for invop lbits:1 sel_parity R/W Select P_INT(0/1)_L for parity lbits:1 sel_efe R/W Select P_INT(0/1)_L for efe lbits:1 sel_sfe R/W Select P_INT(0/1)_L for sfe lbits:1 sel_toe R/W Select P_INT(0/1)_L for toe lbits:2 rsvd1 R Reserved lbits:1 ena_count R/W Enable Count Errors lbits:1 ena_invop R/W Enable Invalid Opcode Errors lbits:1 ena_parity R/W Enable Parity Errors lbits:1 ena_efe R/W Enable End Frame Errors lbits:1 ena_sfe R/W Enable Start Frame Errors lbits:9 rsvd R Reserved lbits:1 ena_dma R/W Enables XOR-DMA operations {} or x_csr 154 xor-dma control and status <byte 5676> ulong value As longword endunion x_csr 154 xor-dma control and status <byte 5680> {x_qda (158 xor_dma q destination address 1 - new for Sprite 4)}

<byte 5680> ulong value {} <byte 5684> {x_co (15c xor_dma RAID 6 coefficients - new for Sprite 4)} <byte 5684> ulong value {} <byte 5688> union m_tr 160 memory timing <byte 5688> {field (By field)} <byte 5688> lbits:1 Twtr R/W Timing, WR to RD cmd delay lbits:3 Trc R/W Timing, Activate to active cmd (same bnk) or Autoref to ' ' lbits:2 Trcd R/W Timing, Activate to RD or WR lbits:3 Tras R/W Timing, Activate to Precharge lbits:2 Trp R/W Timing, Precharge to Activate lbits:3 Trfc R/W Timing, Autoref cmd to Autoref or Activate cmd lbits:1 sdram_avail R Memory Unavailable When Cleared lbits:1 ecc_disable R/W Disable ECC Correction lbits:1 self_ref R/W Refresh Mode: 1=DIMMs,0=Sprite lbits:1 rsvd1 R/W Reserved (R/W from prev. use) lbits:14 rsvd R Reserved {} or m_tr 160 memory timing <byte 5688> ulong value As longword endunion m_tr 160 memory timing <byte 5692> union m_cfg 164 memory configuration <byte 5692> {field (By field)} <byte 5692> lbits:9 refrate R/W Refresh Rate Count lbits:1 refcnten R/W Enable Refresh Rate Counter lbits:1 init_rfsh R/W Issue Auto Refresh Commands lbits:1 rsvd1 R/W Reserved (R/W from prev. use) lbits:12 rfcntr R/W Refresh Cycles with init_rfsh lbits:1 ss_dimms R/W Single Sided DIMMs Installed lbits:1 scrub_en R/W Enable HW Scrubbing lbits:6 rsvd R Reserved {} or m_cfg 164 memory configuration <byte 5692> ulong value As longword endunion m_cfg 164 memory configuration <byte 5696> union m_mrs 168 mode register set <byte 5696> {field (By field)} <byte 5696> lbits:3 burst_length R Burst Length lbits:1 burst_type R Burst Type lbits:3 cas_latency R/W CAS Latency lbits:5 op_mode R/W Operating Mode lbits:20 rsvd R Reserved {} or m_mrs 168 mode register set <byte 5696>

ulong value As longword endunion m_mrs 168 mode register set <byte 5700> union m_emrs 16c extended mode register set <byte 5700> {field (By field)} <byte 5700> lbits:1 sdram_dll_dis R/W Disable DLL in DDR SDRAMs lbits:1 ds R/W Drive Strength(1=Weak,0=Normal) lbits:1 qfc R/W QFC FET Isolation Control lbits:9 xemrs R/W Rsvd emrs JEDEC bits, set 0 lbits:20 rsvd R Reserved {} or m_emrs 16c extended mode register set <byte 5700> ulong value As longword endunion m_emrs 16c extended mode register set <byte 5704> union m_siz 170 DDR SRAM Size <byte 5704> {field (By field)} <byte 5704> lbits:3 ddr_size R/W DDR Memory Size Code lbits:2 installed_dimms R/W Number of DIMMs Installed lbits:1 scrub_test R/W Test bit for HW Scrub Circuit lbits:2 la_socket R/W Socket Number of L.A. (0->3) lbits:1 lap R/W Logic Analyzer Probe Installed lbits:23 rsvd R Reserved {} or m_siz 170 DDR SRAM Size <byte 5704> ulong value As longword endunion m_siz 170 DDR SRAM Size <byte 5708> union m_ese 174 ECC error status even <byte 5708> {field (By field)} <byte 5708> lbits:1 ude R/WCA Test bit for HW Scrub Circuit lbits:1 cde R/WCA Socket Number of L.A. (0->3) lbits:22 rsvd R Reserved lbits:8 syndrome R/WCA Syndrome when cde or ude == 1 {} or m_ese 174 ECC error status even <byte 5708> ulong value As longword endunion m_ese 174 ECC error status even <byte 5712> union m_eso 178 ECC error status odd <byte 5712> {field (By field)} <byte 5712> lbits:1 ude R/WCA Test bit for HW Scrub Circuit lbits:1 cde R/WCA Socket Number of L.A. (0->3) lbits:22 rsvd R Reserved lbits:8 syndrome R/WCA Syndrome when cde or ude == 1 {} or m_eso 178 ECC error status odd <byte 5712> ulong value As longword

endunion m_eso 178 ECC error status odd <byte 5716> union m_eae 17c ECC address error even <byte 5716> {field (By field)} <byte 5716> lbits:32 ecc_aoe_35_4 R ECC Address of Error, bits 35:4 {} or m_eae 17c ECC address error even <byte 5716> ulong value As longword endunion m_eae 17c ECC address error even <byte 5720> union m_eao 180 ECC address error odd <byte 5720> {field (By field)} <byte 5720> lbits:32 ecc_aoe_35_4 R ECC Address of Error, bits 35:4 {} or m_eao 180 ECC address error odd <byte 5720> ulong value As longword endunion m_eao 180 ECC address error odd <byte 5724> union m_esc 184 ECC syndrome preset, correctable error counter <byte 5724> {field (By field)} <byte 5724> lbits:16 cec R/W Correctable Error Counter lbits:8 odd_egs R/W Odd Error Generating Syndrome lbits:8 even_egs R/W Even Error Generating Syndrome {} or m_esc 184 ECC syndrome preset, correctable error counter <byte 5724> ulong value As longword endunion m_esc 184 ECC syndrome preset, correctable error counter <byte 5728> union m_es 188 DDR error status <byte 5728> {field (By field Halts chip - h)} <byte 5728> lbits:1 err_ncb R/W1C New Command Bad h lbits:1 err_cdpe R/W1C Cmd/Data Parity Error h lbits:1 err_ude R/CLL Uncorrectable Data Error h lbits:1 err_bwde R/W1C Bad Write Data Error h lbits:1 err_cde R/CLL Correctable Data Error lbits:3 rsvd2 R Reserved lbits:1 sel_ncb R/W Select P_INT(0/1)_L for ncb's lbits:1 sel_cdpe R/W Select P_INT(0/1)_L for cdpe's lbits:1 sel_ude R/W Select P_INT(0/1)_L for ude's lbits:1 sel_bwde R/W Select P_INT(0/1)_L for bwde's lbits:1 sel_cde R/W Select P_INT(0/1)_L for cde's lbits:3 rsvd1 R Reserved lbits:1 dis_ncb R/W Disable New Command Bad lbits:1 dis_cdpe R/W Disable Cmd/Data Parity Error lbits:1 dis_ude R/W Disable Uncorrectable Data Err lbits:1 dis_bwde R/W Disable Bad Write Data Error lbits:1 dis_cde R/W Disable Correctable Data Error lbits:11 rsvd R Reserved {}

or m_es 188 DDR error status <byte 5728> ulong value As longword endunion m_es 188 DDR error status <byte 5732> union m_sta 18c scrub test address <byte 5732> {field (By field)} <byte 5732> lbits:32 start_addr_35_5 R/W Scrub Test Address, bits 35:5 {} or m_sta 18c scrub test address <byte 5732> ulong value As longword endunion m_sta 18c scrub test address {} <byte 5736> do_not_display[624] union_pad Union Element Padding (DO NOT DISPLAY!) endunion csr Sprite CSR Registers {} <byte 6360> {quartcr[0] (SC28L194 Quad UART Control Registers a, b, c, d)} <byte 6360> union bcrbrk (Offset 0x03) R/W Bid Control, Break Change <byte 6360> {field (By field)} <byte 6360> tbits:3 msb_break_change_int_bid Bits 2:0 MSB of break change interrupt bid tbits:5 reserved Bits 7:3 Reserved {} or bcrbrk (Offset 0x03) R/W Bid Control, Break Change <byte 6360> utiny value As byte endunion bcrbrk (Offset 0x03) R/W Bid Control, Break Change <byte 6361> union iopcr (Offset 0x02) R/W I/O Port Configuration Register <byte 6361> {field (By field)} <byte 6361> tbits:2 io0_control Bits 1:0 I/O0 control tbits:2 io1_control Bits 3:2 I/O1 control tbits:2 io2_control Bits 5:4 I/O2 control tbits:2 io3_control Bits 7:6 I/O3 control {} or iopcr (Offset 0x02) R/W I/O Port Configuration Register <byte 6361> utiny value As byte endunion iopcr (Offset 0x02) R/W I/O Port Configuration Register <byte 6362> union mr1 (Offset 0x01) R/W Mode Register 1 <byte 6362> {field (By field)} <byte 6362> tbits:2 bits_per_character Bit 1:0 Bits per Character tbits:1 parity_type Bit 2 Parity Type tbits:2 parity_mode Bit 4:3 Parity Mode tbits:1 error_mode Bit 5 Error Mode tbits:1 isr_read_mode Bit 6 ISR Read Mode tbits:1 rx_rts_control Bit 7 Receiver RTS Control {}

or mr1 (Offset 0x01) R/W Mode Register 1 <byte 6362> utiny value As byte endunion mr1 (Offset 0x01) R/W Mode Register 1 <byte 6363> union mr0 (Offset 0x00) R/W Mode Register 0 <byte 6363> {field (By field)} <byte 6363> tbits:2 ar_control Bit 1:0 Address Recognition control tbits:2 inband_flow_control_mode Bit 3:2 In-band flow control mode tbits:2 txint Bit 5:4 Transmitter initiation of interrupt bidding condition tbits:1 ar_transparency Bit 6 Address Recognition transparency tbits:1 xon_xoff_transparency Bit 7 Xon/Xoff transparency {} or mr0 (Offset 0x00) R/W Mode Register 0 <byte 6363> utiny value As byte endunion mr0 (Offset 0x00) R/W Mode Register 0 <byte 6364> union bcra (Offset 0x07) R/W Bid Control, Address recognition <byte 6364> {field (By field)} <byte 6364> tbits:3 msb_ar_event_int_bid Bits 2:0 MSB of an address recognition event interr upt bid tbits:5 reserved Bits 7:3 Reserved {} or bcra (Offset 0x07) R/W Bid Control, Address recognition <byte 6364> utiny value As byte endunion bcra (Offset 0x07) R/W Bid Control, Address recognition <byte 6365> union bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff <byte 6365> {field (By field)} <byte 6365> tbits:3 msb_xon_xoff_int_bid Bits 2:0 MSB of an Xon/Xoff interrupt bid tbits:5 reserved Bits 7:3 Reserved {} or bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff <byte 6365> utiny value As byte endunion bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff <byte 6366> {rsvd1 ((Offset 0x05) NA Reserved)} <byte 6366> utiny value {} <byte 6367> union bcrcos (Offset 0x04) R/W Bid Control, Change of State <byte 6367> {field (By field)} <byte 6367> tbits:3 msb_cos_int_bid Bits 2:0 MSB of a COS interrupt bid tbits:5 reserved Bits 7:3 Reserved {} or bcrcos (Offset 0x04) R/W Bid Control, Change of State <byte 6367> utiny value As byte

endunion bcrcos (Offset 0x04) R/W Bid Control, Change of State <byte 6368> union icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only) <byte 6368> {field (By field)} <byte 6368> tbits:7 arbitration_threshold Bits 6:0 Upper seven bits of the Arbitration Thres hold tbits:1 reserved Bit 7 Reserved. Set to 0 {} or icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only) <byte 6368> utiny value As byte endunion icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only) <byte 6369> union arcr (Offset 0x0A) R/W Address Recognition Character <byte 6369> {field (By field)} <byte 6369> tbits:8 multidrop_ac_recognition Bits 7:0 8 Bits of the Multi-Drop Address Chara cter Recognition {} or arcr (Offset 0x0A) R/W Address Recognition Character <byte 6369> utiny value As byte endunion arcr (Offset 0x0A) R/W Address Recognition Character <byte 6370> union xoffcr (Offset 0x09) R/W Xoff Character Register <byte 6370> {field (By field)} <byte 6370> tbits:8 xoff_character_recognition Bits 7:0 8 Bits of the Xoff Character Recogni tion {} or xoffcr (Offset 0x09) R/W Xoff Character Register <byte 6370> utiny value As byte endunion xoffcr (Offset 0x09) R/W Xoff Character Register <byte 6371> union xoncr (Offset 0x08) R/W Xon Character Register <byte 6371> {field (By field)} <byte 6371> tbits:8 xon_character_recognition Bits 7:0 8 Bits of the Xon Character Recogniti on {} or xoncr (Offset 0x08) R/W Xon Character Register <byte 6371> utiny value As byte endunion xoncr (Offset 0x08) R/W Xon Character Register <byte 6372> union c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Off set 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6372> union gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) <byte 6372> {field (By field)} <byte 6372> tbits:1 power_down_mode Bit 0 Power Down Mode tbits:2 int_vector_control Bit 2:1 Interrupt Vector Control

tbits:3 reserved_5_3 Bit 5:3 Reserved tbits:1 sync_bus_cycles Bit 6 Sync bus cycles tbits:1 reserved_7 Bit 7 Reserved {} or gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) <byte 6372> utiny value As byte endunion gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) or c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6372> union ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6372> {field (By field)} <byte 6372> tbits:8 data_bits Bits 7:0 8 data bits of the Interrupt Vector {} or ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6372> utiny value As byte endunion ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) or c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6372> utiny value As byte endunion c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) ( Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6373> union txcsr (Offset 0x0E) R/W Transmitter Clock Select Register <byte 6373> {field (By field)} <byte 6373> tbits:5 tx_rx_clock_select_code Bits 4:0 Transmitter/Receiver Clock select code tbits:3 reserved Bits 7:5 Reserved {} or txcsr (Offset 0x0E) R/W Transmitter Clock Select Register <byte 6373> utiny value As byte endunion txcsr (Offset 0x0E) R/W Transmitter Clock Select Register <byte 6374> union c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-d og Timer Run Control (UARTB only) <byte 6374> {testreg ((Offset 0x0D) R/W Test Register (UARTA only))} <byte 6374> utiny value {} or c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) <byte 6374> union wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) <byte 6374> {field (By field)} <byte 6374> tbits:1 wdt_a Bit 0 WDT a tbits:1 wdt_b Bit 1 WDT b tbits:1 wdt_c Bit 2 WDT c tbits:1 wdt_d Bit 3 WDT d tbits:4 reserved Bits 7:4 Reserved {}

or wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) <byte 6374> utiny value As byte endunion wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) or c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) <byte 6374> utiny value As byte endunion c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watc h-dog Timer Run Control (UARTB only) <byte 6375> union rxcsr (Offset 0x0C) R/W Receiver Clock Select Register <byte 6375> {field (By field)} <byte 6375> tbits:5 tx_rx_clock_select_code Bits 4:0 Transmitter/Receiver Clock select code tbits:3 reserved Bits 7:5 Reserved {} or rxcsr (Offset 0x0C) R/W Receiver Clock Select Register <byte 6375> utiny value As byte endunion rxcsr (Offset 0x0C) R/W Receiver Clock Select Register {} <byte 6376> {quartcr[1] (SC28L194 Quad UART Control Registers a, b, c, d)} <byte 6376> union bcrbrk (Offset 0x03) R/W Bid Control, Break Change <byte 6376> {field (By field)} <byte 6376> tbits:3 msb_break_change_int_bid Bits 2:0 MSB of break change interrupt bid tbits:5 reserved Bits 7:3 Reserved {} or bcrbrk (Offset 0x03) R/W Bid Control, Break Change <byte 6376> utiny value As byte endunion bcrbrk (Offset 0x03) R/W Bid Control, Break Change <byte 6377> union iopcr (Offset 0x02) R/W I/O Port Configuration Register <byte 6377> {field (By field)} <byte 6377> tbits:2 io0_control Bits 1:0 I/O0 control tbits:2 io1_control Bits 3:2 I/O1 control tbits:2 io2_control Bits 5:4 I/O2 control tbits:2 io3_control Bits 7:6 I/O3 control {} or iopcr (Offset 0x02) R/W I/O Port Configuration Register <byte 6377> utiny value As byte endunion iopcr (Offset 0x02) R/W I/O Port Configuration Register <byte 6378> union mr1 (Offset 0x01) R/W Mode Register 1 <byte 6378> {field (By field)} <byte 6378> tbits:2 bits_per_character Bit 1:0 Bits per Character tbits:1 parity_type Bit 2 Parity Type tbits:2 parity_mode Bit 4:3 Parity Mode tbits:1 error_mode Bit 5 Error Mode

tbits:1 isr_read_mode Bit 6 ISR Read Mode tbits:1 rx_rts_control Bit 7 Receiver RTS Control {} or mr1 (Offset 0x01) R/W Mode Register 1 <byte 6378> utiny value As byte endunion mr1 (Offset 0x01) R/W Mode Register 1 <byte 6379> union mr0 (Offset 0x00) R/W Mode Register 0 <byte 6379> {field (By field)} <byte 6379> tbits:2 ar_control Bit 1:0 Address Recognition control tbits:2 inband_flow_control_mode Bit 3:2 In-band flow control mode tbits:2 txint Bit 5:4 Transmitter initiation of interrupt bidding condition tbits:1 ar_transparency Bit 6 Address Recognition transparency tbits:1 xon_xoff_transparency Bit 7 Xon/Xoff transparency {} or mr0 (Offset 0x00) R/W Mode Register 0 <byte 6379> utiny value As byte endunion mr0 (Offset 0x00) R/W Mode Register 0 <byte 6380> union bcra (Offset 0x07) R/W Bid Control, Address recognition <byte 6380> {field (By field)} <byte 6380> tbits:3 msb_ar_event_int_bid Bits 2:0 MSB of an address recognition event interr upt bid tbits:5 reserved Bits 7:3 Reserved {} or bcra (Offset 0x07) R/W Bid Control, Address recognition <byte 6380> utiny value As byte endunion bcra (Offset 0x07) R/W Bid Control, Address recognition <byte 6381> union bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff <byte 6381> {field (By field)} <byte 6381> tbits:3 msb_xon_xoff_int_bid Bits 2:0 MSB of an Xon/Xoff interrupt bid tbits:5 reserved Bits 7:3 Reserved {} or bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff <byte 6381> utiny value As byte endunion bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff <byte 6382> {rsvd1 ((Offset 0x05) NA Reserved)} <byte 6382> utiny value {} <byte 6383> union bcrcos (Offset 0x04) R/W Bid Control, Change of State <byte 6383> {field (By field)} <byte 6383> tbits:3 msb_cos_int_bid Bits 2:0 MSB of a COS interrupt bid tbits:5 reserved Bits 7:3 Reserved {}

or bcrcos (Offset 0x04) R/W Bid Control, Change of State <byte 6383> utiny value As byte endunion bcrcos (Offset 0x04) R/W Bid Control, Change of State <byte 6384> union icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only) <byte 6384> {field (By field)} <byte 6384> tbits:7 arbitration_threshold Bits 6:0 Upper seven bits of the Arbitration Thres hold tbits:1 reserved Bit 7 Reserved. Set to 0 {} or icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only) <byte 6384> utiny value As byte endunion icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only) <byte 6385> union arcr (Offset 0x0A) R/W Address Recognition Character <byte 6385> {field (By field)} <byte 6385> tbits:8 multidrop_ac_recognition Bits 7:0 8 Bits of the Multi-Drop Address Chara cter Recognition {} or arcr (Offset 0x0A) R/W Address Recognition Character <byte 6385> utiny value As byte endunion arcr (Offset 0x0A) R/W Address Recognition Character <byte 6386> union xoffcr (Offset 0x09) R/W Xoff Character Register <byte 6386> {field (By field)} <byte 6386> tbits:8 xoff_character_recognition Bits 7:0 8 Bits of the Xoff Character Recogni tion {} or xoffcr (Offset 0x09) R/W Xoff Character Register <byte 6386> utiny value As byte endunion xoffcr (Offset 0x09) R/W Xoff Character Register <byte 6387> union xoncr (Offset 0x08) R/W Xon Character Register <byte 6387> {field (By field)} <byte 6387> tbits:8 xon_character_recognition Bits 7:0 8 Bits of the Xon Character Recogniti on {} or xoncr (Offset 0x08) R/W Xon Character Register <byte 6387> utiny value As byte endunion xoncr (Offset 0x08) R/W Xon Character Register <byte 6388> union c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Off set 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6388> union gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) <byte 6388> {field (By field)}

<byte 6388> tbits:1 power_down_mode Bit 0 Power Down Mode tbits:2 int_vector_control Bit 2:1 Interrupt Vector Control tbits:3 reserved_5_3 Bit 5:3 Reserved tbits:1 sync_bus_cycles Bit 6 Sync bus cycles tbits:1 reserved_7 Bit 7 Reserved {} or gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) <byte 6388> utiny value As byte endunion gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) or c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6388> union ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6388> {field (By field)} <byte 6388> tbits:8 data_bits Bits 7:0 8 data bits of the Interrupt Vector {} or ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6388> utiny value As byte endunion ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) or c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6388> utiny value As byte endunion c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) ( Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6389> union txcsr (Offset 0x0E) R/W Transmitter Clock Select Register <byte 6389> {field (By field)} <byte 6389> tbits:5 tx_rx_clock_select_code Bits 4:0 Transmitter/Receiver Clock select code tbits:3 reserved Bits 7:5 Reserved {} or txcsr (Offset 0x0E) R/W Transmitter Clock Select Register <byte 6389> utiny value As byte endunion txcsr (Offset 0x0E) R/W Transmitter Clock Select Register <byte 6390> union c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-d og Timer Run Control (UARTB only) <byte 6390> {testreg ((Offset 0x0D) R/W Test Register (UARTA only))} <byte 6390> utiny value {} or c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) <byte 6390> union wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) <byte 6390> {field (By field)} <byte 6390> tbits:1 wdt_a Bit 0 WDT a tbits:1 wdt_b Bit 1 WDT b tbits:1 wdt_c Bit 2 WDT c

tbits:1 wdt_d Bit 3 WDT d tbits:4 reserved Bits 7:4 Reserved {} or wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) <byte 6390> utiny value As byte endunion wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) or c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) <byte 6390> utiny value As byte endunion c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watc h-dog Timer Run Control (UARTB only) <byte 6391> union rxcsr (Offset 0x0C) R/W Receiver Clock Select Register <byte 6391> {field (By field)} <byte 6391> tbits:5 tx_rx_clock_select_code Bits 4:0 Transmitter/Receiver Clock select code tbits:3 reserved Bits 7:5 Reserved {} or rxcsr (Offset 0x0C) R/W Receiver Clock Select Register <byte 6391> utiny value As byte endunion rxcsr (Offset 0x0C) R/W Receiver Clock Select Register {} <byte 6392> {quartcr[2] (SC28L194 Quad UART Control Registers a, b, c, d)} <byte 6392> union bcrbrk (Offset 0x03) R/W Bid Control, Break Change <byte 6392> {field (By field)} <byte 6392> tbits:3 msb_break_change_int_bid Bits 2:0 MSB of break change interrupt bid tbits:5 reserved Bits 7:3 Reserved {} or bcrbrk (Offset 0x03) R/W Bid Control, Break Change <byte 6392> utiny value As byte endunion bcrbrk (Offset 0x03) R/W Bid Control, Break Change <byte 6393> union iopcr (Offset 0x02) R/W I/O Port Configuration Register <byte 6393> {field (By field)} <byte 6393> tbits:2 io0_control Bits 1:0 I/O0 control tbits:2 io1_control Bits 3:2 I/O1 control tbits:2 io2_control Bits 5:4 I/O2 control tbits:2 io3_control Bits 7:6 I/O3 control {} or iopcr (Offset 0x02) R/W I/O Port Configuration Register <byte 6393> utiny value As byte endunion iopcr (Offset 0x02) R/W I/O Port Configuration Register <byte 6394> union mr1 (Offset 0x01) R/W Mode Register 1 <byte 6394> {field (By field)} <byte 6394> tbits:2 bits_per_character Bit 1:0 Bits per Character

tbits:1 parity_type Bit 2 Parity Type tbits:2 parity_mode Bit 4:3 Parity Mode tbits:1 error_mode Bit 5 Error Mode tbits:1 isr_read_mode Bit 6 ISR Read Mode tbits:1 rx_rts_control Bit 7 Receiver RTS Control {} or mr1 (Offset 0x01) R/W Mode Register 1 <byte 6394> utiny value As byte endunion mr1 (Offset 0x01) R/W Mode Register 1 <byte 6395> union mr0 (Offset 0x00) R/W Mode Register 0 <byte 6395> {field (By field)} <byte 6395> tbits:2 ar_control Bit 1:0 Address Recognition control tbits:2 inband_flow_control_mode Bit 3:2 In-band flow control mode tbits:2 txint Bit 5:4 Transmitter initiation of interrupt bidding condition tbits:1 ar_transparency Bit 6 Address Recognition transparency tbits:1 xon_xoff_transparency Bit 7 Xon/Xoff transparency {} or mr0 (Offset 0x00) R/W Mode Register 0 <byte 6395> utiny value As byte endunion mr0 (Offset 0x00) R/W Mode Register 0 <byte 6396> union bcra (Offset 0x07) R/W Bid Control, Address recognition <byte 6396> {field (By field)} <byte 6396> tbits:3 msb_ar_event_int_bid Bits 2:0 MSB of an address recognition event interr upt bid tbits:5 reserved Bits 7:3 Reserved {} or bcra (Offset 0x07) R/W Bid Control, Address recognition <byte 6396> utiny value As byte endunion bcra (Offset 0x07) R/W Bid Control, Address recognition <byte 6397> union bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff <byte 6397> {field (By field)} <byte 6397> tbits:3 msb_xon_xoff_int_bid Bits 2:0 MSB of an Xon/Xoff interrupt bid tbits:5 reserved Bits 7:3 Reserved {} or bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff <byte 6397> utiny value As byte endunion bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff <byte 6398> {rsvd1 ((Offset 0x05) NA Reserved)} <byte 6398> utiny value {} <byte 6399> union bcrcos (Offset 0x04) R/W Bid Control, Change of State <byte 6399> {field (By field)} <byte 6399>

tbits:3 msb_cos_int_bid Bits 2:0 MSB of a COS interrupt bid tbits:5 reserved Bits 7:3 Reserved {} or bcrcos (Offset 0x04) R/W Bid Control, Change of State <byte 6399> utiny value As byte endunion bcrcos (Offset 0x04) R/W Bid Control, Change of State <byte 6400> union icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only) <byte 6400> {field (By field)} <byte 6400> tbits:7 arbitration_threshold Bits 6:0 Upper seven bits of the Arbitration Thres hold tbits:1 reserved Bit 7 Reserved. Set to 0 {} or icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only) <byte 6400> utiny value As byte endunion icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only) <byte 6401> union arcr (Offset 0x0A) R/W Address Recognition Character <byte 6401> {field (By field)} <byte 6401> tbits:8 multidrop_ac_recognition Bits 7:0 8 Bits of the Multi-Drop Address Chara cter Recognition {} or arcr (Offset 0x0A) R/W Address Recognition Character <byte 6401> utiny value As byte endunion arcr (Offset 0x0A) R/W Address Recognition Character <byte 6402> union xoffcr (Offset 0x09) R/W Xoff Character Register <byte 6402> {field (By field)} <byte 6402> tbits:8 xoff_character_recognition Bits 7:0 8 Bits of the Xoff Character Recogni tion {} or xoffcr (Offset 0x09) R/W Xoff Character Register <byte 6402> utiny value As byte endunion xoffcr (Offset 0x09) R/W Xoff Character Register <byte 6403> union xoncr (Offset 0x08) R/W Xon Character Register <byte 6403> {field (By field)} <byte 6403> tbits:8 xon_character_recognition Bits 7:0 8 Bits of the Xon Character Recogniti on {} or xoncr (Offset 0x08) R/W Xon Character Register <byte 6403> utiny value As byte endunion xoncr (Offset 0x08) R/W Xon Character Register <byte 6404> union c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Off set 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6404>

union gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) <byte 6404> {field (By field)} <byte 6404> tbits:1 power_down_mode Bit 0 Power Down Mode tbits:2 int_vector_control Bit 2:1 Interrupt Vector Control tbits:3 reserved_5_3 Bit 5:3 Reserved tbits:1 sync_bus_cycles Bit 6 Sync bus cycles tbits:1 reserved_7 Bit 7 Reserved {} or gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) <byte 6404> utiny value As byte endunion gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) or c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6404> union ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6404> {field (By field)} <byte 6404> tbits:8 data_bits Bits 7:0 8 data bits of the Interrupt Vector {} or ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6404> utiny value As byte endunion ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) or c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6404> utiny value As byte endunion c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) ( Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6405> union txcsr (Offset 0x0E) R/W Transmitter Clock Select Register <byte 6405> {field (By field)} <byte 6405> tbits:5 tx_rx_clock_select_code Bits 4:0 Transmitter/Receiver Clock select code tbits:3 reserved Bits 7:5 Reserved {} or txcsr (Offset 0x0E) R/W Transmitter Clock Select Register <byte 6405> utiny value As byte endunion txcsr (Offset 0x0E) R/W Transmitter Clock Select Register <byte 6406> union c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-d og Timer Run Control (UARTB only) <byte 6406> {testreg ((Offset 0x0D) R/W Test Register (UARTA only))} <byte 6406> utiny value {} or c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) <byte 6406> union wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) <byte 6406> {field (By field)} <byte 6406>

tbits:1 wdt_a Bit 0 WDT a tbits:1 wdt_b Bit 1 WDT b tbits:1 wdt_c Bit 2 WDT c tbits:1 wdt_d Bit 3 WDT d tbits:4 reserved Bits 7:4 Reserved {} or wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) <byte 6406> utiny value As byte endunion wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) or c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) <byte 6406> utiny value As byte endunion c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watc h-dog Timer Run Control (UARTB only) <byte 6407> union rxcsr (Offset 0x0C) R/W Receiver Clock Select Register <byte 6407> {field (By field)} <byte 6407> tbits:5 tx_rx_clock_select_code Bits 4:0 Transmitter/Receiver Clock select code tbits:3 reserved Bits 7:5 Reserved {} or rxcsr (Offset 0x0C) R/W Receiver Clock Select Register <byte 6407> utiny value As byte endunion rxcsr (Offset 0x0C) R/W Receiver Clock Select Register {} <byte 6408> {quartcr[3] (SC28L194 Quad UART Control Registers a, b, c, d)} <byte 6408> union bcrbrk (Offset 0x03) R/W Bid Control, Break Change <byte 6408> {field (By field)} <byte 6408> tbits:3 msb_break_change_int_bid Bits 2:0 MSB of break change interrupt bid tbits:5 reserved Bits 7:3 Reserved {} or bcrbrk (Offset 0x03) R/W Bid Control, Break Change <byte 6408> utiny value As byte endunion bcrbrk (Offset 0x03) R/W Bid Control, Break Change <byte 6409> union iopcr (Offset 0x02) R/W I/O Port Configuration Register <byte 6409> {field (By field)} <byte 6409> tbits:2 io0_control Bits 1:0 I/O0 control tbits:2 io1_control Bits 3:2 I/O1 control tbits:2 io2_control Bits 5:4 I/O2 control tbits:2 io3_control Bits 7:6 I/O3 control {} or iopcr (Offset 0x02) R/W I/O Port Configuration Register <byte 6409> utiny value As byte endunion iopcr (Offset 0x02) R/W I/O Port Configuration Register <byte 6410> union mr1 (Offset 0x01) R/W Mode Register 1 <byte 6410>

{field (By field)} <byte 6410> tbits:2 bits_per_character Bit 1:0 Bits per Character tbits:1 parity_type Bit 2 Parity Type tbits:2 parity_mode Bit 4:3 Parity Mode tbits:1 error_mode Bit 5 Error Mode tbits:1 isr_read_mode Bit 6 ISR Read Mode tbits:1 rx_rts_control Bit 7 Receiver RTS Control {} or mr1 (Offset 0x01) R/W Mode Register 1 <byte 6410> utiny value As byte endunion mr1 (Offset 0x01) R/W Mode Register 1 <byte 6411> union mr0 (Offset 0x00) R/W Mode Register 0 <byte 6411> {field (By field)} <byte 6411> tbits:2 ar_control Bit 1:0 Address Recognition control tbits:2 inband_flow_control_mode Bit 3:2 In-band flow control mode tbits:2 txint Bit 5:4 Transmitter initiation of interrupt bidding condition tbits:1 ar_transparency Bit 6 Address Recognition transparency tbits:1 xon_xoff_transparency Bit 7 Xon/Xoff transparency {} or mr0 (Offset 0x00) R/W Mode Register 0 <byte 6411> utiny value As byte endunion mr0 (Offset 0x00) R/W Mode Register 0 <byte 6412> union bcra (Offset 0x07) R/W Bid Control, Address recognition <byte 6412> {field (By field)} <byte 6412> tbits:3 msb_ar_event_int_bid Bits 2:0 MSB of an address recognition event interr upt bid tbits:5 reserved Bits 7:3 Reserved {} or bcra (Offset 0x07) R/W Bid Control, Address recognition <byte 6412> utiny value As byte endunion bcra (Offset 0x07) R/W Bid Control, Address recognition <byte 6413> union bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff <byte 6413> {field (By field)} <byte 6413> tbits:3 msb_xon_xoff_int_bid Bits 2:0 MSB of an Xon/Xoff interrupt bid tbits:5 reserved Bits 7:3 Reserved {} or bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff <byte 6413> utiny value As byte endunion bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff <byte 6414> {rsvd1 ((Offset 0x05) NA Reserved)} <byte 6414> utiny value {} <byte 6415> union bcrcos (Offset 0x04) R/W Bid Control, Change of State

<byte 6415> {field (By field)} <byte 6415> tbits:3 msb_cos_int_bid Bits 2:0 MSB of a COS interrupt bid tbits:5 reserved Bits 7:3 Reserved {} or bcrcos (Offset 0x04) R/W Bid Control, Change of State <byte 6415> utiny value As byte endunion bcrcos (Offset 0x04) R/W Bid Control, Change of State <byte 6416> union icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only) <byte 6416> {field (By field)} <byte 6416> tbits:7 arbitration_threshold Bits 6:0 Upper seven bits of the Arbitration Thres hold tbits:1 reserved Bit 7 Reserved. Set to 0 {} or icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only) <byte 6416> utiny value As byte endunion icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only) <byte 6417> union arcr (Offset 0x0A) R/W Address Recognition Character <byte 6417> {field (By field)} <byte 6417> tbits:8 multidrop_ac_recognition Bits 7:0 8 Bits of the Multi-Drop Address Chara cter Recognition {} or arcr (Offset 0x0A) R/W Address Recognition Character <byte 6417> utiny value As byte endunion arcr (Offset 0x0A) R/W Address Recognition Character <byte 6418> union xoffcr (Offset 0x09) R/W Xoff Character Register <byte 6418> {field (By field)} <byte 6418> tbits:8 xoff_character_recognition Bits 7:0 8 Bits of the Xoff Character Recogni tion {} or xoffcr (Offset 0x09) R/W Xoff Character Register <byte 6418> utiny value As byte endunion xoffcr (Offset 0x09) R/W Xoff Character Register <byte 6419> union xoncr (Offset 0x08) R/W Xon Character Register <byte 6419> {field (By field)} <byte 6419> tbits:8 xon_character_recognition Bits 7:0 8 Bits of the Xon Character Recogniti on {} or xoncr (Offset 0x08) R/W Xon Character Register <byte 6419> utiny value As byte endunion xoncr (Offset 0x08) R/W Xon Character Register <byte 6420>

union c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Off set 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6420> union gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) <byte 6420> {field (By field)} <byte 6420> tbits:1 power_down_mode Bit 0 Power Down Mode tbits:2 int_vector_control Bit 2:1 Interrupt Vector Control tbits:3 reserved_5_3 Bit 5:3 Reserved tbits:1 sync_bus_cycles Bit 6 Sync bus cycles tbits:1 reserved_7 Bit 7 Reserved {} or gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) <byte 6420> utiny value As byte endunion gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) or c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6420> union ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6420> {field (By field)} <byte 6420> tbits:8 data_bits Bits 7:0 8 data bits of the Interrupt Vector {} or ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6420> utiny value As byte endunion ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) or c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6420> utiny value As byte endunion c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) ( Offset 0x0F) R/W Interrupt Vector Register (UARTB only) <byte 6421> union txcsr (Offset 0x0E) R/W Transmitter Clock Select Register <byte 6421> {field (By field)} <byte 6421> tbits:5 tx_rx_clock_select_code Bits 4:0 Transmitter/Receiver Clock select code tbits:3 reserved Bits 7:5 Reserved {} or txcsr (Offset 0x0E) R/W Transmitter Clock Select Register <byte 6421> utiny value As byte endunion txcsr (Offset 0x0E) R/W Transmitter Clock Select Register <byte 6422> union c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-d og Timer Run Control (UARTB only) <byte 6422> {testreg ((Offset 0x0D) R/W Test Register (UARTA only))} <byte 6422> utiny value {} or c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) <byte 6422> union wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only)

<byte 6422> {field (By field)} <byte 6422> tbits:1 wdt_a Bit 0 WDT a tbits:1 wdt_b Bit 1 WDT b tbits:1 wdt_c Bit 2 WDT c tbits:1 wdt_d Bit 3 WDT d tbits:4 reserved Bits 7:4 Reserved {} or wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) <byte 6422> utiny value As byte endunion wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) or c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only) <byte 6422> utiny value As byte endunion c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watc h-dog Timer Run Control (UARTB only) <byte 6423> union rxcsr (Offset 0x0C) R/W Receiver Clock Select Register <byte 6423> {field (By field)} <byte 6423> tbits:5 tx_rx_clock_select_code Bits 4:0 Transmitter/Receiver Clock select code tbits:3 reserved Bits 7:5 Reserved {} or rxcsr (Offset 0x0C) R/W Receiver Clock Select Register <byte 6423> utiny value As byte endunion rxcsr (Offset 0x0C) R/W Receiver Clock Select Register {} <byte 6424> {quartdr[0] (SC28L194 Quad UART Data Registers a, b, c, d)} <byte 6424> union d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register <byte 6424> union rxfifo (Offset 0x83) R Receiver FIFO Register <byte 6424> {field (By field)} <byte 6424> tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or rxfifo (Offset 0x83) R Receiver FIFO Register <byte 6424> utiny value As byte endunion rxfifo (Offset 0x83) R Receiver FIFO Register or d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FI FO Register <byte 6424> union txfifo (Offset 0x83) W Transmitter FIFO Register <byte 6424> {field (By field)} <byte 6424> tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or txfifo (Offset 0x83) W Transmitter FIFO Register <byte 6424> utiny value As byte

endunion txfifo (Offset 0x83) W Transmitter FIFO Register or d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FI FO Register <byte 6424> utiny value As byte endunion d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmit ter FIFO Register <byte 6425> union d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrup t Mask Register <byte 6425> union isr (Offset 0x82) R Interrupt Status Register <byte 6425> {field (By field)} <byte 6425> tbits:1 txrdy Bit 0 Transmitter has entered arbitration process tbits:1 rxrdy Bit 1 Receiver has entered arbitration process tbits:1 change_break_state Bit 2 Change of Break State tbits:1 reserved Bit 3 Reserved tbits:1 xon_off_event Bit 4 Xon/off event tbits:1 ar_event Bit 5 Address recognition event tbits:1 rx_watch_dog_time_out Bit 6 Receiver Watch-dog Time-out tbits:1 io_port_change_state Bit 7 I/O Port change of state {} or isr (Offset 0x82) R Interrupt Status Register <byte 6425> utiny value As byte endunion isr (Offset 0x82) R Interrupt Status Register or d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt M ask Register <byte 6425> union imr (Offset 0x82) W Interrupt Mask Register <byte 6425> {field (By field)} <byte 6425> tbits:1 txrdy_int_enable Bit 0 TxRDY interrupt enable tbits:1 rxrdy_int_enable Bit 1 RxRDY interrupt enable tbits:1 change_break_state_int_enable Bit 2 Change of Break State interrupt enab le tbits:1 reserved Bit 3 Reserved tbits:1 xon_off_event_int_enable Bit 4 Xon/off event interrupt enable tbits:1 ar_event_int_enable Bit 5 Address recognition event interrupt enable tbits:1 rx_watch_dog_time_out_int_enable Bit 6 Receiver Watch-dog Time-out inter rupt enable tbits:1 io_port_change_state_int_enable Bit 7 I/O Port change of state interrupt ed enable {} or imr (Offset 0x82) W Interrupt Mask Register <byte 6425> utiny value As byte endunion imr (Offset 0x82) W Interrupt Mask Register or d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt M ask Register <byte 6425> utiny value As byte endunion d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Inter rupt Mask Register <byte 6426> union d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Re gister

<byte 6426> union sr (Offset 0x81) R Channel Status Register <byte 6426> {field (By field)} <byte 6426> tbits:1 rx_ready Bit 0 Receiver Ready tbits:1 rx_fifo_full Bit 1 Receiver FIFO Full tbits:1 tx_ready Bit 2 Transmitter Ready tbits:1 tx_empty Bit 3 Transmitter Empty tbits:1 overrun_error Bit 4 Overrun Error tbits:1 parity_error Bit 5 Parity Error tbits:1 framing_error Bit 6 Framing Error tbits:1 received_break Bit 7 Received Break {} or sr (Offset 0x81) R Channel Status Register <byte 6426> utiny value As byte endunion sr (Offset 0x81) R Channel Status Register or d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Regis ter <byte 6426> union cr (Offset 0x81) W Command Register <byte 6426> {field (By field)} <byte 6426> tbits:1 rx_enable_disable Bit 0 Receiver Enable/Disable tbits:1 tx_enable_disable Bit 1 Transmitter Enable/Disable tbits:1 lock_txd_rxfifo_enables Bit 2 Hold present condition of Transmitter & Re ceiver enables/Change Transmitter & Receiver enable conditions tbits:5 channel_command Bits 7:3 Channel Command {} or cr (Offset 0x81) W Command Register <byte 6426> utiny value As byte endunion cr (Offset 0x81) W Command Register or d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Regis ter <byte 6426> utiny value As byte endunion d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register <byte 6427> union mr2 (Offset 0x80) R/W Mode Register 2 <byte 6427> {field (By field)} <byte 6427> tbits:2 stop_length Bit 1:0 Stop Length tbits:2 txint Bit 3:2 Receiver initiation of interrupt bidding condition tbits:1 ctsn_enable_tx Bit 4 CTSN Enable Transmitter tbits:1 tx_rts_control Bit 5 Transmitter RTS Control tbits:2 channel_mode Bits 7:6 Channel Mode {} or mr2 (Offset 0x80) R/W Mode Register 2 <byte 6427> utiny value As byte endunion mr2 (Offset 0x80) R/W Mode Register 2 <byte 6428> union d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6428>

union gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only ) <byte 6428> {field (By field)} <byte 6428> tbits:4 ggpo_0_selection Bits 3:0 Global General Purpose Output 0 Selection tbits:4 ggpo_1_selection Bits 7:4 Global General Purpose Output 1 Selection {} or gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) <byte 6428> utiny value As byte endunion gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA o nly) or d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Of fset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6428> union gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6428> {field (By field)} <byte 6428> tbits:1 gpor_0 Bit 0 GPOR(0) tbits:1 gpor_1 Bit 1 GPOR(1) tbits:1 gpor_2 Bit 2 GPOR(2) tbits:1 gpor_3 Bit 3 GPOR(3) tbits:4 reserved Bits 7:4 Reserved {} or gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6428> utiny value As byte endunion gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only) or d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Of fset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6428> utiny value As byte endunion d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA onl y) (Offset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6429> union xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register <byte 6429> {field (By field)} <byte 6429> tbits:2 txd_character_status Bits 1:0 TxD character status tbits:2 txd_flow_status Bits 3:2 TxD flow status tbits:2 auto_x_character_xmission_status Bits 5:4 Automatic Character transmissi on status tbits:2 received_x_character_status Bits 7:6 Received X Character Status {} or xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register <byte 6429> utiny value As byte endunion xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register <byte 6430> union iopior (Offset 0x85) R/W I/O Port Interrupt and Output <byte 6430> {field (By field)} <byte 6430> tbits:1 io0_output Bit 0 I/O0 output tbits:1 io1_output Bit 1 I/O1 output tbits:1 io2_output Bit 2 I/O2 output tbits:1 io3_output Bit 3 I/O3 output

tbits:1 io0_enable Bit 4 I/O0 enable tbits:1 io1_enable Bit 5 I/O1 enable tbits:1 io2_enable Bit 6 I/O2 enable tbits:1 io3_enable Bit 7 I/O3 enable {} or iopior (Offset 0x85) R/W I/O Port Interrupt and Output <byte 6430> utiny value As byte endunion iopior (Offset 0x85) R/W I/O Port Interrupt and Output <byte 6431> union d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Gene rator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) <byte 6431> union ipr (Offset 0x84) R Input Port Register <byte 6431> {field (By field)} <byte 6431> tbits:1 io0_state Bit 0 I/O0 state tbits:1 io1_state Bit 1 I/O1 state tbits:1 io2_state Bit 2 I/O2 state tbits:1 io3_state Bit 3 I/O3 state tbits:1 io0_change Bit 4 I/O0 change tbits:1 io1_change Bit 5 I/O1 change tbits:1 io2_change Bit 6 I/O2 change tbits:1 io3_change Bit 7 I/O3 change {} or ipr (Offset 0x84) R Input Port Register <byte 6431> utiny value As byte endunion ipr (Offset 0x84) R Input Port Register or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generat or Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Tim er Register Lower a (UARTB only) <byte 6431> union brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UART A only) <byte 6431> {field (By field)} <byte 6431> tbits:8 msb_brg_timer_divisor Bits 7:0 8 MSB of the Baud Rate Generator Timer di visor {} or brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA o nly) <byte 6431> utiny value As byte endunion brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (U ARTA only) or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generat or Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Tim er Register Lower a (UARTB only) <byte 6431> union brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UART B only) <byte 6431> {field (By field)} <byte 6431> tbits:8 lsb_brg_timer_divisor Bits 7:0 8 LSB of the Baud Rate Generator Timer di visor

{} or brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB o nly) <byte 6431> utiny value As byte endunion brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (U ARTB only) or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generat or Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Tim er Register Lower a (UARTB only) <byte 6431> utiny value As byte endunion d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate G enerator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generat or Timer Register Lower a (UARTB only) <byte 6432> union d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) ( Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6432> union gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) <byte 6432> {field (By field)} <byte 6432> tbits:2 clock_selection_gpor_0 Bits 1:0 Clock Selection GPOR(0) tbits:2 clock_selection_gpor_1 Bits 3:2 Clock Selection GPOR(1) tbits:2 clock_selection_gpor_2 Bits 5:4 Clock Selection GPOR(2) tbits:2 clock_selection_gpor_3 Bits 7:6 Clock Selection GPOR(3) {} or gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) <byte 6432> utiny value As byte endunion gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA onl y) or d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Off set 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6432> union gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6432> {field (By field)} <byte 6432> tbits:2 data_selection_gpor_0 Bits 1:0 Data Selection GPOR(0) tbits:2 data_selection_gpor_1 Bits 3:2 Data Selection GPOR(1) tbits:2 data_selection_gpor_2 Bits 5:4 Data Selection GPOR(2) tbits:2 data_selection_gpor_3 Bits 7:6 Data Selection GPOR(3) {} or gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6432> utiny value As byte endunion gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only ) or d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Off set 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6432> utiny value As byte endunion d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only ) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6433> {rsvd3 ((Offset 0x8A) NA Reserved)} <byte 6433> utiny value

{} <byte 6434> {rsvd2 ((Offset 0x89) NA Reserved)} <byte 6434> utiny value {} <byte 6435> {rsvd1 ((Offset 0x88) NA Reserved)} <byte 6435> utiny value {} <byte 6436> union d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Off set 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6436> union gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) <byte 6436> {field (By field)} <byte 6436> tbits:1 power_down_mode Bit 0 Power Down Mode tbits:2 int_vector_control Bit 2:1 Interrupt Vector Control tbits:3 reserved_5_3 Bit 5:3 Reserved tbits:1 sync_bus_cycles Bit 6 Sync bus cycles tbits:1 reserved_7 Bit 7 Reserved {} or gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) <byte 6436> utiny value As byte endunion gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) or d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6436> union gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6436> {field (By field)} <byte 6436> tbits:3 other_types Bit 2:0 Other types tbits:2 reserved Bit 4:3 Reserved tbits:1 tx_interrupt Bit 5 Transmitter Interrupt tbits:2 rx_interrupt Bit 7:6 Receiver Interrupt {} or gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6436> utiny value As byte endunion gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only) or d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6436> utiny value As byte endunion d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) ( Offset 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6437> union d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x 8E) W Global Transmit FIFO Register (UARTA only) <byte 6437> union grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only) <byte 6437> {field (By field)} <byte 6437> tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data

{} or grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only) <byte 6437> utiny value As byte endunion grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only) or d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6437> union gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6437> {field (By field)} <byte 6437> tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6437> utiny value As byte endunion gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) or d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6437> utiny value As byte endunion d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6438> union d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8 D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) <byte 6438> union gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) <byte 6438> {field (By field)} <byte 6438> tbits:4 channel_byte_count_code Bits 3:0 Channel byte count code tbits:4 reserved Bits 7:4 Reserved {} or gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) <byte 6438> utiny value As byte endunion gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Ba ud Rate Generator Timer Register Lower b (UARTB only) <byte 6438> union brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UART A only) <byte 6438> {field (By field)} <byte 6438> tbits:8 msb_brg_timer_divisor Bits 7:0 8 MSB of the Baud Rate Generator Timer di visor {} or brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA o nly) <byte 6438> utiny value As byte endunion brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (U ARTA only) or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Ba

ud Rate Generator Timer Register Lower b (UARTB only) <byte 6438> union brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UART B only) <byte 6438> {field (By field)} <byte 6438> tbits:8 lsb_brg_timer_divisor Bits 7:0 8 LSB of the Baud Rate Generator Timer di visor {} or brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB o nly) <byte 6438> utiny value As byte endunion brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (U ARTB only) or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Ba ud Rate Generator Timer Register Lower b (UARTB only) <byte 6438> utiny value As byte endunion d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) <byte 6439> union d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C ) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Cu rrent Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Time r Control Register (UARTB only) <byte 6439> union cir (Offset 0x8C) R Current Interrupt Register (UARTA only) <byte 6439> {field (By field)} <byte 6439> tbits:3 channel_number Bits 2:0 Channel number tbits:3 current_byte_count_type Bits 5:3 Current byte count/type tbits:2 type Bits 7:6 Type {} or cir (Offset 0x8C) R Current Interrupt Register (UARTA only) <byte 6439> utiny value As byte endunion cir (Offset 0x8C) R Current Interrupt Register (UARTA only) or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Curre nt Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer C ontrol Register (UARTB only) <byte 6439> union gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) <byte 6439> {field (By field)} <byte 6439> tbits:3 channel_code Bits 2:0 Channel code tbits:5 reserved Bits 7:3 Reserved {} or gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) <byte 6439> utiny value As byte endunion gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Curre

nt Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer C ontrol Register (UARTB only) <byte 6439> {ucir ((Offset 0x8C) W Update Current Interrupt Register (UARTA only))} <byte 6439> utiny value {} or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Curre nt Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer C ontrol Register (UARTB only) <byte 6439> union brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) <byte 6439> {field (By field)} <byte 6439> tbits:3 brgtcr_a_clock_selection Bit 2:0 BRGTCR a, Clock selection tbits:1 brgtcr_a_register_control Bit 3 BRGTCR a, Register control tbits:3 brgtcr_b_clock_selection Bit 6:4 BRGTCR b, Clock selection tbits:1 brgtcr_b_register_control Bit 7 BRGTCR b, Register control {} or brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB on ly) <byte 6439> utiny value As byte endunion brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UA RTB only) or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Curre nt Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer C ontrol Register (UARTB only) <byte 6439> utiny value As byte endunion d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0 x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator T imer Control Register (UARTB only) {} <byte 6440> {quartdr[1] (SC28L194 Quad UART Data Registers a, b, c, d)} <byte 6440> union d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register <byte 6440> union rxfifo (Offset 0x83) R Receiver FIFO Register <byte 6440> {field (By field)} <byte 6440> tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or rxfifo (Offset 0x83) R Receiver FIFO Register <byte 6440> utiny value As byte endunion rxfifo (Offset 0x83) R Receiver FIFO Register or d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FI FO Register <byte 6440> union txfifo (Offset 0x83) W Transmitter FIFO Register <byte 6440>

{field (By field)} <byte 6440> tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or txfifo (Offset 0x83) W Transmitter FIFO Register <byte 6440> utiny value As byte endunion txfifo (Offset 0x83) W Transmitter FIFO Register or d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FI FO Register <byte 6440> utiny value As byte endunion d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmit ter FIFO Register <byte 6441> union d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrup t Mask Register <byte 6441> union isr (Offset 0x82) R Interrupt Status Register <byte 6441> {field (By field)} <byte 6441> tbits:1 txrdy Bit 0 Transmitter has entered arbitration process tbits:1 rxrdy Bit 1 Receiver has entered arbitration process tbits:1 change_break_state Bit 2 Change of Break State tbits:1 reserved Bit 3 Reserved tbits:1 xon_off_event Bit 4 Xon/off event tbits:1 ar_event Bit 5 Address recognition event tbits:1 rx_watch_dog_time_out Bit 6 Receiver Watch-dog Time-out tbits:1 io_port_change_state Bit 7 I/O Port change of state {} or isr (Offset 0x82) R Interrupt Status Register <byte 6441> utiny value As byte endunion isr (Offset 0x82) R Interrupt Status Register or d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt M ask Register <byte 6441> union imr (Offset 0x82) W Interrupt Mask Register <byte 6441> {field (By field)} <byte 6441> tbits:1 txrdy_int_enable Bit 0 TxRDY interrupt enable tbits:1 rxrdy_int_enable Bit 1 RxRDY interrupt enable tbits:1 change_break_state_int_enable Bit 2 Change of Break State interrupt enab le tbits:1 reserved Bit 3 Reserved tbits:1 xon_off_event_int_enable Bit 4 Xon/off event interrupt enable tbits:1 ar_event_int_enable Bit 5 Address recognition event interrupt enable tbits:1 rx_watch_dog_time_out_int_enable Bit 6 Receiver Watch-dog Time-out inter rupt enable tbits:1 io_port_change_state_int_enable Bit 7 I/O Port change of state interrupt ed enable {} or imr (Offset 0x82) W Interrupt Mask Register <byte 6441> utiny value As byte endunion imr (Offset 0x82) W Interrupt Mask Register or d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt M ask Register

<byte 6441> utiny value As byte endunion d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Inter rupt Mask Register <byte 6442> union d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Re gister <byte 6442> union sr (Offset 0x81) R Channel Status Register <byte 6442> {field (By field)} <byte 6442> tbits:1 rx_ready Bit 0 Receiver Ready tbits:1 rx_fifo_full Bit 1 Receiver FIFO Full tbits:1 tx_ready Bit 2 Transmitter Ready tbits:1 tx_empty Bit 3 Transmitter Empty tbits:1 overrun_error Bit 4 Overrun Error tbits:1 parity_error Bit 5 Parity Error tbits:1 framing_error Bit 6 Framing Error tbits:1 received_break Bit 7 Received Break {} or sr (Offset 0x81) R Channel Status Register <byte 6442> utiny value As byte endunion sr (Offset 0x81) R Channel Status Register or d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Regis ter <byte 6442> union cr (Offset 0x81) W Command Register <byte 6442> {field (By field)} <byte 6442> tbits:1 rx_enable_disable Bit 0 Receiver Enable/Disable tbits:1 tx_enable_disable Bit 1 Transmitter Enable/Disable tbits:1 lock_txd_rxfifo_enables Bit 2 Hold present condition of Transmitter & Re ceiver enables/Change Transmitter & Receiver enable conditions tbits:5 channel_command Bits 7:3 Channel Command {} or cr (Offset 0x81) W Command Register <byte 6442> utiny value As byte endunion cr (Offset 0x81) W Command Register or d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Regis ter <byte 6442> utiny value As byte endunion d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register <byte 6443> union mr2 (Offset 0x80) R/W Mode Register 2 <byte 6443> {field (By field)} <byte 6443> tbits:2 stop_length Bit 1:0 Stop Length tbits:2 txint Bit 3:2 Receiver initiation of interrupt bidding condition tbits:1 ctsn_enable_tx Bit 4 CTSN Enable Transmitter tbits:1 tx_rts_control Bit 5 Transmitter RTS Control tbits:2 channel_mode Bits 7:6 Channel Mode {} or mr2 (Offset 0x80) R/W Mode Register 2

<byte 6443> utiny value As byte endunion mr2 (Offset 0x80) R/W Mode Register 2 <byte 6444> union d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6444> union gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only ) <byte 6444> {field (By field)} <byte 6444> tbits:4 ggpo_0_selection Bits 3:0 Global General Purpose Output 0 Selection tbits:4 ggpo_1_selection Bits 7:4 Global General Purpose Output 1 Selection {} or gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) <byte 6444> utiny value As byte endunion gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA o nly) or d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Of fset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6444> union gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6444> {field (By field)} <byte 6444> tbits:1 gpor_0 Bit 0 GPOR(0) tbits:1 gpor_1 Bit 1 GPOR(1) tbits:1 gpor_2 Bit 2 GPOR(2) tbits:1 gpor_3 Bit 3 GPOR(3) tbits:4 reserved Bits 7:4 Reserved {} or gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6444> utiny value As byte endunion gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only) or d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Of fset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6444> utiny value As byte endunion d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA onl y) (Offset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6445> union xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register <byte 6445> {field (By field)} <byte 6445> tbits:2 txd_character_status Bits 1:0 TxD character status tbits:2 txd_flow_status Bits 3:2 TxD flow status tbits:2 auto_x_character_xmission_status Bits 5:4 Automatic Character transmissi on status tbits:2 received_x_character_status Bits 7:6 Received X Character Status {} or xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register <byte 6445> utiny value As byte endunion xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register <byte 6446> union iopior (Offset 0x85) R/W I/O Port Interrupt and Output

<byte 6446> {field (By field)} <byte 6446> tbits:1 io0_output Bit 0 I/O0 output tbits:1 io1_output Bit 1 I/O1 output tbits:1 io2_output Bit 2 I/O2 output tbits:1 io3_output Bit 3 I/O3 output tbits:1 io0_enable Bit 4 I/O0 enable tbits:1 io1_enable Bit 5 I/O1 enable tbits:1 io2_enable Bit 6 I/O2 enable tbits:1 io3_enable Bit 7 I/O3 enable {} or iopior (Offset 0x85) R/W I/O Port Interrupt and Output <byte 6446> utiny value As byte endunion iopior (Offset 0x85) R/W I/O Port Interrupt and Output <byte 6447> union d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Gene rator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) <byte 6447> union ipr (Offset 0x84) R Input Port Register <byte 6447> {field (By field)} <byte 6447> tbits:1 io0_state Bit 0 I/O0 state tbits:1 io1_state Bit 1 I/O1 state tbits:1 io2_state Bit 2 I/O2 state tbits:1 io3_state Bit 3 I/O3 state tbits:1 io0_change Bit 4 I/O0 change tbits:1 io1_change Bit 5 I/O1 change tbits:1 io2_change Bit 6 I/O2 change tbits:1 io3_change Bit 7 I/O3 change {} or ipr (Offset 0x84) R Input Port Register <byte 6447> utiny value As byte endunion ipr (Offset 0x84) R Input Port Register or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generat or Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Tim er Register Lower a (UARTB only) <byte 6447> union brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UART A only) <byte 6447> {field (By field)} <byte 6447> tbits:8 msb_brg_timer_divisor Bits 7:0 8 MSB of the Baud Rate Generator Timer di visor {} or brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA o nly) <byte 6447> utiny value As byte endunion brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (U ARTA only) or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generat or Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Tim er Register Lower a (UARTB only) <byte 6447>

union brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UART B only) <byte 6447> {field (By field)} <byte 6447> tbits:8 lsb_brg_timer_divisor Bits 7:0 8 LSB of the Baud Rate Generator Timer di visor {} or brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB o nly) <byte 6447> utiny value As byte endunion brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (U ARTB only) or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generat or Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Tim er Register Lower a (UARTB only) <byte 6447> utiny value As byte endunion d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate G enerator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generat or Timer Register Lower a (UARTB only) <byte 6448> union d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) ( Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6448> union gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) <byte 6448> {field (By field)} <byte 6448> tbits:2 clock_selection_gpor_0 Bits 1:0 Clock Selection GPOR(0) tbits:2 clock_selection_gpor_1 Bits 3:2 Clock Selection GPOR(1) tbits:2 clock_selection_gpor_2 Bits 5:4 Clock Selection GPOR(2) tbits:2 clock_selection_gpor_3 Bits 7:6 Clock Selection GPOR(3) {} or gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) <byte 6448> utiny value As byte endunion gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA onl y) or d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Off set 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6448> union gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6448> {field (By field)} <byte 6448> tbits:2 data_selection_gpor_0 Bits 1:0 Data Selection GPOR(0) tbits:2 data_selection_gpor_1 Bits 3:2 Data Selection GPOR(1) tbits:2 data_selection_gpor_2 Bits 5:4 Data Selection GPOR(2) tbits:2 data_selection_gpor_3 Bits 7:6 Data Selection GPOR(3) {} or gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6448> utiny value As byte endunion gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only ) or d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Off set 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6448>

utiny value As byte endunion d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only ) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6449> {rsvd3 ((Offset 0x8A) NA Reserved)} <byte 6449> utiny value {} <byte 6450> {rsvd2 ((Offset 0x89) NA Reserved)} <byte 6450> utiny value {} <byte 6451> {rsvd1 ((Offset 0x88) NA Reserved)} <byte 6451> utiny value {} <byte 6452> union d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Off set 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6452> union gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) <byte 6452> {field (By field)} <byte 6452> tbits:1 power_down_mode Bit 0 Power Down Mode tbits:2 int_vector_control Bit 2:1 Interrupt Vector Control tbits:3 reserved_5_3 Bit 5:3 Reserved tbits:1 sync_bus_cycles Bit 6 Sync bus cycles tbits:1 reserved_7 Bit 7 Reserved {} or gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) <byte 6452> utiny value As byte endunion gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) or d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6452> union gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6452> {field (By field)} <byte 6452> tbits:3 other_types Bit 2:0 Other types tbits:2 reserved Bit 4:3 Reserved tbits:1 tx_interrupt Bit 5 Transmitter Interrupt tbits:2 rx_interrupt Bit 7:6 Receiver Interrupt {} or gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6452> utiny value As byte endunion gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only) or d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6452> utiny value As byte endunion d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) ( Offset 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6453> union d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x

8E) W Global Transmit FIFO Register (UARTA only) <byte 6453> union grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only) <byte 6453> {field (By field)} <byte 6453> tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only) <byte 6453> utiny value As byte endunion grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only) or d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6453> union gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6453> {field (By field)} <byte 6453> tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6453> utiny value As byte endunion gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) or d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6453> utiny value As byte endunion d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6454> union d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8 D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) <byte 6454> union gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) <byte 6454> {field (By field)} <byte 6454> tbits:4 channel_byte_count_code Bits 3:0 Channel byte count code tbits:4 reserved Bits 7:4 Reserved {} or gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) <byte 6454> utiny value As byte endunion gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Ba ud Rate Generator Timer Register Lower b (UARTB only) <byte 6454> union brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UART A only) <byte 6454> {field (By field)} <byte 6454> tbits:8 msb_brg_timer_divisor Bits 7:0 8 MSB of the Baud Rate Generator Timer di visor {} or brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA o

nly) <byte 6454> utiny value As byte endunion brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (U ARTA only) or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Ba ud Rate Generator Timer Register Lower b (UARTB only) <byte 6454> union brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UART B only) <byte 6454> {field (By field)} <byte 6454> tbits:8 lsb_brg_timer_divisor Bits 7:0 8 LSB of the Baud Rate Generator Timer di visor {} or brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB o nly) <byte 6454> utiny value As byte endunion brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (U ARTB only) or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Ba ud Rate Generator Timer Register Lower b (UARTB only) <byte 6454> utiny value As byte endunion d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) <byte 6455> union d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C ) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Cu rrent Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Time r Control Register (UARTB only) <byte 6455> union cir (Offset 0x8C) R Current Interrupt Register (UARTA only) <byte 6455> {field (By field)} <byte 6455> tbits:3 channel_number Bits 2:0 Channel number tbits:3 current_byte_count_type Bits 5:3 Current byte count/type tbits:2 type Bits 7:6 Type {} or cir (Offset 0x8C) R Current Interrupt Register (UARTA only) <byte 6455> utiny value As byte endunion cir (Offset 0x8C) R Current Interrupt Register (UARTA only) or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Curre nt Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer C ontrol Register (UARTB only) <byte 6455> union gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) <byte 6455> {field (By field)} <byte 6455> tbits:3 channel_code Bits 2:0 Channel code tbits:5 reserved Bits 7:3 Reserved

{} or gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) <byte 6455> utiny value As byte endunion gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Curre nt Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer C ontrol Register (UARTB only) <byte 6455> {ucir ((Offset 0x8C) W Update Current Interrupt Register (UARTA only))} <byte 6455> utiny value {} or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Curre nt Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer C ontrol Register (UARTB only) <byte 6455> union brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) <byte 6455> {field (By field)} <byte 6455> tbits:3 brgtcr_a_clock_selection Bit 2:0 BRGTCR a, Clock selection tbits:1 brgtcr_a_register_control Bit 3 BRGTCR a, Register control tbits:3 brgtcr_b_clock_selection Bit 6:4 BRGTCR b, Clock selection tbits:1 brgtcr_b_register_control Bit 7 BRGTCR b, Register control {} or brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB on ly) <byte 6455> utiny value As byte endunion brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UA RTB only) or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Curre nt Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer C ontrol Register (UARTB only) <byte 6455> utiny value As byte endunion d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0 x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator T imer Control Register (UARTB only) {} <byte 6456> {quartdr[2] (SC28L194 Quad UART Data Registers a, b, c, d)} <byte 6456> union d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register <byte 6456> union rxfifo (Offset 0x83) R Receiver FIFO Register <byte 6456> {field (By field)} <byte 6456> tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or rxfifo (Offset 0x83) R Receiver FIFO Register <byte 6456>

utiny value As byte endunion rxfifo (Offset 0x83) R Receiver FIFO Register or d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FI FO Register <byte 6456> union txfifo (Offset 0x83) W Transmitter FIFO Register <byte 6456> {field (By field)} <byte 6456> tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or txfifo (Offset 0x83) W Transmitter FIFO Register <byte 6456> utiny value As byte endunion txfifo (Offset 0x83) W Transmitter FIFO Register or d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FI FO Register <byte 6456> utiny value As byte endunion d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmit ter FIFO Register <byte 6457> union d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrup t Mask Register <byte 6457> union isr (Offset 0x82) R Interrupt Status Register <byte 6457> {field (By field)} <byte 6457> tbits:1 txrdy Bit 0 Transmitter has entered arbitration process tbits:1 rxrdy Bit 1 Receiver has entered arbitration process tbits:1 change_break_state Bit 2 Change of Break State tbits:1 reserved Bit 3 Reserved tbits:1 xon_off_event Bit 4 Xon/off event tbits:1 ar_event Bit 5 Address recognition event tbits:1 rx_watch_dog_time_out Bit 6 Receiver Watch-dog Time-out tbits:1 io_port_change_state Bit 7 I/O Port change of state {} or isr (Offset 0x82) R Interrupt Status Register <byte 6457> utiny value As byte endunion isr (Offset 0x82) R Interrupt Status Register or d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt M ask Register <byte 6457> union imr (Offset 0x82) W Interrupt Mask Register <byte 6457> {field (By field)} <byte 6457> tbits:1 txrdy_int_enable Bit 0 TxRDY interrupt enable tbits:1 rxrdy_int_enable Bit 1 RxRDY interrupt enable tbits:1 change_break_state_int_enable Bit 2 Change of Break State interrupt enab le tbits:1 reserved Bit 3 Reserved tbits:1 xon_off_event_int_enable Bit 4 Xon/off event interrupt enable tbits:1 ar_event_int_enable Bit 5 Address recognition event interrupt enable tbits:1 rx_watch_dog_time_out_int_enable Bit 6 Receiver Watch-dog Time-out inter rupt enable tbits:1 io_port_change_state_int_enable Bit 7 I/O Port change of state interrupt ed enable

{} or imr (Offset 0x82) W Interrupt Mask Register <byte 6457> utiny value As byte endunion imr (Offset 0x82) W Interrupt Mask Register or d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt M ask Register <byte 6457> utiny value As byte endunion d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Inter rupt Mask Register <byte 6458> union d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Re gister <byte 6458> union sr (Offset 0x81) R Channel Status Register <byte 6458> {field (By field)} <byte 6458> tbits:1 rx_ready Bit 0 Receiver Ready tbits:1 rx_fifo_full Bit 1 Receiver FIFO Full tbits:1 tx_ready Bit 2 Transmitter Ready tbits:1 tx_empty Bit 3 Transmitter Empty tbits:1 overrun_error Bit 4 Overrun Error tbits:1 parity_error Bit 5 Parity Error tbits:1 framing_error Bit 6 Framing Error tbits:1 received_break Bit 7 Received Break {} or sr (Offset 0x81) R Channel Status Register <byte 6458> utiny value As byte endunion sr (Offset 0x81) R Channel Status Register or d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Regis ter <byte 6458> union cr (Offset 0x81) W Command Register <byte 6458> {field (By field)} <byte 6458> tbits:1 rx_enable_disable Bit 0 Receiver Enable/Disable tbits:1 tx_enable_disable Bit 1 Transmitter Enable/Disable tbits:1 lock_txd_rxfifo_enables Bit 2 Hold present condition of Transmitter & Re ceiver enables/Change Transmitter & Receiver enable conditions tbits:5 channel_command Bits 7:3 Channel Command {} or cr (Offset 0x81) W Command Register <byte 6458> utiny value As byte endunion cr (Offset 0x81) W Command Register or d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Regis ter <byte 6458> utiny value As byte endunion d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register <byte 6459> union mr2 (Offset 0x80) R/W Mode Register 2 <byte 6459> {field (By field)} <byte 6459>

tbits:2 stop_length Bit 1:0 Stop Length tbits:2 txint Bit 3:2 Receiver initiation of interrupt bidding condition tbits:1 ctsn_enable_tx Bit 4 CTSN Enable Transmitter tbits:1 tx_rts_control Bit 5 Transmitter RTS Control tbits:2 channel_mode Bits 7:6 Channel Mode {} or mr2 (Offset 0x80) R/W Mode Register 2 <byte 6459> utiny value As byte endunion mr2 (Offset 0x80) R/W Mode Register 2 <byte 6460> union d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6460> union gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only ) <byte 6460> {field (By field)} <byte 6460> tbits:4 ggpo_0_selection Bits 3:0 Global General Purpose Output 0 Selection tbits:4 ggpo_1_selection Bits 7:4 Global General Purpose Output 1 Selection {} or gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) <byte 6460> utiny value As byte endunion gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA o nly) or d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Of fset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6460> union gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6460> {field (By field)} <byte 6460> tbits:1 gpor_0 Bit 0 GPOR(0) tbits:1 gpor_1 Bit 1 GPOR(1) tbits:1 gpor_2 Bit 2 GPOR(2) tbits:1 gpor_3 Bit 3 GPOR(3) tbits:4 reserved Bits 7:4 Reserved {} or gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6460> utiny value As byte endunion gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only) or d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Of fset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6460> utiny value As byte endunion d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA onl y) (Offset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6461> union xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register <byte 6461> {field (By field)} <byte 6461> tbits:2 txd_character_status Bits 1:0 TxD character status tbits:2 txd_flow_status Bits 3:2 TxD flow status tbits:2 auto_x_character_xmission_status Bits 5:4 Automatic Character transmissi on status tbits:2 received_x_character_status Bits 7:6 Received X Character Status

{} or xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register <byte 6461> utiny value As byte endunion xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register <byte 6462> union iopior (Offset 0x85) R/W I/O Port Interrupt and Output <byte 6462> {field (By field)} <byte 6462> tbits:1 io0_output Bit 0 I/O0 output tbits:1 io1_output Bit 1 I/O1 output tbits:1 io2_output Bit 2 I/O2 output tbits:1 io3_output Bit 3 I/O3 output tbits:1 io0_enable Bit 4 I/O0 enable tbits:1 io1_enable Bit 5 I/O1 enable tbits:1 io2_enable Bit 6 I/O2 enable tbits:1 io3_enable Bit 7 I/O3 enable {} or iopior (Offset 0x85) R/W I/O Port Interrupt and Output <byte 6462> utiny value As byte endunion iopior (Offset 0x85) R/W I/O Port Interrupt and Output <byte 6463> union d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Gene rator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) <byte 6463> union ipr (Offset 0x84) R Input Port Register <byte 6463> {field (By field)} <byte 6463> tbits:1 io0_state Bit 0 I/O0 state tbits:1 io1_state Bit 1 I/O1 state tbits:1 io2_state Bit 2 I/O2 state tbits:1 io3_state Bit 3 I/O3 state tbits:1 io0_change Bit 4 I/O0 change tbits:1 io1_change Bit 5 I/O1 change tbits:1 io2_change Bit 6 I/O2 change tbits:1 io3_change Bit 7 I/O3 change {} or ipr (Offset 0x84) R Input Port Register <byte 6463> utiny value As byte endunion ipr (Offset 0x84) R Input Port Register or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generat or Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Tim er Register Lower a (UARTB only) <byte 6463> union brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UART A only) <byte 6463> {field (By field)} <byte 6463> tbits:8 msb_brg_timer_divisor Bits 7:0 8 MSB of the Baud Rate Generator Timer di visor {} or brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA o nly) <byte 6463>

utiny value As byte endunion brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (U ARTA only) or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generat or Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Tim er Register Lower a (UARTB only) <byte 6463> union brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UART B only) <byte 6463> {field (By field)} <byte 6463> tbits:8 lsb_brg_timer_divisor Bits 7:0 8 LSB of the Baud Rate Generator Timer di visor {} or brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB o nly) <byte 6463> utiny value As byte endunion brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (U ARTB only) or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generat or Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Tim er Register Lower a (UARTB only) <byte 6463> utiny value As byte endunion d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate G enerator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generat or Timer Register Lower a (UARTB only) <byte 6464> union d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) ( Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6464> union gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) <byte 6464> {field (By field)} <byte 6464> tbits:2 clock_selection_gpor_0 Bits 1:0 Clock Selection GPOR(0) tbits:2 clock_selection_gpor_1 Bits 3:2 Clock Selection GPOR(1) tbits:2 clock_selection_gpor_2 Bits 5:4 Clock Selection GPOR(2) tbits:2 clock_selection_gpor_3 Bits 7:6 Clock Selection GPOR(3) {} or gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) <byte 6464> utiny value As byte endunion gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA onl y) or d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Off set 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6464> union gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6464> {field (By field)} <byte 6464> tbits:2 data_selection_gpor_0 Bits 1:0 Data Selection GPOR(0) tbits:2 data_selection_gpor_1 Bits 3:2 Data Selection GPOR(1) tbits:2 data_selection_gpor_2 Bits 5:4 Data Selection GPOR(2) tbits:2 data_selection_gpor_3 Bits 7:6 Data Selection GPOR(3) {} or gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only)

<byte 6464> utiny value As byte endunion gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only ) or d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Off set 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6464> utiny value As byte endunion d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only ) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6465> {rsvd3 ((Offset 0x8A) NA Reserved)} <byte 6465> utiny value {} <byte 6466> {rsvd2 ((Offset 0x89) NA Reserved)} <byte 6466> utiny value {} <byte 6467> {rsvd1 ((Offset 0x88) NA Reserved)} <byte 6467> utiny value {} <byte 6468> union d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Off set 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6468> union gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) <byte 6468> {field (By field)} <byte 6468> tbits:1 power_down_mode Bit 0 Power Down Mode tbits:2 int_vector_control Bit 2:1 Interrupt Vector Control tbits:3 reserved_5_3 Bit 5:3 Reserved tbits:1 sync_bus_cycles Bit 6 Sync bus cycles tbits:1 reserved_7 Bit 7 Reserved {} or gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) <byte 6468> utiny value As byte endunion gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) or d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6468> union gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6468> {field (By field)} <byte 6468> tbits:3 other_types Bit 2:0 Other types tbits:2 reserved Bit 4:3 Reserved tbits:1 tx_interrupt Bit 5 Transmitter Interrupt tbits:2 rx_interrupt Bit 7:6 Receiver Interrupt {} or gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6468> utiny value As byte endunion gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only) or d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset

0x8F) R Global Interrupt Type Register (UARTB only) <byte 6468> utiny value As byte endunion d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) ( Offset 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6469> union d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x 8E) W Global Transmit FIFO Register (UARTA only) <byte 6469> union grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only) <byte 6469> {field (By field)} <byte 6469> tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only) <byte 6469> utiny value As byte endunion grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only) or d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6469> union gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6469> {field (By field)} <byte 6469> tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6469> utiny value As byte endunion gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) or d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6469> utiny value As byte endunion d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6470> union d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8 D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) <byte 6470> union gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) <byte 6470> {field (By field)} <byte 6470> tbits:4 channel_byte_count_code Bits 3:0 Channel byte count code tbits:4 reserved Bits 7:4 Reserved {} or gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) <byte 6470> utiny value As byte endunion gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Ba ud Rate Generator Timer Register Lower b (UARTB only) <byte 6470> union brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UART A only)

<byte 6470> {field (By field)} <byte 6470> tbits:8 msb_brg_timer_divisor Bits 7:0 8 MSB of the Baud Rate Generator Timer di visor {} or brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA o nly) <byte 6470> utiny value As byte endunion brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (U ARTA only) or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Ba ud Rate Generator Timer Register Lower b (UARTB only) <byte 6470> union brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UART B only) <byte 6470> {field (By field)} <byte 6470> tbits:8 lsb_brg_timer_divisor Bits 7:0 8 LSB of the Baud Rate Generator Timer di visor {} or brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB o nly) <byte 6470> utiny value As byte endunion brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (U ARTB only) or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Ba ud Rate Generator Timer Register Lower b (UARTB only) <byte 6470> utiny value As byte endunion d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) <byte 6471> union d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C ) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Cu rrent Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Time r Control Register (UARTB only) <byte 6471> union cir (Offset 0x8C) R Current Interrupt Register (UARTA only) <byte 6471> {field (By field)} <byte 6471> tbits:3 channel_number Bits 2:0 Channel number tbits:3 current_byte_count_type Bits 5:3 Current byte count/type tbits:2 type Bits 7:6 Type {} or cir (Offset 0x8C) R Current Interrupt Register (UARTA only) <byte 6471> utiny value As byte endunion cir (Offset 0x8C) R Current Interrupt Register (UARTA only) or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Curre nt Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer C ontrol Register (UARTB only)

<byte 6471> union gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) <byte 6471> {field (By field)} <byte 6471> tbits:3 channel_code Bits 2:0 Channel code tbits:5 reserved Bits 7:3 Reserved {} or gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) <byte 6471> utiny value As byte endunion gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Curre nt Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer C ontrol Register (UARTB only) <byte 6471> {ucir ((Offset 0x8C) W Update Current Interrupt Register (UARTA only))} <byte 6471> utiny value {} or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Curre nt Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer C ontrol Register (UARTB only) <byte 6471> union brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) <byte 6471> {field (By field)} <byte 6471> tbits:3 brgtcr_a_clock_selection Bit 2:0 BRGTCR a, Clock selection tbits:1 brgtcr_a_register_control Bit 3 BRGTCR a, Register control tbits:3 brgtcr_b_clock_selection Bit 6:4 BRGTCR b, Clock selection tbits:1 brgtcr_b_register_control Bit 7 BRGTCR b, Register control {} or brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB on ly) <byte 6471> utiny value As byte endunion brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UA RTB only) or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Curre nt Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer C ontrol Register (UARTB only) <byte 6471> utiny value As byte endunion d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0 x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator T imer Control Register (UARTB only) {} <byte 6472> {quartdr[3] (SC28L194 Quad UART Data Registers a, b, c, d)} <byte 6472> union d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register <byte 6472> union rxfifo (Offset 0x83) R Receiver FIFO Register

<byte 6472> {field (By field)} <byte 6472> tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or rxfifo (Offset 0x83) R Receiver FIFO Register <byte 6472> utiny value As byte endunion rxfifo (Offset 0x83) R Receiver FIFO Register or d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FI FO Register <byte 6472> union txfifo (Offset 0x83) W Transmitter FIFO Register <byte 6472> {field (By field)} <byte 6472> tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or txfifo (Offset 0x83) W Transmitter FIFO Register <byte 6472> utiny value As byte endunion txfifo (Offset 0x83) W Transmitter FIFO Register or d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FI FO Register <byte 6472> utiny value As byte endunion d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmit ter FIFO Register <byte 6473> union d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrup t Mask Register <byte 6473> union isr (Offset 0x82) R Interrupt Status Register <byte 6473> {field (By field)} <byte 6473> tbits:1 txrdy Bit 0 Transmitter has entered arbitration process tbits:1 rxrdy Bit 1 Receiver has entered arbitration process tbits:1 change_break_state Bit 2 Change of Break State tbits:1 reserved Bit 3 Reserved tbits:1 xon_off_event Bit 4 Xon/off event tbits:1 ar_event Bit 5 Address recognition event tbits:1 rx_watch_dog_time_out Bit 6 Receiver Watch-dog Time-out tbits:1 io_port_change_state Bit 7 I/O Port change of state {} or isr (Offset 0x82) R Interrupt Status Register <byte 6473> utiny value As byte endunion isr (Offset 0x82) R Interrupt Status Register or d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt M ask Register <byte 6473> union imr (Offset 0x82) W Interrupt Mask Register <byte 6473> {field (By field)} <byte 6473> tbits:1 txrdy_int_enable Bit 0 TxRDY interrupt enable tbits:1 rxrdy_int_enable Bit 1 RxRDY interrupt enable tbits:1 change_break_state_int_enable Bit 2 Change of Break State interrupt enab le

tbits:1 reserved Bit 3 Reserved tbits:1 xon_off_event_int_enable Bit 4 Xon/off event interrupt enable tbits:1 ar_event_int_enable Bit 5 Address recognition event interrupt enable tbits:1 rx_watch_dog_time_out_int_enable Bit 6 Receiver Watch-dog Time-out inter rupt enable tbits:1 io_port_change_state_int_enable Bit 7 I/O Port change of state interrupt ed enable {} or imr (Offset 0x82) W Interrupt Mask Register <byte 6473> utiny value As byte endunion imr (Offset 0x82) W Interrupt Mask Register or d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt M ask Register <byte 6473> utiny value As byte endunion d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Inter rupt Mask Register <byte 6474> union d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Re gister <byte 6474> union sr (Offset 0x81) R Channel Status Register <byte 6474> {field (By field)} <byte 6474> tbits:1 rx_ready Bit 0 Receiver Ready tbits:1 rx_fifo_full Bit 1 Receiver FIFO Full tbits:1 tx_ready Bit 2 Transmitter Ready tbits:1 tx_empty Bit 3 Transmitter Empty tbits:1 overrun_error Bit 4 Overrun Error tbits:1 parity_error Bit 5 Parity Error tbits:1 framing_error Bit 6 Framing Error tbits:1 received_break Bit 7 Received Break {} or sr (Offset 0x81) R Channel Status Register <byte 6474> utiny value As byte endunion sr (Offset 0x81) R Channel Status Register or d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Regis ter <byte 6474> union cr (Offset 0x81) W Command Register <byte 6474> {field (By field)} <byte 6474> tbits:1 rx_enable_disable Bit 0 Receiver Enable/Disable tbits:1 tx_enable_disable Bit 1 Transmitter Enable/Disable tbits:1 lock_txd_rxfifo_enables Bit 2 Hold present condition of Transmitter & Re ceiver enables/Change Transmitter & Receiver enable conditions tbits:5 channel_command Bits 7:3 Channel Command {} or cr (Offset 0x81) W Command Register <byte 6474> utiny value As byte endunion cr (Offset 0x81) W Command Register or d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Regis ter <byte 6474> utiny value As byte

endunion d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register <byte 6475> union mr2 (Offset 0x80) R/W Mode Register 2 <byte 6475> {field (By field)} <byte 6475> tbits:2 stop_length Bit 1:0 Stop Length tbits:2 txint Bit 3:2 Receiver initiation of interrupt bidding condition tbits:1 ctsn_enable_tx Bit 4 CTSN Enable Transmitter tbits:1 tx_rts_control Bit 5 Transmitter RTS Control tbits:2 channel_mode Bits 7:6 Channel Mode {} or mr2 (Offset 0x80) R/W Mode Register 2 <byte 6475> utiny value As byte endunion mr2 (Offset 0x80) R/W Mode Register 2 <byte 6476> union d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6476> union gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only ) <byte 6476> {field (By field)} <byte 6476> tbits:4 ggpo_0_selection Bits 3:0 Global General Purpose Output 0 Selection tbits:4 ggpo_1_selection Bits 7:4 Global General Purpose Output 1 Selection {} or gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) <byte 6476> utiny value As byte endunion gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA o nly) or d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Of fset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6476> union gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6476> {field (By field)} <byte 6476> tbits:1 gpor_0 Bit 0 GPOR(0) tbits:1 gpor_1 Bit 1 GPOR(1) tbits:1 gpor_2 Bit 2 GPOR(2) tbits:1 gpor_3 Bit 3 GPOR(3) tbits:4 reserved Bits 7:4 Reserved {} or gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6476> utiny value As byte endunion gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only) or d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Of fset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6476> utiny value As byte endunion d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA onl y) (Offset 0x87) R/W General Purpose Output Register (UARTB only) <byte 6477> union xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register <byte 6477>

{field (By field)} <byte 6477> tbits:2 txd_character_status Bits 1:0 TxD character status tbits:2 txd_flow_status Bits 3:2 TxD flow status tbits:2 auto_x_character_xmission_status Bits 5:4 Automatic Character transmissi on status tbits:2 received_x_character_status Bits 7:6 Received X Character Status {} or xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register <byte 6477> utiny value As byte endunion xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register <byte 6478> union iopior (Offset 0x85) R/W I/O Port Interrupt and Output <byte 6478> {field (By field)} <byte 6478> tbits:1 io0_output Bit 0 I/O0 output tbits:1 io1_output Bit 1 I/O1 output tbits:1 io2_output Bit 2 I/O2 output tbits:1 io3_output Bit 3 I/O3 output tbits:1 io0_enable Bit 4 I/O0 enable tbits:1 io1_enable Bit 5 I/O1 enable tbits:1 io2_enable Bit 6 I/O2 enable tbits:1 io3_enable Bit 7 I/O3 enable {} or iopior (Offset 0x85) R/W I/O Port Interrupt and Output <byte 6478> utiny value As byte endunion iopior (Offset 0x85) R/W I/O Port Interrupt and Output <byte 6479> union d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Gene rator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only) <byte 6479> union ipr (Offset 0x84) R Input Port Register <byte 6479> {field (By field)} <byte 6479> tbits:1 io0_state Bit 0 I/O0 state tbits:1 io1_state Bit 1 I/O1 state tbits:1 io2_state Bit 2 I/O2 state tbits:1 io3_state Bit 3 I/O3 state tbits:1 io0_change Bit 4 I/O0 change tbits:1 io1_change Bit 5 I/O1 change tbits:1 io2_change Bit 6 I/O2 change tbits:1 io3_change Bit 7 I/O3 change {} or ipr (Offset 0x84) R Input Port Register <byte 6479> utiny value As byte endunion ipr (Offset 0x84) R Input Port Register or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generat or Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Tim er Register Lower a (UARTB only) <byte 6479> union brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UART A only) <byte 6479> {field (By field)}

<byte 6479> tbits:8 msb_brg_timer_divisor Bits 7:0 8 MSB of the Baud Rate Generator Timer di visor {} or brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA o nly) <byte 6479> utiny value As byte endunion brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (U ARTA only) or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generat or Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Tim er Register Lower a (UARTB only) <byte 6479> union brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UART B only) <byte 6479> {field (By field)} <byte 6479> tbits:8 lsb_brg_timer_divisor Bits 7:0 8 LSB of the Baud Rate Generator Timer di visor {} or brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB o nly) <byte 6479> utiny value As byte endunion brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (U ARTB only) or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generat or Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Tim er Register Lower a (UARTB only) <byte 6479> utiny value As byte endunion d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate G enerator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generat or Timer Register Lower a (UARTB only) <byte 6480> union d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) ( Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6480> union gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) <byte 6480> {field (By field)} <byte 6480> tbits:2 clock_selection_gpor_0 Bits 1:0 Clock Selection GPOR(0) tbits:2 clock_selection_gpor_1 Bits 3:2 Clock Selection GPOR(1) tbits:2 clock_selection_gpor_2 Bits 5:4 Clock Selection GPOR(2) tbits:2 clock_selection_gpor_3 Bits 7:6 Clock Selection GPOR(3) {} or gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) <byte 6480> utiny value As byte endunion gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA onl y) or d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Off set 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6480> union gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6480> {field (By field)}

<byte 6480> tbits:2 data_selection_gpor_0 Bits 1:0 Data Selection GPOR(0) tbits:2 data_selection_gpor_1 Bits 3:2 Data Selection GPOR(1) tbits:2 data_selection_gpor_2 Bits 5:4 Data Selection GPOR(2) tbits:2 data_selection_gpor_3 Bits 7:6 Data Selection GPOR(3) {} or gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6480> utiny value As byte endunion gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only ) or d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Off set 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6480> utiny value As byte endunion d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only ) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only) <byte 6481> {rsvd3 ((Offset 0x8A) NA Reserved)} <byte 6481> utiny value {} <byte 6482> {rsvd2 ((Offset 0x89) NA Reserved)} <byte 6482> utiny value {} <byte 6483> {rsvd1 ((Offset 0x88) NA Reserved)} <byte 6483> utiny value {} <byte 6484> union d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Off set 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6484> union gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) <byte 6484> {field (By field)} <byte 6484> tbits:1 power_down_mode Bit 0 Power Down Mode tbits:2 int_vector_control Bit 2:1 Interrupt Vector Control tbits:3 reserved_5_3 Bit 5:3 Reserved tbits:1 sync_bus_cycles Bit 6 Sync bus cycles tbits:1 reserved_7 Bit 7 Reserved {} or gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) <byte 6484> utiny value As byte endunion gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) or d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6484> union gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6484> {field (By field)} <byte 6484> tbits:3 other_types Bit 2:0 Other types tbits:2 reserved Bit 4:3 Reserved tbits:1 tx_interrupt Bit 5 Transmitter Interrupt

tbits:2 rx_interrupt Bit 7:6 Receiver Interrupt {} or gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6484> utiny value As byte endunion gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only) or d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6484> utiny value As byte endunion d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) ( Offset 0x8F) R Global Interrupt Type Register (UARTB only) <byte 6485> union d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x 8E) W Global Transmit FIFO Register (UARTA only) <byte 6485> union grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only) <byte 6485> {field (By field)} <byte 6485> tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only) <byte 6485> utiny value As byte endunion grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only) or d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6485> union gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6485> {field (By field)} <byte 6485> tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data {} or gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6485> utiny value As byte endunion gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) or d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6485> utiny value As byte endunion d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only) <byte 6486> union d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8 D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) <byte 6486> union gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) <byte 6486> {field (By field)} <byte 6486> tbits:4 channel_byte_count_code Bits 3:0 Channel byte count code tbits:4 reserved Bits 7:4 Reserved {} or gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) <byte 6486> utiny value As byte

endunion gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Ba ud Rate Generator Timer Register Lower b (UARTB only) <byte 6486> union brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UART A only) <byte 6486> {field (By field)} <byte 6486> tbits:8 msb_brg_timer_divisor Bits 7:0 8 MSB of the Baud Rate Generator Timer di visor {} or brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA o nly) <byte 6486> utiny value As byte endunion brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (U ARTA only) or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Ba ud Rate Generator Timer Register Lower b (UARTB only) <byte 6486> union brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UART B only) <byte 6486> {field (By field)} <byte 6486> tbits:8 lsb_brg_timer_divisor Bits 7:0 8 LSB of the Baud Rate Generator Timer di visor {} or brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB o nly) <byte 6486> utiny value As byte endunion brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (U ARTB only) or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Ba ud Rate Generator Timer Register Lower b (UARTB only) <byte 6486> utiny value As byte endunion d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only) <byte 6487> union d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C ) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Cu rrent Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Time r Control Register (UARTB only) <byte 6487> union cir (Offset 0x8C) R Current Interrupt Register (UARTA only) <byte 6487> {field (By field)} <byte 6487> tbits:3 channel_number Bits 2:0 Channel number tbits:3 current_byte_count_type Bits 5:3 Current byte count/type tbits:2 type Bits 7:6 Type {} or cir (Offset 0x8C) R Current Interrupt Register (UARTA only)

<byte 6487> utiny value As byte endunion cir (Offset 0x8C) R Current Interrupt Register (UARTA only) or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Curre nt Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer C ontrol Register (UARTB only) <byte 6487> union gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) <byte 6487> {field (By field)} <byte 6487> tbits:3 channel_code Bits 2:0 Channel code tbits:5 reserved Bits 7:3 Reserved {} or gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) <byte 6487> utiny value As byte endunion gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Curre nt Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer C ontrol Register (UARTB only) <byte 6487> {ucir ((Offset 0x8C) W Update Current Interrupt Register (UARTA only))} <byte 6487> utiny value {} or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Curre nt Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer C ontrol Register (UARTB only) <byte 6487> union brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only) <byte 6487> {field (By field)} <byte 6487> tbits:3 brgtcr_a_clock_selection Bit 2:0 BRGTCR a, Clock selection tbits:1 brgtcr_a_register_control Bit 3 BRGTCR a, Register control tbits:3 brgtcr_b_clock_selection Bit 6:4 BRGTCR b, Clock selection tbits:1 brgtcr_b_register_control Bit 7 BRGTCR b, Register control {} or brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB on ly) <byte 6487> utiny value As byte endunion brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UA RTB only) or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Curre nt Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer C ontrol Register (UARTB only) <byte 6487> utiny value As byte endunion d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0 x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator T imer Control Register (UARTB only) {}

<byte 6488> {tachyon (Tachyon DX2+ register save area)} <byte 6488> union portcorr[0] Port Correlation <byte 6488> ulong portcorra Port Correlation As Longword or portcorr[0] Port Correlation <byte 6488> {portcorr (Port Correlation By Field)} <byte 6488> utiny real_port Real hardware port number <byte 6489> utiny port_type Port type <byte 6490> ushort reserved Reserved {} endunion portcorr[0] Port Correlation <byte 6492> union portcorr[1] Port Correlation <byte 6492> ulong portcorra Port Correlation As Longword or portcorr[1] Port Correlation <byte 6492> {portcorr (Port Correlation By Field)} <byte 6492> utiny real_port Real hardware port number <byte 6493> utiny port_type Port type <byte 6494> ushort reserved Reserved {} endunion portcorr[1] Port Correlation <byte 6496> union portcorr[2] Port Correlation <byte 6496> ulong portcorra Port Correlation As Longword or portcorr[2] Port Correlation <byte 6496> {portcorr (Port Correlation By Field)} <byte 6496> utiny real_port Real hardware port number <byte 6497> utiny port_type Port type <byte 6498> ushort reserved Reserved {} endunion portcorr[2] Port Correlation <byte 6500> union portcorr[3] Port Correlation <byte 6500> ulong portcorra Port Correlation As Longword or portcorr[3] Port Correlation <byte 6500> {portcorr (Port Correlation By Field)} <byte 6500> utiny real_port Real hardware port number <byte 6501> utiny port_type Port type <byte 6502> ushort reserved Reserved

{} endunion portcorr[3] Port Correlation <byte 6504> union portcorr[4] Port Correlation <byte 6504> ulong portcorra Port Correlation As Longword or portcorr[4] Port Correlation <byte 6504> {portcorr (Port Correlation By Field)} <byte 6504> utiny real_port Real hardware port number <byte 6505> utiny port_type Port type <byte 6506> ushort reserved Reserved {} endunion portcorr[4] Port Correlation <byte 6508> union portcorr[5] Port Correlation <byte 6508> ulong portcorra Port Correlation As Longword or portcorr[5] Port Correlation <byte 6508> {portcorr (Port Correlation By Field)} <byte 6508> utiny real_port Real hardware port number <byte 6509> utiny port_type Port type <byte 6510> ushort reserved Reserved {} endunion portcorr[5] Port Correlation <byte 6512> union portcorr[6] Port Correlation <byte 6512> ulong portcorra Port Correlation As Longword or portcorr[6] Port Correlation <byte 6512> {portcorr (Port Correlation By Field)} <byte 6512> utiny real_port Real hardware port number <byte 6513> utiny port_type Port type <byte 6514> ushort reserved Reserved {} endunion portcorr[6] Port Correlation <byte 6516> union portcorr[7] Port Correlation <byte 6516> ulong portcorra Port Correlation As Longword or portcorr[7] Port Correlation <byte 6516> {portcorr (Port Correlation By Field)} <byte 6516> utiny real_port Real hardware port number <byte 6517> utiny port_type Port type <byte 6518> ushort reserved Reserved

{} endunion portcorr[7] Port Correlation <byte 6520> union portcorr[8] Port Correlation <byte 6520> ulong portcorra Port Correlation As Longword or portcorr[8] Port Correlation <byte 6520> {portcorr (Port Correlation By Field)} <byte 6520> utiny real_port Real hardware port number <byte 6521> utiny port_type Port type <byte 6522> ushort reserved Reserved {} endunion portcorr[8] Port Correlation <byte 6524> union portcorr[9] Port Correlation <byte 6524> ulong portcorra Port Correlation As Longword or portcorr[9] Port Correlation <byte 6524> {portcorr (Port Correlation By Field)} <byte 6524> utiny real_port Real hardware port number <byte 6525> utiny port_type Port type <byte 6526> ushort reserved Reserved {} endunion portcorr[9] Port Correlation <byte 6528> union portcorr[10] Port Correlation <byte 6528> ulong portcorra Port Correlation As Longword or portcorr[10] Port Correlation <byte 6528> {portcorr (Port Correlation By Field)} <byte 6528> utiny real_port Real hardware port number <byte 6529> utiny port_type Port type <byte 6530> ushort reserved Reserved {} endunion portcorr[10] Port Correlation <byte 6532> union portcorr[11] Port Correlation <byte 6532> ulong portcorra Port Correlation As Longword or portcorr[11] Port Correlation <byte 6532> {portcorr (Port Correlation By Field)} <byte 6532> utiny real_port Real hardware port number <byte 6533> utiny port_type Port type <byte 6534> ushort reserved Reserved

{} endunion portcorr[11] Port Correlation <byte 6536> union csr[0] Tachyon DX2+ CSR Registers <byte 6536> ulong[128] csra Tachyon DX2+ CSR Registers As Longwords or csr[0] Tachyon DX2+ CSR Registers <byte 6536> {csr (Tachyon DX2+ CSR Registers By Field)} <byte 6536> union erq_base (Offset 000) ERQ Base (write only) <byte 6536> {field (By field)} <byte 6536> lbits:32 address ERQ Base Address {} or erq_base (Offset 000) ERQ Base (write only) <byte 6536> ulong value As longword endunion erq_base (Offset 000) ERQ Base (write only) <byte 6540> union erq_len (Offset 004) ERQ Length (write only) <byte 6540> {field (By field)} <byte 6540> lbits:12 length ERQ Length lbits:20 reserved Reserved {} or erq_len (Offset 004) ERQ Length (write only) <byte 6540> ulong value As longword endunion erq_len (Offset 004) ERQ Length (write only) <byte 6544> union erq_prod (Offset 008) ERQ Producer Index <byte 6544> {field (By field)} <byte 6544> lbits:12 index ERQ Producer Index lbits:20 reserved Reserved {} or erq_prod (Offset 008) ERQ Producer Index <byte 6544> ulong value As longword endunion erq_prod (Offset 008) ERQ Producer Index <byte 6548> union erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 6548> {field (By field)} <byte 6548> lbits:32 address ERQ Consumer Index Address {} or erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 6548> ulong value As longword endunion erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 6552> union erq_cons (Offset 010) ERQ Consumer Index <byte 6552> {field (By field)} <byte 6552>

lbits:12 index ERQ Consumer Index lbits:20 reserved Reserved {} or erq_cons (Offset 010) ERQ Consumer Index <byte 6552> ulong value As longword endunion erq_cons (Offset 010) ERQ Consumer Index <byte 6556> {rsvd1[0] ((Offset 014-04F) Reserved)} <byte 6556> ulong value {} <byte 6560> {rsvd1[1] ((Offset 014-04F) Reserved)} <byte 6560> ulong value {} <byte 6564> {rsvd1[2] ((Offset 014-04F) Reserved)} <byte 6564> ulong value {} <byte 6568> {rsvd1[3] ((Offset 014-04F) Reserved)} <byte 6568> ulong value {} <byte 6572> {rsvd1[4] ((Offset 014-04F) Reserved)} <byte 6572> ulong value {} <byte 6576> {rsvd1[5] ((Offset 014-04F) Reserved)} <byte 6576> ulong value {} <byte 6580> {rsvd1[6] ((Offset 014-04F) Reserved)} <byte 6580> ulong value {} <byte 6584> {rsvd1[7] ((Offset 014-04F) Reserved)} <byte 6584> ulong value {} <byte 6588> {rsvd1[8] ((Offset 014-04F) Reserved)} <byte 6588> ulong value {} <byte 6592> {rsvd1[9] ((Offset 014-04F) Reserved)} <byte 6592> ulong value {} <byte 6596> {rsvd1[10] ((Offset 014-04F) Reserved)} <byte 6596>

ulong value {} <byte 6600> {rsvd1[11] ((Offset 014-04F) Reserved)} <byte 6600> ulong value {} <byte 6604> {rsvd1[12] ((Offset 014-04F) Reserved)} <byte 6604> ulong value {} <byte 6608> {rsvd1[13] ((Offset 014-04F) Reserved)} <byte 6608> ulong value {} <byte 6612> {rsvd1[14] ((Offset 014-04F) Reserved)} <byte 6612> ulong value {} <byte 6616> union sfq_base (Offset 050) SFQ Base (write only) <byte 6616> {field (By field)} <byte 6616> lbits:32 address SFQ Base Address {} or sfq_base (Offset 050) SFQ Base (write only) <byte 6616> ulong value As longword endunion sfq_base (Offset 050) SFQ Base (write only) <byte 6620> union sfq_len (Offset 054) SFQ Length (write only) <byte 6620> {field (By field)} <byte 6620> lbits:12 length SFQ Length lbits:20 reserved Reserved {} or sfq_len (Offset 054) SFQ Length (write only) <byte 6620> ulong value As longword endunion sfq_len (Offset 054) SFQ Length (write only) <byte 6624> union sfq_cons (Offset 058) SFQ Consumer Index <byte 6624> {field (By field)} <byte 6624> lbits:12 index SFQ Consumer Index lbits:20 reserved Reserved {} or sfq_cons (Offset 058) SFQ Consumer Index <byte 6624> ulong value As longword endunion sfq_cons (Offset 058) SFQ Consumer Index <byte 6628> {rsvd2[0] ((Offset 05C-07B) Reserved)} <byte 6628>

ulong value {} <byte 6632> {rsvd2[1] ((Offset 05C-07B) Reserved)} <byte 6632> ulong value {} <byte 6636> {rsvd2[2] ((Offset 05C-07B) Reserved)} <byte 6636> ulong value {} <byte 6640> {rsvd2[3] ((Offset 05C-07B) Reserved)} <byte 6640> ulong value {} <byte 6644> {rsvd2[4] ((Offset 05C-07B) Reserved)} <byte 6644> ulong value {} <byte 6648> {rsvd2[5] ((Offset 05C-07B) Reserved)} <byte 6648> ulong value {} <byte 6652> {rsvd2[6] ((Offset 05C-07B) Reserved)} <byte 6652> ulong value {} <byte 6656> {rsvd2[7] ((Offset 05C-07B) Reserved)} <byte 6656> ulong value {} <byte 6660> union int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 6660> {field (By field)} <byte 6660> lbits:4 timer Interrupt Timer Value lbits:3 reserved Reserved lbits:1 ihf Interrupt when IMQ Half Full lbits:24 reserved1 Reserved {} or int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 6660> ulong value As longword endunion int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 6664> union imq_base (Offset 080) IMQ Base (write only) <byte 6664> {field (By field)} <byte 6664> lbits:32 address IMQ Base Address {} or imq_base (Offset 080) IMQ Base (write only) <byte 6664>

ulong value As longword endunion imq_base (Offset 080) IMQ Base (write only) <byte 6668> union imq_len (Offset 084) IMQ Length (write only) <byte 6668> {field (By field)} <byte 6668> lbits:12 length IMQ Length lbits:20 reserved Reserved {} or imq_len (Offset 084) IMQ Length (write only) <byte 6668> ulong value As longword endunion imq_len (Offset 084) IMQ Length (write only) <byte 6672> union imq_cons (Offset 088) IMQ Consumer Index <byte 6672> {field (By field)} <byte 6672> lbits:12 index IMQ Consumer Index lbits:20 reserved Reserved {} or imq_cons (Offset 088) IMQ Consumer Index <byte 6672> ulong value As longword endunion imq_cons (Offset 088) IMQ Consumer Index <byte 6676> union imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 6676> {field (By field)} <byte 6676> lbits:32 address IMQ Producer Index Address {} or imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 6676> ulong value As longword endunion imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 6680> {rsvd3[0] ((Offset 090-0FC) Reserved)} <byte 6680> ulong value {} <byte 6684> {rsvd3[1] ((Offset 090-0FC) Reserved)} <byte 6684> ulong value {} <byte 6688> {rsvd3[2] ((Offset 090-0FC) Reserved)} <byte 6688> ulong value {} <byte 6692> {rsvd3[3] ((Offset 090-0FC) Reserved)} <byte 6692> ulong value {} <byte 6696> {rsvd3[4] ((Offset 090-0FC) Reserved)} <byte 6696>

ulong value {} <byte 6700> {rsvd3[5] ((Offset 090-0FC) Reserved)} <byte 6700> ulong value {} <byte 6704> {rsvd3[6] ((Offset 090-0FC) Reserved)} <byte 6704> ulong value {} <byte 6708> {rsvd3[7] ((Offset 090-0FC) Reserved)} <byte 6708> ulong value {} <byte 6712> {rsvd3[8] ((Offset 090-0FC) Reserved)} <byte 6712> ulong value {} <byte 6716> {rsvd3[9] ((Offset 090-0FC) Reserved)} <byte 6716> ulong value {} <byte 6720> {rsvd3[10] ((Offset 090-0FC) Reserved)} <byte 6720> ulong value {} <byte 6724> {rsvd3[11] ((Offset 090-0FC) Reserved)} <byte 6724> ulong value {} <byte 6728> {rsvd3[12] ((Offset 090-0FC) Reserved)} <byte 6728> ulong value {} <byte 6732> {rsvd3[13] ((Offset 090-0FC) Reserved)} <byte 6732> ulong value {} <byte 6736> {rsvd3[14] ((Offset 090-0FC) Reserved)} <byte 6736> ulong value {} <byte 6740> {rsvd3[15] ((Offset 090-0FC) Reserved)} <byte 6740> ulong value {} <byte 6744> {rsvd3[16] ((Offset 090-0FC) Reserved)} <byte 6744>

ulong value {} <byte 6748> {rsvd3[17] ((Offset 090-0FC) Reserved)} <byte 6748> ulong value {} <byte 6752> {rsvd3[18] ((Offset 090-0FC) Reserved)} <byte 6752> ulong value {} <byte 6756> {rsvd3[19] ((Offset 090-0FC) Reserved)} <byte 6756> ulong value {} <byte 6760> {rsvd3[20] ((Offset 090-0FC) Reserved)} <byte 6760> ulong value {} <byte 6764> {rsvd3[21] ((Offset 090-0FC) Reserved)} <byte 6764> ulong value {} <byte 6768> {rsvd3[22] ((Offset 090-0FC) Reserved)} <byte 6768> ulong value {} <byte 6772> {rsvd3[23] ((Offset 090-0FC) Reserved)} <byte 6772> ulong value {} <byte 6776> {rsvd3[24] ((Offset 090-0FC) Reserved)} <byte 6776> ulong value {} <byte 6780> {rsvd3[25] ((Offset 090-0FC) Reserved)} <byte 6780> ulong value {} <byte 6784> {rsvd3[26] ((Offset 090-0FC) Reserved)} <byte 6784> ulong value {} <byte 6788> {rsvd3[27] ((Offset 090-0FC) Reserved)} <byte 6788> ulong value {} <byte 6792> union fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 6792>

{field (By field)} <byte 6792> lbits:6 bec Termination Receive lbits:3 reserved4 Reserved lbits:1 xrb Wrapback lbits:2 reserved Reserved lbits:3 xem Output pre-emphasis lbits:4 reserved1 Reserved lbits:1 mustbe1 Must be 1 lbits:1 stb Start BERT lbits:1 enb Enable BERT lbits:2 sdm Signal differential mode lbits:2 rxs Receiver Speed lbits:2 txs Transmitter Speed lbits:1 reserved3 Reserved lbits:1 xlr Force iTR to lock reference clock lbits:1 reserved0 Reserved lbits:1 xcv Type of Transceiver {} or fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 6792> ulong value As longword endunion fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 6796> union fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 6796> {field (By field)} <byte 6796> lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 6796> ulong value As longword endunion fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 6800>

{rsvd3a[0] ((Offset 108-10f) Reserved)} <byte 6800> ulong value {} <byte 6804> {rsvd3a[1] ((Offset 108-10f) Reserved)} <byte 6804> ulong value {} <byte 6808> union sfp_cmd_status (Offset 110) SFP command and status <byte 6808> {field (No description available)} <byte 6808> lbits:1 gna Generate NACK lbits:1 rts Reset Slave lbits:1 wrc Write command lbits:1 rdc Read command lbits:1 gst Generate Stop lbits:1 sta Generate Start lbits:2 reserved1 Reserved lbits:1 rna Received NACK lbits:1 sby SFP Busy lbits:1 tip Transfer in progress lbits:9 reserved Reserved lbits:12 lp Clock Divisor {} or sfp_cmd_status (Offset 110) SFP command and status <byte 6808> ulong value endunion sfp_cmd_status (Offset 110) SFP command and status <byte 6812> union sfp_data (Offset 114) SFP data <byte 6812> {field (By field)} <byte 6812> lbits:8 sfpd SFPD Transmit lbits:24 reserved Reserved {} or sfp_data (Offset 114) SFP data <byte 6812> ulong value As longword endunion sfp_data (Offset 114) SFP data <byte 6816> union fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 6816> {field (By field)} <byte 6816> lbits:1 tbe Transmit Link BIST error lbits:1 tlr Transmit Link BIST reset lbits:1 tle Transmit Link BIST enable lbits:1 rbe Receive Link BIST error lbits:1 rll Receive Link BIST loop-back lbits:1 rlr Receive Link BIST reset lbits:1 rle Receive Link BIST enable lbits:7 reserved3 Reserved lbits:1 ipl ITR PPL Lock lbits:1 reserved2 Reserved lbits:1 dtf Disable transceiver LOS filter lbits:1 dtl Disable transceiver LOS

lbits:1 dsr Disable iTR RXLOS lbits:1 ttd Transceiver Tx Disable lbits:2 reserved1 Reserved lbits:1 rfl Receive ast Lock Disable lbits:9 reserved Reserved {} or fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 6816> ulong value As longword endunion fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 6820> union fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 6820> {field (By field)} <byte 6820> lbits:32 reserved Reserved {} or fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 6820> ulong value As longword endunion fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 6824> {rsvd3b[0] ((Offset 120-13F) Reserved)} <byte 6824> ulong value {} <byte 6828> {rsvd3b[1] ((Offset 120-13F) Reserved)} <byte 6828> ulong value {} <byte 6832> {rsvd3b[2] ((Offset 120-13F) Reserved)} <byte 6832> ulong value {} <byte 6836> {rsvd3b[3] ((Offset 120-13F) Reserved)} <byte 6836> ulong value {} <byte 6840> {rsvd3b[4] ((Offset 120-13F) Reserved)} <byte 6840> ulong value {} <byte 6844> {rsvd3b[5] ((Offset 120-13F) Reserved)} <byte 6844> ulong value {} <byte 6848> {rsvd3b[6] ((Offset 120-13F) Reserved)} <byte 6848> ulong value {} <byte 6852> {rsvd3b[7] ((Offset 120-13F) Reserved)} <byte 6852> ulong value

{} <byte 6856> union sest_base (Offset 140) SEST Base (write only) <byte 6856> {field (By field)} <byte 6856> lbits:32 address SEST Base Address {} or sest_base (Offset 140) SEST Base (write only) <byte 6856> ulong value As longword endunion sest_base (Offset 140) SEST Base (write only) <byte 6860> union sest_len (Offset 144) SEST Length (write only) <byte 6860> {field (By field)} <byte 6860> lbits:16 length SEST Length lbits:16 reserved Reserved {} or sest_len (Offset 144) SEST Length (write only) <byte 6860> ulong value As longword endunion sest_len (Offset 144) SEST Length (write only) <byte 6864> {rsvd4 ((Offset 148) Reserved)} <byte 6864> ulong value {} <byte 6868> union scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 6868> {field (By field)} <byte 6868> lbits:16 tail Tail lbits:16 head Head {} or scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 6868> ulong value As longword endunion scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 6872> union prog_addr (Offset 150) Programmable Address register <byte 6872> {field (By field)} <byte 6872> lbits:20 ra ROM/RAM address lbits:11 reserved Reserved lbits:1 inc Increment {} or prog_addr (Offset 150) Programmable Address register <byte 6872> ulong value As longword endunion prog_addr (Offset 150) Programmable Address register <byte 6876> union prog_data (Offset 154) programmable data register <byte 6876> {field (By field)} <byte 6876> lbits:32 pdr Programmable data

{} or prog_data (Offset 154) programmable data register <byte 6876> ulong value As longword endunion prog_data (Offset 154) programmable data register <byte 6880> {rsvd5[0] ((Offset 158-15F) Reserved)} <byte 6880> ulong value {} <byte 6884> {rsvd5[1] ((Offset 158-15F) Reserved)} <byte 6884> ulong value {} <byte 6888> union int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 6888> {field (By field)} <byte 6888> lbits:32 address Interrupt Message Address {} or int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 6888> ulong value As longword endunion int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 6892> union int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 6892> {field (By field)} <byte 6892> lbits:32 value Interrupt Message Value {} or int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 6892> ulong value As longword endunion int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 6896> union sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 6896> {field (By field)} <byte 6896> lbits:8 length SGL Page Length lbits:24 reserved Reserved {} or sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 6896> ulong value As longword endunion sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 6900> union my_id (Offset 16C) My ID <byte 6900> {field (By field)} <byte 6900> lbits:24 id My ID lbits:8 reserved Reserved {} or my_id (Offset 16C) My ID <byte 6900> ulong value As longword

endunion my_id (Offset 16C) My ID <byte 6904> union gpio (Offset 170) General Purpose I/O <byte 6904> {field (By field)} <byte 6904> lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:1 gc5 General Purpose Control 5 lbits:1 gc6 General Purpose Control 6 lbits:1 gc7 General Purpose Control 7 lbits:8 reserved Reserved lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose I/O 4 lbits:1 gp5 General Purpose I/O 5 lbits:1 gp6 General Purpose I/O 6 lbits:1 gp7 General Purpose I/O 7 lbits:8 reserved1 Reserved {} or gpio (Offset 170) General Purpose I/O <byte 6904> ulong value As longword endunion gpio (Offset 170) General Purpose I/O <byte 6908> {rsvd6a ((Offset 174-177) Reserved)} <byte 6908> ulong value {} <byte 6912> union edc_config (Offset 178) EDC Configuration Register <byte 6912> {field (By field)} <byte 6912> lbits:16 io_seed Starting Seed lbits:16 reserved Reserved {} or edc_config (Offset 178) EDC Configuration Register <byte 6912> ulong value As longword endunion edc_config (Offset 178) EDC Configuration Register <byte 6916> union dx4_config3 (Offset 17C) DX4 Configuration Register 3 <byte 6916> {field (By field)} <byte 6916> lbits:9 pfs2 Programmable Frame size field 2 lbits:9 pfs3 Programmable Frame size field 3 lbits:9 pfs4 Programmable Frame size field 4 lbits:5 reserved Reserved {} or dx4_config3 (Offset 17C) DX4 Configuration Register 3 <byte 6916> ulong value As longword endunion dx4_config3 (Offset 17C) DX4 Configuration Register 3

<byte 6920> union tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 6920> {field (By field)} <byte 6920> lbits:9 pfs Programmable Frame Size lbits:15 reserved Reserved lbits:8 esi_range Exchange_ID Signaled Interrupt Range {} or tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 6920> ulong value As longword endunion tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 6924> union tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 6924> {field (By field)} <byte 6924> lbits:1 fad FCP Assist Disable lbits:1 ino In Order lbits:1 dof Discard OOO FCP Frames lbits:1 fua FCP Unassisted ACK Enable lbits:1 ime Interrupt Message Enable lbits:1 fab Fabric lbits:1 sic S_ID Copy Enable lbits:1 eqs Equal Service lbits:2 reserved Reserved lbits:1 aks Automatic ACK lbits:1 ddf Disable Delayed Freeze lbits:1 ebe Enable Big Endian Mode lbits:11 reserved1 Reserved lbits:1 fc2 FCP Class 2 Reassembly Enable lbits:1 reserved2 Reserved lbits:1 sdf Save Discarded Frames lbits:1 rde Response Detect Enable lbits:1 dam Default ACK Model lbits:2 reserved3 Reserved lbits:1 m66 66 MHz Enabled {} or tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 6924> ulong value As longword endunion tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 6928> union tach_control (Offset 188) Tachyon DX2+ Control <byte 6928> {field (By field)} <byte 6928> lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:3 reserved Reserved lbits:1 feq Freeze ERQ lbits:1 ffa Freeze FCP Assists lbits:2 reserved1 Reserved lbits:1 fis Freeze Inbound FCP Assists When Frame Placed in SFQ lbits:1 fib Freeze Inbound FCP Assists lbits:2 reserved2 Reserved

lbits:1 req Resume ERQ lbits:1 rif Resume Inbound FCP Assists lbits:1 rof Resume Outbound FCP Assists lbits:12 reserved3 Reserved lbits:1 crs Core Reset {} or tach_control (Offset 188) Tachyon DX2+ Control <byte 6928> ulong value As longword endunion tach_control (Offset 188) Tachyon DX2+ Control <byte 6932> union tach_status (Offset 18C) Tachyon DX2+ Status <byte 6932> {field (By field)} <byte 6932> lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose Input 4 lbits:5 reserved Reserved lbits:1 ipe Inbound Parity Error lbits:1 ope Outbound Parity Error lbits:4 reserved1 Reserved lbits:1 eqf ERQ Frozen lbits:1 iff Inbound FCP Assists Frozen lbits:1 off Outbound FCP Assists Frozen lbits:4 reserved2 Reserved lbits:1 ifce Inbound FIFO CRC Error lbits:1 ofce Outbound FIFO CRC Error lbits:1 m66 66 Mhz Enabled lbits:1 ile Inbound Link Control FIFO Empty lbits:1 ole Outbound Link Control List Empty lbits:1 ife Inbound FIFO Empty lbits:1 ofe Outbound FIFO Empty lbits:1 imf IMQ Full lbits:1 ssf SFQ Full {} or tach_status (Offset 18C) Tachyon DX2+ Status <byte 6932> ulong value As longword endunion tach_status (Offset 18C) Tachyon DX2+ Status <byte 6936> {rsvd7 ((Offset 190) Reserved)} <byte 6936> ulong value {} <byte 6940> union hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 6940> {field (By field)} <byte 6940> lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 6940> ulong value As longword

endunion hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 6944> union hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 6944> {field (By field)} <byte 6944> lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 6944> ulong value As longword endunion hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 6948> union inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 6948> {field (By field)} <byte 6948> lbits:24 reserved Reserved lbits:8 sest_lru_count SEST LRU Count {} or inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 6948> ulong value As longword endunion inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 6952> union inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 6952> {field (By field)} <byte 6952> lbits:8 discd_frames Discarded Frame Count lbits:24 reserved Reserved {} or inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 6952> ulong value As longword endunion inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 6956> union ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) <byte 6956> {field (By field)} <byte 6956> lbits:28 threshold EE_Credit Zero Timer Threshold lbits:4 reserved Reserved {} or ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) <byte 6956> ulong value As longword endunion ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only ) <byte 6960> union up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 6960> {field (By field)} <byte 6960> lbits:12 reserved Reserved lbits:1 upper_addr1 Upper Data Address--44 bit data space lbits:19 upper_addr Upper Data Address

{} or up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 6960> ulong value As longword endunion up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 6964> union up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 6964> {field (By field)} <byte 6964> lbits:32 upper_addr Upper Control Address {} or up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 6964> ulong value As longword endunion up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 6968> union dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 6968> {field (By field)} <byte 6968> lbits:1 ef AL_PA 0xEF DHD Login Information lbits:1 e8 AL_PA 0xE8 DHD Login Information lbits:1 e4 AL_PA 0xE4 DHD Login Information lbits:1 e2 AL_PA 0xE2 DHD Login Information lbits:1 e1 AL_PA 0xE1 DHD Login Information lbits:1 e0 AL_PA 0xE0 DHD Login Information lbits:1 dc AL_PA 0xDC DHD Login Information lbits:1 da AL_PA 0xDA DHD Login Information lbits:1 d9 AL_PA 0xD9 DHD Login Information lbits:1 d6 AL_PA 0xD6 DHD Login Information lbits:1 d5 AL_PA 0xD5 DHD Login Information lbits:1 d4 AL_PA 0xD4 DHD Login Information lbits:1 d3 AL_PA 0xD3 DHD Login Information lbits:1 d2 AL_PA 0xD2 DHD Login Information lbits:1 d1 AL_PA 0xD1 DHD Login Information lbits:1 ce AL_PA 0xCE DHD Login Information lbits:1 cd AL_PA 0xCD DHD Login Information lbits:1 cc AL_PA 0xCC DHD Login Information lbits:1 cb AL_PA 0xCB DHD Login Information lbits:1 ca AL_PA 0xCA DHD Login Information lbits:1 c9 AL_PA 0xC9 DHD Login Information lbits:1 c7 AL_PA 0xC7 DHD Login Information lbits:1 c6 AL_PA 0xC6 DHD Login Information lbits:1 c5 AL_PA 0xC5 DHD Login Information lbits:1 c3 AL_PA 0xC3 DHD Login Information lbits:1 bc AL_PA 0xBC DHD Login Information lbits:1 ba AL_PA 0xBA DHD Login Information lbits:1 b9 AL_PA 0xB9 DHD Login Information lbits:1 b6 AL_PA 0xB6 DHD Login Information lbits:1 b5 AL_PA 0xB5 DHD Login Information lbits:1 b4 AL_PA 0xB4 DHD Login Information lbits:1 b3 AL_PA 0xB3 DHD Login Information {} or dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 6968> ulong value As longword endunion dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 6972> union dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2

<byte 6972> {field (By field)} <byte 6972> lbits:1 alpab2 AL_PA 0xB2 DHD Login Information lbits:1 alpab1 AL_PA 0xB1 DHD Login Information lbits:1 alpaae AL_PA 0xAE DHD Login Information lbits:1 alpaad AL_PA 0xAD DHD Login Information lbits:1 alpaac AL_PA 0xAC DHD Login Information lbits:1 alpaab AL_PA 0xAB DHD Login Information lbits:1 alpaaa AL_PA 0xAA DHD Login Information lbits:1 alpaa9 AL_PA 0xA9 DHD Login Information lbits:1 alpaa7 AL_PA 0xA7 DHD Login Information lbits:1 alpaa6 AL_PA 0xA6 DHD Login Information lbits:1 alpaa5 AL_PA 0xA5 DHD Login Information lbits:1 alpaa3 AL_PA 0xA3 DHD Login Information lbits:1 alpa9f AL_PA 0x9F DHD Login Information lbits:1 alpa9e AL_PA 0x9E DHD Login Information lbits:1 alpa9d AL_PA 0x9D DHD Login Information lbits:1 alpa9b AL_PA 0x9B DHD Login Information lbits:1 alpa98 AL_PA 0x98 DHD Login Information lbits:1 alpa97 AL_PA 0x97 DHD Login Information lbits:1 alpa90 AL_PA 0x90 DHD Login Information lbits:1 alpa8f AL_PA 0x8F DHD Login Information lbits:1 alpa88 AL_PA 0x88 DHD Login Information lbits:1 alpa84 AL_PA 0x84 DHD Login Information lbits:1 alpa82 AL_PA 0x82 DHD Login Information lbits:1 alpa81 AL_PA 0x81 DHD Login Information lbits:1 alpa80 AL_PA 0x80 DHD Login Information lbits:1 alpa7c AL_PA 0x7C DHD Login Information lbits:1 alpa7a AL_PA 0x7A DHD Login Information lbits:1 alpa79 AL_PA 0x79 DHD Login Information lbits:1 alpa76 AL_PA 0x76 DHD Login Information lbits:1 alpa75 AL_PA 0x75 DHD Login Information lbits:1 alpa74 AL_PA 0x74 DHD Login Information lbits:1 alpa73 AL_PA 0x73 DHD Login Information {} or dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 6972> ulong value As longword endunion dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 6976> union dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 6976> {field (By field)} <byte 6976> lbits:1 alpa72 AL_PA 0x72 DHD Login Information lbits:1 alpa71 AL_PA 0x71 DHD Login Information lbits:1 alpa6e AL_PA 0x6E DHD Login Information lbits:1 alpa6d AL_PA 0x6D DHD Login Information lbits:1 alpa6c AL_PA 0x6C DHD Login Information lbits:1 alpa6b AL_PA 0x6B DHD Login Information lbits:1 alpa6a AL_PA 0x6A DHD Login Information lbits:1 alpa69 AL_PA 0x69 DHD Login Information lbits:1 alpa67 AL_PA 0x67 DHD Login Information lbits:1 alpa66 AL_PA 0x66 DHD Login Information lbits:1 alpa65 AL_PA 0x65 DHD Login Information lbits:1 alpa63 AL_PA 0x63 DHD Login Information lbits:1 alpa5c AL_PA 0x5C DHD Login Information lbits:1 alpa5a AL_PA 0x5A DHD Login Information lbits:1 alpa59 AL_PA 0x59 DHD Login Information

lbits:1 alpa56 AL_PA 0x56 DHD Login Information lbits:1 alpa55 AL_PA 0x55 DHD Login Information lbits:1 alpa54 AL_PA 0x54 DHD Login Information lbits:1 alpa53 AL_PA 0x53 DHD Login Information lbits:1 alpa52 AL_PA 0x52 DHD Login Information lbits:1 alpa51 AL_PA 0x51 DHD Login Information lbits:1 alpa4e AL_PA 0x4E DHD Login Information lbits:1 alpa4d AL_PA 0x4D DHD Login Information lbits:1 alpa4c AL_PA 0x4C DHD Login Information lbits:1 alpa4b AL_PA 0x4B DHD Login Information lbits:1 alpa4a AL_PA 0x4A DHD Login Information lbits:1 alpa49 AL_PA 0x49 DHD Login Information lbits:1 alpa47 AL_PA 0x47 DHD Login Information lbits:1 alpa46 AL_PA 0x46 DHD Login Information lbits:1 alpa45 AL_PA 0x45 DHD Login Information lbits:1 alpa43 AL_PA 0x43 DHD Login Information lbits:1 alpa3c AL_PA 0x3C DHD Login Information {} or dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 6976> ulong value As longword endunion dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 6980> union dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 6980> {field (By field)} <byte 6980> lbits:1 alpa3a AL_PA 0x3A DHD Login Information lbits:1 alpa39 AL_PA 0x39 DHD Login Information lbits:1 alpa36 AL_PA 0x36 DHD Login Information lbits:1 alpa35 AL_PA 0x35 DHD Login Information lbits:1 alpa34 AL_PA 0x34 DHD Login Information lbits:1 alpa33 AL_PA 0x33 DHD Login Information lbits:1 alpa32 AL_PA 0x32 DHD Login Information lbits:1 alpa31 AL_PA 0x31 DHD Login Information lbits:1 alpa2e AL_PA 0x2E DHD Login Information lbits:1 alpa2d AL_PA 0x2D DHD Login Information lbits:1 alpa2c AL_PA 0x2C DHD Login Information lbits:1 alpa2b AL_PA 0x2B DHD Login Information lbits:1 alpa2a AL_PA 0x2A DHD Login Information lbits:1 alpa29 AL_PA 0x29 DHD Login Information lbits:1 alpa27 AL_PA 0x27 DHD Login Information lbits:1 alpa26 AL_PA 0x26 DHD Login Information lbits:1 alpa25 AL_PA 0x25 DHD Login Information lbits:1 alpa23 AL_PA 0x23 DHD Login Information lbits:1 alpa1f AL_PA 0x1F DHD Login Information lbits:1 alpa1e AL_PA 0x1E DHD Login Information lbits:1 alpa1d AL_PA 0x1D DHD Login Information lbits:1 alpa1b AL_PA 0x1B DHD Login Information lbits:1 alpa18 AL_PA 0x18 DHD Login Information lbits:1 alpa17 AL_PA 0x17 DHD Login Information lbits:1 alpa10 AL_PA 0x10 DHD Login Information lbits:1 alpa0f AL_PA 0x0F DHD Login Information lbits:1 alpa08 AL_PA 0x08 DHD Login Information lbits:1 alpa04 AL_PA 0x04 DHD Login Information lbits:1 alpa02 AL_PA 0x02 DHD Login Information lbits:1 alpa01 AL_PA 0x01 DHD Login Information lbits:1 alpa00 AL_PA 0x00 DHD Login Information lbits:1 reserved Reserved {}

or dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 6980> ulong value As longword endunion dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 6984> union fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 6984> {field (By field)} <byte 6984> lbits:1 bli Bypass Loop Initialization lbits:1 reserved Reserved lbits:1 enp Enable N_Port Mode lbits:1 lr Login Required lbits:1 inif Initialize as Fabric lbits:1 rf Respond to Fabric Address lbits:1 blm Bypass Loop Map lbits:1 sa Acquire Soft Address lbits:1 ha Acquire Hard Address lbits:1 aq Acquire Previously Acquired Address lbits:1 fa Acquire Fabric Aquired Address lbits:1 td Timer Disable lbits:1 sap Skip Arbitration Phase lbits:1 elb External Loopback/Pad Loopback lbits:1 ilb Internal loopback lbits:1 npi Initialize as N_Port lbits:8 bb_credit BB_Credit lbits:8 al_pa Desired AL_PA {} or fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 6984> ulong value As longword endunion fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 6988> union fm_control (Offset 1C4) Frame Manager Control <byte 6988> {field (By field)} <byte 6988> lbits:3 cmd State Machine Command lbits:1 cl Close Loop Request lbits:1 reserved Reserved lbits:1 sp Send Prim_Reg lbits:1 sq Primitive Sequence lbits:25 reserved1 Reserved {} or fm_control (Offset 1C4) Frame Manager Control <byte 6988> ulong value As longword endunion fm_control (Offset 1C4) Frame Manager Control <byte 6992> union fm_status (Offset 1C8) Frame Manager Status <byte 6992> {field (By field)} <byte 6992> lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure

lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_status (Offset 1C8) Frame Manager Status <byte 6992> ulong value As longword endunion fm_status (Offset 1C8) Frame Manager Status <byte 6996> union fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 6996> {field (By field)} <byte 6996> lbits:16 ed_tov Error Detect Time-Out lbits:9 rt_tov Receiver Transmitter Time-Out lbits:7 reserved Reserved {} or fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 6996> ulong value As longword endunion fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 7000> union fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 7000> {field (By field)} <byte 7000> lbits:8 link_fail Link Fail Count lbits:8 loss_of_sync Loss of Synchronization Count lbits:8 bad_rx_char Bad Received Character Count lbits:8 loss_of_signal Loss of Signal Count {} or fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 7000> ulong value As longword endunion fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 7004> union fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 7004> {field (By field)} <byte 7004> lbits:8 proto_er Protocol Error Count lbits:8 bad_crc Bad CRC Count lbits:8 dis_frm Discarded Frames lbits:8 rx_eofa Received EOFa

{} or fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 7004> ulong value As longword endunion fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 7008> union fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 7008> {field (By field)} <byte 7008> lbits:9 al_time Arbitrated Loop Time-Out lbits:7 reserved Reserved lbits:16 lp_tov Loop Time-Out {} or fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 7008> ulong value As longword endunion fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 7012> union fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 7012> {field (By field)} <byte 7012> lbits:24 bb0_timer BB_Credit Timer lbits:8 reserved Reserved {} or fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 7012> ulong value As longword endunion fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 7016> union fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 7016> {field (By field)} <byte 7016> lbits:32 wwn World Wide Name {} or fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 7016> ulong value As longword endunion fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 7020> union fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 7020> {field (By field)} <byte 7020> lbits:32 wwn World Wide Name {} or fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 7020> ulong value As longword endunion fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 7024> union fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 7024> {field (By field)} <byte 7024> lbits:8 lipf_alpa AL_PA of Most Recent LIPf Received lbits:8 bad_alpa AL_PA of Most Recent OPN Sent and Returned Without Being Accept ed

lbits:8 acq_alpa AL_PA Acquired During Loop Initialization lbits:8 reserved Reserved {} or fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 7024> ulong value As longword endunion fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 7028> union fm_primitive (Offset 1EC) Frame Manager Primitive <byte 7028> {field (By field)} <byte 7028> lbits:24 prim_value Primitive to be Sent lbits:8 reserved Reserved {} or fm_primitive (Offset 1EC) Frame Manager Primitive <byte 7028> ulong value As longword endunion fm_primitive (Offset 1EC) Frame Manager Primitive <byte 7032> union fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 7032> {field (By field)} <byte 7032> lbits:8 exp_frm Expired Frames lbits:24 reserved Reserved {} or fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 7032> ulong value As longword endunion fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 7036> union fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 7036> {field (By field)} <byte 7036> lbits:1 dac Disable Auto Close lbits:2 nbc Non-zero Login BB_Credit lbits:1 eei Enable ERR_INIT lbits:1 icb Ignore Close Bit lbits:2 atv Arbitration Threshold Value lbits:1 gde Garbage Deletion Enable lbits:8 laa Lowest Allowable AL_PA lbits:5 reserved Reserved lbits:1 dao Disable 2xAL_TIME Timeout on Open lbits:3 reserved1 Reserved lbits:1 prm Promiscuous Mode lbits:1 wpe Wait For Port Enable lbits:1 fmh Force Monitor State With Hard Address lbits:1 fmn Force Monitor Non-participating State lbits:1 dlm Disable Loop Master lbits:1 dsa Disable Soft Address Selection lbits:1 ilp Ignore LPB/LPE Primitive Sequences {} or fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 7036> ulong value As longword endunion fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 7040> union pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED

<byte 7040> {field (By field)} <byte 7040> {pci_rsvd1F8 ((Offset 1F8) Reserved)} <byte 7040> utiny value {} <byte 7041> {pci_rsvd1F9 ((Offset 1F9) Reserved)} <byte 7041> utiny value {} <byte 7042> union romctr (Offset 1FA) PCI ROM Control <byte 7042> {field (By field)} <byte 7042> tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or romctr (Offset 1FA) PCI ROM Control <byte 7042> utiny value As byte endunion romctr (Offset 1FA) PCI ROM Control <byte 7043> union mctr (Offset 1FB) PCI Master Control <byte 7043> {field (By field)} <byte 7043> tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or mctr (Offset 1FB) PCI Master Control <byte 7043> utiny value As byte endunion mctr (Offset 1FB) PCI Master Control {} or pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED <byte 7040> ulong value As longword endunion pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED <byte 7044> union pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST <byte 7044> {field (By field)} <byte 7044> union softrst (Offset 1FC) PCI Interface Reset Control <byte 7044> {field (By field)} <byte 7044> tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or softrst (Offset 1FC) PCI Interface Reset Control <byte 7044> utiny value As byte

endunion softrst (Offset 1FC) PCI Interface Reset Control <byte 7045> union intpend (Offset 1FD) PCI Interrupt Pending <byte 7045> {field (By field)} <byte 7045> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intpend (Offset 1FD) PCI Interrupt Pending <byte 7045> utiny value As byte endunion intpend (Offset 1FD) PCI Interrupt Pending <byte 7046> union inten (Offset 1FE) PCI Interrupt Enable <byte 7046> {field (By field)} <byte 7046> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or inten (Offset 1FE) PCI Interrupt Enable <byte 7046> utiny value As byte endunion inten (Offset 1FE) PCI Interrupt Enable <byte 7047> union intstat (Offset 1FF) PCI Interrupt Status <byte 7047> {field (By field)} <byte 7047> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intstat (Offset 1FF) PCI Interrupt Status <byte 7047> utiny value As byte endunion intstat (Offset 1FF) PCI Interrupt Status {} or pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST <byte 7044> ulong value As longword endunion pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST {} endunion csr[0] Tachyon DX2+ CSR Registers <byte 7048> union csr[1] Tachyon DX2+ CSR Registers <byte 7048> ulong[128] csra Tachyon DX2+ CSR Registers As Longwords

or csr[1] Tachyon DX2+ CSR Registers <byte 7048> {csr (Tachyon DX2+ CSR Registers By Field)} <byte 7048> union erq_base (Offset 000) ERQ Base (write only) <byte 7048> {field (By field)} <byte 7048> lbits:32 address ERQ Base Address {} or erq_base (Offset 000) ERQ Base (write only) <byte 7048> ulong value As longword endunion erq_base (Offset 000) ERQ Base (write only) <byte 7052> union erq_len (Offset 004) ERQ Length (write only) <byte 7052> {field (By field)} <byte 7052> lbits:12 length ERQ Length lbits:20 reserved Reserved {} or erq_len (Offset 004) ERQ Length (write only) <byte 7052> ulong value As longword endunion erq_len (Offset 004) ERQ Length (write only) <byte 7056> union erq_prod (Offset 008) ERQ Producer Index <byte 7056> {field (By field)} <byte 7056> lbits:12 index ERQ Producer Index lbits:20 reserved Reserved {} or erq_prod (Offset 008) ERQ Producer Index <byte 7056> ulong value As longword endunion erq_prod (Offset 008) ERQ Producer Index <byte 7060> union erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 7060> {field (By field)} <byte 7060> lbits:32 address ERQ Consumer Index Address {} or erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 7060> ulong value As longword endunion erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 7064> union erq_cons (Offset 010) ERQ Consumer Index <byte 7064> {field (By field)} <byte 7064> lbits:12 index ERQ Consumer Index lbits:20 reserved Reserved {} or erq_cons (Offset 010) ERQ Consumer Index <byte 7064> ulong value As longword

endunion erq_cons (Offset 010) ERQ Consumer Index <byte 7068> {rsvd1[0] ((Offset 014-04F) Reserved)} <byte 7068> ulong value {} <byte 7072> {rsvd1[1] ((Offset 014-04F) Reserved)} <byte 7072> ulong value {} <byte 7076> {rsvd1[2] ((Offset 014-04F) Reserved)} <byte 7076> ulong value {} <byte 7080> {rsvd1[3] ((Offset 014-04F) Reserved)} <byte 7080> ulong value {} <byte 7084> {rsvd1[4] ((Offset 014-04F) Reserved)} <byte 7084> ulong value {} <byte 7088> {rsvd1[5] ((Offset 014-04F) Reserved)} <byte 7088> ulong value {} <byte 7092> {rsvd1[6] ((Offset 014-04F) Reserved)} <byte 7092> ulong value {} <byte 7096> {rsvd1[7] ((Offset 014-04F) Reserved)} <byte 7096> ulong value {} <byte 7100> {rsvd1[8] ((Offset 014-04F) Reserved)} <byte 7100> ulong value {} <byte 7104> {rsvd1[9] ((Offset 014-04F) Reserved)} <byte 7104> ulong value {} <byte 7108> {rsvd1[10] ((Offset 014-04F) Reserved)} <byte 7108> ulong value {} <byte 7112> {rsvd1[11] ((Offset 014-04F) Reserved)} <byte 7112> ulong value

{} <byte 7116> {rsvd1[12] ((Offset 014-04F) Reserved)} <byte 7116> ulong value {} <byte 7120> {rsvd1[13] ((Offset 014-04F) Reserved)} <byte 7120> ulong value {} <byte 7124> {rsvd1[14] ((Offset 014-04F) Reserved)} <byte 7124> ulong value {} <byte 7128> union sfq_base (Offset 050) SFQ Base (write only) <byte 7128> {field (By field)} <byte 7128> lbits:32 address SFQ Base Address {} or sfq_base (Offset 050) SFQ Base (write only) <byte 7128> ulong value As longword endunion sfq_base (Offset 050) SFQ Base (write only) <byte 7132> union sfq_len (Offset 054) SFQ Length (write only) <byte 7132> {field (By field)} <byte 7132> lbits:12 length SFQ Length lbits:20 reserved Reserved {} or sfq_len (Offset 054) SFQ Length (write only) <byte 7132> ulong value As longword endunion sfq_len (Offset 054) SFQ Length (write only) <byte 7136> union sfq_cons (Offset 058) SFQ Consumer Index <byte 7136> {field (By field)} <byte 7136> lbits:12 index SFQ Consumer Index lbits:20 reserved Reserved {} or sfq_cons (Offset 058) SFQ Consumer Index <byte 7136> ulong value As longword endunion sfq_cons (Offset 058) SFQ Consumer Index <byte 7140> {rsvd2[0] ((Offset 05C-07B) Reserved)} <byte 7140> ulong value {} <byte 7144> {rsvd2[1] ((Offset 05C-07B) Reserved)} <byte 7144> ulong value

{} <byte 7148> {rsvd2[2] ((Offset 05C-07B) Reserved)} <byte 7148> ulong value {} <byte 7152> {rsvd2[3] ((Offset 05C-07B) Reserved)} <byte 7152> ulong value {} <byte 7156> {rsvd2[4] ((Offset 05C-07B) Reserved)} <byte 7156> ulong value {} <byte 7160> {rsvd2[5] ((Offset 05C-07B) Reserved)} <byte 7160> ulong value {} <byte 7164> {rsvd2[6] ((Offset 05C-07B) Reserved)} <byte 7164> ulong value {} <byte 7168> {rsvd2[7] ((Offset 05C-07B) Reserved)} <byte 7168> ulong value {} <byte 7172> union int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 7172> {field (By field)} <byte 7172> lbits:4 timer Interrupt Timer Value lbits:3 reserved Reserved lbits:1 ihf Interrupt when IMQ Half Full lbits:24 reserved1 Reserved {} or int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 7172> ulong value As longword endunion int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 7176> union imq_base (Offset 080) IMQ Base (write only) <byte 7176> {field (By field)} <byte 7176> lbits:32 address IMQ Base Address {} or imq_base (Offset 080) IMQ Base (write only) <byte 7176> ulong value As longword endunion imq_base (Offset 080) IMQ Base (write only) <byte 7180> union imq_len (Offset 084) IMQ Length (write only) <byte 7180> {field (By field)}

<byte 7180> lbits:12 length IMQ Length lbits:20 reserved Reserved {} or imq_len (Offset 084) IMQ Length (write only) <byte 7180> ulong value As longword endunion imq_len (Offset 084) IMQ Length (write only) <byte 7184> union imq_cons (Offset 088) IMQ Consumer Index <byte 7184> {field (By field)} <byte 7184> lbits:12 index IMQ Consumer Index lbits:20 reserved Reserved {} or imq_cons (Offset 088) IMQ Consumer Index <byte 7184> ulong value As longword endunion imq_cons (Offset 088) IMQ Consumer Index <byte 7188> union imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 7188> {field (By field)} <byte 7188> lbits:32 address IMQ Producer Index Address {} or imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 7188> ulong value As longword endunion imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 7192> {rsvd3[0] ((Offset 090-0FC) Reserved)} <byte 7192> ulong value {} <byte 7196> {rsvd3[1] ((Offset 090-0FC) Reserved)} <byte 7196> ulong value {} <byte 7200> {rsvd3[2] ((Offset 090-0FC) Reserved)} <byte 7200> ulong value {} <byte 7204> {rsvd3[3] ((Offset 090-0FC) Reserved)} <byte 7204> ulong value {} <byte 7208> {rsvd3[4] ((Offset 090-0FC) Reserved)} <byte 7208> ulong value {} <byte 7212> {rsvd3[5] ((Offset 090-0FC) Reserved)} <byte 7212> ulong value

{} <byte 7216> {rsvd3[6] ((Offset 090-0FC) Reserved)} <byte 7216> ulong value {} <byte 7220> {rsvd3[7] ((Offset 090-0FC) Reserved)} <byte 7220> ulong value {} <byte 7224> {rsvd3[8] ((Offset 090-0FC) Reserved)} <byte 7224> ulong value {} <byte 7228> {rsvd3[9] ((Offset 090-0FC) Reserved)} <byte 7228> ulong value {} <byte 7232> {rsvd3[10] ((Offset 090-0FC) Reserved)} <byte 7232> ulong value {} <byte 7236> {rsvd3[11] ((Offset 090-0FC) Reserved)} <byte 7236> ulong value {} <byte 7240> {rsvd3[12] ((Offset 090-0FC) Reserved)} <byte 7240> ulong value {} <byte 7244> {rsvd3[13] ((Offset 090-0FC) Reserved)} <byte 7244> ulong value {} <byte 7248> {rsvd3[14] ((Offset 090-0FC) Reserved)} <byte 7248> ulong value {} <byte 7252> {rsvd3[15] ((Offset 090-0FC) Reserved)} <byte 7252> ulong value {} <byte 7256> {rsvd3[16] ((Offset 090-0FC) Reserved)} <byte 7256> ulong value {} <byte 7260> {rsvd3[17] ((Offset 090-0FC) Reserved)} <byte 7260> ulong value

{} <byte 7264> {rsvd3[18] ((Offset 090-0FC) Reserved)} <byte 7264> ulong value {} <byte 7268> {rsvd3[19] ((Offset 090-0FC) Reserved)} <byte 7268> ulong value {} <byte 7272> {rsvd3[20] ((Offset 090-0FC) Reserved)} <byte 7272> ulong value {} <byte 7276> {rsvd3[21] ((Offset 090-0FC) Reserved)} <byte 7276> ulong value {} <byte 7280> {rsvd3[22] ((Offset 090-0FC) Reserved)} <byte 7280> ulong value {} <byte 7284> {rsvd3[23] ((Offset 090-0FC) Reserved)} <byte 7284> ulong value {} <byte 7288> {rsvd3[24] ((Offset 090-0FC) Reserved)} <byte 7288> ulong value {} <byte 7292> {rsvd3[25] ((Offset 090-0FC) Reserved)} <byte 7292> ulong value {} <byte 7296> {rsvd3[26] ((Offset 090-0FC) Reserved)} <byte 7296> ulong value {} <byte 7300> {rsvd3[27] ((Offset 090-0FC) Reserved)} <byte 7300> ulong value {} <byte 7304> union fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 7304> {field (By field)} <byte 7304> lbits:6 bec Termination Receive lbits:3 reserved4 Reserved lbits:1 xrb Wrapback lbits:2 reserved Reserved

lbits:3 xem Output pre-emphasis lbits:4 reserved1 Reserved lbits:1 mustbe1 Must be 1 lbits:1 stb Start BERT lbits:1 enb Enable BERT lbits:2 sdm Signal differential mode lbits:2 rxs Receiver Speed lbits:2 txs Transmitter Speed lbits:1 reserved3 Reserved lbits:1 xlr Force iTR to lock reference clock lbits:1 reserved0 Reserved lbits:1 xcv Type of Transceiver {} or fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 7304> ulong value As longword endunion fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 7308> union fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 7308> {field (By field)} <byte 7308> lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 7308> ulong value As longword endunion fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 7312> {rsvd3a[0] ((Offset 108-10f) Reserved)} <byte 7312> ulong value {} <byte 7316> {rsvd3a[1] ((Offset 108-10f) Reserved)}

<byte 7316> ulong value {} <byte 7320> union sfp_cmd_status (Offset 110) SFP command and status <byte 7320> {field (No description available)} <byte 7320> lbits:1 gna Generate NACK lbits:1 rts Reset Slave lbits:1 wrc Write command lbits:1 rdc Read command lbits:1 gst Generate Stop lbits:1 sta Generate Start lbits:2 reserved1 Reserved lbits:1 rna Received NACK lbits:1 sby SFP Busy lbits:1 tip Transfer in progress lbits:9 reserved Reserved lbits:12 lp Clock Divisor {} or sfp_cmd_status (Offset 110) SFP command and status <byte 7320> ulong value endunion sfp_cmd_status (Offset 110) SFP command and status <byte 7324> union sfp_data (Offset 114) SFP data <byte 7324> {field (By field)} <byte 7324> lbits:8 sfpd SFPD Transmit lbits:24 reserved Reserved {} or sfp_data (Offset 114) SFP data <byte 7324> ulong value As longword endunion sfp_data (Offset 114) SFP data <byte 7328> union fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 7328> {field (By field)} <byte 7328> lbits:1 tbe Transmit Link BIST error lbits:1 tlr Transmit Link BIST reset lbits:1 tle Transmit Link BIST enable lbits:1 rbe Receive Link BIST error lbits:1 rll Receive Link BIST loop-back lbits:1 rlr Receive Link BIST reset lbits:1 rle Receive Link BIST enable lbits:7 reserved3 Reserved lbits:1 ipl ITR PPL Lock lbits:1 reserved2 Reserved lbits:1 dtf Disable transceiver LOS filter lbits:1 dtl Disable transceiver LOS lbits:1 dsr Disable iTR RXLOS lbits:1 ttd Transceiver Tx Disable lbits:2 reserved1 Reserved lbits:1 rfl Receive ast Lock Disable lbits:9 reserved Reserved {}

or fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 7328> ulong value As longword endunion fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 7332> union fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 7332> {field (By field)} <byte 7332> lbits:32 reserved Reserved {} or fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 7332> ulong value As longword endunion fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 7336> {rsvd3b[0] ((Offset 120-13F) Reserved)} <byte 7336> ulong value {} <byte 7340> {rsvd3b[1] ((Offset 120-13F) Reserved)} <byte 7340> ulong value {} <byte 7344> {rsvd3b[2] ((Offset 120-13F) Reserved)} <byte 7344> ulong value {} <byte 7348> {rsvd3b[3] ((Offset 120-13F) Reserved)} <byte 7348> ulong value {} <byte 7352> {rsvd3b[4] ((Offset 120-13F) Reserved)} <byte 7352> ulong value {} <byte 7356> {rsvd3b[5] ((Offset 120-13F) Reserved)} <byte 7356> ulong value {} <byte 7360> {rsvd3b[6] ((Offset 120-13F) Reserved)} <byte 7360> ulong value {} <byte 7364> {rsvd3b[7] ((Offset 120-13F) Reserved)} <byte 7364> ulong value {} <byte 7368> union sest_base (Offset 140) SEST Base (write only) <byte 7368> {field (By field)} <byte 7368>

lbits:32 address SEST Base Address {} or sest_base (Offset 140) SEST Base (write only) <byte 7368> ulong value As longword endunion sest_base (Offset 140) SEST Base (write only) <byte 7372> union sest_len (Offset 144) SEST Length (write only) <byte 7372> {field (By field)} <byte 7372> lbits:16 length SEST Length lbits:16 reserved Reserved {} or sest_len (Offset 144) SEST Length (write only) <byte 7372> ulong value As longword endunion sest_len (Offset 144) SEST Length (write only) <byte 7376> {rsvd4 ((Offset 148) Reserved)} <byte 7376> ulong value {} <byte 7380> union scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 7380> {field (By field)} <byte 7380> lbits:16 tail Tail lbits:16 head Head {} or scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 7380> ulong value As longword endunion scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 7384> union prog_addr (Offset 150) Programmable Address register <byte 7384> {field (By field)} <byte 7384> lbits:20 ra ROM/RAM address lbits:11 reserved Reserved lbits:1 inc Increment {} or prog_addr (Offset 150) Programmable Address register <byte 7384> ulong value As longword endunion prog_addr (Offset 150) Programmable Address register <byte 7388> union prog_data (Offset 154) programmable data register <byte 7388> {field (By field)} <byte 7388> lbits:32 pdr Programmable data {} or prog_data (Offset 154) programmable data register <byte 7388> ulong value As longword endunion prog_data (Offset 154) programmable data register <byte 7392>

{rsvd5[0] ((Offset 158-15F) Reserved)} <byte 7392> ulong value {} <byte 7396> {rsvd5[1] ((Offset 158-15F) Reserved)} <byte 7396> ulong value {} <byte 7400> union int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 7400> {field (By field)} <byte 7400> lbits:32 address Interrupt Message Address {} or int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 7400> ulong value As longword endunion int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 7404> union int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 7404> {field (By field)} <byte 7404> lbits:32 value Interrupt Message Value {} or int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 7404> ulong value As longword endunion int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 7408> union sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 7408> {field (By field)} <byte 7408> lbits:8 length SGL Page Length lbits:24 reserved Reserved {} or sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 7408> ulong value As longword endunion sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 7412> union my_id (Offset 16C) My ID <byte 7412> {field (By field)} <byte 7412> lbits:24 id My ID lbits:8 reserved Reserved {} or my_id (Offset 16C) My ID <byte 7412> ulong value As longword endunion my_id (Offset 16C) My ID <byte 7416> union gpio (Offset 170) General Purpose I/O <byte 7416> {field (By field)} <byte 7416>

lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:1 gc5 General Purpose Control 5 lbits:1 gc6 General Purpose Control 6 lbits:1 gc7 General Purpose Control 7 lbits:8 reserved Reserved lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose I/O 4 lbits:1 gp5 General Purpose I/O 5 lbits:1 gp6 General Purpose I/O 6 lbits:1 gp7 General Purpose I/O 7 lbits:8 reserved1 Reserved {} or gpio (Offset 170) General Purpose I/O <byte 7416> ulong value As longword endunion gpio (Offset 170) General Purpose I/O <byte 7420> {rsvd6a ((Offset 174-177) Reserved)} <byte 7420> ulong value {} <byte 7424> union edc_config (Offset 178) EDC Configuration Register <byte 7424> {field (By field)} <byte 7424> lbits:16 io_seed Starting Seed lbits:16 reserved Reserved {} or edc_config (Offset 178) EDC Configuration Register <byte 7424> ulong value As longword endunion edc_config (Offset 178) EDC Configuration Register <byte 7428> union dx4_config3 (Offset 17C) DX4 Configuration Register 3 <byte 7428> {field (By field)} <byte 7428> lbits:9 pfs2 Programmable Frame size field 2 lbits:9 pfs3 Programmable Frame size field 3 lbits:9 pfs4 Programmable Frame size field 4 lbits:5 reserved Reserved {} or dx4_config3 (Offset 17C) DX4 Configuration Register 3 <byte 7428> ulong value As longword endunion dx4_config3 (Offset 17C) DX4 Configuration Register 3 <byte 7432> union tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 7432> {field (By field)} <byte 7432> lbits:9 pfs Programmable Frame Size

lbits:15 reserved Reserved lbits:8 esi_range Exchange_ID Signaled Interrupt Range {} or tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 7432> ulong value As longword endunion tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 7436> union tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 7436> {field (By field)} <byte 7436> lbits:1 fad FCP Assist Disable lbits:1 ino In Order lbits:1 dof Discard OOO FCP Frames lbits:1 fua FCP Unassisted ACK Enable lbits:1 ime Interrupt Message Enable lbits:1 fab Fabric lbits:1 sic S_ID Copy Enable lbits:1 eqs Equal Service lbits:2 reserved Reserved lbits:1 aks Automatic ACK lbits:1 ddf Disable Delayed Freeze lbits:1 ebe Enable Big Endian Mode lbits:11 reserved1 Reserved lbits:1 fc2 FCP Class 2 Reassembly Enable lbits:1 reserved2 Reserved lbits:1 sdf Save Discarded Frames lbits:1 rde Response Detect Enable lbits:1 dam Default ACK Model lbits:2 reserved3 Reserved lbits:1 m66 66 MHz Enabled {} or tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 7436> ulong value As longword endunion tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 7440> union tach_control (Offset 188) Tachyon DX2+ Control <byte 7440> {field (By field)} <byte 7440> lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:3 reserved Reserved lbits:1 feq Freeze ERQ lbits:1 ffa Freeze FCP Assists lbits:2 reserved1 Reserved lbits:1 fis Freeze Inbound FCP Assists When Frame Placed in SFQ lbits:1 fib Freeze Inbound FCP Assists lbits:2 reserved2 Reserved lbits:1 req Resume ERQ lbits:1 rif Resume Inbound FCP Assists lbits:1 rof Resume Outbound FCP Assists lbits:12 reserved3 Reserved lbits:1 crs Core Reset {}

or tach_control (Offset 188) Tachyon DX2+ Control <byte 7440> ulong value As longword endunion tach_control (Offset 188) Tachyon DX2+ Control <byte 7444> union tach_status (Offset 18C) Tachyon DX2+ Status <byte 7444> {field (By field)} <byte 7444> lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose Input 4 lbits:5 reserved Reserved lbits:1 ipe Inbound Parity Error lbits:1 ope Outbound Parity Error lbits:4 reserved1 Reserved lbits:1 eqf ERQ Frozen lbits:1 iff Inbound FCP Assists Frozen lbits:1 off Outbound FCP Assists Frozen lbits:4 reserved2 Reserved lbits:1 ifce Inbound FIFO CRC Error lbits:1 ofce Outbound FIFO CRC Error lbits:1 m66 66 Mhz Enabled lbits:1 ile Inbound Link Control FIFO Empty lbits:1 ole Outbound Link Control List Empty lbits:1 ife Inbound FIFO Empty lbits:1 ofe Outbound FIFO Empty lbits:1 imf IMQ Full lbits:1 ssf SFQ Full {} or tach_status (Offset 18C) Tachyon DX2+ Status <byte 7444> ulong value As longword endunion tach_status (Offset 18C) Tachyon DX2+ Status <byte 7448> {rsvd7 ((Offset 190) Reserved)} <byte 7448> ulong value {} <byte 7452> union hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 7452> {field (By field)} <byte 7452> lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 7452> ulong value As longword endunion hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 7456> union hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 7456> {field (By field)} <byte 7456>

lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 7456> ulong value As longword endunion hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 7460> union inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 7460> {field (By field)} <byte 7460> lbits:24 reserved Reserved lbits:8 sest_lru_count SEST LRU Count {} or inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 7460> ulong value As longword endunion inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 7464> union inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 7464> {field (By field)} <byte 7464> lbits:8 discd_frames Discarded Frame Count lbits:24 reserved Reserved {} or inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 7464> ulong value As longword endunion inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 7468> union ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) <byte 7468> {field (By field)} <byte 7468> lbits:28 threshold EE_Credit Zero Timer Threshold lbits:4 reserved Reserved {} or ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) <byte 7468> ulong value As longword endunion ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only ) <byte 7472> union up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 7472> {field (By field)} <byte 7472> lbits:12 reserved Reserved lbits:1 upper_addr1 Upper Data Address--44 bit data space lbits:19 upper_addr Upper Data Address {} or up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 7472> ulong value As longword endunion up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 7476>

union up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 7476> {field (By field)} <byte 7476> lbits:32 upper_addr Upper Control Address {} or up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 7476> ulong value As longword endunion up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 7480> union dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 7480> {field (By field)} <byte 7480> lbits:1 ef AL_PA 0xEF DHD Login Information lbits:1 e8 AL_PA 0xE8 DHD Login Information lbits:1 e4 AL_PA 0xE4 DHD Login Information lbits:1 e2 AL_PA 0xE2 DHD Login Information lbits:1 e1 AL_PA 0xE1 DHD Login Information lbits:1 e0 AL_PA 0xE0 DHD Login Information lbits:1 dc AL_PA 0xDC DHD Login Information lbits:1 da AL_PA 0xDA DHD Login Information lbits:1 d9 AL_PA 0xD9 DHD Login Information lbits:1 d6 AL_PA 0xD6 DHD Login Information lbits:1 d5 AL_PA 0xD5 DHD Login Information lbits:1 d4 AL_PA 0xD4 DHD Login Information lbits:1 d3 AL_PA 0xD3 DHD Login Information lbits:1 d2 AL_PA 0xD2 DHD Login Information lbits:1 d1 AL_PA 0xD1 DHD Login Information lbits:1 ce AL_PA 0xCE DHD Login Information lbits:1 cd AL_PA 0xCD DHD Login Information lbits:1 cc AL_PA 0xCC DHD Login Information lbits:1 cb AL_PA 0xCB DHD Login Information lbits:1 ca AL_PA 0xCA DHD Login Information lbits:1 c9 AL_PA 0xC9 DHD Login Information lbits:1 c7 AL_PA 0xC7 DHD Login Information lbits:1 c6 AL_PA 0xC6 DHD Login Information lbits:1 c5 AL_PA 0xC5 DHD Login Information lbits:1 c3 AL_PA 0xC3 DHD Login Information lbits:1 bc AL_PA 0xBC DHD Login Information lbits:1 ba AL_PA 0xBA DHD Login Information lbits:1 b9 AL_PA 0xB9 DHD Login Information lbits:1 b6 AL_PA 0xB6 DHD Login Information lbits:1 b5 AL_PA 0xB5 DHD Login Information lbits:1 b4 AL_PA 0xB4 DHD Login Information lbits:1 b3 AL_PA 0xB3 DHD Login Information {} or dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 7480> ulong value As longword endunion dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 7484> union dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 7484> {field (By field)} <byte 7484> lbits:1 alpab2 AL_PA 0xB2 DHD Login Information lbits:1 alpab1 AL_PA 0xB1 DHD Login Information lbits:1 alpaae AL_PA 0xAE DHD Login Information

lbits:1 alpaad AL_PA 0xAD DHD Login Information lbits:1 alpaac AL_PA 0xAC DHD Login Information lbits:1 alpaab AL_PA 0xAB DHD Login Information lbits:1 alpaaa AL_PA 0xAA DHD Login Information lbits:1 alpaa9 AL_PA 0xA9 DHD Login Information lbits:1 alpaa7 AL_PA 0xA7 DHD Login Information lbits:1 alpaa6 AL_PA 0xA6 DHD Login Information lbits:1 alpaa5 AL_PA 0xA5 DHD Login Information lbits:1 alpaa3 AL_PA 0xA3 DHD Login Information lbits:1 alpa9f AL_PA 0x9F DHD Login Information lbits:1 alpa9e AL_PA 0x9E DHD Login Information lbits:1 alpa9d AL_PA 0x9D DHD Login Information lbits:1 alpa9b AL_PA 0x9B DHD Login Information lbits:1 alpa98 AL_PA 0x98 DHD Login Information lbits:1 alpa97 AL_PA 0x97 DHD Login Information lbits:1 alpa90 AL_PA 0x90 DHD Login Information lbits:1 alpa8f AL_PA 0x8F DHD Login Information lbits:1 alpa88 AL_PA 0x88 DHD Login Information lbits:1 alpa84 AL_PA 0x84 DHD Login Information lbits:1 alpa82 AL_PA 0x82 DHD Login Information lbits:1 alpa81 AL_PA 0x81 DHD Login Information lbits:1 alpa80 AL_PA 0x80 DHD Login Information lbits:1 alpa7c AL_PA 0x7C DHD Login Information lbits:1 alpa7a AL_PA 0x7A DHD Login Information lbits:1 alpa79 AL_PA 0x79 DHD Login Information lbits:1 alpa76 AL_PA 0x76 DHD Login Information lbits:1 alpa75 AL_PA 0x75 DHD Login Information lbits:1 alpa74 AL_PA 0x74 DHD Login Information lbits:1 alpa73 AL_PA 0x73 DHD Login Information {} or dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 7484> ulong value As longword endunion dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 7488> union dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 7488> {field (By field)} <byte 7488> lbits:1 alpa72 AL_PA 0x72 DHD Login Information lbits:1 alpa71 AL_PA 0x71 DHD Login Information lbits:1 alpa6e AL_PA 0x6E DHD Login Information lbits:1 alpa6d AL_PA 0x6D DHD Login Information lbits:1 alpa6c AL_PA 0x6C DHD Login Information lbits:1 alpa6b AL_PA 0x6B DHD Login Information lbits:1 alpa6a AL_PA 0x6A DHD Login Information lbits:1 alpa69 AL_PA 0x69 DHD Login Information lbits:1 alpa67 AL_PA 0x67 DHD Login Information lbits:1 alpa66 AL_PA 0x66 DHD Login Information lbits:1 alpa65 AL_PA 0x65 DHD Login Information lbits:1 alpa63 AL_PA 0x63 DHD Login Information lbits:1 alpa5c AL_PA 0x5C DHD Login Information lbits:1 alpa5a AL_PA 0x5A DHD Login Information lbits:1 alpa59 AL_PA 0x59 DHD Login Information lbits:1 alpa56 AL_PA 0x56 DHD Login Information lbits:1 alpa55 AL_PA 0x55 DHD Login Information lbits:1 alpa54 AL_PA 0x54 DHD Login Information lbits:1 alpa53 AL_PA 0x53 DHD Login Information lbits:1 alpa52 AL_PA 0x52 DHD Login Information lbits:1 alpa51 AL_PA 0x51 DHD Login Information

lbits:1 alpa4e AL_PA 0x4E DHD Login Information lbits:1 alpa4d AL_PA 0x4D DHD Login Information lbits:1 alpa4c AL_PA 0x4C DHD Login Information lbits:1 alpa4b AL_PA 0x4B DHD Login Information lbits:1 alpa4a AL_PA 0x4A DHD Login Information lbits:1 alpa49 AL_PA 0x49 DHD Login Information lbits:1 alpa47 AL_PA 0x47 DHD Login Information lbits:1 alpa46 AL_PA 0x46 DHD Login Information lbits:1 alpa45 AL_PA 0x45 DHD Login Information lbits:1 alpa43 AL_PA 0x43 DHD Login Information lbits:1 alpa3c AL_PA 0x3C DHD Login Information {} or dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 7488> ulong value As longword endunion dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 7492> union dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 7492> {field (By field)} <byte 7492> lbits:1 alpa3a AL_PA 0x3A DHD Login Information lbits:1 alpa39 AL_PA 0x39 DHD Login Information lbits:1 alpa36 AL_PA 0x36 DHD Login Information lbits:1 alpa35 AL_PA 0x35 DHD Login Information lbits:1 alpa34 AL_PA 0x34 DHD Login Information lbits:1 alpa33 AL_PA 0x33 DHD Login Information lbits:1 alpa32 AL_PA 0x32 DHD Login Information lbits:1 alpa31 AL_PA 0x31 DHD Login Information lbits:1 alpa2e AL_PA 0x2E DHD Login Information lbits:1 alpa2d AL_PA 0x2D DHD Login Information lbits:1 alpa2c AL_PA 0x2C DHD Login Information lbits:1 alpa2b AL_PA 0x2B DHD Login Information lbits:1 alpa2a AL_PA 0x2A DHD Login Information lbits:1 alpa29 AL_PA 0x29 DHD Login Information lbits:1 alpa27 AL_PA 0x27 DHD Login Information lbits:1 alpa26 AL_PA 0x26 DHD Login Information lbits:1 alpa25 AL_PA 0x25 DHD Login Information lbits:1 alpa23 AL_PA 0x23 DHD Login Information lbits:1 alpa1f AL_PA 0x1F DHD Login Information lbits:1 alpa1e AL_PA 0x1E DHD Login Information lbits:1 alpa1d AL_PA 0x1D DHD Login Information lbits:1 alpa1b AL_PA 0x1B DHD Login Information lbits:1 alpa18 AL_PA 0x18 DHD Login Information lbits:1 alpa17 AL_PA 0x17 DHD Login Information lbits:1 alpa10 AL_PA 0x10 DHD Login Information lbits:1 alpa0f AL_PA 0x0F DHD Login Information lbits:1 alpa08 AL_PA 0x08 DHD Login Information lbits:1 alpa04 AL_PA 0x04 DHD Login Information lbits:1 alpa02 AL_PA 0x02 DHD Login Information lbits:1 alpa01 AL_PA 0x01 DHD Login Information lbits:1 alpa00 AL_PA 0x00 DHD Login Information lbits:1 reserved Reserved {} or dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 7492> ulong value As longword endunion dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 7496> union fm_config1 (Offset 1C0) Frame Manager Configuration 1

<byte 7496> {field (By field)} <byte 7496> lbits:1 bli Bypass Loop Initialization lbits:1 reserved Reserved lbits:1 enp Enable N_Port Mode lbits:1 lr Login Required lbits:1 inif Initialize as Fabric lbits:1 rf Respond to Fabric Address lbits:1 blm Bypass Loop Map lbits:1 sa Acquire Soft Address lbits:1 ha Acquire Hard Address lbits:1 aq Acquire Previously Acquired Address lbits:1 fa Acquire Fabric Aquired Address lbits:1 td Timer Disable lbits:1 sap Skip Arbitration Phase lbits:1 elb External Loopback/Pad Loopback lbits:1 ilb Internal loopback lbits:1 npi Initialize as N_Port lbits:8 bb_credit BB_Credit lbits:8 al_pa Desired AL_PA {} or fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 7496> ulong value As longword endunion fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 7500> union fm_control (Offset 1C4) Frame Manager Control <byte 7500> {field (By field)} <byte 7500> lbits:3 cmd State Machine Command lbits:1 cl Close Loop Request lbits:1 reserved Reserved lbits:1 sp Send Prim_Reg lbits:1 sq Primitive Sequence lbits:25 reserved1 Reserved {} or fm_control (Offset 1C4) Frame Manager Control <byte 7500> ulong value As longword endunion fm_control (Offset 1C4) Frame Manager Control <byte 7504> union fm_status (Offset 1C8) Frame Manager Status <byte 7504> {field (By field)} <byte 7504> lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out

lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_status (Offset 1C8) Frame Manager Status <byte 7504> ulong value As longword endunion fm_status (Offset 1C8) Frame Manager Status <byte 7508> union fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 7508> {field (By field)} <byte 7508> lbits:16 ed_tov Error Detect Time-Out lbits:9 rt_tov Receiver Transmitter Time-Out lbits:7 reserved Reserved {} or fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 7508> ulong value As longword endunion fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 7512> union fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 7512> {field (By field)} <byte 7512> lbits:8 link_fail Link Fail Count lbits:8 loss_of_sync Loss of Synchronization Count lbits:8 bad_rx_char Bad Received Character Count lbits:8 loss_of_signal Loss of Signal Count {} or fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 7512> ulong value As longword endunion fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 7516> union fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 7516> {field (By field)} <byte 7516> lbits:8 proto_er Protocol Error Count lbits:8 bad_crc Bad CRC Count lbits:8 dis_frm Discarded Frames lbits:8 rx_eofa Received EOFa {} or fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 7516> ulong value As longword endunion fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 7520>

union fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 7520> {field (By field)} <byte 7520> lbits:9 al_time Arbitrated Loop Time-Out lbits:7 reserved Reserved lbits:16 lp_tov Loop Time-Out {} or fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 7520> ulong value As longword endunion fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 7524> union fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 7524> {field (By field)} <byte 7524> lbits:24 bb0_timer BB_Credit Timer lbits:8 reserved Reserved {} or fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 7524> ulong value As longword endunion fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 7528> union fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 7528> {field (By field)} <byte 7528> lbits:32 wwn World Wide Name {} or fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 7528> ulong value As longword endunion fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 7532> union fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 7532> {field (By field)} <byte 7532> lbits:32 wwn World Wide Name {} or fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 7532> ulong value As longword endunion fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 7536> union fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 7536> {field (By field)} <byte 7536> lbits:8 lipf_alpa AL_PA of Most Recent LIPf Received lbits:8 bad_alpa AL_PA of Most Recent OPN Sent and Returned Without Being Accept ed lbits:8 acq_alpa AL_PA Acquired During Loop Initialization lbits:8 reserved Reserved {} or fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 7536> ulong value As longword

endunion fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 7540> union fm_primitive (Offset 1EC) Frame Manager Primitive <byte 7540> {field (By field)} <byte 7540> lbits:24 prim_value Primitive to be Sent lbits:8 reserved Reserved {} or fm_primitive (Offset 1EC) Frame Manager Primitive <byte 7540> ulong value As longword endunion fm_primitive (Offset 1EC) Frame Manager Primitive <byte 7544> union fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 7544> {field (By field)} <byte 7544> lbits:8 exp_frm Expired Frames lbits:24 reserved Reserved {} or fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 7544> ulong value As longword endunion fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 7548> union fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 7548> {field (By field)} <byte 7548> lbits:1 dac Disable Auto Close lbits:2 nbc Non-zero Login BB_Credit lbits:1 eei Enable ERR_INIT lbits:1 icb Ignore Close Bit lbits:2 atv Arbitration Threshold Value lbits:1 gde Garbage Deletion Enable lbits:8 laa Lowest Allowable AL_PA lbits:5 reserved Reserved lbits:1 dao Disable 2xAL_TIME Timeout on Open lbits:3 reserved1 Reserved lbits:1 prm Promiscuous Mode lbits:1 wpe Wait For Port Enable lbits:1 fmh Force Monitor State With Hard Address lbits:1 fmn Force Monitor Non-participating State lbits:1 dlm Disable Loop Master lbits:1 dsa Disable Soft Address Selection lbits:1 ilp Ignore LPB/LPE Primitive Sequences {} or fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 7548> ulong value As longword endunion fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 7552> union pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED <byte 7552> {field (By field)} <byte 7552> {pci_rsvd1F8 ((Offset 1F8) Reserved)} <byte 7552> utiny value

{} <byte 7553> {pci_rsvd1F9 ((Offset 1F9) Reserved)} <byte 7553> utiny value {} <byte 7554> union romctr (Offset 1FA) PCI ROM Control <byte 7554> {field (By field)} <byte 7554> tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or romctr (Offset 1FA) PCI ROM Control <byte 7554> utiny value As byte endunion romctr (Offset 1FA) PCI ROM Control <byte 7555> union mctr (Offset 1FB) PCI Master Control <byte 7555> {field (By field)} <byte 7555> tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or mctr (Offset 1FB) PCI Master Control <byte 7555> utiny value As byte endunion mctr (Offset 1FB) PCI Master Control {} or pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED <byte 7552> ulong value As longword endunion pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED <byte 7556> union pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST <byte 7556> {field (By field)} <byte 7556> union softrst (Offset 1FC) PCI Interface Reset Control <byte 7556> {field (By field)} <byte 7556> tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or softrst (Offset 1FC) PCI Interface Reset Control <byte 7556> utiny value As byte endunion softrst (Offset 1FC) PCI Interface Reset Control <byte 7557> union intpend (Offset 1FD) PCI Interrupt Pending <byte 7557> {field (By field)} <byte 7557>

tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intpend (Offset 1FD) PCI Interrupt Pending <byte 7557> utiny value As byte endunion intpend (Offset 1FD) PCI Interrupt Pending <byte 7558> union inten (Offset 1FE) PCI Interrupt Enable <byte 7558> {field (By field)} <byte 7558> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or inten (Offset 1FE) PCI Interrupt Enable <byte 7558> utiny value As byte endunion inten (Offset 1FE) PCI Interrupt Enable <byte 7559> union intstat (Offset 1FF) PCI Interrupt Status <byte 7559> {field (By field)} <byte 7559> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intstat (Offset 1FF) PCI Interrupt Status <byte 7559> utiny value As byte endunion intstat (Offset 1FF) PCI Interrupt Status {} or pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST <byte 7556> ulong value As longword endunion pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST {} endunion csr[1] Tachyon DX2+ CSR Registers <byte 7560> union csr[2] Tachyon DX2+ CSR Registers <byte 7560> ulong[128] csra Tachyon DX2+ CSR Registers As Longwords or csr[2] Tachyon DX2+ CSR Registers <byte 7560> {csr (Tachyon DX2+ CSR Registers By Field)} <byte 7560> union erq_base (Offset 000) ERQ Base (write only) <byte 7560>

{field (By field)} <byte 7560> lbits:32 address ERQ Base Address {} or erq_base (Offset 000) ERQ Base (write only) <byte 7560> ulong value As longword endunion erq_base (Offset 000) ERQ Base (write only) <byte 7564> union erq_len (Offset 004) ERQ Length (write only) <byte 7564> {field (By field)} <byte 7564> lbits:12 length ERQ Length lbits:20 reserved Reserved {} or erq_len (Offset 004) ERQ Length (write only) <byte 7564> ulong value As longword endunion erq_len (Offset 004) ERQ Length (write only) <byte 7568> union erq_prod (Offset 008) ERQ Producer Index <byte 7568> {field (By field)} <byte 7568> lbits:12 index ERQ Producer Index lbits:20 reserved Reserved {} or erq_prod (Offset 008) ERQ Producer Index <byte 7568> ulong value As longword endunion erq_prod (Offset 008) ERQ Producer Index <byte 7572> union erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 7572> {field (By field)} <byte 7572> lbits:32 address ERQ Consumer Index Address {} or erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 7572> ulong value As longword endunion erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 7576> union erq_cons (Offset 010) ERQ Consumer Index <byte 7576> {field (By field)} <byte 7576> lbits:12 index ERQ Consumer Index lbits:20 reserved Reserved {} or erq_cons (Offset 010) ERQ Consumer Index <byte 7576> ulong value As longword endunion erq_cons (Offset 010) ERQ Consumer Index <byte 7580> {rsvd1[0] ((Offset 014-04F) Reserved)} <byte 7580> ulong value {}

<byte 7584> {rsvd1[1] ((Offset 014-04F) Reserved)} <byte 7584> ulong value {} <byte 7588> {rsvd1[2] ((Offset 014-04F) Reserved)} <byte 7588> ulong value {} <byte 7592> {rsvd1[3] ((Offset 014-04F) Reserved)} <byte 7592> ulong value {} <byte 7596> {rsvd1[4] ((Offset 014-04F) Reserved)} <byte 7596> ulong value {} <byte 7600> {rsvd1[5] ((Offset 014-04F) Reserved)} <byte 7600> ulong value {} <byte 7604> {rsvd1[6] ((Offset 014-04F) Reserved)} <byte 7604> ulong value {} <byte 7608> {rsvd1[7] ((Offset 014-04F) Reserved)} <byte 7608> ulong value {} <byte 7612> {rsvd1[8] ((Offset 014-04F) Reserved)} <byte 7612> ulong value {} <byte 7616> {rsvd1[9] ((Offset 014-04F) Reserved)} <byte 7616> ulong value {} <byte 7620> {rsvd1[10] ((Offset 014-04F) Reserved)} <byte 7620> ulong value {} <byte 7624> {rsvd1[11] ((Offset 014-04F) Reserved)} <byte 7624> ulong value {} <byte 7628> {rsvd1[12] ((Offset 014-04F) Reserved)} <byte 7628> ulong value {}

<byte 7632> {rsvd1[13] ((Offset 014-04F) Reserved)} <byte 7632> ulong value {} <byte 7636> {rsvd1[14] ((Offset 014-04F) Reserved)} <byte 7636> ulong value {} <byte 7640> union sfq_base (Offset 050) SFQ Base (write only) <byte 7640> {field (By field)} <byte 7640> lbits:32 address SFQ Base Address {} or sfq_base (Offset 050) SFQ Base (write only) <byte 7640> ulong value As longword endunion sfq_base (Offset 050) SFQ Base (write only) <byte 7644> union sfq_len (Offset 054) SFQ Length (write only) <byte 7644> {field (By field)} <byte 7644> lbits:12 length SFQ Length lbits:20 reserved Reserved {} or sfq_len (Offset 054) SFQ Length (write only) <byte 7644> ulong value As longword endunion sfq_len (Offset 054) SFQ Length (write only) <byte 7648> union sfq_cons (Offset 058) SFQ Consumer Index <byte 7648> {field (By field)} <byte 7648> lbits:12 index SFQ Consumer Index lbits:20 reserved Reserved {} or sfq_cons (Offset 058) SFQ Consumer Index <byte 7648> ulong value As longword endunion sfq_cons (Offset 058) SFQ Consumer Index <byte 7652> {rsvd2[0] ((Offset 05C-07B) Reserved)} <byte 7652> ulong value {} <byte 7656> {rsvd2[1] ((Offset 05C-07B) Reserved)} <byte 7656> ulong value {} <byte 7660> {rsvd2[2] ((Offset 05C-07B) Reserved)} <byte 7660> ulong value {}

<byte 7664> {rsvd2[3] ((Offset 05C-07B) Reserved)} <byte 7664> ulong value {} <byte 7668> {rsvd2[4] ((Offset 05C-07B) Reserved)} <byte 7668> ulong value {} <byte 7672> {rsvd2[5] ((Offset 05C-07B) Reserved)} <byte 7672> ulong value {} <byte 7676> {rsvd2[6] ((Offset 05C-07B) Reserved)} <byte 7676> ulong value {} <byte 7680> {rsvd2[7] ((Offset 05C-07B) Reserved)} <byte 7680> ulong value {} <byte 7684> union int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 7684> {field (By field)} <byte 7684> lbits:4 timer Interrupt Timer Value lbits:3 reserved Reserved lbits:1 ihf Interrupt when IMQ Half Full lbits:24 reserved1 Reserved {} or int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 7684> ulong value As longword endunion int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 7688> union imq_base (Offset 080) IMQ Base (write only) <byte 7688> {field (By field)} <byte 7688> lbits:32 address IMQ Base Address {} or imq_base (Offset 080) IMQ Base (write only) <byte 7688> ulong value As longword endunion imq_base (Offset 080) IMQ Base (write only) <byte 7692> union imq_len (Offset 084) IMQ Length (write only) <byte 7692> {field (By field)} <byte 7692> lbits:12 length IMQ Length lbits:20 reserved Reserved {} or imq_len (Offset 084) IMQ Length (write only) <byte 7692>

ulong value As longword endunion imq_len (Offset 084) IMQ Length (write only) <byte 7696> union imq_cons (Offset 088) IMQ Consumer Index <byte 7696> {field (By field)} <byte 7696> lbits:12 index IMQ Consumer Index lbits:20 reserved Reserved {} or imq_cons (Offset 088) IMQ Consumer Index <byte 7696> ulong value As longword endunion imq_cons (Offset 088) IMQ Consumer Index <byte 7700> union imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 7700> {field (By field)} <byte 7700> lbits:32 address IMQ Producer Index Address {} or imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 7700> ulong value As longword endunion imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 7704> {rsvd3[0] ((Offset 090-0FC) Reserved)} <byte 7704> ulong value {} <byte 7708> {rsvd3[1] ((Offset 090-0FC) Reserved)} <byte 7708> ulong value {} <byte 7712> {rsvd3[2] ((Offset 090-0FC) Reserved)} <byte 7712> ulong value {} <byte 7716> {rsvd3[3] ((Offset 090-0FC) Reserved)} <byte 7716> ulong value {} <byte 7720> {rsvd3[4] ((Offset 090-0FC) Reserved)} <byte 7720> ulong value {} <byte 7724> {rsvd3[5] ((Offset 090-0FC) Reserved)} <byte 7724> ulong value {} <byte 7728> {rsvd3[6] ((Offset 090-0FC) Reserved)} <byte 7728> ulong value {}

<byte 7732> {rsvd3[7] ((Offset 090-0FC) Reserved)} <byte 7732> ulong value {} <byte 7736> {rsvd3[8] ((Offset 090-0FC) Reserved)} <byte 7736> ulong value {} <byte 7740> {rsvd3[9] ((Offset 090-0FC) Reserved)} <byte 7740> ulong value {} <byte 7744> {rsvd3[10] ((Offset 090-0FC) Reserved)} <byte 7744> ulong value {} <byte 7748> {rsvd3[11] ((Offset 090-0FC) Reserved)} <byte 7748> ulong value {} <byte 7752> {rsvd3[12] ((Offset 090-0FC) Reserved)} <byte 7752> ulong value {} <byte 7756> {rsvd3[13] ((Offset 090-0FC) Reserved)} <byte 7756> ulong value {} <byte 7760> {rsvd3[14] ((Offset 090-0FC) Reserved)} <byte 7760> ulong value {} <byte 7764> {rsvd3[15] ((Offset 090-0FC) Reserved)} <byte 7764> ulong value {} <byte 7768> {rsvd3[16] ((Offset 090-0FC) Reserved)} <byte 7768> ulong value {} <byte 7772> {rsvd3[17] ((Offset 090-0FC) Reserved)} <byte 7772> ulong value {} <byte 7776> {rsvd3[18] ((Offset 090-0FC) Reserved)} <byte 7776> ulong value {}

<byte 7780> {rsvd3[19] ((Offset 090-0FC) Reserved)} <byte 7780> ulong value {} <byte 7784> {rsvd3[20] ((Offset 090-0FC) Reserved)} <byte 7784> ulong value {} <byte 7788> {rsvd3[21] ((Offset 090-0FC) Reserved)} <byte 7788> ulong value {} <byte 7792> {rsvd3[22] ((Offset 090-0FC) Reserved)} <byte 7792> ulong value {} <byte 7796> {rsvd3[23] ((Offset 090-0FC) Reserved)} <byte 7796> ulong value {} <byte 7800> {rsvd3[24] ((Offset 090-0FC) Reserved)} <byte 7800> ulong value {} <byte 7804> {rsvd3[25] ((Offset 090-0FC) Reserved)} <byte 7804> ulong value {} <byte 7808> {rsvd3[26] ((Offset 090-0FC) Reserved)} <byte 7808> ulong value {} <byte 7812> {rsvd3[27] ((Offset 090-0FC) Reserved)} <byte 7812> ulong value {} <byte 7816> union fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 7816> {field (By field)} <byte 7816> lbits:6 bec Termination Receive lbits:3 reserved4 Reserved lbits:1 xrb Wrapback lbits:2 reserved Reserved lbits:3 xem Output pre-emphasis lbits:4 reserved1 Reserved lbits:1 mustbe1 Must be 1 lbits:1 stb Start BERT lbits:1 enb Enable BERT lbits:2 sdm Signal differential mode

lbits:2 rxs Receiver Speed lbits:2 txs Transmitter Speed lbits:1 reserved3 Reserved lbits:1 xlr Force iTR to lock reference clock lbits:1 reserved0 Reserved lbits:1 xcv Type of Transceiver {} or fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 7816> ulong value As longword endunion fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 7820> union fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 7820> {field (By field)} <byte 7820> lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 7820> ulong value As longword endunion fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 7824> {rsvd3a[0] ((Offset 108-10f) Reserved)} <byte 7824> ulong value {} <byte 7828> {rsvd3a[1] ((Offset 108-10f) Reserved)} <byte 7828> ulong value {} <byte 7832> union sfp_cmd_status (Offset 110) SFP command and status <byte 7832>

{field (No description available)} <byte 7832> lbits:1 gna Generate NACK lbits:1 rts Reset Slave lbits:1 wrc Write command lbits:1 rdc Read command lbits:1 gst Generate Stop lbits:1 sta Generate Start lbits:2 reserved1 Reserved lbits:1 rna Received NACK lbits:1 sby SFP Busy lbits:1 tip Transfer in progress lbits:9 reserved Reserved lbits:12 lp Clock Divisor {} or sfp_cmd_status (Offset 110) SFP command and status <byte 7832> ulong value endunion sfp_cmd_status (Offset 110) SFP command and status <byte 7836> union sfp_data (Offset 114) SFP data <byte 7836> {field (By field)} <byte 7836> lbits:8 sfpd SFPD Transmit lbits:24 reserved Reserved {} or sfp_data (Offset 114) SFP data <byte 7836> ulong value As longword endunion sfp_data (Offset 114) SFP data <byte 7840> union fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 7840> {field (By field)} <byte 7840> lbits:1 tbe Transmit Link BIST error lbits:1 tlr Transmit Link BIST reset lbits:1 tle Transmit Link BIST enable lbits:1 rbe Receive Link BIST error lbits:1 rll Receive Link BIST loop-back lbits:1 rlr Receive Link BIST reset lbits:1 rle Receive Link BIST enable lbits:7 reserved3 Reserved lbits:1 ipl ITR PPL Lock lbits:1 reserved2 Reserved lbits:1 dtf Disable transceiver LOS filter lbits:1 dtl Disable transceiver LOS lbits:1 dsr Disable iTR RXLOS lbits:1 ttd Transceiver Tx Disable lbits:2 reserved1 Reserved lbits:1 rfl Receive ast Lock Disable lbits:9 reserved Reserved {} or fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 7840> ulong value As longword endunion fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 7844> union fm_config5 (Offset 11C) Frame Manager Configuration 5

<byte 7844> {field (By field)} <byte 7844> lbits:32 reserved Reserved {} or fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 7844> ulong value As longword endunion fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 7848> {rsvd3b[0] ((Offset 120-13F) Reserved)} <byte 7848> ulong value {} <byte 7852> {rsvd3b[1] ((Offset 120-13F) Reserved)} <byte 7852> ulong value {} <byte 7856> {rsvd3b[2] ((Offset 120-13F) Reserved)} <byte 7856> ulong value {} <byte 7860> {rsvd3b[3] ((Offset 120-13F) Reserved)} <byte 7860> ulong value {} <byte 7864> {rsvd3b[4] ((Offset 120-13F) Reserved)} <byte 7864> ulong value {} <byte 7868> {rsvd3b[5] ((Offset 120-13F) Reserved)} <byte 7868> ulong value {} <byte 7872> {rsvd3b[6] ((Offset 120-13F) Reserved)} <byte 7872> ulong value {} <byte 7876> {rsvd3b[7] ((Offset 120-13F) Reserved)} <byte 7876> ulong value {} <byte 7880> union sest_base (Offset 140) SEST Base (write only) <byte 7880> {field (By field)} <byte 7880> lbits:32 address SEST Base Address {} or sest_base (Offset 140) SEST Base (write only) <byte 7880> ulong value As longword endunion sest_base (Offset 140) SEST Base (write only)

<byte 7884> union sest_len (Offset 144) SEST Length (write only) <byte 7884> {field (By field)} <byte 7884> lbits:16 length SEST Length lbits:16 reserved Reserved {} or sest_len (Offset 144) SEST Length (write only) <byte 7884> ulong value As longword endunion sest_len (Offset 144) SEST Length (write only) <byte 7888> {rsvd4 ((Offset 148) Reserved)} <byte 7888> ulong value {} <byte 7892> union scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 7892> {field (By field)} <byte 7892> lbits:16 tail Tail lbits:16 head Head {} or scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 7892> ulong value As longword endunion scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 7896> union prog_addr (Offset 150) Programmable Address register <byte 7896> {field (By field)} <byte 7896> lbits:20 ra ROM/RAM address lbits:11 reserved Reserved lbits:1 inc Increment {} or prog_addr (Offset 150) Programmable Address register <byte 7896> ulong value As longword endunion prog_addr (Offset 150) Programmable Address register <byte 7900> union prog_data (Offset 154) programmable data register <byte 7900> {field (By field)} <byte 7900> lbits:32 pdr Programmable data {} or prog_data (Offset 154) programmable data register <byte 7900> ulong value As longword endunion prog_data (Offset 154) programmable data register <byte 7904> {rsvd5[0] ((Offset 158-15F) Reserved)} <byte 7904> ulong value {} <byte 7908> {rsvd5[1] ((Offset 158-15F) Reserved)}

<byte 7908> ulong value {} <byte 7912> union int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 7912> {field (By field)} <byte 7912> lbits:32 address Interrupt Message Address {} or int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 7912> ulong value As longword endunion int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 7916> union int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 7916> {field (By field)} <byte 7916> lbits:32 value Interrupt Message Value {} or int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 7916> ulong value As longword endunion int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 7920> union sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 7920> {field (By field)} <byte 7920> lbits:8 length SGL Page Length lbits:24 reserved Reserved {} or sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 7920> ulong value As longword endunion sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 7924> union my_id (Offset 16C) My ID <byte 7924> {field (By field)} <byte 7924> lbits:24 id My ID lbits:8 reserved Reserved {} or my_id (Offset 16C) My ID <byte 7924> ulong value As longword endunion my_id (Offset 16C) My ID <byte 7928> union gpio (Offset 170) General Purpose I/O <byte 7928> {field (By field)} <byte 7928> lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:1 gc5 General Purpose Control 5

lbits:1 gc6 General Purpose Control 6 lbits:1 gc7 General Purpose Control 7 lbits:8 reserved Reserved lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose I/O 4 lbits:1 gp5 General Purpose I/O 5 lbits:1 gp6 General Purpose I/O 6 lbits:1 gp7 General Purpose I/O 7 lbits:8 reserved1 Reserved {} or gpio (Offset 170) General Purpose I/O <byte 7928> ulong value As longword endunion gpio (Offset 170) General Purpose I/O <byte 7932> {rsvd6a ((Offset 174-177) Reserved)} <byte 7932> ulong value {} <byte 7936> union edc_config (Offset 178) EDC Configuration Register <byte 7936> {field (By field)} <byte 7936> lbits:16 io_seed Starting Seed lbits:16 reserved Reserved {} or edc_config (Offset 178) EDC Configuration Register <byte 7936> ulong value As longword endunion edc_config (Offset 178) EDC Configuration Register <byte 7940> union dx4_config3 (Offset 17C) DX4 Configuration Register 3 <byte 7940> {field (By field)} <byte 7940> lbits:9 pfs2 Programmable Frame size field 2 lbits:9 pfs3 Programmable Frame size field 3 lbits:9 pfs4 Programmable Frame size field 4 lbits:5 reserved Reserved {} or dx4_config3 (Offset 17C) DX4 Configuration Register 3 <byte 7940> ulong value As longword endunion dx4_config3 (Offset 17C) DX4 Configuration Register 3 <byte 7944> union tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 7944> {field (By field)} <byte 7944> lbits:9 pfs Programmable Frame Size lbits:15 reserved Reserved lbits:8 esi_range Exchange_ID Signaled Interrupt Range {} or tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 7944> ulong value As longword

endunion tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 7948> union tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 7948> {field (By field)} <byte 7948> lbits:1 fad FCP Assist Disable lbits:1 ino In Order lbits:1 dof Discard OOO FCP Frames lbits:1 fua FCP Unassisted ACK Enable lbits:1 ime Interrupt Message Enable lbits:1 fab Fabric lbits:1 sic S_ID Copy Enable lbits:1 eqs Equal Service lbits:2 reserved Reserved lbits:1 aks Automatic ACK lbits:1 ddf Disable Delayed Freeze lbits:1 ebe Enable Big Endian Mode lbits:11 reserved1 Reserved lbits:1 fc2 FCP Class 2 Reassembly Enable lbits:1 reserved2 Reserved lbits:1 sdf Save Discarded Frames lbits:1 rde Response Detect Enable lbits:1 dam Default ACK Model lbits:2 reserved3 Reserved lbits:1 m66 66 MHz Enabled {} or tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 7948> ulong value As longword endunion tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 7952> union tach_control (Offset 188) Tachyon DX2+ Control <byte 7952> {field (By field)} <byte 7952> lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:3 reserved Reserved lbits:1 feq Freeze ERQ lbits:1 ffa Freeze FCP Assists lbits:2 reserved1 Reserved lbits:1 fis Freeze Inbound FCP Assists When Frame Placed in SFQ lbits:1 fib Freeze Inbound FCP Assists lbits:2 reserved2 Reserved lbits:1 req Resume ERQ lbits:1 rif Resume Inbound FCP Assists lbits:1 rof Resume Outbound FCP Assists lbits:12 reserved3 Reserved lbits:1 crs Core Reset {} or tach_control (Offset 188) Tachyon DX2+ Control <byte 7952> ulong value As longword endunion tach_control (Offset 188) Tachyon DX2+ Control <byte 7956> union tach_status (Offset 18C) Tachyon DX2+ Status

<byte 7956> {field (By field)} <byte 7956> lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose Input 4 lbits:5 reserved Reserved lbits:1 ipe Inbound Parity Error lbits:1 ope Outbound Parity Error lbits:4 reserved1 Reserved lbits:1 eqf ERQ Frozen lbits:1 iff Inbound FCP Assists Frozen lbits:1 off Outbound FCP Assists Frozen lbits:4 reserved2 Reserved lbits:1 ifce Inbound FIFO CRC Error lbits:1 ofce Outbound FIFO CRC Error lbits:1 m66 66 Mhz Enabled lbits:1 ile Inbound Link Control FIFO Empty lbits:1 ole Outbound Link Control List Empty lbits:1 ife Inbound FIFO Empty lbits:1 ofe Outbound FIFO Empty lbits:1 imf IMQ Full lbits:1 ssf SFQ Full {} or tach_status (Offset 18C) Tachyon DX2+ Status <byte 7956> ulong value As longword endunion tach_status (Offset 18C) Tachyon DX2+ Status <byte 7960> {rsvd7 ((Offset 190) Reserved)} <byte 7960> ulong value {} <byte 7964> union hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 7964> {field (By field)} <byte 7964> lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 7964> ulong value As longword endunion hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 7968> union hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 7968> {field (By field)} <byte 7968> lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send2 (Offset 198) High Priority Send 2 (write only)

<byte 7968> ulong value As longword endunion hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 7972> union inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 7972> {field (By field)} <byte 7972> lbits:24 reserved Reserved lbits:8 sest_lru_count SEST LRU Count {} or inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 7972> ulong value As longword endunion inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 7976> union inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 7976> {field (By field)} <byte 7976> lbits:8 discd_frames Discarded Frame Count lbits:24 reserved Reserved {} or inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 7976> ulong value As longword endunion inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 7980> union ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) <byte 7980> {field (By field)} <byte 7980> lbits:28 threshold EE_Credit Zero Timer Threshold lbits:4 reserved Reserved {} or ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) <byte 7980> ulong value As longword endunion ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only ) <byte 7984> union up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 7984> {field (By field)} <byte 7984> lbits:12 reserved Reserved lbits:1 upper_addr1 Upper Data Address--44 bit data space lbits:19 upper_addr Upper Data Address {} or up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 7984> ulong value As longword endunion up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 7988> union up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 7988> {field (By field)} <byte 7988> lbits:32 upper_addr Upper Control Address {}

or up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 7988> ulong value As longword endunion up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 7992> union dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 7992> {field (By field)} <byte 7992> lbits:1 ef AL_PA 0xEF DHD Login Information lbits:1 e8 AL_PA 0xE8 DHD Login Information lbits:1 e4 AL_PA 0xE4 DHD Login Information lbits:1 e2 AL_PA 0xE2 DHD Login Information lbits:1 e1 AL_PA 0xE1 DHD Login Information lbits:1 e0 AL_PA 0xE0 DHD Login Information lbits:1 dc AL_PA 0xDC DHD Login Information lbits:1 da AL_PA 0xDA DHD Login Information lbits:1 d9 AL_PA 0xD9 DHD Login Information lbits:1 d6 AL_PA 0xD6 DHD Login Information lbits:1 d5 AL_PA 0xD5 DHD Login Information lbits:1 d4 AL_PA 0xD4 DHD Login Information lbits:1 d3 AL_PA 0xD3 DHD Login Information lbits:1 d2 AL_PA 0xD2 DHD Login Information lbits:1 d1 AL_PA 0xD1 DHD Login Information lbits:1 ce AL_PA 0xCE DHD Login Information lbits:1 cd AL_PA 0xCD DHD Login Information lbits:1 cc AL_PA 0xCC DHD Login Information lbits:1 cb AL_PA 0xCB DHD Login Information lbits:1 ca AL_PA 0xCA DHD Login Information lbits:1 c9 AL_PA 0xC9 DHD Login Information lbits:1 c7 AL_PA 0xC7 DHD Login Information lbits:1 c6 AL_PA 0xC6 DHD Login Information lbits:1 c5 AL_PA 0xC5 DHD Login Information lbits:1 c3 AL_PA 0xC3 DHD Login Information lbits:1 bc AL_PA 0xBC DHD Login Information lbits:1 ba AL_PA 0xBA DHD Login Information lbits:1 b9 AL_PA 0xB9 DHD Login Information lbits:1 b6 AL_PA 0xB6 DHD Login Information lbits:1 b5 AL_PA 0xB5 DHD Login Information lbits:1 b4 AL_PA 0xB4 DHD Login Information lbits:1 b3 AL_PA 0xB3 DHD Login Information {} or dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 7992> ulong value As longword endunion dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 7996> union dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 7996> {field (By field)} <byte 7996> lbits:1 alpab2 AL_PA 0xB2 DHD Login Information lbits:1 alpab1 AL_PA 0xB1 DHD Login Information lbits:1 alpaae AL_PA 0xAE DHD Login Information lbits:1 alpaad AL_PA 0xAD DHD Login Information lbits:1 alpaac AL_PA 0xAC DHD Login Information lbits:1 alpaab AL_PA 0xAB DHD Login Information lbits:1 alpaaa AL_PA 0xAA DHD Login Information lbits:1 alpaa9 AL_PA 0xA9 DHD Login Information lbits:1 alpaa7 AL_PA 0xA7 DHD Login Information

lbits:1 alpaa6 AL_PA 0xA6 DHD Login Information lbits:1 alpaa5 AL_PA 0xA5 DHD Login Information lbits:1 alpaa3 AL_PA 0xA3 DHD Login Information lbits:1 alpa9f AL_PA 0x9F DHD Login Information lbits:1 alpa9e AL_PA 0x9E DHD Login Information lbits:1 alpa9d AL_PA 0x9D DHD Login Information lbits:1 alpa9b AL_PA 0x9B DHD Login Information lbits:1 alpa98 AL_PA 0x98 DHD Login Information lbits:1 alpa97 AL_PA 0x97 DHD Login Information lbits:1 alpa90 AL_PA 0x90 DHD Login Information lbits:1 alpa8f AL_PA 0x8F DHD Login Information lbits:1 alpa88 AL_PA 0x88 DHD Login Information lbits:1 alpa84 AL_PA 0x84 DHD Login Information lbits:1 alpa82 AL_PA 0x82 DHD Login Information lbits:1 alpa81 AL_PA 0x81 DHD Login Information lbits:1 alpa80 AL_PA 0x80 DHD Login Information lbits:1 alpa7c AL_PA 0x7C DHD Login Information lbits:1 alpa7a AL_PA 0x7A DHD Login Information lbits:1 alpa79 AL_PA 0x79 DHD Login Information lbits:1 alpa76 AL_PA 0x76 DHD Login Information lbits:1 alpa75 AL_PA 0x75 DHD Login Information lbits:1 alpa74 AL_PA 0x74 DHD Login Information lbits:1 alpa73 AL_PA 0x73 DHD Login Information {} or dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 7996> ulong value As longword endunion dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 8000> union dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 8000> {field (By field)} <byte 8000> lbits:1 alpa72 AL_PA 0x72 DHD Login Information lbits:1 alpa71 AL_PA 0x71 DHD Login Information lbits:1 alpa6e AL_PA 0x6E DHD Login Information lbits:1 alpa6d AL_PA 0x6D DHD Login Information lbits:1 alpa6c AL_PA 0x6C DHD Login Information lbits:1 alpa6b AL_PA 0x6B DHD Login Information lbits:1 alpa6a AL_PA 0x6A DHD Login Information lbits:1 alpa69 AL_PA 0x69 DHD Login Information lbits:1 alpa67 AL_PA 0x67 DHD Login Information lbits:1 alpa66 AL_PA 0x66 DHD Login Information lbits:1 alpa65 AL_PA 0x65 DHD Login Information lbits:1 alpa63 AL_PA 0x63 DHD Login Information lbits:1 alpa5c AL_PA 0x5C DHD Login Information lbits:1 alpa5a AL_PA 0x5A DHD Login Information lbits:1 alpa59 AL_PA 0x59 DHD Login Information lbits:1 alpa56 AL_PA 0x56 DHD Login Information lbits:1 alpa55 AL_PA 0x55 DHD Login Information lbits:1 alpa54 AL_PA 0x54 DHD Login Information lbits:1 alpa53 AL_PA 0x53 DHD Login Information lbits:1 alpa52 AL_PA 0x52 DHD Login Information lbits:1 alpa51 AL_PA 0x51 DHD Login Information lbits:1 alpa4e AL_PA 0x4E DHD Login Information lbits:1 alpa4d AL_PA 0x4D DHD Login Information lbits:1 alpa4c AL_PA 0x4C DHD Login Information lbits:1 alpa4b AL_PA 0x4B DHD Login Information lbits:1 alpa4a AL_PA 0x4A DHD Login Information lbits:1 alpa49 AL_PA 0x49 DHD Login Information

lbits:1 alpa47 AL_PA 0x47 DHD Login Information lbits:1 alpa46 AL_PA 0x46 DHD Login Information lbits:1 alpa45 AL_PA 0x45 DHD Login Information lbits:1 alpa43 AL_PA 0x43 DHD Login Information lbits:1 alpa3c AL_PA 0x3C DHD Login Information {} or dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 8000> ulong value As longword endunion dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 8004> union dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 8004> {field (By field)} <byte 8004> lbits:1 alpa3a AL_PA 0x3A DHD Login Information lbits:1 alpa39 AL_PA 0x39 DHD Login Information lbits:1 alpa36 AL_PA 0x36 DHD Login Information lbits:1 alpa35 AL_PA 0x35 DHD Login Information lbits:1 alpa34 AL_PA 0x34 DHD Login Information lbits:1 alpa33 AL_PA 0x33 DHD Login Information lbits:1 alpa32 AL_PA 0x32 DHD Login Information lbits:1 alpa31 AL_PA 0x31 DHD Login Information lbits:1 alpa2e AL_PA 0x2E DHD Login Information lbits:1 alpa2d AL_PA 0x2D DHD Login Information lbits:1 alpa2c AL_PA 0x2C DHD Login Information lbits:1 alpa2b AL_PA 0x2B DHD Login Information lbits:1 alpa2a AL_PA 0x2A DHD Login Information lbits:1 alpa29 AL_PA 0x29 DHD Login Information lbits:1 alpa27 AL_PA 0x27 DHD Login Information lbits:1 alpa26 AL_PA 0x26 DHD Login Information lbits:1 alpa25 AL_PA 0x25 DHD Login Information lbits:1 alpa23 AL_PA 0x23 DHD Login Information lbits:1 alpa1f AL_PA 0x1F DHD Login Information lbits:1 alpa1e AL_PA 0x1E DHD Login Information lbits:1 alpa1d AL_PA 0x1D DHD Login Information lbits:1 alpa1b AL_PA 0x1B DHD Login Information lbits:1 alpa18 AL_PA 0x18 DHD Login Information lbits:1 alpa17 AL_PA 0x17 DHD Login Information lbits:1 alpa10 AL_PA 0x10 DHD Login Information lbits:1 alpa0f AL_PA 0x0F DHD Login Information lbits:1 alpa08 AL_PA 0x08 DHD Login Information lbits:1 alpa04 AL_PA 0x04 DHD Login Information lbits:1 alpa02 AL_PA 0x02 DHD Login Information lbits:1 alpa01 AL_PA 0x01 DHD Login Information lbits:1 alpa00 AL_PA 0x00 DHD Login Information lbits:1 reserved Reserved {} or dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 8004> ulong value As longword endunion dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 8008> union fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 8008> {field (By field)} <byte 8008> lbits:1 bli Bypass Loop Initialization lbits:1 reserved Reserved lbits:1 enp Enable N_Port Mode

lbits:1 lr Login Required lbits:1 inif Initialize as Fabric lbits:1 rf Respond to Fabric Address lbits:1 blm Bypass Loop Map lbits:1 sa Acquire Soft Address lbits:1 ha Acquire Hard Address lbits:1 aq Acquire Previously Acquired Address lbits:1 fa Acquire Fabric Aquired Address lbits:1 td Timer Disable lbits:1 sap Skip Arbitration Phase lbits:1 elb External Loopback/Pad Loopback lbits:1 ilb Internal loopback lbits:1 npi Initialize as N_Port lbits:8 bb_credit BB_Credit lbits:8 al_pa Desired AL_PA {} or fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 8008> ulong value As longword endunion fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 8012> union fm_control (Offset 1C4) Frame Manager Control <byte 8012> {field (By field)} <byte 8012> lbits:3 cmd State Machine Command lbits:1 cl Close Loop Request lbits:1 reserved Reserved lbits:1 sp Send Prim_Reg lbits:1 sq Primitive Sequence lbits:25 reserved1 Reserved {} or fm_control (Offset 1C4) Frame Manager Control <byte 8012> ulong value As longword endunion fm_control (Offset 1C4) Frame Manager Control <byte 8016> union fm_status (Offset 1C8) Frame Manager Status <byte 8016> {field (By field)} <byte 8016> lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal

lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_status (Offset 1C8) Frame Manager Status <byte 8016> ulong value As longword endunion fm_status (Offset 1C8) Frame Manager Status <byte 8020> union fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 8020> {field (By field)} <byte 8020> lbits:16 ed_tov Error Detect Time-Out lbits:9 rt_tov Receiver Transmitter Time-Out lbits:7 reserved Reserved {} or fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 8020> ulong value As longword endunion fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 8024> union fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 8024> {field (By field)} <byte 8024> lbits:8 link_fail Link Fail Count lbits:8 loss_of_sync Loss of Synchronization Count lbits:8 bad_rx_char Bad Received Character Count lbits:8 loss_of_signal Loss of Signal Count {} or fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 8024> ulong value As longword endunion fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 8028> union fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 8028> {field (By field)} <byte 8028> lbits:8 proto_er Protocol Error Count lbits:8 bad_crc Bad CRC Count lbits:8 dis_frm Discarded Frames lbits:8 rx_eofa Received EOFa {} or fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 8028> ulong value As longword endunion fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 8032> union fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 8032> {field (By field)} <byte 8032> lbits:9 al_time Arbitrated Loop Time-Out lbits:7 reserved Reserved

lbits:16 lp_tov Loop Time-Out {} or fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 8032> ulong value As longword endunion fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 8036> union fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 8036> {field (By field)} <byte 8036> lbits:24 bb0_timer BB_Credit Timer lbits:8 reserved Reserved {} or fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 8036> ulong value As longword endunion fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 8040> union fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 8040> {field (By field)} <byte 8040> lbits:32 wwn World Wide Name {} or fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 8040> ulong value As longword endunion fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 8044> union fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 8044> {field (By field)} <byte 8044> lbits:32 wwn World Wide Name {} or fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 8044> ulong value As longword endunion fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 8048> union fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 8048> {field (By field)} <byte 8048> lbits:8 lipf_alpa AL_PA of Most Recent LIPf Received lbits:8 bad_alpa AL_PA of Most Recent OPN Sent and Returned Without Being Accept ed lbits:8 acq_alpa AL_PA Acquired During Loop Initialization lbits:8 reserved Reserved {} or fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 8048> ulong value As longword endunion fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 8052> union fm_primitive (Offset 1EC) Frame Manager Primitive <byte 8052> {field (By field)} <byte 8052>

lbits:24 prim_value Primitive to be Sent lbits:8 reserved Reserved {} or fm_primitive (Offset 1EC) Frame Manager Primitive <byte 8052> ulong value As longword endunion fm_primitive (Offset 1EC) Frame Manager Primitive <byte 8056> union fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 8056> {field (By field)} <byte 8056> lbits:8 exp_frm Expired Frames lbits:24 reserved Reserved {} or fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 8056> ulong value As longword endunion fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 8060> union fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 8060> {field (By field)} <byte 8060> lbits:1 dac Disable Auto Close lbits:2 nbc Non-zero Login BB_Credit lbits:1 eei Enable ERR_INIT lbits:1 icb Ignore Close Bit lbits:2 atv Arbitration Threshold Value lbits:1 gde Garbage Deletion Enable lbits:8 laa Lowest Allowable AL_PA lbits:5 reserved Reserved lbits:1 dao Disable 2xAL_TIME Timeout on Open lbits:3 reserved1 Reserved lbits:1 prm Promiscuous Mode lbits:1 wpe Wait For Port Enable lbits:1 fmh Force Monitor State With Hard Address lbits:1 fmn Force Monitor Non-participating State lbits:1 dlm Disable Loop Master lbits:1 dsa Disable Soft Address Selection lbits:1 ilp Ignore LPB/LPE Primitive Sequences {} or fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 8060> ulong value As longword endunion fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 8064> union pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED <byte 8064> {field (By field)} <byte 8064> {pci_rsvd1F8 ((Offset 1F8) Reserved)} <byte 8064> utiny value {} <byte 8065> {pci_rsvd1F9 ((Offset 1F9) Reserved)} <byte 8065> utiny value {}

<byte 8066> union romctr (Offset 1FA) PCI ROM Control <byte 8066> {field (By field)} <byte 8066> tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or romctr (Offset 1FA) PCI ROM Control <byte 8066> utiny value As byte endunion romctr (Offset 1FA) PCI ROM Control <byte 8067> union mctr (Offset 1FB) PCI Master Control <byte 8067> {field (By field)} <byte 8067> tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or mctr (Offset 1FB) PCI Master Control <byte 8067> utiny value As byte endunion mctr (Offset 1FB) PCI Master Control {} or pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED <byte 8064> ulong value As longword endunion pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED <byte 8068> union pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST <byte 8068> {field (By field)} <byte 8068> union softrst (Offset 1FC) PCI Interface Reset Control <byte 8068> {field (By field)} <byte 8068> tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or softrst (Offset 1FC) PCI Interface Reset Control <byte 8068> utiny value As byte endunion softrst (Offset 1FC) PCI Interface Reset Control <byte 8069> union intpend (Offset 1FD) PCI Interrupt Pending <byte 8069> {field (By field)} <byte 8069> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved

{} or intpend (Offset 1FD) PCI Interrupt Pending <byte 8069> utiny value As byte endunion intpend (Offset 1FD) PCI Interrupt Pending <byte 8070> union inten (Offset 1FE) PCI Interrupt Enable <byte 8070> {field (By field)} <byte 8070> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or inten (Offset 1FE) PCI Interrupt Enable <byte 8070> utiny value As byte endunion inten (Offset 1FE) PCI Interrupt Enable <byte 8071> union intstat (Offset 1FF) PCI Interrupt Status <byte 8071> {field (By field)} <byte 8071> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intstat (Offset 1FF) PCI Interrupt Status <byte 8071> utiny value As byte endunion intstat (Offset 1FF) PCI Interrupt Status {} or pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST <byte 8068> ulong value As longword endunion pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST {} endunion csr[2] Tachyon DX2+ CSR Registers <byte 8072> union csr[3] Tachyon DX2+ CSR Registers <byte 8072> ulong[128] csra Tachyon DX2+ CSR Registers As Longwords or csr[3] Tachyon DX2+ CSR Registers <byte 8072> {csr (Tachyon DX2+ CSR Registers By Field)} <byte 8072> union erq_base (Offset 000) ERQ Base (write only) <byte 8072> {field (By field)} <byte 8072> lbits:32 address ERQ Base Address {} or erq_base (Offset 000) ERQ Base (write only) <byte 8072>

ulong value As longword endunion erq_base (Offset 000) ERQ Base (write only) <byte 8076> union erq_len (Offset 004) ERQ Length (write only) <byte 8076> {field (By field)} <byte 8076> lbits:12 length ERQ Length lbits:20 reserved Reserved {} or erq_len (Offset 004) ERQ Length (write only) <byte 8076> ulong value As longword endunion erq_len (Offset 004) ERQ Length (write only) <byte 8080> union erq_prod (Offset 008) ERQ Producer Index <byte 8080> {field (By field)} <byte 8080> lbits:12 index ERQ Producer Index lbits:20 reserved Reserved {} or erq_prod (Offset 008) ERQ Producer Index <byte 8080> ulong value As longword endunion erq_prod (Offset 008) ERQ Producer Index <byte 8084> union erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 8084> {field (By field)} <byte 8084> lbits:32 address ERQ Consumer Index Address {} or erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 8084> ulong value As longword endunion erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 8088> union erq_cons (Offset 010) ERQ Consumer Index <byte 8088> {field (By field)} <byte 8088> lbits:12 index ERQ Consumer Index lbits:20 reserved Reserved {} or erq_cons (Offset 010) ERQ Consumer Index <byte 8088> ulong value As longword endunion erq_cons (Offset 010) ERQ Consumer Index <byte 8092> {rsvd1[0] ((Offset 014-04F) Reserved)} <byte 8092> ulong value {} <byte 8096> {rsvd1[1] ((Offset 014-04F) Reserved)} <byte 8096> ulong value {} <byte 8100>

{rsvd1[2] ((Offset 014-04F) Reserved)} <byte 8100> ulong value {} <byte 8104> {rsvd1[3] ((Offset 014-04F) Reserved)} <byte 8104> ulong value {} <byte 8108> {rsvd1[4] ((Offset 014-04F) Reserved)} <byte 8108> ulong value {} <byte 8112> {rsvd1[5] ((Offset 014-04F) Reserved)} <byte 8112> ulong value {} <byte 8116> {rsvd1[6] ((Offset 014-04F) Reserved)} <byte 8116> ulong value {} <byte 8120> {rsvd1[7] ((Offset 014-04F) Reserved)} <byte 8120> ulong value {} <byte 8124> {rsvd1[8] ((Offset 014-04F) Reserved)} <byte 8124> ulong value {} <byte 8128> {rsvd1[9] ((Offset 014-04F) Reserved)} <byte 8128> ulong value {} <byte 8132> {rsvd1[10] ((Offset 014-04F) Reserved)} <byte 8132> ulong value {} <byte 8136> {rsvd1[11] ((Offset 014-04F) Reserved)} <byte 8136> ulong value {} <byte 8140> {rsvd1[12] ((Offset 014-04F) Reserved)} <byte 8140> ulong value {} <byte 8144> {rsvd1[13] ((Offset 014-04F) Reserved)} <byte 8144> ulong value {} <byte 8148>

{rsvd1[14] ((Offset 014-04F) Reserved)} <byte 8148> ulong value {} <byte 8152> union sfq_base (Offset 050) SFQ Base (write only) <byte 8152> {field (By field)} <byte 8152> lbits:32 address SFQ Base Address {} or sfq_base (Offset 050) SFQ Base (write only) <byte 8152> ulong value As longword endunion sfq_base (Offset 050) SFQ Base (write only) <byte 8156> union sfq_len (Offset 054) SFQ Length (write only) <byte 8156> {field (By field)} <byte 8156> lbits:12 length SFQ Length lbits:20 reserved Reserved {} or sfq_len (Offset 054) SFQ Length (write only) <byte 8156> ulong value As longword endunion sfq_len (Offset 054) SFQ Length (write only) <byte 8160> union sfq_cons (Offset 058) SFQ Consumer Index <byte 8160> {field (By field)} <byte 8160> lbits:12 index SFQ Consumer Index lbits:20 reserved Reserved {} or sfq_cons (Offset 058) SFQ Consumer Index <byte 8160> ulong value As longword endunion sfq_cons (Offset 058) SFQ Consumer Index <byte 8164> {rsvd2[0] ((Offset 05C-07B) Reserved)} <byte 8164> ulong value {} <byte 8168> {rsvd2[1] ((Offset 05C-07B) Reserved)} <byte 8168> ulong value {} <byte 8172> {rsvd2[2] ((Offset 05C-07B) Reserved)} <byte 8172> ulong value {} <byte 8176> {rsvd2[3] ((Offset 05C-07B) Reserved)} <byte 8176> ulong value {} <byte 8180>

{rsvd2[4] ((Offset 05C-07B) Reserved)} <byte 8180> ulong value {} <byte 8184> {rsvd2[5] ((Offset 05C-07B) Reserved)} <byte 8184> ulong value {} <byte 8188> {rsvd2[6] ((Offset 05C-07B) Reserved)} <byte 8188> ulong value {} <byte 8192> {rsvd2[7] ((Offset 05C-07B) Reserved)} <byte 8192> ulong value {} <byte 8196> union int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 8196> {field (By field)} <byte 8196> lbits:4 timer Interrupt Timer Value lbits:3 reserved Reserved lbits:1 ihf Interrupt when IMQ Half Full lbits:24 reserved1 Reserved {} or int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 8196> ulong value As longword endunion int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 8200> union imq_base (Offset 080) IMQ Base (write only) <byte 8200> {field (By field)} <byte 8200> lbits:32 address IMQ Base Address {} or imq_base (Offset 080) IMQ Base (write only) <byte 8200> ulong value As longword endunion imq_base (Offset 080) IMQ Base (write only) <byte 8204> union imq_len (Offset 084) IMQ Length (write only) <byte 8204> {field (By field)} <byte 8204> lbits:12 length IMQ Length lbits:20 reserved Reserved {} or imq_len (Offset 084) IMQ Length (write only) <byte 8204> ulong value As longword endunion imq_len (Offset 084) IMQ Length (write only) <byte 8208> union imq_cons (Offset 088) IMQ Consumer Index <byte 8208> {field (By field)}

<byte 8208> lbits:12 index IMQ Consumer Index lbits:20 reserved Reserved {} or imq_cons (Offset 088) IMQ Consumer Index <byte 8208> ulong value As longword endunion imq_cons (Offset 088) IMQ Consumer Index <byte 8212> union imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 8212> {field (By field)} <byte 8212> lbits:32 address IMQ Producer Index Address {} or imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 8212> ulong value As longword endunion imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 8216> {rsvd3[0] ((Offset 090-0FC) Reserved)} <byte 8216> ulong value {} <byte 8220> {rsvd3[1] ((Offset 090-0FC) Reserved)} <byte 8220> ulong value {} <byte 8224> {rsvd3[2] ((Offset 090-0FC) Reserved)} <byte 8224> ulong value {} <byte 8228> {rsvd3[3] ((Offset 090-0FC) Reserved)} <byte 8228> ulong value {} <byte 8232> {rsvd3[4] ((Offset 090-0FC) Reserved)} <byte 8232> ulong value {} <byte 8236> {rsvd3[5] ((Offset 090-0FC) Reserved)} <byte 8236> ulong value {} <byte 8240> {rsvd3[6] ((Offset 090-0FC) Reserved)} <byte 8240> ulong value {} <byte 8244> {rsvd3[7] ((Offset 090-0FC) Reserved)} <byte 8244> ulong value {} <byte 8248>

{rsvd3[8] ((Offset 090-0FC) Reserved)} <byte 8248> ulong value {} <byte 8252> {rsvd3[9] ((Offset 090-0FC) Reserved)} <byte 8252> ulong value {} <byte 8256> {rsvd3[10] ((Offset 090-0FC) Reserved)} <byte 8256> ulong value {} <byte 8260> {rsvd3[11] ((Offset 090-0FC) Reserved)} <byte 8260> ulong value {} <byte 8264> {rsvd3[12] ((Offset 090-0FC) Reserved)} <byte 8264> ulong value {} <byte 8268> {rsvd3[13] ((Offset 090-0FC) Reserved)} <byte 8268> ulong value {} <byte 8272> {rsvd3[14] ((Offset 090-0FC) Reserved)} <byte 8272> ulong value {} <byte 8276> {rsvd3[15] ((Offset 090-0FC) Reserved)} <byte 8276> ulong value {} <byte 8280> {rsvd3[16] ((Offset 090-0FC) Reserved)} <byte 8280> ulong value {} <byte 8284> {rsvd3[17] ((Offset 090-0FC) Reserved)} <byte 8284> ulong value {} <byte 8288> {rsvd3[18] ((Offset 090-0FC) Reserved)} <byte 8288> ulong value {} <byte 8292> {rsvd3[19] ((Offset 090-0FC) Reserved)} <byte 8292> ulong value {} <byte 8296>

{rsvd3[20] ((Offset 090-0FC) Reserved)} <byte 8296> ulong value {} <byte 8300> {rsvd3[21] ((Offset 090-0FC) Reserved)} <byte 8300> ulong value {} <byte 8304> {rsvd3[22] ((Offset 090-0FC) Reserved)} <byte 8304> ulong value {} <byte 8308> {rsvd3[23] ((Offset 090-0FC) Reserved)} <byte 8308> ulong value {} <byte 8312> {rsvd3[24] ((Offset 090-0FC) Reserved)} <byte 8312> ulong value {} <byte 8316> {rsvd3[25] ((Offset 090-0FC) Reserved)} <byte 8316> ulong value {} <byte 8320> {rsvd3[26] ((Offset 090-0FC) Reserved)} <byte 8320> ulong value {} <byte 8324> {rsvd3[27] ((Offset 090-0FC) Reserved)} <byte 8324> ulong value {} <byte 8328> union fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 8328> {field (By field)} <byte 8328> lbits:6 bec Termination Receive lbits:3 reserved4 Reserved lbits:1 xrb Wrapback lbits:2 reserved Reserved lbits:3 xem Output pre-emphasis lbits:4 reserved1 Reserved lbits:1 mustbe1 Must be 1 lbits:1 stb Start BERT lbits:1 enb Enable BERT lbits:2 sdm Signal differential mode lbits:2 rxs Receiver Speed lbits:2 txs Transmitter Speed lbits:1 reserved3 Reserved lbits:1 xlr Force iTR to lock reference clock lbits:1 reserved0 Reserved lbits:1 xcv Type of Transceiver

{} or fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 8328> ulong value As longword endunion fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 8332> union fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 8332> {field (By field)} <byte 8332> lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 8332> ulong value As longword endunion fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 8336> {rsvd3a[0] ((Offset 108-10f) Reserved)} <byte 8336> ulong value {} <byte 8340> {rsvd3a[1] ((Offset 108-10f) Reserved)} <byte 8340> ulong value {} <byte 8344> union sfp_cmd_status (Offset 110) SFP command and status <byte 8344> {field (No description available)} <byte 8344> lbits:1 gna Generate NACK lbits:1 rts Reset Slave lbits:1 wrc Write command lbits:1 rdc Read command

lbits:1 gst Generate Stop lbits:1 sta Generate Start lbits:2 reserved1 Reserved lbits:1 rna Received NACK lbits:1 sby SFP Busy lbits:1 tip Transfer in progress lbits:9 reserved Reserved lbits:12 lp Clock Divisor {} or sfp_cmd_status (Offset 110) SFP command and status <byte 8344> ulong value endunion sfp_cmd_status (Offset 110) SFP command and status <byte 8348> union sfp_data (Offset 114) SFP data <byte 8348> {field (By field)} <byte 8348> lbits:8 sfpd SFPD Transmit lbits:24 reserved Reserved {} or sfp_data (Offset 114) SFP data <byte 8348> ulong value As longword endunion sfp_data (Offset 114) SFP data <byte 8352> union fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 8352> {field (By field)} <byte 8352> lbits:1 tbe Transmit Link BIST error lbits:1 tlr Transmit Link BIST reset lbits:1 tle Transmit Link BIST enable lbits:1 rbe Receive Link BIST error lbits:1 rll Receive Link BIST loop-back lbits:1 rlr Receive Link BIST reset lbits:1 rle Receive Link BIST enable lbits:7 reserved3 Reserved lbits:1 ipl ITR PPL Lock lbits:1 reserved2 Reserved lbits:1 dtf Disable transceiver LOS filter lbits:1 dtl Disable transceiver LOS lbits:1 dsr Disable iTR RXLOS lbits:1 ttd Transceiver Tx Disable lbits:2 reserved1 Reserved lbits:1 rfl Receive ast Lock Disable lbits:9 reserved Reserved {} or fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 8352> ulong value As longword endunion fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 8356> union fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 8356> {field (By field)} <byte 8356> lbits:32 reserved Reserved {} or fm_config5 (Offset 11C) Frame Manager Configuration 5

<byte 8356> ulong value As longword endunion fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 8360> {rsvd3b[0] ((Offset 120-13F) Reserved)} <byte 8360> ulong value {} <byte 8364> {rsvd3b[1] ((Offset 120-13F) Reserved)} <byte 8364> ulong value {} <byte 8368> {rsvd3b[2] ((Offset 120-13F) Reserved)} <byte 8368> ulong value {} <byte 8372> {rsvd3b[3] ((Offset 120-13F) Reserved)} <byte 8372> ulong value {} <byte 8376> {rsvd3b[4] ((Offset 120-13F) Reserved)} <byte 8376> ulong value {} <byte 8380> {rsvd3b[5] ((Offset 120-13F) Reserved)} <byte 8380> ulong value {} <byte 8384> {rsvd3b[6] ((Offset 120-13F) Reserved)} <byte 8384> ulong value {} <byte 8388> {rsvd3b[7] ((Offset 120-13F) Reserved)} <byte 8388> ulong value {} <byte 8392> union sest_base (Offset 140) SEST Base (write only) <byte 8392> {field (By field)} <byte 8392> lbits:32 address SEST Base Address {} or sest_base (Offset 140) SEST Base (write only) <byte 8392> ulong value As longword endunion sest_base (Offset 140) SEST Base (write only) <byte 8396> union sest_len (Offset 144) SEST Length (write only) <byte 8396> {field (By field)} <byte 8396> lbits:16 length SEST Length

lbits:16 reserved Reserved {} or sest_len (Offset 144) SEST Length (write only) <byte 8396> ulong value As longword endunion sest_len (Offset 144) SEST Length (write only) <byte 8400> {rsvd4 ((Offset 148) Reserved)} <byte 8400> ulong value {} <byte 8404> union scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 8404> {field (By field)} <byte 8404> lbits:16 tail Tail lbits:16 head Head {} or scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 8404> ulong value As longword endunion scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 8408> union prog_addr (Offset 150) Programmable Address register <byte 8408> {field (By field)} <byte 8408> lbits:20 ra ROM/RAM address lbits:11 reserved Reserved lbits:1 inc Increment {} or prog_addr (Offset 150) Programmable Address register <byte 8408> ulong value As longword endunion prog_addr (Offset 150) Programmable Address register <byte 8412> union prog_data (Offset 154) programmable data register <byte 8412> {field (By field)} <byte 8412> lbits:32 pdr Programmable data {} or prog_data (Offset 154) programmable data register <byte 8412> ulong value As longword endunion prog_data (Offset 154) programmable data register <byte 8416> {rsvd5[0] ((Offset 158-15F) Reserved)} <byte 8416> ulong value {} <byte 8420> {rsvd5[1] ((Offset 158-15F) Reserved)} <byte 8420> ulong value {} <byte 8424> union int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 8424>

{field (By field)} <byte 8424> lbits:32 address Interrupt Message Address {} or int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 8424> ulong value As longword endunion int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 8428> union int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 8428> {field (By field)} <byte 8428> lbits:32 value Interrupt Message Value {} or int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 8428> ulong value As longword endunion int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 8432> union sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 8432> {field (By field)} <byte 8432> lbits:8 length SGL Page Length lbits:24 reserved Reserved {} or sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 8432> ulong value As longword endunion sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 8436> union my_id (Offset 16C) My ID <byte 8436> {field (By field)} <byte 8436> lbits:24 id My ID lbits:8 reserved Reserved {} or my_id (Offset 16C) My ID <byte 8436> ulong value As longword endunion my_id (Offset 16C) My ID <byte 8440> union gpio (Offset 170) General Purpose I/O <byte 8440> {field (By field)} <byte 8440> lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:1 gc5 General Purpose Control 5 lbits:1 gc6 General Purpose Control 6 lbits:1 gc7 General Purpose Control 7 lbits:8 reserved Reserved lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2

lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose I/O 4 lbits:1 gp5 General Purpose I/O 5 lbits:1 gp6 General Purpose I/O 6 lbits:1 gp7 General Purpose I/O 7 lbits:8 reserved1 Reserved {} or gpio (Offset 170) General Purpose I/O <byte 8440> ulong value As longword endunion gpio (Offset 170) General Purpose I/O <byte 8444> {rsvd6a ((Offset 174-177) Reserved)} <byte 8444> ulong value {} <byte 8448> union edc_config (Offset 178) EDC Configuration Register <byte 8448> {field (By field)} <byte 8448> lbits:16 io_seed Starting Seed lbits:16 reserved Reserved {} or edc_config (Offset 178) EDC Configuration Register <byte 8448> ulong value As longword endunion edc_config (Offset 178) EDC Configuration Register <byte 8452> union dx4_config3 (Offset 17C) DX4 Configuration Register 3 <byte 8452> {field (By field)} <byte 8452> lbits:9 pfs2 Programmable Frame size field 2 lbits:9 pfs3 Programmable Frame size field 3 lbits:9 pfs4 Programmable Frame size field 4 lbits:5 reserved Reserved {} or dx4_config3 (Offset 17C) DX4 Configuration Register 3 <byte 8452> ulong value As longword endunion dx4_config3 (Offset 17C) DX4 Configuration Register 3 <byte 8456> union tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 8456> {field (By field)} <byte 8456> lbits:9 pfs Programmable Frame Size lbits:15 reserved Reserved lbits:8 esi_range Exchange_ID Signaled Interrupt Range {} or tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 8456> ulong value As longword endunion tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 8460> union tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 8460> {field (By field)} <byte 8460>

lbits:1 fad FCP Assist Disable lbits:1 ino In Order lbits:1 dof Discard OOO FCP Frames lbits:1 fua FCP Unassisted ACK Enable lbits:1 ime Interrupt Message Enable lbits:1 fab Fabric lbits:1 sic S_ID Copy Enable lbits:1 eqs Equal Service lbits:2 reserved Reserved lbits:1 aks Automatic ACK lbits:1 ddf Disable Delayed Freeze lbits:1 ebe Enable Big Endian Mode lbits:11 reserved1 Reserved lbits:1 fc2 FCP Class 2 Reassembly Enable lbits:1 reserved2 Reserved lbits:1 sdf Save Discarded Frames lbits:1 rde Response Detect Enable lbits:1 dam Default ACK Model lbits:2 reserved3 Reserved lbits:1 m66 66 MHz Enabled {} or tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 8460> ulong value As longword endunion tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 8464> union tach_control (Offset 188) Tachyon DX2+ Control <byte 8464> {field (By field)} <byte 8464> lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:3 reserved Reserved lbits:1 feq Freeze ERQ lbits:1 ffa Freeze FCP Assists lbits:2 reserved1 Reserved lbits:1 fis Freeze Inbound FCP Assists When Frame Placed in SFQ lbits:1 fib Freeze Inbound FCP Assists lbits:2 reserved2 Reserved lbits:1 req Resume ERQ lbits:1 rif Resume Inbound FCP Assists lbits:1 rof Resume Outbound FCP Assists lbits:12 reserved3 Reserved lbits:1 crs Core Reset {} or tach_control (Offset 188) Tachyon DX2+ Control <byte 8464> ulong value As longword endunion tach_control (Offset 188) Tachyon DX2+ Control <byte 8468> union tach_status (Offset 18C) Tachyon DX2+ Status <byte 8468> {field (By field)} <byte 8468> lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2

lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose Input 4 lbits:5 reserved Reserved lbits:1 ipe Inbound Parity Error lbits:1 ope Outbound Parity Error lbits:4 reserved1 Reserved lbits:1 eqf ERQ Frozen lbits:1 iff Inbound FCP Assists Frozen lbits:1 off Outbound FCP Assists Frozen lbits:4 reserved2 Reserved lbits:1 ifce Inbound FIFO CRC Error lbits:1 ofce Outbound FIFO CRC Error lbits:1 m66 66 Mhz Enabled lbits:1 ile Inbound Link Control FIFO Empty lbits:1 ole Outbound Link Control List Empty lbits:1 ife Inbound FIFO Empty lbits:1 ofe Outbound FIFO Empty lbits:1 imf IMQ Full lbits:1 ssf SFQ Full {} or tach_status (Offset 18C) Tachyon DX2+ Status <byte 8468> ulong value As longword endunion tach_status (Offset 18C) Tachyon DX2+ Status <byte 8472> {rsvd7 ((Offset 190) Reserved)} <byte 8472> ulong value {} <byte 8476> union hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 8476> {field (By field)} <byte 8476> lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 8476> ulong value As longword endunion hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 8480> union hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 8480> {field (By field)} <byte 8480> lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 8480> ulong value As longword endunion hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 8484> union inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 8484>

{field (By field)} <byte 8484> lbits:24 reserved Reserved lbits:8 sest_lru_count SEST LRU Count {} or inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 8484> ulong value As longword endunion inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 8488> union inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 8488> {field (By field)} <byte 8488> lbits:8 discd_frames Discarded Frame Count lbits:24 reserved Reserved {} or inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 8488> ulong value As longword endunion inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 8492> union ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) <byte 8492> {field (By field)} <byte 8492> lbits:28 threshold EE_Credit Zero Timer Threshold lbits:4 reserved Reserved {} or ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) <byte 8492> ulong value As longword endunion ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only ) <byte 8496> union up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 8496> {field (By field)} <byte 8496> lbits:12 reserved Reserved lbits:1 upper_addr1 Upper Data Address--44 bit data space lbits:19 upper_addr Upper Data Address {} or up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 8496> ulong value As longword endunion up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 8500> union up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 8500> {field (By field)} <byte 8500> lbits:32 upper_addr Upper Control Address {} or up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 8500> ulong value As longword endunion up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 8504> union dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3

<byte 8504> {field (By field)} <byte 8504> lbits:1 ef AL_PA 0xEF DHD Login Information lbits:1 e8 AL_PA 0xE8 DHD Login Information lbits:1 e4 AL_PA 0xE4 DHD Login Information lbits:1 e2 AL_PA 0xE2 DHD Login Information lbits:1 e1 AL_PA 0xE1 DHD Login Information lbits:1 e0 AL_PA 0xE0 DHD Login Information lbits:1 dc AL_PA 0xDC DHD Login Information lbits:1 da AL_PA 0xDA DHD Login Information lbits:1 d9 AL_PA 0xD9 DHD Login Information lbits:1 d6 AL_PA 0xD6 DHD Login Information lbits:1 d5 AL_PA 0xD5 DHD Login Information lbits:1 d4 AL_PA 0xD4 DHD Login Information lbits:1 d3 AL_PA 0xD3 DHD Login Information lbits:1 d2 AL_PA 0xD2 DHD Login Information lbits:1 d1 AL_PA 0xD1 DHD Login Information lbits:1 ce AL_PA 0xCE DHD Login Information lbits:1 cd AL_PA 0xCD DHD Login Information lbits:1 cc AL_PA 0xCC DHD Login Information lbits:1 cb AL_PA 0xCB DHD Login Information lbits:1 ca AL_PA 0xCA DHD Login Information lbits:1 c9 AL_PA 0xC9 DHD Login Information lbits:1 c7 AL_PA 0xC7 DHD Login Information lbits:1 c6 AL_PA 0xC6 DHD Login Information lbits:1 c5 AL_PA 0xC5 DHD Login Information lbits:1 c3 AL_PA 0xC3 DHD Login Information lbits:1 bc AL_PA 0xBC DHD Login Information lbits:1 ba AL_PA 0xBA DHD Login Information lbits:1 b9 AL_PA 0xB9 DHD Login Information lbits:1 b6 AL_PA 0xB6 DHD Login Information lbits:1 b5 AL_PA 0xB5 DHD Login Information lbits:1 b4 AL_PA 0xB4 DHD Login Information lbits:1 b3 AL_PA 0xB3 DHD Login Information {} or dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 8504> ulong value As longword endunion dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 8508> union dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 8508> {field (By field)} <byte 8508> lbits:1 alpab2 AL_PA 0xB2 DHD Login Information lbits:1 alpab1 AL_PA 0xB1 DHD Login Information lbits:1 alpaae AL_PA 0xAE DHD Login Information lbits:1 alpaad AL_PA 0xAD DHD Login Information lbits:1 alpaac AL_PA 0xAC DHD Login Information lbits:1 alpaab AL_PA 0xAB DHD Login Information lbits:1 alpaaa AL_PA 0xAA DHD Login Information lbits:1 alpaa9 AL_PA 0xA9 DHD Login Information lbits:1 alpaa7 AL_PA 0xA7 DHD Login Information lbits:1 alpaa6 AL_PA 0xA6 DHD Login Information lbits:1 alpaa5 AL_PA 0xA5 DHD Login Information lbits:1 alpaa3 AL_PA 0xA3 DHD Login Information lbits:1 alpa9f AL_PA 0x9F DHD Login Information lbits:1 alpa9e AL_PA 0x9E DHD Login Information lbits:1 alpa9d AL_PA 0x9D DHD Login Information

lbits:1 alpa9b AL_PA 0x9B DHD Login Information lbits:1 alpa98 AL_PA 0x98 DHD Login Information lbits:1 alpa97 AL_PA 0x97 DHD Login Information lbits:1 alpa90 AL_PA 0x90 DHD Login Information lbits:1 alpa8f AL_PA 0x8F DHD Login Information lbits:1 alpa88 AL_PA 0x88 DHD Login Information lbits:1 alpa84 AL_PA 0x84 DHD Login Information lbits:1 alpa82 AL_PA 0x82 DHD Login Information lbits:1 alpa81 AL_PA 0x81 DHD Login Information lbits:1 alpa80 AL_PA 0x80 DHD Login Information lbits:1 alpa7c AL_PA 0x7C DHD Login Information lbits:1 alpa7a AL_PA 0x7A DHD Login Information lbits:1 alpa79 AL_PA 0x79 DHD Login Information lbits:1 alpa76 AL_PA 0x76 DHD Login Information lbits:1 alpa75 AL_PA 0x75 DHD Login Information lbits:1 alpa74 AL_PA 0x74 DHD Login Information lbits:1 alpa73 AL_PA 0x73 DHD Login Information {} or dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 8508> ulong value As longword endunion dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 8512> union dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 8512> {field (By field)} <byte 8512> lbits:1 alpa72 AL_PA 0x72 DHD Login Information lbits:1 alpa71 AL_PA 0x71 DHD Login Information lbits:1 alpa6e AL_PA 0x6E DHD Login Information lbits:1 alpa6d AL_PA 0x6D DHD Login Information lbits:1 alpa6c AL_PA 0x6C DHD Login Information lbits:1 alpa6b AL_PA 0x6B DHD Login Information lbits:1 alpa6a AL_PA 0x6A DHD Login Information lbits:1 alpa69 AL_PA 0x69 DHD Login Information lbits:1 alpa67 AL_PA 0x67 DHD Login Information lbits:1 alpa66 AL_PA 0x66 DHD Login Information lbits:1 alpa65 AL_PA 0x65 DHD Login Information lbits:1 alpa63 AL_PA 0x63 DHD Login Information lbits:1 alpa5c AL_PA 0x5C DHD Login Information lbits:1 alpa5a AL_PA 0x5A DHD Login Information lbits:1 alpa59 AL_PA 0x59 DHD Login Information lbits:1 alpa56 AL_PA 0x56 DHD Login Information lbits:1 alpa55 AL_PA 0x55 DHD Login Information lbits:1 alpa54 AL_PA 0x54 DHD Login Information lbits:1 alpa53 AL_PA 0x53 DHD Login Information lbits:1 alpa52 AL_PA 0x52 DHD Login Information lbits:1 alpa51 AL_PA 0x51 DHD Login Information lbits:1 alpa4e AL_PA 0x4E DHD Login Information lbits:1 alpa4d AL_PA 0x4D DHD Login Information lbits:1 alpa4c AL_PA 0x4C DHD Login Information lbits:1 alpa4b AL_PA 0x4B DHD Login Information lbits:1 alpa4a AL_PA 0x4A DHD Login Information lbits:1 alpa49 AL_PA 0x49 DHD Login Information lbits:1 alpa47 AL_PA 0x47 DHD Login Information lbits:1 alpa46 AL_PA 0x46 DHD Login Information lbits:1 alpa45 AL_PA 0x45 DHD Login Information lbits:1 alpa43 AL_PA 0x43 DHD Login Information lbits:1 alpa3c AL_PA 0x3C DHD Login Information {}

or dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 8512> ulong value As longword endunion dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 8516> union dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 8516> {field (By field)} <byte 8516> lbits:1 alpa3a AL_PA 0x3A DHD Login Information lbits:1 alpa39 AL_PA 0x39 DHD Login Information lbits:1 alpa36 AL_PA 0x36 DHD Login Information lbits:1 alpa35 AL_PA 0x35 DHD Login Information lbits:1 alpa34 AL_PA 0x34 DHD Login Information lbits:1 alpa33 AL_PA 0x33 DHD Login Information lbits:1 alpa32 AL_PA 0x32 DHD Login Information lbits:1 alpa31 AL_PA 0x31 DHD Login Information lbits:1 alpa2e AL_PA 0x2E DHD Login Information lbits:1 alpa2d AL_PA 0x2D DHD Login Information lbits:1 alpa2c AL_PA 0x2C DHD Login Information lbits:1 alpa2b AL_PA 0x2B DHD Login Information lbits:1 alpa2a AL_PA 0x2A DHD Login Information lbits:1 alpa29 AL_PA 0x29 DHD Login Information lbits:1 alpa27 AL_PA 0x27 DHD Login Information lbits:1 alpa26 AL_PA 0x26 DHD Login Information lbits:1 alpa25 AL_PA 0x25 DHD Login Information lbits:1 alpa23 AL_PA 0x23 DHD Login Information lbits:1 alpa1f AL_PA 0x1F DHD Login Information lbits:1 alpa1e AL_PA 0x1E DHD Login Information lbits:1 alpa1d AL_PA 0x1D DHD Login Information lbits:1 alpa1b AL_PA 0x1B DHD Login Information lbits:1 alpa18 AL_PA 0x18 DHD Login Information lbits:1 alpa17 AL_PA 0x17 DHD Login Information lbits:1 alpa10 AL_PA 0x10 DHD Login Information lbits:1 alpa0f AL_PA 0x0F DHD Login Information lbits:1 alpa08 AL_PA 0x08 DHD Login Information lbits:1 alpa04 AL_PA 0x04 DHD Login Information lbits:1 alpa02 AL_PA 0x02 DHD Login Information lbits:1 alpa01 AL_PA 0x01 DHD Login Information lbits:1 alpa00 AL_PA 0x00 DHD Login Information lbits:1 reserved Reserved {} or dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 8516> ulong value As longword endunion dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 8520> union fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 8520> {field (By field)} <byte 8520> lbits:1 bli Bypass Loop Initialization lbits:1 reserved Reserved lbits:1 enp Enable N_Port Mode lbits:1 lr Login Required lbits:1 inif Initialize as Fabric lbits:1 rf Respond to Fabric Address lbits:1 blm Bypass Loop Map lbits:1 sa Acquire Soft Address lbits:1 ha Acquire Hard Address

lbits:1 aq Acquire Previously Acquired Address lbits:1 fa Acquire Fabric Aquired Address lbits:1 td Timer Disable lbits:1 sap Skip Arbitration Phase lbits:1 elb External Loopback/Pad Loopback lbits:1 ilb Internal loopback lbits:1 npi Initialize as N_Port lbits:8 bb_credit BB_Credit lbits:8 al_pa Desired AL_PA {} or fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 8520> ulong value As longword endunion fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 8524> union fm_control (Offset 1C4) Frame Manager Control <byte 8524> {field (By field)} <byte 8524> lbits:3 cmd State Machine Command lbits:1 cl Close Loop Request lbits:1 reserved Reserved lbits:1 sp Send Prim_Reg lbits:1 sq Primitive Sequence lbits:25 reserved1 Reserved {} or fm_control (Offset 1C4) Frame Manager Control <byte 8524> ulong value As longword endunion fm_control (Offset 1C4) Frame Manager Control <byte 8528> union fm_status (Offset 1C8) Frame Manager Status <byte 8528> {field (By field)} <byte 8528> lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error

lbits:1 lp Loop {} or fm_status (Offset 1C8) Frame Manager Status <byte 8528> ulong value As longword endunion fm_status (Offset 1C8) Frame Manager Status <byte 8532> union fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 8532> {field (By field)} <byte 8532> lbits:16 ed_tov Error Detect Time-Out lbits:9 rt_tov Receiver Transmitter Time-Out lbits:7 reserved Reserved {} or fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 8532> ulong value As longword endunion fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 8536> union fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 8536> {field (By field)} <byte 8536> lbits:8 link_fail Link Fail Count lbits:8 loss_of_sync Loss of Synchronization Count lbits:8 bad_rx_char Bad Received Character Count lbits:8 loss_of_signal Loss of Signal Count {} or fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 8536> ulong value As longword endunion fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 8540> union fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 8540> {field (By field)} <byte 8540> lbits:8 proto_er Protocol Error Count lbits:8 bad_crc Bad CRC Count lbits:8 dis_frm Discarded Frames lbits:8 rx_eofa Received EOFa {} or fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 8540> ulong value As longword endunion fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 8544> union fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 8544> {field (By field)} <byte 8544> lbits:9 al_time Arbitrated Loop Time-Out lbits:7 reserved Reserved lbits:16 lp_tov Loop Time-Out {} or fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 8544> ulong value As longword endunion fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2

<byte 8548> union fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 8548> {field (By field)} <byte 8548> lbits:24 bb0_timer BB_Credit Timer lbits:8 reserved Reserved {} or fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 8548> ulong value As longword endunion fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 8552> union fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 8552> {field (By field)} <byte 8552> lbits:32 wwn World Wide Name {} or fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 8552> ulong value As longword endunion fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 8556> union fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 8556> {field (By field)} <byte 8556> lbits:32 wwn World Wide Name {} or fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 8556> ulong value As longword endunion fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 8560> union fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 8560> {field (By field)} <byte 8560> lbits:8 lipf_alpa AL_PA of Most Recent LIPf Received lbits:8 bad_alpa AL_PA of Most Recent OPN Sent and Returned Without Being Accept ed lbits:8 acq_alpa AL_PA Acquired During Loop Initialization lbits:8 reserved Reserved {} or fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 8560> ulong value As longword endunion fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 8564> union fm_primitive (Offset 1EC) Frame Manager Primitive <byte 8564> {field (By field)} <byte 8564> lbits:24 prim_value Primitive to be Sent lbits:8 reserved Reserved {} or fm_primitive (Offset 1EC) Frame Manager Primitive <byte 8564> ulong value As longword

endunion fm_primitive (Offset 1EC) Frame Manager Primitive <byte 8568> union fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 8568> {field (By field)} <byte 8568> lbits:8 exp_frm Expired Frames lbits:24 reserved Reserved {} or fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 8568> ulong value As longword endunion fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 8572> union fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 8572> {field (By field)} <byte 8572> lbits:1 dac Disable Auto Close lbits:2 nbc Non-zero Login BB_Credit lbits:1 eei Enable ERR_INIT lbits:1 icb Ignore Close Bit lbits:2 atv Arbitration Threshold Value lbits:1 gde Garbage Deletion Enable lbits:8 laa Lowest Allowable AL_PA lbits:5 reserved Reserved lbits:1 dao Disable 2xAL_TIME Timeout on Open lbits:3 reserved1 Reserved lbits:1 prm Promiscuous Mode lbits:1 wpe Wait For Port Enable lbits:1 fmh Force Monitor State With Hard Address lbits:1 fmn Force Monitor Non-participating State lbits:1 dlm Disable Loop Master lbits:1 dsa Disable Soft Address Selection lbits:1 ilp Ignore LPB/LPE Primitive Sequences {} or fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 8572> ulong value As longword endunion fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 8576> union pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED <byte 8576> {field (By field)} <byte 8576> {pci_rsvd1F8 ((Offset 1F8) Reserved)} <byte 8576> utiny value {} <byte 8577> {pci_rsvd1F9 ((Offset 1F9) Reserved)} <byte 8577> utiny value {} <byte 8578> union romctr (Offset 1FA) PCI ROM Control <byte 8578> {field (By field)} <byte 8578> tbits:1 vpp_en ROM VPP Enable

tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or romctr (Offset 1FA) PCI ROM Control <byte 8578> utiny value As byte endunion romctr (Offset 1FA) PCI ROM Control <byte 8579> union mctr (Offset 1FB) PCI Master Control <byte 8579> {field (By field)} <byte 8579> tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or mctr (Offset 1FB) PCI Master Control <byte 8579> utiny value As byte endunion mctr (Offset 1FB) PCI Master Control {} or pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED <byte 8576> ulong value As longword endunion pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED <byte 8580> union pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST <byte 8580> {field (By field)} <byte 8580> union softrst (Offset 1FC) PCI Interface Reset Control <byte 8580> {field (By field)} <byte 8580> tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or softrst (Offset 1FC) PCI Interface Reset Control <byte 8580> utiny value As byte endunion softrst (Offset 1FC) PCI Interface Reset Control <byte 8581> union intpend (Offset 1FD) PCI Interrupt Pending <byte 8581> {field (By field)} <byte 8581> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intpend (Offset 1FD) PCI Interrupt Pending <byte 8581> utiny value As byte endunion intpend (Offset 1FD) PCI Interrupt Pending <byte 8582>

union inten (Offset 1FE) PCI Interrupt Enable <byte 8582> {field (By field)} <byte 8582> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or inten (Offset 1FE) PCI Interrupt Enable <byte 8582> utiny value As byte endunion inten (Offset 1FE) PCI Interrupt Enable <byte 8583> union intstat (Offset 1FF) PCI Interrupt Status <byte 8583> {field (By field)} <byte 8583> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intstat (Offset 1FF) PCI Interrupt Status <byte 8583> utiny value As byte endunion intstat (Offset 1FF) PCI Interrupt Status {} or pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST <byte 8580> ulong value As longword endunion pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST {} endunion csr[3] Tachyon DX2+ CSR Registers <byte 8584> union csr[4] Tachyon DX2+ CSR Registers <byte 8584> ulong[128] csra Tachyon DX2+ CSR Registers As Longwords or csr[4] Tachyon DX2+ CSR Registers <byte 8584> {csr (Tachyon DX2+ CSR Registers By Field)} <byte 8584> union erq_base (Offset 000) ERQ Base (write only) <byte 8584> {field (By field)} <byte 8584> lbits:32 address ERQ Base Address {} or erq_base (Offset 000) ERQ Base (write only) <byte 8584> ulong value As longword endunion erq_base (Offset 000) ERQ Base (write only) <byte 8588> union erq_len (Offset 004) ERQ Length (write only) <byte 8588> {field (By field)}

<byte 8588> lbits:12 length ERQ Length lbits:20 reserved Reserved {} or erq_len (Offset 004) ERQ Length (write only) <byte 8588> ulong value As longword endunion erq_len (Offset 004) ERQ Length (write only) <byte 8592> union erq_prod (Offset 008) ERQ Producer Index <byte 8592> {field (By field)} <byte 8592> lbits:12 index ERQ Producer Index lbits:20 reserved Reserved {} or erq_prod (Offset 008) ERQ Producer Index <byte 8592> ulong value As longword endunion erq_prod (Offset 008) ERQ Producer Index <byte 8596> union erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 8596> {field (By field)} <byte 8596> lbits:32 address ERQ Consumer Index Address {} or erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 8596> ulong value As longword endunion erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 8600> union erq_cons (Offset 010) ERQ Consumer Index <byte 8600> {field (By field)} <byte 8600> lbits:12 index ERQ Consumer Index lbits:20 reserved Reserved {} or erq_cons (Offset 010) ERQ Consumer Index <byte 8600> ulong value As longword endunion erq_cons (Offset 010) ERQ Consumer Index <byte 8604> {rsvd1[0] ((Offset 014-04F) Reserved)} <byte 8604> ulong value {} <byte 8608> {rsvd1[1] ((Offset 014-04F) Reserved)} <byte 8608> ulong value {} <byte 8612> {rsvd1[2] ((Offset 014-04F) Reserved)} <byte 8612> ulong value {} <byte 8616> {rsvd1[3] ((Offset 014-04F) Reserved)}

<byte 8616> ulong value {} <byte 8620> {rsvd1[4] ((Offset 014-04F) Reserved)} <byte 8620> ulong value {} <byte 8624> {rsvd1[5] ((Offset 014-04F) Reserved)} <byte 8624> ulong value {} <byte 8628> {rsvd1[6] ((Offset 014-04F) Reserved)} <byte 8628> ulong value {} <byte 8632> {rsvd1[7] ((Offset 014-04F) Reserved)} <byte 8632> ulong value {} <byte 8636> {rsvd1[8] ((Offset 014-04F) Reserved)} <byte 8636> ulong value {} <byte 8640> {rsvd1[9] ((Offset 014-04F) Reserved)} <byte 8640> ulong value {} <byte 8644> {rsvd1[10] ((Offset 014-04F) Reserved)} <byte 8644> ulong value {} <byte 8648> {rsvd1[11] ((Offset 014-04F) Reserved)} <byte 8648> ulong value {} <byte 8652> {rsvd1[12] ((Offset 014-04F) Reserved)} <byte 8652> ulong value {} <byte 8656> {rsvd1[13] ((Offset 014-04F) Reserved)} <byte 8656> ulong value {} <byte 8660> {rsvd1[14] ((Offset 014-04F) Reserved)} <byte 8660> ulong value {} <byte 8664> union sfq_base (Offset 050) SFQ Base (write only)

<byte 8664> {field (By field)} <byte 8664> lbits:32 address SFQ Base Address {} or sfq_base (Offset 050) SFQ Base (write only) <byte 8664> ulong value As longword endunion sfq_base (Offset 050) SFQ Base (write only) <byte 8668> union sfq_len (Offset 054) SFQ Length (write only) <byte 8668> {field (By field)} <byte 8668> lbits:12 length SFQ Length lbits:20 reserved Reserved {} or sfq_len (Offset 054) SFQ Length (write only) <byte 8668> ulong value As longword endunion sfq_len (Offset 054) SFQ Length (write only) <byte 8672> union sfq_cons (Offset 058) SFQ Consumer Index <byte 8672> {field (By field)} <byte 8672> lbits:12 index SFQ Consumer Index lbits:20 reserved Reserved {} or sfq_cons (Offset 058) SFQ Consumer Index <byte 8672> ulong value As longword endunion sfq_cons (Offset 058) SFQ Consumer Index <byte 8676> {rsvd2[0] ((Offset 05C-07B) Reserved)} <byte 8676> ulong value {} <byte 8680> {rsvd2[1] ((Offset 05C-07B) Reserved)} <byte 8680> ulong value {} <byte 8684> {rsvd2[2] ((Offset 05C-07B) Reserved)} <byte 8684> ulong value {} <byte 8688> {rsvd2[3] ((Offset 05C-07B) Reserved)} <byte 8688> ulong value {} <byte 8692> {rsvd2[4] ((Offset 05C-07B) Reserved)} <byte 8692> ulong value {} <byte 8696> {rsvd2[5] ((Offset 05C-07B) Reserved)}

<byte 8696> ulong value {} <byte 8700> {rsvd2[6] ((Offset 05C-07B) Reserved)} <byte 8700> ulong value {} <byte 8704> {rsvd2[7] ((Offset 05C-07B) Reserved)} <byte 8704> ulong value {} <byte 8708> union int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 8708> {field (By field)} <byte 8708> lbits:4 timer Interrupt Timer Value lbits:3 reserved Reserved lbits:1 ihf Interrupt when IMQ Half Full lbits:24 reserved1 Reserved {} or int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 8708> ulong value As longword endunion int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 8712> union imq_base (Offset 080) IMQ Base (write only) <byte 8712> {field (By field)} <byte 8712> lbits:32 address IMQ Base Address {} or imq_base (Offset 080) IMQ Base (write only) <byte 8712> ulong value As longword endunion imq_base (Offset 080) IMQ Base (write only) <byte 8716> union imq_len (Offset 084) IMQ Length (write only) <byte 8716> {field (By field)} <byte 8716> lbits:12 length IMQ Length lbits:20 reserved Reserved {} or imq_len (Offset 084) IMQ Length (write only) <byte 8716> ulong value As longword endunion imq_len (Offset 084) IMQ Length (write only) <byte 8720> union imq_cons (Offset 088) IMQ Consumer Index <byte 8720> {field (By field)} <byte 8720> lbits:12 index IMQ Consumer Index lbits:20 reserved Reserved {} or imq_cons (Offset 088) IMQ Consumer Index <byte 8720>

ulong value As longword endunion imq_cons (Offset 088) IMQ Consumer Index <byte 8724> union imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 8724> {field (By field)} <byte 8724> lbits:32 address IMQ Producer Index Address {} or imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 8724> ulong value As longword endunion imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 8728> {rsvd3[0] ((Offset 090-0FC) Reserved)} <byte 8728> ulong value {} <byte 8732> {rsvd3[1] ((Offset 090-0FC) Reserved)} <byte 8732> ulong value {} <byte 8736> {rsvd3[2] ((Offset 090-0FC) Reserved)} <byte 8736> ulong value {} <byte 8740> {rsvd3[3] ((Offset 090-0FC) Reserved)} <byte 8740> ulong value {} <byte 8744> {rsvd3[4] ((Offset 090-0FC) Reserved)} <byte 8744> ulong value {} <byte 8748> {rsvd3[5] ((Offset 090-0FC) Reserved)} <byte 8748> ulong value {} <byte 8752> {rsvd3[6] ((Offset 090-0FC) Reserved)} <byte 8752> ulong value {} <byte 8756> {rsvd3[7] ((Offset 090-0FC) Reserved)} <byte 8756> ulong value {} <byte 8760> {rsvd3[8] ((Offset 090-0FC) Reserved)} <byte 8760> ulong value {} <byte 8764> {rsvd3[9] ((Offset 090-0FC) Reserved)}

<byte 8764> ulong value {} <byte 8768> {rsvd3[10] ((Offset <byte 8768> ulong value {} <byte 8772> {rsvd3[11] ((Offset <byte 8772> ulong value {} <byte 8776> {rsvd3[12] ((Offset <byte 8776> ulong value {} <byte 8780> {rsvd3[13] ((Offset <byte 8780> ulong value {} <byte 8784> {rsvd3[14] ((Offset <byte 8784> ulong value {} <byte 8788> {rsvd3[15] ((Offset <byte 8788> ulong value {} <byte 8792> {rsvd3[16] ((Offset <byte 8792> ulong value {} <byte 8796> {rsvd3[17] ((Offset <byte 8796> ulong value {} <byte 8800> {rsvd3[18] ((Offset <byte 8800> ulong value {} <byte 8804> {rsvd3[19] ((Offset <byte 8804> ulong value {} <byte 8808> {rsvd3[20] ((Offset <byte 8808> ulong value {} <byte 8812> {rsvd3[21] ((Offset

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

<byte 8812> ulong value {} <byte 8816> {rsvd3[22] ((Offset 090-0FC) Reserved)} <byte 8816> ulong value {} <byte 8820> {rsvd3[23] ((Offset 090-0FC) Reserved)} <byte 8820> ulong value {} <byte 8824> {rsvd3[24] ((Offset 090-0FC) Reserved)} <byte 8824> ulong value {} <byte 8828> {rsvd3[25] ((Offset 090-0FC) Reserved)} <byte 8828> ulong value {} <byte 8832> {rsvd3[26] ((Offset 090-0FC) Reserved)} <byte 8832> ulong value {} <byte 8836> {rsvd3[27] ((Offset 090-0FC) Reserved)} <byte 8836> ulong value {} <byte 8840> union fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 8840> {field (By field)} <byte 8840> lbits:6 bec Termination Receive lbits:3 reserved4 Reserved lbits:1 xrb Wrapback lbits:2 reserved Reserved lbits:3 xem Output pre-emphasis lbits:4 reserved1 Reserved lbits:1 mustbe1 Must be 1 lbits:1 stb Start BERT lbits:1 enb Enable BERT lbits:2 sdm Signal differential mode lbits:2 rxs Receiver Speed lbits:2 txs Transmitter Speed lbits:1 reserved3 Reserved lbits:1 xlr Force iTR to lock reference clock lbits:1 reserved0 Reserved lbits:1 xcv Type of Transceiver {} or fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 8840> ulong value As longword endunion fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 8844>

union fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 8844> {field (By field)} <byte 8844> lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 8844> ulong value As longword endunion fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 8848> {rsvd3a[0] ((Offset 108-10f) Reserved)} <byte 8848> ulong value {} <byte 8852> {rsvd3a[1] ((Offset 108-10f) Reserved)} <byte 8852> ulong value {} <byte 8856> union sfp_cmd_status (Offset 110) SFP command and status <byte 8856> {field (No description available)} <byte 8856> lbits:1 gna Generate NACK lbits:1 rts Reset Slave lbits:1 wrc Write command lbits:1 rdc Read command lbits:1 gst Generate Stop lbits:1 sta Generate Start lbits:2 reserved1 Reserved lbits:1 rna Received NACK lbits:1 sby SFP Busy lbits:1 tip Transfer in progress

lbits:9 reserved Reserved lbits:12 lp Clock Divisor {} or sfp_cmd_status (Offset 110) SFP command and status <byte 8856> ulong value endunion sfp_cmd_status (Offset 110) SFP command and status <byte 8860> union sfp_data (Offset 114) SFP data <byte 8860> {field (By field)} <byte 8860> lbits:8 sfpd SFPD Transmit lbits:24 reserved Reserved {} or sfp_data (Offset 114) SFP data <byte 8860> ulong value As longword endunion sfp_data (Offset 114) SFP data <byte 8864> union fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 8864> {field (By field)} <byte 8864> lbits:1 tbe Transmit Link BIST error lbits:1 tlr Transmit Link BIST reset lbits:1 tle Transmit Link BIST enable lbits:1 rbe Receive Link BIST error lbits:1 rll Receive Link BIST loop-back lbits:1 rlr Receive Link BIST reset lbits:1 rle Receive Link BIST enable lbits:7 reserved3 Reserved lbits:1 ipl ITR PPL Lock lbits:1 reserved2 Reserved lbits:1 dtf Disable transceiver LOS filter lbits:1 dtl Disable transceiver LOS lbits:1 dsr Disable iTR RXLOS lbits:1 ttd Transceiver Tx Disable lbits:2 reserved1 Reserved lbits:1 rfl Receive ast Lock Disable lbits:9 reserved Reserved {} or fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 8864> ulong value As longword endunion fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 8868> union fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 8868> {field (By field)} <byte 8868> lbits:32 reserved Reserved {} or fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 8868> ulong value As longword endunion fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 8872> {rsvd3b[0] ((Offset 120-13F) Reserved)} <byte 8872>

ulong value {} <byte 8876> {rsvd3b[1] ((Offset 120-13F) Reserved)} <byte 8876> ulong value {} <byte 8880> {rsvd3b[2] ((Offset 120-13F) Reserved)} <byte 8880> ulong value {} <byte 8884> {rsvd3b[3] ((Offset 120-13F) Reserved)} <byte 8884> ulong value {} <byte 8888> {rsvd3b[4] ((Offset 120-13F) Reserved)} <byte 8888> ulong value {} <byte 8892> {rsvd3b[5] ((Offset 120-13F) Reserved)} <byte 8892> ulong value {} <byte 8896> {rsvd3b[6] ((Offset 120-13F) Reserved)} <byte 8896> ulong value {} <byte 8900> {rsvd3b[7] ((Offset 120-13F) Reserved)} <byte 8900> ulong value {} <byte 8904> union sest_base (Offset 140) SEST Base (write only) <byte 8904> {field (By field)} <byte 8904> lbits:32 address SEST Base Address {} or sest_base (Offset 140) SEST Base (write only) <byte 8904> ulong value As longword endunion sest_base (Offset 140) SEST Base (write only) <byte 8908> union sest_len (Offset 144) SEST Length (write only) <byte 8908> {field (By field)} <byte 8908> lbits:16 length SEST Length lbits:16 reserved Reserved {} or sest_len (Offset 144) SEST Length (write only) <byte 8908> ulong value As longword endunion sest_len (Offset 144) SEST Length (write only)

<byte 8912> {rsvd4 ((Offset 148) Reserved)} <byte 8912> ulong value {} <byte 8916> union scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 8916> {field (By field)} <byte 8916> lbits:16 tail Tail lbits:16 head Head {} or scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 8916> ulong value As longword endunion scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 8920> union prog_addr (Offset 150) Programmable Address register <byte 8920> {field (By field)} <byte 8920> lbits:20 ra ROM/RAM address lbits:11 reserved Reserved lbits:1 inc Increment {} or prog_addr (Offset 150) Programmable Address register <byte 8920> ulong value As longword endunion prog_addr (Offset 150) Programmable Address register <byte 8924> union prog_data (Offset 154) programmable data register <byte 8924> {field (By field)} <byte 8924> lbits:32 pdr Programmable data {} or prog_data (Offset 154) programmable data register <byte 8924> ulong value As longword endunion prog_data (Offset 154) programmable data register <byte 8928> {rsvd5[0] ((Offset 158-15F) Reserved)} <byte 8928> ulong value {} <byte 8932> {rsvd5[1] ((Offset 158-15F) Reserved)} <byte 8932> ulong value {} <byte 8936> union int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 8936> {field (By field)} <byte 8936> lbits:32 address Interrupt Message Address {} or int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 8936>

ulong value As longword endunion int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 8940> union int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 8940> {field (By field)} <byte 8940> lbits:32 value Interrupt Message Value {} or int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 8940> ulong value As longword endunion int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 8944> union sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 8944> {field (By field)} <byte 8944> lbits:8 length SGL Page Length lbits:24 reserved Reserved {} or sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 8944> ulong value As longword endunion sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 8948> union my_id (Offset 16C) My ID <byte 8948> {field (By field)} <byte 8948> lbits:24 id My ID lbits:8 reserved Reserved {} or my_id (Offset 16C) My ID <byte 8948> ulong value As longword endunion my_id (Offset 16C) My ID <byte 8952> union gpio (Offset 170) General Purpose I/O <byte 8952> {field (By field)} <byte 8952> lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:1 gc5 General Purpose Control 5 lbits:1 gc6 General Purpose Control 6 lbits:1 gc7 General Purpose Control 7 lbits:8 reserved Reserved lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose I/O 4 lbits:1 gp5 General Purpose I/O 5 lbits:1 gp6 General Purpose I/O 6 lbits:1 gp7 General Purpose I/O 7 lbits:8 reserved1 Reserved

{} or gpio (Offset 170) General Purpose I/O <byte 8952> ulong value As longword endunion gpio (Offset 170) General Purpose I/O <byte 8956> {rsvd6a ((Offset 174-177) Reserved)} <byte 8956> ulong value {} <byte 8960> union edc_config (Offset 178) EDC Configuration Register <byte 8960> {field (By field)} <byte 8960> lbits:16 io_seed Starting Seed lbits:16 reserved Reserved {} or edc_config (Offset 178) EDC Configuration Register <byte 8960> ulong value As longword endunion edc_config (Offset 178) EDC Configuration Register <byte 8964> union dx4_config3 (Offset 17C) DX4 Configuration Register 3 <byte 8964> {field (By field)} <byte 8964> lbits:9 pfs2 Programmable Frame size field 2 lbits:9 pfs3 Programmable Frame size field 3 lbits:9 pfs4 Programmable Frame size field 4 lbits:5 reserved Reserved {} or dx4_config3 (Offset 17C) DX4 Configuration Register 3 <byte 8964> ulong value As longword endunion dx4_config3 (Offset 17C) DX4 Configuration Register 3 <byte 8968> union tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 8968> {field (By field)} <byte 8968> lbits:9 pfs Programmable Frame Size lbits:15 reserved Reserved lbits:8 esi_range Exchange_ID Signaled Interrupt Range {} or tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 8968> ulong value As longword endunion tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 8972> union tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 8972> {field (By field)} <byte 8972> lbits:1 fad FCP Assist Disable lbits:1 ino In Order lbits:1 dof Discard OOO FCP Frames lbits:1 fua FCP Unassisted ACK Enable lbits:1 ime Interrupt Message Enable lbits:1 fab Fabric

lbits:1 sic S_ID Copy Enable lbits:1 eqs Equal Service lbits:2 reserved Reserved lbits:1 aks Automatic ACK lbits:1 ddf Disable Delayed Freeze lbits:1 ebe Enable Big Endian Mode lbits:11 reserved1 Reserved lbits:1 fc2 FCP Class 2 Reassembly Enable lbits:1 reserved2 Reserved lbits:1 sdf Save Discarded Frames lbits:1 rde Response Detect Enable lbits:1 dam Default ACK Model lbits:2 reserved3 Reserved lbits:1 m66 66 MHz Enabled {} or tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 8972> ulong value As longword endunion tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 8976> union tach_control (Offset 188) Tachyon DX2+ Control <byte 8976> {field (By field)} <byte 8976> lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:3 reserved Reserved lbits:1 feq Freeze ERQ lbits:1 ffa Freeze FCP Assists lbits:2 reserved1 Reserved lbits:1 fis Freeze Inbound FCP Assists When Frame Placed in SFQ lbits:1 fib Freeze Inbound FCP Assists lbits:2 reserved2 Reserved lbits:1 req Resume ERQ lbits:1 rif Resume Inbound FCP Assists lbits:1 rof Resume Outbound FCP Assists lbits:12 reserved3 Reserved lbits:1 crs Core Reset {} or tach_control (Offset 188) Tachyon DX2+ Control <byte 8976> ulong value As longword endunion tach_control (Offset 188) Tachyon DX2+ Control <byte 8980> union tach_status (Offset 18C) Tachyon DX2+ Status <byte 8980> {field (By field)} <byte 8980> lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose Input 4 lbits:5 reserved Reserved lbits:1 ipe Inbound Parity Error lbits:1 ope Outbound Parity Error lbits:4 reserved1 Reserved

lbits:1 eqf ERQ Frozen lbits:1 iff Inbound FCP Assists Frozen lbits:1 off Outbound FCP Assists Frozen lbits:4 reserved2 Reserved lbits:1 ifce Inbound FIFO CRC Error lbits:1 ofce Outbound FIFO CRC Error lbits:1 m66 66 Mhz Enabled lbits:1 ile Inbound Link Control FIFO Empty lbits:1 ole Outbound Link Control List Empty lbits:1 ife Inbound FIFO Empty lbits:1 ofe Outbound FIFO Empty lbits:1 imf IMQ Full lbits:1 ssf SFQ Full {} or tach_status (Offset 18C) Tachyon DX2+ Status <byte 8980> ulong value As longword endunion tach_status (Offset 18C) Tachyon DX2+ Status <byte 8984> {rsvd7 ((Offset 190) Reserved)} <byte 8984> ulong value {} <byte 8988> union hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 8988> {field (By field)} <byte 8988> lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 8988> ulong value As longword endunion hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 8992> union hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 8992> {field (By field)} <byte 8992> lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 8992> ulong value As longword endunion hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 8996> union inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 8996> {field (By field)} <byte 8996> lbits:24 reserved Reserved lbits:8 sest_lru_count SEST LRU Count {} or inbound_rstat1 (Offset 19C) Inbound Resource Status 1

<byte 8996> ulong value As longword endunion inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 9000> union inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 9000> {field (By field)} <byte 9000> lbits:8 discd_frames Discarded Frame Count lbits:24 reserved Reserved {} or inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 9000> ulong value As longword endunion inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 9004> union ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) <byte 9004> {field (By field)} <byte 9004> lbits:28 threshold EE_Credit Zero Timer Threshold lbits:4 reserved Reserved {} or ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) <byte 9004> ulong value As longword endunion ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only ) <byte 9008> union up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 9008> {field (By field)} <byte 9008> lbits:12 reserved Reserved lbits:1 upper_addr1 Upper Data Address--44 bit data space lbits:19 upper_addr Upper Data Address {} or up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 9008> ulong value As longword endunion up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 9012> union up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 9012> {field (By field)} <byte 9012> lbits:32 upper_addr Upper Control Address {} or up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 9012> ulong value As longword endunion up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 9016> union dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 9016> {field (By field)} <byte 9016> lbits:1 ef AL_PA 0xEF DHD Login Information lbits:1 e8 AL_PA 0xE8 DHD Login Information lbits:1 e4 AL_PA 0xE4 DHD Login Information

lbits:1 e2 AL_PA 0xE2 DHD Login Information lbits:1 e1 AL_PA 0xE1 DHD Login Information lbits:1 e0 AL_PA 0xE0 DHD Login Information lbits:1 dc AL_PA 0xDC DHD Login Information lbits:1 da AL_PA 0xDA DHD Login Information lbits:1 d9 AL_PA 0xD9 DHD Login Information lbits:1 d6 AL_PA 0xD6 DHD Login Information lbits:1 d5 AL_PA 0xD5 DHD Login Information lbits:1 d4 AL_PA 0xD4 DHD Login Information lbits:1 d3 AL_PA 0xD3 DHD Login Information lbits:1 d2 AL_PA 0xD2 DHD Login Information lbits:1 d1 AL_PA 0xD1 DHD Login Information lbits:1 ce AL_PA 0xCE DHD Login Information lbits:1 cd AL_PA 0xCD DHD Login Information lbits:1 cc AL_PA 0xCC DHD Login Information lbits:1 cb AL_PA 0xCB DHD Login Information lbits:1 ca AL_PA 0xCA DHD Login Information lbits:1 c9 AL_PA 0xC9 DHD Login Information lbits:1 c7 AL_PA 0xC7 DHD Login Information lbits:1 c6 AL_PA 0xC6 DHD Login Information lbits:1 c5 AL_PA 0xC5 DHD Login Information lbits:1 c3 AL_PA 0xC3 DHD Login Information lbits:1 bc AL_PA 0xBC DHD Login Information lbits:1 ba AL_PA 0xBA DHD Login Information lbits:1 b9 AL_PA 0xB9 DHD Login Information lbits:1 b6 AL_PA 0xB6 DHD Login Information lbits:1 b5 AL_PA 0xB5 DHD Login Information lbits:1 b4 AL_PA 0xB4 DHD Login Information lbits:1 b3 AL_PA 0xB3 DHD Login Information {} or dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 9016> ulong value As longword endunion dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 9020> union dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 9020> {field (By field)} <byte 9020> lbits:1 alpab2 AL_PA 0xB2 DHD Login Information lbits:1 alpab1 AL_PA 0xB1 DHD Login Information lbits:1 alpaae AL_PA 0xAE DHD Login Information lbits:1 alpaad AL_PA 0xAD DHD Login Information lbits:1 alpaac AL_PA 0xAC DHD Login Information lbits:1 alpaab AL_PA 0xAB DHD Login Information lbits:1 alpaaa AL_PA 0xAA DHD Login Information lbits:1 alpaa9 AL_PA 0xA9 DHD Login Information lbits:1 alpaa7 AL_PA 0xA7 DHD Login Information lbits:1 alpaa6 AL_PA 0xA6 DHD Login Information lbits:1 alpaa5 AL_PA 0xA5 DHD Login Information lbits:1 alpaa3 AL_PA 0xA3 DHD Login Information lbits:1 alpa9f AL_PA 0x9F DHD Login Information lbits:1 alpa9e AL_PA 0x9E DHD Login Information lbits:1 alpa9d AL_PA 0x9D DHD Login Information lbits:1 alpa9b AL_PA 0x9B DHD Login Information lbits:1 alpa98 AL_PA 0x98 DHD Login Information lbits:1 alpa97 AL_PA 0x97 DHD Login Information lbits:1 alpa90 AL_PA 0x90 DHD Login Information lbits:1 alpa8f AL_PA 0x8F DHD Login Information lbits:1 alpa88 AL_PA 0x88 DHD Login Information

lbits:1 alpa84 AL_PA 0x84 DHD Login Information lbits:1 alpa82 AL_PA 0x82 DHD Login Information lbits:1 alpa81 AL_PA 0x81 DHD Login Information lbits:1 alpa80 AL_PA 0x80 DHD Login Information lbits:1 alpa7c AL_PA 0x7C DHD Login Information lbits:1 alpa7a AL_PA 0x7A DHD Login Information lbits:1 alpa79 AL_PA 0x79 DHD Login Information lbits:1 alpa76 AL_PA 0x76 DHD Login Information lbits:1 alpa75 AL_PA 0x75 DHD Login Information lbits:1 alpa74 AL_PA 0x74 DHD Login Information lbits:1 alpa73 AL_PA 0x73 DHD Login Information {} or dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 9020> ulong value As longword endunion dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 9024> union dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 9024> {field (By field)} <byte 9024> lbits:1 alpa72 AL_PA 0x72 DHD Login Information lbits:1 alpa71 AL_PA 0x71 DHD Login Information lbits:1 alpa6e AL_PA 0x6E DHD Login Information lbits:1 alpa6d AL_PA 0x6D DHD Login Information lbits:1 alpa6c AL_PA 0x6C DHD Login Information lbits:1 alpa6b AL_PA 0x6B DHD Login Information lbits:1 alpa6a AL_PA 0x6A DHD Login Information lbits:1 alpa69 AL_PA 0x69 DHD Login Information lbits:1 alpa67 AL_PA 0x67 DHD Login Information lbits:1 alpa66 AL_PA 0x66 DHD Login Information lbits:1 alpa65 AL_PA 0x65 DHD Login Information lbits:1 alpa63 AL_PA 0x63 DHD Login Information lbits:1 alpa5c AL_PA 0x5C DHD Login Information lbits:1 alpa5a AL_PA 0x5A DHD Login Information lbits:1 alpa59 AL_PA 0x59 DHD Login Information lbits:1 alpa56 AL_PA 0x56 DHD Login Information lbits:1 alpa55 AL_PA 0x55 DHD Login Information lbits:1 alpa54 AL_PA 0x54 DHD Login Information lbits:1 alpa53 AL_PA 0x53 DHD Login Information lbits:1 alpa52 AL_PA 0x52 DHD Login Information lbits:1 alpa51 AL_PA 0x51 DHD Login Information lbits:1 alpa4e AL_PA 0x4E DHD Login Information lbits:1 alpa4d AL_PA 0x4D DHD Login Information lbits:1 alpa4c AL_PA 0x4C DHD Login Information lbits:1 alpa4b AL_PA 0x4B DHD Login Information lbits:1 alpa4a AL_PA 0x4A DHD Login Information lbits:1 alpa49 AL_PA 0x49 DHD Login Information lbits:1 alpa47 AL_PA 0x47 DHD Login Information lbits:1 alpa46 AL_PA 0x46 DHD Login Information lbits:1 alpa45 AL_PA 0x45 DHD Login Information lbits:1 alpa43 AL_PA 0x43 DHD Login Information lbits:1 alpa3c AL_PA 0x3C DHD Login Information {} or dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 9024> ulong value As longword endunion dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 9028> union dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0

<byte 9028> {field (By field)} <byte 9028> lbits:1 alpa3a AL_PA 0x3A DHD Login Information lbits:1 alpa39 AL_PA 0x39 DHD Login Information lbits:1 alpa36 AL_PA 0x36 DHD Login Information lbits:1 alpa35 AL_PA 0x35 DHD Login Information lbits:1 alpa34 AL_PA 0x34 DHD Login Information lbits:1 alpa33 AL_PA 0x33 DHD Login Information lbits:1 alpa32 AL_PA 0x32 DHD Login Information lbits:1 alpa31 AL_PA 0x31 DHD Login Information lbits:1 alpa2e AL_PA 0x2E DHD Login Information lbits:1 alpa2d AL_PA 0x2D DHD Login Information lbits:1 alpa2c AL_PA 0x2C DHD Login Information lbits:1 alpa2b AL_PA 0x2B DHD Login Information lbits:1 alpa2a AL_PA 0x2A DHD Login Information lbits:1 alpa29 AL_PA 0x29 DHD Login Information lbits:1 alpa27 AL_PA 0x27 DHD Login Information lbits:1 alpa26 AL_PA 0x26 DHD Login Information lbits:1 alpa25 AL_PA 0x25 DHD Login Information lbits:1 alpa23 AL_PA 0x23 DHD Login Information lbits:1 alpa1f AL_PA 0x1F DHD Login Information lbits:1 alpa1e AL_PA 0x1E DHD Login Information lbits:1 alpa1d AL_PA 0x1D DHD Login Information lbits:1 alpa1b AL_PA 0x1B DHD Login Information lbits:1 alpa18 AL_PA 0x18 DHD Login Information lbits:1 alpa17 AL_PA 0x17 DHD Login Information lbits:1 alpa10 AL_PA 0x10 DHD Login Information lbits:1 alpa0f AL_PA 0x0F DHD Login Information lbits:1 alpa08 AL_PA 0x08 DHD Login Information lbits:1 alpa04 AL_PA 0x04 DHD Login Information lbits:1 alpa02 AL_PA 0x02 DHD Login Information lbits:1 alpa01 AL_PA 0x01 DHD Login Information lbits:1 alpa00 AL_PA 0x00 DHD Login Information lbits:1 reserved Reserved {} or dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 9028> ulong value As longword endunion dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 9032> union fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 9032> {field (By field)} <byte 9032> lbits:1 bli Bypass Loop Initialization lbits:1 reserved Reserved lbits:1 enp Enable N_Port Mode lbits:1 lr Login Required lbits:1 inif Initialize as Fabric lbits:1 rf Respond to Fabric Address lbits:1 blm Bypass Loop Map lbits:1 sa Acquire Soft Address lbits:1 ha Acquire Hard Address lbits:1 aq Acquire Previously Acquired Address lbits:1 fa Acquire Fabric Aquired Address lbits:1 td Timer Disable lbits:1 sap Skip Arbitration Phase lbits:1 elb External Loopback/Pad Loopback lbits:1 ilb Internal loopback

lbits:1 npi Initialize as N_Port lbits:8 bb_credit BB_Credit lbits:8 al_pa Desired AL_PA {} or fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 9032> ulong value As longword endunion fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 9036> union fm_control (Offset 1C4) Frame Manager Control <byte 9036> {field (By field)} <byte 9036> lbits:3 cmd State Machine Command lbits:1 cl Close Loop Request lbits:1 reserved Reserved lbits:1 sp Send Prim_Reg lbits:1 sq Primitive Sequence lbits:25 reserved1 Reserved {} or fm_control (Offset 1C4) Frame Manager Control <byte 9036> ulong value As longword endunion fm_control (Offset 1C4) Frame Manager Control <byte 9040> union fm_status (Offset 1C8) Frame Manager Status <byte 9040> {field (By field)} <byte 9040> lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_status (Offset 1C8) Frame Manager Status <byte 9040> ulong value As longword endunion fm_status (Offset 1C8) Frame Manager Status

<byte 9044> union fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 9044> {field (By field)} <byte 9044> lbits:16 ed_tov Error Detect Time-Out lbits:9 rt_tov Receiver Transmitter Time-Out lbits:7 reserved Reserved {} or fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 9044> ulong value As longword endunion fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 9048> union fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 9048> {field (By field)} <byte 9048> lbits:8 link_fail Link Fail Count lbits:8 loss_of_sync Loss of Synchronization Count lbits:8 bad_rx_char Bad Received Character Count lbits:8 loss_of_signal Loss of Signal Count {} or fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 9048> ulong value As longword endunion fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 9052> union fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 9052> {field (By field)} <byte 9052> lbits:8 proto_er Protocol Error Count lbits:8 bad_crc Bad CRC Count lbits:8 dis_frm Discarded Frames lbits:8 rx_eofa Received EOFa {} or fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 9052> ulong value As longword endunion fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 9056> union fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 9056> {field (By field)} <byte 9056> lbits:9 al_time Arbitrated Loop Time-Out lbits:7 reserved Reserved lbits:16 lp_tov Loop Time-Out {} or fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 9056> ulong value As longword endunion fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 9060> union fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 9060> {field (By field)} <byte 9060> lbits:24 bb0_timer BB_Credit Timer

lbits:8 reserved Reserved {} or fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 9060> ulong value As longword endunion fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 9064> union fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 9064> {field (By field)} <byte 9064> lbits:32 wwn World Wide Name {} or fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 9064> ulong value As longword endunion fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 9068> union fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 9068> {field (By field)} <byte 9068> lbits:32 wwn World Wide Name {} or fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 9068> ulong value As longword endunion fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 9072> union fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 9072> {field (By field)} <byte 9072> lbits:8 lipf_alpa AL_PA of Most Recent LIPf Received lbits:8 bad_alpa AL_PA of Most Recent OPN Sent and Returned Without Being Accept ed lbits:8 acq_alpa AL_PA Acquired During Loop Initialization lbits:8 reserved Reserved {} or fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 9072> ulong value As longword endunion fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 9076> union fm_primitive (Offset 1EC) Frame Manager Primitive <byte 9076> {field (By field)} <byte 9076> lbits:24 prim_value Primitive to be Sent lbits:8 reserved Reserved {} or fm_primitive (Offset 1EC) Frame Manager Primitive <byte 9076> ulong value As longword endunion fm_primitive (Offset 1EC) Frame Manager Primitive <byte 9080> union fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 9080> {field (By field)} <byte 9080>

lbits:8 exp_frm Expired Frames lbits:24 reserved Reserved {} or fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 9080> ulong value As longword endunion fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 9084> union fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 9084> {field (By field)} <byte 9084> lbits:1 dac Disable Auto Close lbits:2 nbc Non-zero Login BB_Credit lbits:1 eei Enable ERR_INIT lbits:1 icb Ignore Close Bit lbits:2 atv Arbitration Threshold Value lbits:1 gde Garbage Deletion Enable lbits:8 laa Lowest Allowable AL_PA lbits:5 reserved Reserved lbits:1 dao Disable 2xAL_TIME Timeout on Open lbits:3 reserved1 Reserved lbits:1 prm Promiscuous Mode lbits:1 wpe Wait For Port Enable lbits:1 fmh Force Monitor State With Hard Address lbits:1 fmn Force Monitor Non-participating State lbits:1 dlm Disable Loop Master lbits:1 dsa Disable Soft Address Selection lbits:1 ilp Ignore LPB/LPE Primitive Sequences {} or fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 9084> ulong value As longword endunion fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 9088> union pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED <byte 9088> {field (By field)} <byte 9088> {pci_rsvd1F8 ((Offset 1F8) Reserved)} <byte 9088> utiny value {} <byte 9089> {pci_rsvd1F9 ((Offset 1F9) Reserved)} <byte 9089> utiny value {} <byte 9090> union romctr (Offset 1FA) PCI ROM Control <byte 9090> {field (By field)} <byte 9090> tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or romctr (Offset 1FA) PCI ROM Control <byte 9090>

utiny value As byte endunion romctr (Offset 1FA) PCI ROM Control <byte 9091> union mctr (Offset 1FB) PCI Master Control <byte 9091> {field (By field)} <byte 9091> tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or mctr (Offset 1FB) PCI Master Control <byte 9091> utiny value As byte endunion mctr (Offset 1FB) PCI Master Control {} or pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED <byte 9088> ulong value As longword endunion pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED <byte 9092> union pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST <byte 9092> {field (By field)} <byte 9092> union softrst (Offset 1FC) PCI Interface Reset Control <byte 9092> {field (By field)} <byte 9092> tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or softrst (Offset 1FC) PCI Interface Reset Control <byte 9092> utiny value As byte endunion softrst (Offset 1FC) PCI Interface Reset Control <byte 9093> union intpend (Offset 1FD) PCI Interrupt Pending <byte 9093> {field (By field)} <byte 9093> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intpend (Offset 1FD) PCI Interrupt Pending <byte 9093> utiny value As byte endunion intpend (Offset 1FD) PCI Interrupt Pending <byte 9094> union inten (Offset 1FE) PCI Interrupt Enable <byte 9094> {field (By field)} <byte 9094> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt

tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or inten (Offset 1FE) PCI Interrupt Enable <byte 9094> utiny value As byte endunion inten (Offset 1FE) PCI Interrupt Enable <byte 9095> union intstat (Offset 1FF) PCI Interrupt Status <byte 9095> {field (By field)} <byte 9095> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intstat (Offset 1FF) PCI Interrupt Status <byte 9095> utiny value As byte endunion intstat (Offset 1FF) PCI Interrupt Status {} or pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST <byte 9092> ulong value As longword endunion pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST {} endunion csr[4] Tachyon DX2+ CSR Registers <byte 9096> union csr[5] Tachyon DX2+ CSR Registers <byte 9096> ulong[128] csra Tachyon DX2+ CSR Registers As Longwords or csr[5] Tachyon DX2+ CSR Registers <byte 9096> {csr (Tachyon DX2+ CSR Registers By Field)} <byte 9096> union erq_base (Offset 000) ERQ Base (write only) <byte 9096> {field (By field)} <byte 9096> lbits:32 address ERQ Base Address {} or erq_base (Offset 000) ERQ Base (write only) <byte 9096> ulong value As longword endunion erq_base (Offset 000) ERQ Base (write only) <byte 9100> union erq_len (Offset 004) ERQ Length (write only) <byte 9100> {field (By field)} <byte 9100> lbits:12 length ERQ Length lbits:20 reserved Reserved {} or erq_len (Offset 004) ERQ Length (write only) <byte 9100>

ulong value As longword endunion erq_len (Offset 004) ERQ Length (write only) <byte 9104> union erq_prod (Offset 008) ERQ Producer Index <byte 9104> {field (By field)} <byte 9104> lbits:12 index ERQ Producer Index lbits:20 reserved Reserved {} or erq_prod (Offset 008) ERQ Producer Index <byte 9104> ulong value As longword endunion erq_prod (Offset 008) ERQ Producer Index <byte 9108> union erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 9108> {field (By field)} <byte 9108> lbits:32 address ERQ Consumer Index Address {} or erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 9108> ulong value As longword endunion erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 9112> union erq_cons (Offset 010) ERQ Consumer Index <byte 9112> {field (By field)} <byte 9112> lbits:12 index ERQ Consumer Index lbits:20 reserved Reserved {} or erq_cons (Offset 010) ERQ Consumer Index <byte 9112> ulong value As longword endunion erq_cons (Offset 010) ERQ Consumer Index <byte 9116> {rsvd1[0] ((Offset 014-04F) Reserved)} <byte 9116> ulong value {} <byte 9120> {rsvd1[1] ((Offset 014-04F) Reserved)} <byte 9120> ulong value {} <byte 9124> {rsvd1[2] ((Offset 014-04F) Reserved)} <byte 9124> ulong value {} <byte 9128> {rsvd1[3] ((Offset 014-04F) Reserved)} <byte 9128> ulong value {} <byte 9132> {rsvd1[4] ((Offset 014-04F) Reserved)} <byte 9132>

ulong value {} <byte 9136> {rsvd1[5] ((Offset 014-04F) Reserved)} <byte 9136> ulong value {} <byte 9140> {rsvd1[6] ((Offset 014-04F) Reserved)} <byte 9140> ulong value {} <byte 9144> {rsvd1[7] ((Offset 014-04F) Reserved)} <byte 9144> ulong value {} <byte 9148> {rsvd1[8] ((Offset 014-04F) Reserved)} <byte 9148> ulong value {} <byte 9152> {rsvd1[9] ((Offset 014-04F) Reserved)} <byte 9152> ulong value {} <byte 9156> {rsvd1[10] ((Offset 014-04F) Reserved)} <byte 9156> ulong value {} <byte 9160> {rsvd1[11] ((Offset 014-04F) Reserved)} <byte 9160> ulong value {} <byte 9164> {rsvd1[12] ((Offset 014-04F) Reserved)} <byte 9164> ulong value {} <byte 9168> {rsvd1[13] ((Offset 014-04F) Reserved)} <byte 9168> ulong value {} <byte 9172> {rsvd1[14] ((Offset 014-04F) Reserved)} <byte 9172> ulong value {} <byte 9176> union sfq_base (Offset 050) SFQ Base (write only) <byte 9176> {field (By field)} <byte 9176> lbits:32 address SFQ Base Address {} or sfq_base (Offset 050) SFQ Base (write only)

<byte 9176> ulong value As longword endunion sfq_base (Offset 050) SFQ Base (write only) <byte 9180> union sfq_len (Offset 054) SFQ Length (write only) <byte 9180> {field (By field)} <byte 9180> lbits:12 length SFQ Length lbits:20 reserved Reserved {} or sfq_len (Offset 054) SFQ Length (write only) <byte 9180> ulong value As longword endunion sfq_len (Offset 054) SFQ Length (write only) <byte 9184> union sfq_cons (Offset 058) SFQ Consumer Index <byte 9184> {field (By field)} <byte 9184> lbits:12 index SFQ Consumer Index lbits:20 reserved Reserved {} or sfq_cons (Offset 058) SFQ Consumer Index <byte 9184> ulong value As longword endunion sfq_cons (Offset 058) SFQ Consumer Index <byte 9188> {rsvd2[0] ((Offset 05C-07B) Reserved)} <byte 9188> ulong value {} <byte 9192> {rsvd2[1] ((Offset 05C-07B) Reserved)} <byte 9192> ulong value {} <byte 9196> {rsvd2[2] ((Offset 05C-07B) Reserved)} <byte 9196> ulong value {} <byte 9200> {rsvd2[3] ((Offset 05C-07B) Reserved)} <byte 9200> ulong value {} <byte 9204> {rsvd2[4] ((Offset 05C-07B) Reserved)} <byte 9204> ulong value {} <byte 9208> {rsvd2[5] ((Offset 05C-07B) Reserved)} <byte 9208> ulong value {} <byte 9212> {rsvd2[6] ((Offset 05C-07B) Reserved)} <byte 9212>

ulong value {} <byte 9216> {rsvd2[7] ((Offset 05C-07B) Reserved)} <byte 9216> ulong value {} <byte 9220> union int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 9220> {field (By field)} <byte 9220> lbits:4 timer Interrupt Timer Value lbits:3 reserved Reserved lbits:1 ihf Interrupt when IMQ Half Full lbits:24 reserved1 Reserved {} or int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 9220> ulong value As longword endunion int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 9224> union imq_base (Offset 080) IMQ Base (write only) <byte 9224> {field (By field)} <byte 9224> lbits:32 address IMQ Base Address {} or imq_base (Offset 080) IMQ Base (write only) <byte 9224> ulong value As longword endunion imq_base (Offset 080) IMQ Base (write only) <byte 9228> union imq_len (Offset 084) IMQ Length (write only) <byte 9228> {field (By field)} <byte 9228> lbits:12 length IMQ Length lbits:20 reserved Reserved {} or imq_len (Offset 084) IMQ Length (write only) <byte 9228> ulong value As longword endunion imq_len (Offset 084) IMQ Length (write only) <byte 9232> union imq_cons (Offset 088) IMQ Consumer Index <byte 9232> {field (By field)} <byte 9232> lbits:12 index IMQ Consumer Index lbits:20 reserved Reserved {} or imq_cons (Offset 088) IMQ Consumer Index <byte 9232> ulong value As longword endunion imq_cons (Offset 088) IMQ Consumer Index <byte 9236> union imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 9236> {field (By field)}

<byte 9236> lbits:32 address IMQ Producer Index Address {} or imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 9236> ulong value As longword endunion imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 9240> {rsvd3[0] ((Offset 090-0FC) Reserved)} <byte 9240> ulong value {} <byte 9244> {rsvd3[1] ((Offset 090-0FC) Reserved)} <byte 9244> ulong value {} <byte 9248> {rsvd3[2] ((Offset 090-0FC) Reserved)} <byte 9248> ulong value {} <byte 9252> {rsvd3[3] ((Offset 090-0FC) Reserved)} <byte 9252> ulong value {} <byte 9256> {rsvd3[4] ((Offset 090-0FC) Reserved)} <byte 9256> ulong value {} <byte 9260> {rsvd3[5] ((Offset 090-0FC) Reserved)} <byte 9260> ulong value {} <byte 9264> {rsvd3[6] ((Offset 090-0FC) Reserved)} <byte 9264> ulong value {} <byte 9268> {rsvd3[7] ((Offset 090-0FC) Reserved)} <byte 9268> ulong value {} <byte 9272> {rsvd3[8] ((Offset 090-0FC) Reserved)} <byte 9272> ulong value {} <byte 9276> {rsvd3[9] ((Offset 090-0FC) Reserved)} <byte 9276> ulong value {} <byte 9280> {rsvd3[10] ((Offset 090-0FC) Reserved)} <byte 9280>

ulong value {} <byte 9284> {rsvd3[11] ((Offset <byte 9284> ulong value {} <byte 9288> {rsvd3[12] ((Offset <byte 9288> ulong value {} <byte 9292> {rsvd3[13] ((Offset <byte 9292> ulong value {} <byte 9296> {rsvd3[14] ((Offset <byte 9296> ulong value {} <byte 9300> {rsvd3[15] ((Offset <byte 9300> ulong value {} <byte 9304> {rsvd3[16] ((Offset <byte 9304> ulong value {} <byte 9308> {rsvd3[17] ((Offset <byte 9308> ulong value {} <byte 9312> {rsvd3[18] ((Offset <byte 9312> ulong value {} <byte 9316> {rsvd3[19] ((Offset <byte 9316> ulong value {} <byte 9320> {rsvd3[20] ((Offset <byte 9320> ulong value {} <byte 9324> {rsvd3[21] ((Offset <byte 9324> ulong value {} <byte 9328> {rsvd3[22] ((Offset <byte 9328>

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

ulong value {} <byte 9332> {rsvd3[23] ((Offset 090-0FC) Reserved)} <byte 9332> ulong value {} <byte 9336> {rsvd3[24] ((Offset 090-0FC) Reserved)} <byte 9336> ulong value {} <byte 9340> {rsvd3[25] ((Offset 090-0FC) Reserved)} <byte 9340> ulong value {} <byte 9344> {rsvd3[26] ((Offset 090-0FC) Reserved)} <byte 9344> ulong value {} <byte 9348> {rsvd3[27] ((Offset 090-0FC) Reserved)} <byte 9348> ulong value {} <byte 9352> union fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 9352> {field (By field)} <byte 9352> lbits:6 bec Termination Receive lbits:3 reserved4 Reserved lbits:1 xrb Wrapback lbits:2 reserved Reserved lbits:3 xem Output pre-emphasis lbits:4 reserved1 Reserved lbits:1 mustbe1 Must be 1 lbits:1 stb Start BERT lbits:1 enb Enable BERT lbits:2 sdm Signal differential mode lbits:2 rxs Receiver Speed lbits:2 txs Transmitter Speed lbits:1 reserved3 Reserved lbits:1 xlr Force iTR to lock reference clock lbits:1 reserved0 Reserved lbits:1 xcv Type of Transceiver {} or fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 9352> ulong value As longword endunion fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 9356> union fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 9356> {field (By field)} <byte 9356> lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine

lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 9356> ulong value As longword endunion fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 9360> {rsvd3a[0] ((Offset 108-10f) Reserved)} <byte 9360> ulong value {} <byte 9364> {rsvd3a[1] ((Offset 108-10f) Reserved)} <byte 9364> ulong value {} <byte 9368> union sfp_cmd_status (Offset 110) SFP command and status <byte 9368> {field (No description available)} <byte 9368> lbits:1 gna Generate NACK lbits:1 rts Reset Slave lbits:1 wrc Write command lbits:1 rdc Read command lbits:1 gst Generate Stop lbits:1 sta Generate Start lbits:2 reserved1 Reserved lbits:1 rna Received NACK lbits:1 sby SFP Busy lbits:1 tip Transfer in progress lbits:9 reserved Reserved lbits:12 lp Clock Divisor {} or sfp_cmd_status (Offset 110) SFP command and status <byte 9368> ulong value

endunion sfp_cmd_status (Offset 110) SFP command and status <byte 9372> union sfp_data (Offset 114) SFP data <byte 9372> {field (By field)} <byte 9372> lbits:8 sfpd SFPD Transmit lbits:24 reserved Reserved {} or sfp_data (Offset 114) SFP data <byte 9372> ulong value As longword endunion sfp_data (Offset 114) SFP data <byte 9376> union fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 9376> {field (By field)} <byte 9376> lbits:1 tbe Transmit Link BIST error lbits:1 tlr Transmit Link BIST reset lbits:1 tle Transmit Link BIST enable lbits:1 rbe Receive Link BIST error lbits:1 rll Receive Link BIST loop-back lbits:1 rlr Receive Link BIST reset lbits:1 rle Receive Link BIST enable lbits:7 reserved3 Reserved lbits:1 ipl ITR PPL Lock lbits:1 reserved2 Reserved lbits:1 dtf Disable transceiver LOS filter lbits:1 dtl Disable transceiver LOS lbits:1 dsr Disable iTR RXLOS lbits:1 ttd Transceiver Tx Disable lbits:2 reserved1 Reserved lbits:1 rfl Receive ast Lock Disable lbits:9 reserved Reserved {} or fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 9376> ulong value As longword endunion fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 9380> union fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 9380> {field (By field)} <byte 9380> lbits:32 reserved Reserved {} or fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 9380> ulong value As longword endunion fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 9384> {rsvd3b[0] ((Offset 120-13F) Reserved)} <byte 9384> ulong value {} <byte 9388> {rsvd3b[1] ((Offset 120-13F) Reserved)} <byte 9388> ulong value

{} <byte 9392> {rsvd3b[2] ((Offset 120-13F) Reserved)} <byte 9392> ulong value {} <byte 9396> {rsvd3b[3] ((Offset 120-13F) Reserved)} <byte 9396> ulong value {} <byte 9400> {rsvd3b[4] ((Offset 120-13F) Reserved)} <byte 9400> ulong value {} <byte 9404> {rsvd3b[5] ((Offset 120-13F) Reserved)} <byte 9404> ulong value {} <byte 9408> {rsvd3b[6] ((Offset 120-13F) Reserved)} <byte 9408> ulong value {} <byte 9412> {rsvd3b[7] ((Offset 120-13F) Reserved)} <byte 9412> ulong value {} <byte 9416> union sest_base (Offset 140) SEST Base (write only) <byte 9416> {field (By field)} <byte 9416> lbits:32 address SEST Base Address {} or sest_base (Offset 140) SEST Base (write only) <byte 9416> ulong value As longword endunion sest_base (Offset 140) SEST Base (write only) <byte 9420> union sest_len (Offset 144) SEST Length (write only) <byte 9420> {field (By field)} <byte 9420> lbits:16 length SEST Length lbits:16 reserved Reserved {} or sest_len (Offset 144) SEST Length (write only) <byte 9420> ulong value As longword endunion sest_len (Offset 144) SEST Length (write only) <byte 9424> {rsvd4 ((Offset 148) Reserved)} <byte 9424> ulong value {} <byte 9428>

union scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 9428> {field (By field)} <byte 9428> lbits:16 tail Tail lbits:16 head Head {} or scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 9428> ulong value As longword endunion scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 9432> union prog_addr (Offset 150) Programmable Address register <byte 9432> {field (By field)} <byte 9432> lbits:20 ra ROM/RAM address lbits:11 reserved Reserved lbits:1 inc Increment {} or prog_addr (Offset 150) Programmable Address register <byte 9432> ulong value As longword endunion prog_addr (Offset 150) Programmable Address register <byte 9436> union prog_data (Offset 154) programmable data register <byte 9436> {field (By field)} <byte 9436> lbits:32 pdr Programmable data {} or prog_data (Offset 154) programmable data register <byte 9436> ulong value As longword endunion prog_data (Offset 154) programmable data register <byte 9440> {rsvd5[0] ((Offset 158-15F) Reserved)} <byte 9440> ulong value {} <byte 9444> {rsvd5[1] ((Offset 158-15F) Reserved)} <byte 9444> ulong value {} <byte 9448> union int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 9448> {field (By field)} <byte 9448> lbits:32 address Interrupt Message Address {} or int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 9448> ulong value As longword endunion int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 9452> union int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 9452> {field (By field)}

<byte 9452> lbits:32 value Interrupt Message Value {} or int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 9452> ulong value As longword endunion int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 9456> union sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 9456> {field (By field)} <byte 9456> lbits:8 length SGL Page Length lbits:24 reserved Reserved {} or sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 9456> ulong value As longword endunion sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 9460> union my_id (Offset 16C) My ID <byte 9460> {field (By field)} <byte 9460> lbits:24 id My ID lbits:8 reserved Reserved {} or my_id (Offset 16C) My ID <byte 9460> ulong value As longword endunion my_id (Offset 16C) My ID <byte 9464> union gpio (Offset 170) General Purpose I/O <byte 9464> {field (By field)} <byte 9464> lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:1 gc5 General Purpose Control 5 lbits:1 gc6 General Purpose Control 6 lbits:1 gc7 General Purpose Control 7 lbits:8 reserved Reserved lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose I/O 4 lbits:1 gp5 General Purpose I/O 5 lbits:1 gp6 General Purpose I/O 6 lbits:1 gp7 General Purpose I/O 7 lbits:8 reserved1 Reserved {} or gpio (Offset 170) General Purpose I/O <byte 9464> ulong value As longword endunion gpio (Offset 170) General Purpose I/O <byte 9468>

{rsvd6a ((Offset 174-177) Reserved)} <byte 9468> ulong value {} <byte 9472> union edc_config (Offset 178) EDC Configuration Register <byte 9472> {field (By field)} <byte 9472> lbits:16 io_seed Starting Seed lbits:16 reserved Reserved {} or edc_config (Offset 178) EDC Configuration Register <byte 9472> ulong value As longword endunion edc_config (Offset 178) EDC Configuration Register <byte 9476> union dx4_config3 (Offset 17C) DX4 Configuration Register 3 <byte 9476> {field (By field)} <byte 9476> lbits:9 pfs2 Programmable Frame size field 2 lbits:9 pfs3 Programmable Frame size field 3 lbits:9 pfs4 Programmable Frame size field 4 lbits:5 reserved Reserved {} or dx4_config3 (Offset 17C) DX4 Configuration Register 3 <byte 9476> ulong value As longword endunion dx4_config3 (Offset 17C) DX4 Configuration Register 3 <byte 9480> union tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 9480> {field (By field)} <byte 9480> lbits:9 pfs Programmable Frame Size lbits:15 reserved Reserved lbits:8 esi_range Exchange_ID Signaled Interrupt Range {} or tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 9480> ulong value As longword endunion tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 9484> union tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 9484> {field (By field)} <byte 9484> lbits:1 fad FCP Assist Disable lbits:1 ino In Order lbits:1 dof Discard OOO FCP Frames lbits:1 fua FCP Unassisted ACK Enable lbits:1 ime Interrupt Message Enable lbits:1 fab Fabric lbits:1 sic S_ID Copy Enable lbits:1 eqs Equal Service lbits:2 reserved Reserved lbits:1 aks Automatic ACK lbits:1 ddf Disable Delayed Freeze lbits:1 ebe Enable Big Endian Mode

lbits:11 reserved1 Reserved lbits:1 fc2 FCP Class 2 Reassembly Enable lbits:1 reserved2 Reserved lbits:1 sdf Save Discarded Frames lbits:1 rde Response Detect Enable lbits:1 dam Default ACK Model lbits:2 reserved3 Reserved lbits:1 m66 66 MHz Enabled {} or tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 9484> ulong value As longword endunion tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 9488> union tach_control (Offset 188) Tachyon DX2+ Control <byte 9488> {field (By field)} <byte 9488> lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:3 reserved Reserved lbits:1 feq Freeze ERQ lbits:1 ffa Freeze FCP Assists lbits:2 reserved1 Reserved lbits:1 fis Freeze Inbound FCP Assists When Frame Placed in SFQ lbits:1 fib Freeze Inbound FCP Assists lbits:2 reserved2 Reserved lbits:1 req Resume ERQ lbits:1 rif Resume Inbound FCP Assists lbits:1 rof Resume Outbound FCP Assists lbits:12 reserved3 Reserved lbits:1 crs Core Reset {} or tach_control (Offset 188) Tachyon DX2+ Control <byte 9488> ulong value As longword endunion tach_control (Offset 188) Tachyon DX2+ Control <byte 9492> union tach_status (Offset 18C) Tachyon DX2+ Status <byte 9492> {field (By field)} <byte 9492> lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose Input 4 lbits:5 reserved Reserved lbits:1 ipe Inbound Parity Error lbits:1 ope Outbound Parity Error lbits:4 reserved1 Reserved lbits:1 eqf ERQ Frozen lbits:1 iff Inbound FCP Assists Frozen lbits:1 off Outbound FCP Assists Frozen lbits:4 reserved2 Reserved lbits:1 ifce Inbound FIFO CRC Error lbits:1 ofce Outbound FIFO CRC Error

lbits:1 m66 66 Mhz Enabled lbits:1 ile Inbound Link Control FIFO Empty lbits:1 ole Outbound Link Control List Empty lbits:1 ife Inbound FIFO Empty lbits:1 ofe Outbound FIFO Empty lbits:1 imf IMQ Full lbits:1 ssf SFQ Full {} or tach_status (Offset 18C) Tachyon DX2+ Status <byte 9492> ulong value As longword endunion tach_status (Offset 18C) Tachyon DX2+ Status <byte 9496> {rsvd7 ((Offset 190) Reserved)} <byte 9496> ulong value {} <byte 9500> union hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 9500> {field (By field)} <byte 9500> lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 9500> ulong value As longword endunion hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 9504> union hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 9504> {field (By field)} <byte 9504> lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 9504> ulong value As longword endunion hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 9508> union inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 9508> {field (By field)} <byte 9508> lbits:24 reserved Reserved lbits:8 sest_lru_count SEST LRU Count {} or inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 9508> ulong value As longword endunion inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 9512> union inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 9512>

{field (By field)} <byte 9512> lbits:8 discd_frames Discarded Frame Count lbits:24 reserved Reserved {} or inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 9512> ulong value As longword endunion inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 9516> union ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) <byte 9516> {field (By field)} <byte 9516> lbits:28 threshold EE_Credit Zero Timer Threshold lbits:4 reserved Reserved {} or ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) <byte 9516> ulong value As longword endunion ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only ) <byte 9520> union up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 9520> {field (By field)} <byte 9520> lbits:12 reserved Reserved lbits:1 upper_addr1 Upper Data Address--44 bit data space lbits:19 upper_addr Upper Data Address {} or up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 9520> ulong value As longword endunion up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 9524> union up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 9524> {field (By field)} <byte 9524> lbits:32 upper_addr Upper Control Address {} or up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 9524> ulong value As longword endunion up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 9528> union dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 9528> {field (By field)} <byte 9528> lbits:1 ef AL_PA 0xEF DHD Login Information lbits:1 e8 AL_PA 0xE8 DHD Login Information lbits:1 e4 AL_PA 0xE4 DHD Login Information lbits:1 e2 AL_PA 0xE2 DHD Login Information lbits:1 e1 AL_PA 0xE1 DHD Login Information lbits:1 e0 AL_PA 0xE0 DHD Login Information lbits:1 dc AL_PA 0xDC DHD Login Information lbits:1 da AL_PA 0xDA DHD Login Information lbits:1 d9 AL_PA 0xD9 DHD Login Information

lbits:1 d6 AL_PA 0xD6 DHD Login Information lbits:1 d5 AL_PA 0xD5 DHD Login Information lbits:1 d4 AL_PA 0xD4 DHD Login Information lbits:1 d3 AL_PA 0xD3 DHD Login Information lbits:1 d2 AL_PA 0xD2 DHD Login Information lbits:1 d1 AL_PA 0xD1 DHD Login Information lbits:1 ce AL_PA 0xCE DHD Login Information lbits:1 cd AL_PA 0xCD DHD Login Information lbits:1 cc AL_PA 0xCC DHD Login Information lbits:1 cb AL_PA 0xCB DHD Login Information lbits:1 ca AL_PA 0xCA DHD Login Information lbits:1 c9 AL_PA 0xC9 DHD Login Information lbits:1 c7 AL_PA 0xC7 DHD Login Information lbits:1 c6 AL_PA 0xC6 DHD Login Information lbits:1 c5 AL_PA 0xC5 DHD Login Information lbits:1 c3 AL_PA 0xC3 DHD Login Information lbits:1 bc AL_PA 0xBC DHD Login Information lbits:1 ba AL_PA 0xBA DHD Login Information lbits:1 b9 AL_PA 0xB9 DHD Login Information lbits:1 b6 AL_PA 0xB6 DHD Login Information lbits:1 b5 AL_PA 0xB5 DHD Login Information lbits:1 b4 AL_PA 0xB4 DHD Login Information lbits:1 b3 AL_PA 0xB3 DHD Login Information {} or dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 9528> ulong value As longword endunion dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 9532> union dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 9532> {field (By field)} <byte 9532> lbits:1 alpab2 AL_PA 0xB2 DHD Login Information lbits:1 alpab1 AL_PA 0xB1 DHD Login Information lbits:1 alpaae AL_PA 0xAE DHD Login Information lbits:1 alpaad AL_PA 0xAD DHD Login Information lbits:1 alpaac AL_PA 0xAC DHD Login Information lbits:1 alpaab AL_PA 0xAB DHD Login Information lbits:1 alpaaa AL_PA 0xAA DHD Login Information lbits:1 alpaa9 AL_PA 0xA9 DHD Login Information lbits:1 alpaa7 AL_PA 0xA7 DHD Login Information lbits:1 alpaa6 AL_PA 0xA6 DHD Login Information lbits:1 alpaa5 AL_PA 0xA5 DHD Login Information lbits:1 alpaa3 AL_PA 0xA3 DHD Login Information lbits:1 alpa9f AL_PA 0x9F DHD Login Information lbits:1 alpa9e AL_PA 0x9E DHD Login Information lbits:1 alpa9d AL_PA 0x9D DHD Login Information lbits:1 alpa9b AL_PA 0x9B DHD Login Information lbits:1 alpa98 AL_PA 0x98 DHD Login Information lbits:1 alpa97 AL_PA 0x97 DHD Login Information lbits:1 alpa90 AL_PA 0x90 DHD Login Information lbits:1 alpa8f AL_PA 0x8F DHD Login Information lbits:1 alpa88 AL_PA 0x88 DHD Login Information lbits:1 alpa84 AL_PA 0x84 DHD Login Information lbits:1 alpa82 AL_PA 0x82 DHD Login Information lbits:1 alpa81 AL_PA 0x81 DHD Login Information lbits:1 alpa80 AL_PA 0x80 DHD Login Information lbits:1 alpa7c AL_PA 0x7C DHD Login Information lbits:1 alpa7a AL_PA 0x7A DHD Login Information

lbits:1 alpa79 AL_PA 0x79 DHD Login Information lbits:1 alpa76 AL_PA 0x76 DHD Login Information lbits:1 alpa75 AL_PA 0x75 DHD Login Information lbits:1 alpa74 AL_PA 0x74 DHD Login Information lbits:1 alpa73 AL_PA 0x73 DHD Login Information {} or dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 9532> ulong value As longword endunion dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 9536> union dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 9536> {field (By field)} <byte 9536> lbits:1 alpa72 AL_PA 0x72 DHD Login Information lbits:1 alpa71 AL_PA 0x71 DHD Login Information lbits:1 alpa6e AL_PA 0x6E DHD Login Information lbits:1 alpa6d AL_PA 0x6D DHD Login Information lbits:1 alpa6c AL_PA 0x6C DHD Login Information lbits:1 alpa6b AL_PA 0x6B DHD Login Information lbits:1 alpa6a AL_PA 0x6A DHD Login Information lbits:1 alpa69 AL_PA 0x69 DHD Login Information lbits:1 alpa67 AL_PA 0x67 DHD Login Information lbits:1 alpa66 AL_PA 0x66 DHD Login Information lbits:1 alpa65 AL_PA 0x65 DHD Login Information lbits:1 alpa63 AL_PA 0x63 DHD Login Information lbits:1 alpa5c AL_PA 0x5C DHD Login Information lbits:1 alpa5a AL_PA 0x5A DHD Login Information lbits:1 alpa59 AL_PA 0x59 DHD Login Information lbits:1 alpa56 AL_PA 0x56 DHD Login Information lbits:1 alpa55 AL_PA 0x55 DHD Login Information lbits:1 alpa54 AL_PA 0x54 DHD Login Information lbits:1 alpa53 AL_PA 0x53 DHD Login Information lbits:1 alpa52 AL_PA 0x52 DHD Login Information lbits:1 alpa51 AL_PA 0x51 DHD Login Information lbits:1 alpa4e AL_PA 0x4E DHD Login Information lbits:1 alpa4d AL_PA 0x4D DHD Login Information lbits:1 alpa4c AL_PA 0x4C DHD Login Information lbits:1 alpa4b AL_PA 0x4B DHD Login Information lbits:1 alpa4a AL_PA 0x4A DHD Login Information lbits:1 alpa49 AL_PA 0x49 DHD Login Information lbits:1 alpa47 AL_PA 0x47 DHD Login Information lbits:1 alpa46 AL_PA 0x46 DHD Login Information lbits:1 alpa45 AL_PA 0x45 DHD Login Information lbits:1 alpa43 AL_PA 0x43 DHD Login Information lbits:1 alpa3c AL_PA 0x3C DHD Login Information {} or dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 9536> ulong value As longword endunion dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 9540> union dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 9540> {field (By field)} <byte 9540> lbits:1 alpa3a AL_PA 0x3A DHD Login Information lbits:1 alpa39 AL_PA 0x39 DHD Login Information lbits:1 alpa36 AL_PA 0x36 DHD Login Information

lbits:1 alpa35 AL_PA 0x35 DHD Login Information lbits:1 alpa34 AL_PA 0x34 DHD Login Information lbits:1 alpa33 AL_PA 0x33 DHD Login Information lbits:1 alpa32 AL_PA 0x32 DHD Login Information lbits:1 alpa31 AL_PA 0x31 DHD Login Information lbits:1 alpa2e AL_PA 0x2E DHD Login Information lbits:1 alpa2d AL_PA 0x2D DHD Login Information lbits:1 alpa2c AL_PA 0x2C DHD Login Information lbits:1 alpa2b AL_PA 0x2B DHD Login Information lbits:1 alpa2a AL_PA 0x2A DHD Login Information lbits:1 alpa29 AL_PA 0x29 DHD Login Information lbits:1 alpa27 AL_PA 0x27 DHD Login Information lbits:1 alpa26 AL_PA 0x26 DHD Login Information lbits:1 alpa25 AL_PA 0x25 DHD Login Information lbits:1 alpa23 AL_PA 0x23 DHD Login Information lbits:1 alpa1f AL_PA 0x1F DHD Login Information lbits:1 alpa1e AL_PA 0x1E DHD Login Information lbits:1 alpa1d AL_PA 0x1D DHD Login Information lbits:1 alpa1b AL_PA 0x1B DHD Login Information lbits:1 alpa18 AL_PA 0x18 DHD Login Information lbits:1 alpa17 AL_PA 0x17 DHD Login Information lbits:1 alpa10 AL_PA 0x10 DHD Login Information lbits:1 alpa0f AL_PA 0x0F DHD Login Information lbits:1 alpa08 AL_PA 0x08 DHD Login Information lbits:1 alpa04 AL_PA 0x04 DHD Login Information lbits:1 alpa02 AL_PA 0x02 DHD Login Information lbits:1 alpa01 AL_PA 0x01 DHD Login Information lbits:1 alpa00 AL_PA 0x00 DHD Login Information lbits:1 reserved Reserved {} or dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 9540> ulong value As longword endunion dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 9544> union fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 9544> {field (By field)} <byte 9544> lbits:1 bli Bypass Loop Initialization lbits:1 reserved Reserved lbits:1 enp Enable N_Port Mode lbits:1 lr Login Required lbits:1 inif Initialize as Fabric lbits:1 rf Respond to Fabric Address lbits:1 blm Bypass Loop Map lbits:1 sa Acquire Soft Address lbits:1 ha Acquire Hard Address lbits:1 aq Acquire Previously Acquired Address lbits:1 fa Acquire Fabric Aquired Address lbits:1 td Timer Disable lbits:1 sap Skip Arbitration Phase lbits:1 elb External Loopback/Pad Loopback lbits:1 ilb Internal loopback lbits:1 npi Initialize as N_Port lbits:8 bb_credit BB_Credit lbits:8 al_pa Desired AL_PA {} or fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 9544>

ulong value As longword endunion fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 9548> union fm_control (Offset 1C4) Frame Manager Control <byte 9548> {field (By field)} <byte 9548> lbits:3 cmd State Machine Command lbits:1 cl Close Loop Request lbits:1 reserved Reserved lbits:1 sp Send Prim_Reg lbits:1 sq Primitive Sequence lbits:25 reserved1 Reserved {} or fm_control (Offset 1C4) Frame Manager Control <byte 9548> ulong value As longword endunion fm_control (Offset 1C4) Frame Manager Control <byte 9552> union fm_status (Offset 1C8) Frame Manager Status <byte 9552> {field (By field)} <byte 9552> lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_status (Offset 1C8) Frame Manager Status <byte 9552> ulong value As longword endunion fm_status (Offset 1C8) Frame Manager Status <byte 9556> union fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 9556> {field (By field)} <byte 9556> lbits:16 ed_tov Error Detect Time-Out

lbits:9 rt_tov Receiver Transmitter Time-Out lbits:7 reserved Reserved {} or fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 9556> ulong value As longword endunion fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 9560> union fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 9560> {field (By field)} <byte 9560> lbits:8 link_fail Link Fail Count lbits:8 loss_of_sync Loss of Synchronization Count lbits:8 bad_rx_char Bad Received Character Count lbits:8 loss_of_signal Loss of Signal Count {} or fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 9560> ulong value As longword endunion fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 9564> union fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 9564> {field (By field)} <byte 9564> lbits:8 proto_er Protocol Error Count lbits:8 bad_crc Bad CRC Count lbits:8 dis_frm Discarded Frames lbits:8 rx_eofa Received EOFa {} or fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 9564> ulong value As longword endunion fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 9568> union fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 9568> {field (By field)} <byte 9568> lbits:9 al_time Arbitrated Loop Time-Out lbits:7 reserved Reserved lbits:16 lp_tov Loop Time-Out {} or fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 9568> ulong value As longword endunion fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 9572> union fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 9572> {field (By field)} <byte 9572> lbits:24 bb0_timer BB_Credit Timer lbits:8 reserved Reserved {} or fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 9572> ulong value As longword endunion fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer

<byte 9576> union fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 9576> {field (By field)} <byte 9576> lbits:32 wwn World Wide Name {} or fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 9576> ulong value As longword endunion fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 9580> union fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 9580> {field (By field)} <byte 9580> lbits:32 wwn World Wide Name {} or fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 9580> ulong value As longword endunion fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 9584> union fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 9584> {field (By field)} <byte 9584> lbits:8 lipf_alpa AL_PA of Most Recent LIPf Received lbits:8 bad_alpa AL_PA of Most Recent OPN Sent and Returned Without Being Accept ed lbits:8 acq_alpa AL_PA Acquired During Loop Initialization lbits:8 reserved Reserved {} or fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 9584> ulong value As longword endunion fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 9588> union fm_primitive (Offset 1EC) Frame Manager Primitive <byte 9588> {field (By field)} <byte 9588> lbits:24 prim_value Primitive to be Sent lbits:8 reserved Reserved {} or fm_primitive (Offset 1EC) Frame Manager Primitive <byte 9588> ulong value As longword endunion fm_primitive (Offset 1EC) Frame Manager Primitive <byte 9592> union fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 9592> {field (By field)} <byte 9592> lbits:8 exp_frm Expired Frames lbits:24 reserved Reserved {} or fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 9592> ulong value As longword

endunion fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 9596> union fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 9596> {field (By field)} <byte 9596> lbits:1 dac Disable Auto Close lbits:2 nbc Non-zero Login BB_Credit lbits:1 eei Enable ERR_INIT lbits:1 icb Ignore Close Bit lbits:2 atv Arbitration Threshold Value lbits:1 gde Garbage Deletion Enable lbits:8 laa Lowest Allowable AL_PA lbits:5 reserved Reserved lbits:1 dao Disable 2xAL_TIME Timeout on Open lbits:3 reserved1 Reserved lbits:1 prm Promiscuous Mode lbits:1 wpe Wait For Port Enable lbits:1 fmh Force Monitor State With Hard Address lbits:1 fmn Force Monitor Non-participating State lbits:1 dlm Disable Loop Master lbits:1 dsa Disable Soft Address Selection lbits:1 ilp Ignore LPB/LPE Primitive Sequences {} or fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 9596> ulong value As longword endunion fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 9600> union pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED <byte 9600> {field (By field)} <byte 9600> {pci_rsvd1F8 ((Offset 1F8) Reserved)} <byte 9600> utiny value {} <byte 9601> {pci_rsvd1F9 ((Offset 1F9) Reserved)} <byte 9601> utiny value {} <byte 9602> union romctr (Offset 1FA) PCI ROM Control <byte 9602> {field (By field)} <byte 9602> tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or romctr (Offset 1FA) PCI ROM Control <byte 9602> utiny value As byte endunion romctr (Offset 1FA) PCI ROM Control <byte 9603> union mctr (Offset 1FB) PCI Master Control <byte 9603> {field (By field)}

<byte 9603> tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or mctr (Offset 1FB) PCI Master Control <byte 9603> utiny value As byte endunion mctr (Offset 1FB) PCI Master Control {} or pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED <byte 9600> ulong value As longword endunion pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED <byte 9604> union pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST <byte 9604> {field (By field)} <byte 9604> union softrst (Offset 1FC) PCI Interface Reset Control <byte 9604> {field (By field)} <byte 9604> tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or softrst (Offset 1FC) PCI Interface Reset Control <byte 9604> utiny value As byte endunion softrst (Offset 1FC) PCI Interface Reset Control <byte 9605> union intpend (Offset 1FD) PCI Interrupt Pending <byte 9605> {field (By field)} <byte 9605> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intpend (Offset 1FD) PCI Interrupt Pending <byte 9605> utiny value As byte endunion intpend (Offset 1FD) PCI Interrupt Pending <byte 9606> union inten (Offset 1FE) PCI Interrupt Enable <byte 9606> {field (By field)} <byte 9606> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or inten (Offset 1FE) PCI Interrupt Enable

<byte 9606> utiny value As byte endunion inten (Offset 1FE) PCI Interrupt Enable <byte 9607> union intstat (Offset 1FF) PCI Interrupt Status <byte 9607> {field (By field)} <byte 9607> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intstat (Offset 1FF) PCI Interrupt Status <byte 9607> utiny value As byte endunion intstat (Offset 1FF) PCI Interrupt Status {} or pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST <byte 9604> ulong value As longword endunion pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST {} endunion csr[5] Tachyon DX2+ CSR Registers <byte 9608> union csr[6] Tachyon DX2+ CSR Registers <byte 9608> ulong[128] csra Tachyon DX2+ CSR Registers As Longwords or csr[6] Tachyon DX2+ CSR Registers <byte 9608> {csr (Tachyon DX2+ CSR Registers By Field)} <byte 9608> union erq_base (Offset 000) ERQ Base (write only) <byte 9608> {field (By field)} <byte 9608> lbits:32 address ERQ Base Address {} or erq_base (Offset 000) ERQ Base (write only) <byte 9608> ulong value As longword endunion erq_base (Offset 000) ERQ Base (write only) <byte 9612> union erq_len (Offset 004) ERQ Length (write only) <byte 9612> {field (By field)} <byte 9612> lbits:12 length ERQ Length lbits:20 reserved Reserved {} or erq_len (Offset 004) ERQ Length (write only) <byte 9612> ulong value As longword endunion erq_len (Offset 004) ERQ Length (write only) <byte 9616> union erq_prod (Offset 008) ERQ Producer Index <byte 9616> {field (By field)}

<byte 9616> lbits:12 index ERQ Producer Index lbits:20 reserved Reserved {} or erq_prod (Offset 008) ERQ Producer Index <byte 9616> ulong value As longword endunion erq_prod (Offset 008) ERQ Producer Index <byte 9620> union erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 9620> {field (By field)} <byte 9620> lbits:32 address ERQ Consumer Index Address {} or erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 9620> ulong value As longword endunion erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 9624> union erq_cons (Offset 010) ERQ Consumer Index <byte 9624> {field (By field)} <byte 9624> lbits:12 index ERQ Consumer Index lbits:20 reserved Reserved {} or erq_cons (Offset 010) ERQ Consumer Index <byte 9624> ulong value As longword endunion erq_cons (Offset 010) ERQ Consumer Index <byte 9628> {rsvd1[0] ((Offset 014-04F) Reserved)} <byte 9628> ulong value {} <byte 9632> {rsvd1[1] ((Offset 014-04F) Reserved)} <byte 9632> ulong value {} <byte 9636> {rsvd1[2] ((Offset 014-04F) Reserved)} <byte 9636> ulong value {} <byte 9640> {rsvd1[3] ((Offset 014-04F) Reserved)} <byte 9640> ulong value {} <byte 9644> {rsvd1[4] ((Offset 014-04F) Reserved)} <byte 9644> ulong value {} <byte 9648> {rsvd1[5] ((Offset 014-04F) Reserved)} <byte 9648> ulong value

{} <byte 9652> {rsvd1[6] ((Offset 014-04F) Reserved)} <byte 9652> ulong value {} <byte 9656> {rsvd1[7] ((Offset 014-04F) Reserved)} <byte 9656> ulong value {} <byte 9660> {rsvd1[8] ((Offset 014-04F) Reserved)} <byte 9660> ulong value {} <byte 9664> {rsvd1[9] ((Offset 014-04F) Reserved)} <byte 9664> ulong value {} <byte 9668> {rsvd1[10] ((Offset 014-04F) Reserved)} <byte 9668> ulong value {} <byte 9672> {rsvd1[11] ((Offset 014-04F) Reserved)} <byte 9672> ulong value {} <byte 9676> {rsvd1[12] ((Offset 014-04F) Reserved)} <byte 9676> ulong value {} <byte 9680> {rsvd1[13] ((Offset 014-04F) Reserved)} <byte 9680> ulong value {} <byte 9684> {rsvd1[14] ((Offset 014-04F) Reserved)} <byte 9684> ulong value {} <byte 9688> union sfq_base (Offset 050) SFQ Base (write only) <byte 9688> {field (By field)} <byte 9688> lbits:32 address SFQ Base Address {} or sfq_base (Offset 050) SFQ Base (write only) <byte 9688> ulong value As longword endunion sfq_base (Offset 050) SFQ Base (write only) <byte 9692> union sfq_len (Offset 054) SFQ Length (write only) <byte 9692>

{field (By field)} <byte 9692> lbits:12 length SFQ Length lbits:20 reserved Reserved {} or sfq_len (Offset 054) SFQ Length (write only) <byte 9692> ulong value As longword endunion sfq_len (Offset 054) SFQ Length (write only) <byte 9696> union sfq_cons (Offset 058) SFQ Consumer Index <byte 9696> {field (By field)} <byte 9696> lbits:12 index SFQ Consumer Index lbits:20 reserved Reserved {} or sfq_cons (Offset 058) SFQ Consumer Index <byte 9696> ulong value As longword endunion sfq_cons (Offset 058) SFQ Consumer Index <byte 9700> {rsvd2[0] ((Offset 05C-07B) Reserved)} <byte 9700> ulong value {} <byte 9704> {rsvd2[1] ((Offset 05C-07B) Reserved)} <byte 9704> ulong value {} <byte 9708> {rsvd2[2] ((Offset 05C-07B) Reserved)} <byte 9708> ulong value {} <byte 9712> {rsvd2[3] ((Offset 05C-07B) Reserved)} <byte 9712> ulong value {} <byte 9716> {rsvd2[4] ((Offset 05C-07B) Reserved)} <byte 9716> ulong value {} <byte 9720> {rsvd2[5] ((Offset 05C-07B) Reserved)} <byte 9720> ulong value {} <byte 9724> {rsvd2[6] ((Offset 05C-07B) Reserved)} <byte 9724> ulong value {} <byte 9728> {rsvd2[7] ((Offset 05C-07B) Reserved)} <byte 9728> ulong value

{} <byte 9732> union int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 9732> {field (By field)} <byte 9732> lbits:4 timer Interrupt Timer Value lbits:3 reserved Reserved lbits:1 ihf Interrupt when IMQ Half Full lbits:24 reserved1 Reserved {} or int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 9732> ulong value As longword endunion int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 9736> union imq_base (Offset 080) IMQ Base (write only) <byte 9736> {field (By field)} <byte 9736> lbits:32 address IMQ Base Address {} or imq_base (Offset 080) IMQ Base (write only) <byte 9736> ulong value As longword endunion imq_base (Offset 080) IMQ Base (write only) <byte 9740> union imq_len (Offset 084) IMQ Length (write only) <byte 9740> {field (By field)} <byte 9740> lbits:12 length IMQ Length lbits:20 reserved Reserved {} or imq_len (Offset 084) IMQ Length (write only) <byte 9740> ulong value As longword endunion imq_len (Offset 084) IMQ Length (write only) <byte 9744> union imq_cons (Offset 088) IMQ Consumer Index <byte 9744> {field (By field)} <byte 9744> lbits:12 index IMQ Consumer Index lbits:20 reserved Reserved {} or imq_cons (Offset 088) IMQ Consumer Index <byte 9744> ulong value As longword endunion imq_cons (Offset 088) IMQ Consumer Index <byte 9748> union imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 9748> {field (By field)} <byte 9748> lbits:32 address IMQ Producer Index Address {} or imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 9748> ulong value As longword

endunion imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 9752> {rsvd3[0] ((Offset 090-0FC) Reserved)} <byte 9752> ulong value {} <byte 9756> {rsvd3[1] ((Offset 090-0FC) Reserved)} <byte 9756> ulong value {} <byte 9760> {rsvd3[2] ((Offset 090-0FC) Reserved)} <byte 9760> ulong value {} <byte 9764> {rsvd3[3] ((Offset 090-0FC) Reserved)} <byte 9764> ulong value {} <byte 9768> {rsvd3[4] ((Offset 090-0FC) Reserved)} <byte 9768> ulong value {} <byte 9772> {rsvd3[5] ((Offset 090-0FC) Reserved)} <byte 9772> ulong value {} <byte 9776> {rsvd3[6] ((Offset 090-0FC) Reserved)} <byte 9776> ulong value {} <byte 9780> {rsvd3[7] ((Offset 090-0FC) Reserved)} <byte 9780> ulong value {} <byte 9784> {rsvd3[8] ((Offset 090-0FC) Reserved)} <byte 9784> ulong value {} <byte 9788> {rsvd3[9] ((Offset 090-0FC) Reserved)} <byte 9788> ulong value {} <byte 9792> {rsvd3[10] ((Offset 090-0FC) Reserved)} <byte 9792> ulong value {} <byte 9796> {rsvd3[11] ((Offset 090-0FC) Reserved)} <byte 9796> ulong value

{} <byte 9800> {rsvd3[12] ((Offset <byte 9800> ulong value {} <byte 9804> {rsvd3[13] ((Offset <byte 9804> ulong value {} <byte 9808> {rsvd3[14] ((Offset <byte 9808> ulong value {} <byte 9812> {rsvd3[15] ((Offset <byte 9812> ulong value {} <byte 9816> {rsvd3[16] ((Offset <byte 9816> ulong value {} <byte 9820> {rsvd3[17] ((Offset <byte 9820> ulong value {} <byte 9824> {rsvd3[18] ((Offset <byte 9824> ulong value {} <byte 9828> {rsvd3[19] ((Offset <byte 9828> ulong value {} <byte 9832> {rsvd3[20] ((Offset <byte 9832> ulong value {} <byte 9836> {rsvd3[21] ((Offset <byte 9836> ulong value {} <byte 9840> {rsvd3[22] ((Offset <byte 9840> ulong value {} <byte 9844> {rsvd3[23] ((Offset <byte 9844> ulong value

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

{} <byte 9848> {rsvd3[24] ((Offset 090-0FC) Reserved)} <byte 9848> ulong value {} <byte 9852> {rsvd3[25] ((Offset 090-0FC) Reserved)} <byte 9852> ulong value {} <byte 9856> {rsvd3[26] ((Offset 090-0FC) Reserved)} <byte 9856> ulong value {} <byte 9860> {rsvd3[27] ((Offset 090-0FC) Reserved)} <byte 9860> ulong value {} <byte 9864> union fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 9864> {field (By field)} <byte 9864> lbits:6 bec Termination Receive lbits:3 reserved4 Reserved lbits:1 xrb Wrapback lbits:2 reserved Reserved lbits:3 xem Output pre-emphasis lbits:4 reserved1 Reserved lbits:1 mustbe1 Must be 1 lbits:1 stb Start BERT lbits:1 enb Enable BERT lbits:2 sdm Signal differential mode lbits:2 rxs Receiver Speed lbits:2 txs Transmitter Speed lbits:1 reserved3 Reserved lbits:1 xlr Force iTR to lock reference clock lbits:1 reserved0 Reserved lbits:1 xcv Type of Transceiver {} or fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 9864> ulong value As longword endunion fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 9868> union fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 9868> {field (By field)} <byte 9868> lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required

lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 9868> ulong value As longword endunion fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 9872> {rsvd3a[0] ((Offset 108-10f) Reserved)} <byte 9872> ulong value {} <byte 9876> {rsvd3a[1] ((Offset 108-10f) Reserved)} <byte 9876> ulong value {} <byte 9880> union sfp_cmd_status (Offset 110) SFP command and status <byte 9880> {field (No description available)} <byte 9880> lbits:1 gna Generate NACK lbits:1 rts Reset Slave lbits:1 wrc Write command lbits:1 rdc Read command lbits:1 gst Generate Stop lbits:1 sta Generate Start lbits:2 reserved1 Reserved lbits:1 rna Received NACK lbits:1 sby SFP Busy lbits:1 tip Transfer in progress lbits:9 reserved Reserved lbits:12 lp Clock Divisor {} or sfp_cmd_status (Offset 110) SFP command and status <byte 9880> ulong value endunion sfp_cmd_status (Offset 110) SFP command and status <byte 9884> union sfp_data (Offset 114) SFP data <byte 9884> {field (By field)} <byte 9884>

lbits:8 sfpd SFPD Transmit lbits:24 reserved Reserved {} or sfp_data (Offset 114) SFP data <byte 9884> ulong value As longword endunion sfp_data (Offset 114) SFP data <byte 9888> union fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 9888> {field (By field)} <byte 9888> lbits:1 tbe Transmit Link BIST error lbits:1 tlr Transmit Link BIST reset lbits:1 tle Transmit Link BIST enable lbits:1 rbe Receive Link BIST error lbits:1 rll Receive Link BIST loop-back lbits:1 rlr Receive Link BIST reset lbits:1 rle Receive Link BIST enable lbits:7 reserved3 Reserved lbits:1 ipl ITR PPL Lock lbits:1 reserved2 Reserved lbits:1 dtf Disable transceiver LOS filter lbits:1 dtl Disable transceiver LOS lbits:1 dsr Disable iTR RXLOS lbits:1 ttd Transceiver Tx Disable lbits:2 reserved1 Reserved lbits:1 rfl Receive ast Lock Disable lbits:9 reserved Reserved {} or fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 9888> ulong value As longword endunion fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 9892> union fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 9892> {field (By field)} <byte 9892> lbits:32 reserved Reserved {} or fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 9892> ulong value As longword endunion fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 9896> {rsvd3b[0] ((Offset 120-13F) Reserved)} <byte 9896> ulong value {} <byte 9900> {rsvd3b[1] ((Offset 120-13F) Reserved)} <byte 9900> ulong value {} <byte 9904> {rsvd3b[2] ((Offset 120-13F) Reserved)} <byte 9904> ulong value {}

<byte 9908> {rsvd3b[3] ((Offset 120-13F) Reserved)} <byte 9908> ulong value {} <byte 9912> {rsvd3b[4] ((Offset 120-13F) Reserved)} <byte 9912> ulong value {} <byte 9916> {rsvd3b[5] ((Offset 120-13F) Reserved)} <byte 9916> ulong value {} <byte 9920> {rsvd3b[6] ((Offset 120-13F) Reserved)} <byte 9920> ulong value {} <byte 9924> {rsvd3b[7] ((Offset 120-13F) Reserved)} <byte 9924> ulong value {} <byte 9928> union sest_base (Offset 140) SEST Base (write only) <byte 9928> {field (By field)} <byte 9928> lbits:32 address SEST Base Address {} or sest_base (Offset 140) SEST Base (write only) <byte 9928> ulong value As longword endunion sest_base (Offset 140) SEST Base (write only) <byte 9932> union sest_len (Offset 144) SEST Length (write only) <byte 9932> {field (By field)} <byte 9932> lbits:16 length SEST Length lbits:16 reserved Reserved {} or sest_len (Offset 144) SEST Length (write only) <byte 9932> ulong value As longword endunion sest_len (Offset 144) SEST Length (write only) <byte 9936> {rsvd4 ((Offset 148) Reserved)} <byte 9936> ulong value {} <byte 9940> union scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 9940> {field (By field)} <byte 9940> lbits:16 tail Tail lbits:16 head Head

{} or scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 9940> ulong value As longword endunion scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 9944> union prog_addr (Offset 150) Programmable Address register <byte 9944> {field (By field)} <byte 9944> lbits:20 ra ROM/RAM address lbits:11 reserved Reserved lbits:1 inc Increment {} or prog_addr (Offset 150) Programmable Address register <byte 9944> ulong value As longword endunion prog_addr (Offset 150) Programmable Address register <byte 9948> union prog_data (Offset 154) programmable data register <byte 9948> {field (By field)} <byte 9948> lbits:32 pdr Programmable data {} or prog_data (Offset 154) programmable data register <byte 9948> ulong value As longword endunion prog_data (Offset 154) programmable data register <byte 9952> {rsvd5[0] ((Offset 158-15F) Reserved)} <byte 9952> ulong value {} <byte 9956> {rsvd5[1] ((Offset 158-15F) Reserved)} <byte 9956> ulong value {} <byte 9960> union int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 9960> {field (By field)} <byte 9960> lbits:32 address Interrupt Message Address {} or int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 9960> ulong value As longword endunion int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 9964> union int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 9964> {field (By field)} <byte 9964> lbits:32 value Interrupt Message Value {} or int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 9964> ulong value As longword

endunion int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 9968> union sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 9968> {field (By field)} <byte 9968> lbits:8 length SGL Page Length lbits:24 reserved Reserved {} or sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 9968> ulong value As longword endunion sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 9972> union my_id (Offset 16C) My ID <byte 9972> {field (By field)} <byte 9972> lbits:24 id My ID lbits:8 reserved Reserved {} or my_id (Offset 16C) My ID <byte 9972> ulong value As longword endunion my_id (Offset 16C) My ID <byte 9976> union gpio (Offset 170) General Purpose I/O <byte 9976> {field (By field)} <byte 9976> lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:1 gc5 General Purpose Control 5 lbits:1 gc6 General Purpose Control 6 lbits:1 gc7 General Purpose Control 7 lbits:8 reserved Reserved lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose I/O 4 lbits:1 gp5 General Purpose I/O 5 lbits:1 gp6 General Purpose I/O 6 lbits:1 gp7 General Purpose I/O 7 lbits:8 reserved1 Reserved {} or gpio (Offset 170) General Purpose I/O <byte 9976> ulong value As longword endunion gpio (Offset 170) General Purpose I/O <byte 9980> {rsvd6a ((Offset 174-177) Reserved)} <byte 9980> ulong value {} <byte 9984> union edc_config (Offset 178) EDC Configuration Register

<byte 9984> {field (By field)} <byte 9984> lbits:16 io_seed Starting Seed lbits:16 reserved Reserved {} or edc_config (Offset 178) EDC Configuration Register <byte 9984> ulong value As longword endunion edc_config (Offset 178) EDC Configuration Register <byte 9988> union dx4_config3 (Offset 17C) DX4 Configuration Register 3 <byte 9988> {field (By field)} <byte 9988> lbits:9 pfs2 Programmable Frame size field 2 lbits:9 pfs3 Programmable Frame size field 3 lbits:9 pfs4 Programmable Frame size field 4 lbits:5 reserved Reserved {} or dx4_config3 (Offset 17C) DX4 Configuration Register 3 <byte 9988> ulong value As longword endunion dx4_config3 (Offset 17C) DX4 Configuration Register 3 <byte 9992> union tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 9992> {field (By field)} <byte 9992> lbits:9 pfs Programmable Frame Size lbits:15 reserved Reserved lbits:8 esi_range Exchange_ID Signaled Interrupt Range {} or tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 9992> ulong value As longword endunion tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 9996> union tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 9996> {field (By field)} <byte 9996> lbits:1 fad FCP Assist Disable lbits:1 ino In Order lbits:1 dof Discard OOO FCP Frames lbits:1 fua FCP Unassisted ACK Enable lbits:1 ime Interrupt Message Enable lbits:1 fab Fabric lbits:1 sic S_ID Copy Enable lbits:1 eqs Equal Service lbits:2 reserved Reserved lbits:1 aks Automatic ACK lbits:1 ddf Disable Delayed Freeze lbits:1 ebe Enable Big Endian Mode lbits:11 reserved1 Reserved lbits:1 fc2 FCP Class 2 Reassembly Enable lbits:1 reserved2 Reserved lbits:1 sdf Save Discarded Frames lbits:1 rde Response Detect Enable lbits:1 dam Default ACK Model

lbits:2 reserved3 Reserved lbits:1 m66 66 MHz Enabled {} or tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 9996> ulong value As longword endunion tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 10000> union tach_control (Offset 188) Tachyon DX2+ Control <byte 10000> {field (By field)} <byte 10000> lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:3 reserved Reserved lbits:1 feq Freeze ERQ lbits:1 ffa Freeze FCP Assists lbits:2 reserved1 Reserved lbits:1 fis Freeze Inbound FCP Assists When Frame Placed in SFQ lbits:1 fib Freeze Inbound FCP Assists lbits:2 reserved2 Reserved lbits:1 req Resume ERQ lbits:1 rif Resume Inbound FCP Assists lbits:1 rof Resume Outbound FCP Assists lbits:12 reserved3 Reserved lbits:1 crs Core Reset {} or tach_control (Offset 188) Tachyon DX2+ Control <byte 10000> ulong value As longword endunion tach_control (Offset 188) Tachyon DX2+ Control <byte 10004> union tach_status (Offset 18C) Tachyon DX2+ Status <byte 10004> {field (By field)} <byte 10004> lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose Input 4 lbits:5 reserved Reserved lbits:1 ipe Inbound Parity Error lbits:1 ope Outbound Parity Error lbits:4 reserved1 Reserved lbits:1 eqf ERQ Frozen lbits:1 iff Inbound FCP Assists Frozen lbits:1 off Outbound FCP Assists Frozen lbits:4 reserved2 Reserved lbits:1 ifce Inbound FIFO CRC Error lbits:1 ofce Outbound FIFO CRC Error lbits:1 m66 66 Mhz Enabled lbits:1 ile Inbound Link Control FIFO Empty lbits:1 ole Outbound Link Control List Empty lbits:1 ife Inbound FIFO Empty lbits:1 ofe Outbound FIFO Empty lbits:1 imf IMQ Full

lbits:1 ssf SFQ Full {} or tach_status (Offset 18C) Tachyon DX2+ Status <byte 10004> ulong value As longword endunion tach_status (Offset 18C) Tachyon DX2+ Status <byte 10008> {rsvd7 ((Offset 190) Reserved)} <byte 10008> ulong value {} <byte 10012> union hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 10012> {field (By field)} <byte 10012> lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 10012> ulong value As longword endunion hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 10016> union hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 10016> {field (By field)} <byte 10016> lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 10016> ulong value As longword endunion hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 10020> union inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 10020> {field (By field)} <byte 10020> lbits:24 reserved Reserved lbits:8 sest_lru_count SEST LRU Count {} or inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 10020> ulong value As longword endunion inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 10024> union inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 10024> {field (By field)} <byte 10024> lbits:8 discd_frames Discarded Frame Count lbits:24 reserved Reserved {} or inbound_rstat2 (Offset 1A0) Inbound Resource Status 2

<byte 10024> ulong value As longword endunion inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 10028> union ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) <byte 10028> {field (By field)} <byte 10028> lbits:28 threshold EE_Credit Zero Timer Threshold lbits:4 reserved Reserved {} or ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) <byte 10028> ulong value As longword endunion ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only ) <byte 10032> union up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 10032> {field (By field)} <byte 10032> lbits:12 reserved Reserved lbits:1 upper_addr1 Upper Data Address--44 bit data space lbits:19 upper_addr Upper Data Address {} or up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 10032> ulong value As longword endunion up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 10036> union up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 10036> {field (By field)} <byte 10036> lbits:32 upper_addr Upper Control Address {} or up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 10036> ulong value As longword endunion up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 10040> union dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 10040> {field (By field)} <byte 10040> lbits:1 ef AL_PA 0xEF DHD Login Information lbits:1 e8 AL_PA 0xE8 DHD Login Information lbits:1 e4 AL_PA 0xE4 DHD Login Information lbits:1 e2 AL_PA 0xE2 DHD Login Information lbits:1 e1 AL_PA 0xE1 DHD Login Information lbits:1 e0 AL_PA 0xE0 DHD Login Information lbits:1 dc AL_PA 0xDC DHD Login Information lbits:1 da AL_PA 0xDA DHD Login Information lbits:1 d9 AL_PA 0xD9 DHD Login Information lbits:1 d6 AL_PA 0xD6 DHD Login Information lbits:1 d5 AL_PA 0xD5 DHD Login Information lbits:1 d4 AL_PA 0xD4 DHD Login Information lbits:1 d3 AL_PA 0xD3 DHD Login Information lbits:1 d2 AL_PA 0xD2 DHD Login Information lbits:1 d1 AL_PA 0xD1 DHD Login Information

lbits:1 ce AL_PA 0xCE DHD Login Information lbits:1 cd AL_PA 0xCD DHD Login Information lbits:1 cc AL_PA 0xCC DHD Login Information lbits:1 cb AL_PA 0xCB DHD Login Information lbits:1 ca AL_PA 0xCA DHD Login Information lbits:1 c9 AL_PA 0xC9 DHD Login Information lbits:1 c7 AL_PA 0xC7 DHD Login Information lbits:1 c6 AL_PA 0xC6 DHD Login Information lbits:1 c5 AL_PA 0xC5 DHD Login Information lbits:1 c3 AL_PA 0xC3 DHD Login Information lbits:1 bc AL_PA 0xBC DHD Login Information lbits:1 ba AL_PA 0xBA DHD Login Information lbits:1 b9 AL_PA 0xB9 DHD Login Information lbits:1 b6 AL_PA 0xB6 DHD Login Information lbits:1 b5 AL_PA 0xB5 DHD Login Information lbits:1 b4 AL_PA 0xB4 DHD Login Information lbits:1 b3 AL_PA 0xB3 DHD Login Information {} or dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 10040> ulong value As longword endunion dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 10044> union dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 10044> {field (By field)} <byte 10044> lbits:1 alpab2 AL_PA 0xB2 DHD Login Information lbits:1 alpab1 AL_PA 0xB1 DHD Login Information lbits:1 alpaae AL_PA 0xAE DHD Login Information lbits:1 alpaad AL_PA 0xAD DHD Login Information lbits:1 alpaac AL_PA 0xAC DHD Login Information lbits:1 alpaab AL_PA 0xAB DHD Login Information lbits:1 alpaaa AL_PA 0xAA DHD Login Information lbits:1 alpaa9 AL_PA 0xA9 DHD Login Information lbits:1 alpaa7 AL_PA 0xA7 DHD Login Information lbits:1 alpaa6 AL_PA 0xA6 DHD Login Information lbits:1 alpaa5 AL_PA 0xA5 DHD Login Information lbits:1 alpaa3 AL_PA 0xA3 DHD Login Information lbits:1 alpa9f AL_PA 0x9F DHD Login Information lbits:1 alpa9e AL_PA 0x9E DHD Login Information lbits:1 alpa9d AL_PA 0x9D DHD Login Information lbits:1 alpa9b AL_PA 0x9B DHD Login Information lbits:1 alpa98 AL_PA 0x98 DHD Login Information lbits:1 alpa97 AL_PA 0x97 DHD Login Information lbits:1 alpa90 AL_PA 0x90 DHD Login Information lbits:1 alpa8f AL_PA 0x8F DHD Login Information lbits:1 alpa88 AL_PA 0x88 DHD Login Information lbits:1 alpa84 AL_PA 0x84 DHD Login Information lbits:1 alpa82 AL_PA 0x82 DHD Login Information lbits:1 alpa81 AL_PA 0x81 DHD Login Information lbits:1 alpa80 AL_PA 0x80 DHD Login Information lbits:1 alpa7c AL_PA 0x7C DHD Login Information lbits:1 alpa7a AL_PA 0x7A DHD Login Information lbits:1 alpa79 AL_PA 0x79 DHD Login Information lbits:1 alpa76 AL_PA 0x76 DHD Login Information lbits:1 alpa75 AL_PA 0x75 DHD Login Information lbits:1 alpa74 AL_PA 0x74 DHD Login Information lbits:1 alpa73 AL_PA 0x73 DHD Login Information {}

or dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 10044> ulong value As longword endunion dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 10048> union dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 10048> {field (By field)} <byte 10048> lbits:1 alpa72 AL_PA 0x72 DHD Login Information lbits:1 alpa71 AL_PA 0x71 DHD Login Information lbits:1 alpa6e AL_PA 0x6E DHD Login Information lbits:1 alpa6d AL_PA 0x6D DHD Login Information lbits:1 alpa6c AL_PA 0x6C DHD Login Information lbits:1 alpa6b AL_PA 0x6B DHD Login Information lbits:1 alpa6a AL_PA 0x6A DHD Login Information lbits:1 alpa69 AL_PA 0x69 DHD Login Information lbits:1 alpa67 AL_PA 0x67 DHD Login Information lbits:1 alpa66 AL_PA 0x66 DHD Login Information lbits:1 alpa65 AL_PA 0x65 DHD Login Information lbits:1 alpa63 AL_PA 0x63 DHD Login Information lbits:1 alpa5c AL_PA 0x5C DHD Login Information lbits:1 alpa5a AL_PA 0x5A DHD Login Information lbits:1 alpa59 AL_PA 0x59 DHD Login Information lbits:1 alpa56 AL_PA 0x56 DHD Login Information lbits:1 alpa55 AL_PA 0x55 DHD Login Information lbits:1 alpa54 AL_PA 0x54 DHD Login Information lbits:1 alpa53 AL_PA 0x53 DHD Login Information lbits:1 alpa52 AL_PA 0x52 DHD Login Information lbits:1 alpa51 AL_PA 0x51 DHD Login Information lbits:1 alpa4e AL_PA 0x4E DHD Login Information lbits:1 alpa4d AL_PA 0x4D DHD Login Information lbits:1 alpa4c AL_PA 0x4C DHD Login Information lbits:1 alpa4b AL_PA 0x4B DHD Login Information lbits:1 alpa4a AL_PA 0x4A DHD Login Information lbits:1 alpa49 AL_PA 0x49 DHD Login Information lbits:1 alpa47 AL_PA 0x47 DHD Login Information lbits:1 alpa46 AL_PA 0x46 DHD Login Information lbits:1 alpa45 AL_PA 0x45 DHD Login Information lbits:1 alpa43 AL_PA 0x43 DHD Login Information lbits:1 alpa3c AL_PA 0x3C DHD Login Information {} or dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 10048> ulong value As longword endunion dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 10052> union dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 10052> {field (By field)} <byte 10052> lbits:1 alpa3a AL_PA 0x3A DHD Login Information lbits:1 alpa39 AL_PA 0x39 DHD Login Information lbits:1 alpa36 AL_PA 0x36 DHD Login Information lbits:1 alpa35 AL_PA 0x35 DHD Login Information lbits:1 alpa34 AL_PA 0x34 DHD Login Information lbits:1 alpa33 AL_PA 0x33 DHD Login Information lbits:1 alpa32 AL_PA 0x32 DHD Login Information lbits:1 alpa31 AL_PA 0x31 DHD Login Information lbits:1 alpa2e AL_PA 0x2E DHD Login Information

lbits:1 alpa2d AL_PA 0x2D DHD Login Information lbits:1 alpa2c AL_PA 0x2C DHD Login Information lbits:1 alpa2b AL_PA 0x2B DHD Login Information lbits:1 alpa2a AL_PA 0x2A DHD Login Information lbits:1 alpa29 AL_PA 0x29 DHD Login Information lbits:1 alpa27 AL_PA 0x27 DHD Login Information lbits:1 alpa26 AL_PA 0x26 DHD Login Information lbits:1 alpa25 AL_PA 0x25 DHD Login Information lbits:1 alpa23 AL_PA 0x23 DHD Login Information lbits:1 alpa1f AL_PA 0x1F DHD Login Information lbits:1 alpa1e AL_PA 0x1E DHD Login Information lbits:1 alpa1d AL_PA 0x1D DHD Login Information lbits:1 alpa1b AL_PA 0x1B DHD Login Information lbits:1 alpa18 AL_PA 0x18 DHD Login Information lbits:1 alpa17 AL_PA 0x17 DHD Login Information lbits:1 alpa10 AL_PA 0x10 DHD Login Information lbits:1 alpa0f AL_PA 0x0F DHD Login Information lbits:1 alpa08 AL_PA 0x08 DHD Login Information lbits:1 alpa04 AL_PA 0x04 DHD Login Information lbits:1 alpa02 AL_PA 0x02 DHD Login Information lbits:1 alpa01 AL_PA 0x01 DHD Login Information lbits:1 alpa00 AL_PA 0x00 DHD Login Information lbits:1 reserved Reserved {} or dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 10052> ulong value As longword endunion dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 10056> union fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 10056> {field (By field)} <byte 10056> lbits:1 bli Bypass Loop Initialization lbits:1 reserved Reserved lbits:1 enp Enable N_Port Mode lbits:1 lr Login Required lbits:1 inif Initialize as Fabric lbits:1 rf Respond to Fabric Address lbits:1 blm Bypass Loop Map lbits:1 sa Acquire Soft Address lbits:1 ha Acquire Hard Address lbits:1 aq Acquire Previously Acquired Address lbits:1 fa Acquire Fabric Aquired Address lbits:1 td Timer Disable lbits:1 sap Skip Arbitration Phase lbits:1 elb External Loopback/Pad Loopback lbits:1 ilb Internal loopback lbits:1 npi Initialize as N_Port lbits:8 bb_credit BB_Credit lbits:8 al_pa Desired AL_PA {} or fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 10056> ulong value As longword endunion fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 10060> union fm_control (Offset 1C4) Frame Manager Control <byte 10060> {field (By field)}

<byte 10060> lbits:3 cmd State Machine Command lbits:1 cl Close Loop Request lbits:1 reserved Reserved lbits:1 sp Send Prim_Reg lbits:1 sq Primitive Sequence lbits:25 reserved1 Reserved {} or fm_control (Offset 1C4) Frame Manager Control <byte 10060> ulong value As longword endunion fm_control (Offset 1C4) Frame Manager Control <byte 10064> union fm_status (Offset 1C8) Frame Manager Status <byte 10064> {field (By field)} <byte 10064> lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_status (Offset 1C8) Frame Manager Status <byte 10064> ulong value As longword endunion fm_status (Offset 1C8) Frame Manager Status <byte 10068> union fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 10068> {field (By field)} <byte 10068> lbits:16 ed_tov Error Detect Time-Out lbits:9 rt_tov Receiver Transmitter Time-Out lbits:7 reserved Reserved {} or fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 10068> ulong value As longword

endunion fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 10072> union fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 10072> {field (By field)} <byte 10072> lbits:8 link_fail Link Fail Count lbits:8 loss_of_sync Loss of Synchronization Count lbits:8 bad_rx_char Bad Received Character Count lbits:8 loss_of_signal Loss of Signal Count {} or fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 10072> ulong value As longword endunion fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 10076> union fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 10076> {field (By field)} <byte 10076> lbits:8 proto_er Protocol Error Count lbits:8 bad_crc Bad CRC Count lbits:8 dis_frm Discarded Frames lbits:8 rx_eofa Received EOFa {} or fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 10076> ulong value As longword endunion fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 10080> union fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 10080> {field (By field)} <byte 10080> lbits:9 al_time Arbitrated Loop Time-Out lbits:7 reserved Reserved lbits:16 lp_tov Loop Time-Out {} or fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 10080> ulong value As longword endunion fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 10084> union fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 10084> {field (By field)} <byte 10084> lbits:24 bb0_timer BB_Credit Timer lbits:8 reserved Reserved {} or fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 10084> ulong value As longword endunion fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 10088> union fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 10088> {field (By field)} <byte 10088> lbits:32 wwn World Wide Name

{} or fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 10088> ulong value As longword endunion fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 10092> union fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 10092> {field (By field)} <byte 10092> lbits:32 wwn World Wide Name {} or fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 10092> ulong value As longword endunion fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 10096> union fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 10096> {field (By field)} <byte 10096> lbits:8 lipf_alpa AL_PA of Most Recent LIPf Received lbits:8 bad_alpa AL_PA of Most Recent OPN Sent and Returned Without Being Accept ed lbits:8 acq_alpa AL_PA Acquired During Loop Initialization lbits:8 reserved Reserved {} or fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 10096> ulong value As longword endunion fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 10100> union fm_primitive (Offset 1EC) Frame Manager Primitive <byte 10100> {field (By field)} <byte 10100> lbits:24 prim_value Primitive to be Sent lbits:8 reserved Reserved {} or fm_primitive (Offset 1EC) Frame Manager Primitive <byte 10100> ulong value As longword endunion fm_primitive (Offset 1EC) Frame Manager Primitive <byte 10104> union fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 10104> {field (By field)} <byte 10104> lbits:8 exp_frm Expired Frames lbits:24 reserved Reserved {} or fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 10104> ulong value As longword endunion fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 10108> union fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 10108> {field (By field)} <byte 10108>

lbits:1 dac Disable Auto Close lbits:2 nbc Non-zero Login BB_Credit lbits:1 eei Enable ERR_INIT lbits:1 icb Ignore Close Bit lbits:2 atv Arbitration Threshold Value lbits:1 gde Garbage Deletion Enable lbits:8 laa Lowest Allowable AL_PA lbits:5 reserved Reserved lbits:1 dao Disable 2xAL_TIME Timeout on Open lbits:3 reserved1 Reserved lbits:1 prm Promiscuous Mode lbits:1 wpe Wait For Port Enable lbits:1 fmh Force Monitor State With Hard Address lbits:1 fmn Force Monitor Non-participating State lbits:1 dlm Disable Loop Master lbits:1 dsa Disable Soft Address Selection lbits:1 ilp Ignore LPB/LPE Primitive Sequences {} or fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 10108> ulong value As longword endunion fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 10112> union pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED <byte 10112> {field (By field)} <byte 10112> {pci_rsvd1F8 ((Offset 1F8) Reserved)} <byte 10112> utiny value {} <byte 10113> {pci_rsvd1F9 ((Offset 1F9) Reserved)} <byte 10113> utiny value {} <byte 10114> union romctr (Offset 1FA) PCI ROM Control <byte 10114> {field (By field)} <byte 10114> tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or romctr (Offset 1FA) PCI ROM Control <byte 10114> utiny value As byte endunion romctr (Offset 1FA) PCI ROM Control <byte 10115> union mctr (Offset 1FB) PCI Master Control <byte 10115> {field (By field)} <byte 10115> tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {}

or mctr (Offset 1FB) PCI Master Control <byte 10115> utiny value As byte endunion mctr (Offset 1FB) PCI Master Control {} or pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED <byte 10112> ulong value As longword endunion pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED <byte 10116> union pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST <byte 10116> {field (By field)} <byte 10116> union softrst (Offset 1FC) PCI Interface Reset Control <byte 10116> {field (By field)} <byte 10116> tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or softrst (Offset 1FC) PCI Interface Reset Control <byte 10116> utiny value As byte endunion softrst (Offset 1FC) PCI Interface Reset Control <byte 10117> union intpend (Offset 1FD) PCI Interrupt Pending <byte 10117> {field (By field)} <byte 10117> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intpend (Offset 1FD) PCI Interrupt Pending <byte 10117> utiny value As byte endunion intpend (Offset 1FD) PCI Interrupt Pending <byte 10118> union inten (Offset 1FE) PCI Interrupt Enable <byte 10118> {field (By field)} <byte 10118> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or inten (Offset 1FE) PCI Interrupt Enable <byte 10118> utiny value As byte endunion inten (Offset 1FE) PCI Interrupt Enable <byte 10119> union intstat (Offset 1FF) PCI Interrupt Status <byte 10119>

{field (By field)} <byte 10119> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intstat (Offset 1FF) PCI Interrupt Status <byte 10119> utiny value As byte endunion intstat (Offset 1FF) PCI Interrupt Status {} or pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST <byte 10116> ulong value As longword endunion pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST {} endunion csr[6] Tachyon DX2+ CSR Registers <byte 10120> union csr[7] Tachyon DX2+ CSR Registers <byte 10120> ulong[128] csra Tachyon DX2+ CSR Registers As Longwords or csr[7] Tachyon DX2+ CSR Registers <byte 10120> {csr (Tachyon DX2+ CSR Registers By Field)} <byte 10120> union erq_base (Offset 000) ERQ Base (write only) <byte 10120> {field (By field)} <byte 10120> lbits:32 address ERQ Base Address {} or erq_base (Offset 000) ERQ Base (write only) <byte 10120> ulong value As longword endunion erq_base (Offset 000) ERQ Base (write only) <byte 10124> union erq_len (Offset 004) ERQ Length (write only) <byte 10124> {field (By field)} <byte 10124> lbits:12 length ERQ Length lbits:20 reserved Reserved {} or erq_len (Offset 004) ERQ Length (write only) <byte 10124> ulong value As longword endunion erq_len (Offset 004) ERQ Length (write only) <byte 10128> union erq_prod (Offset 008) ERQ Producer Index <byte 10128> {field (By field)} <byte 10128> lbits:12 index ERQ Producer Index lbits:20 reserved Reserved {} or erq_prod (Offset 008) ERQ Producer Index <byte 10128>

ulong value As longword endunion erq_prod (Offset 008) ERQ Producer Index <byte 10132> union erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 10132> {field (By field)} <byte 10132> lbits:32 address ERQ Consumer Index Address {} or erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 10132> ulong value As longword endunion erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 10136> union erq_cons (Offset 010) ERQ Consumer Index <byte 10136> {field (By field)} <byte 10136> lbits:12 index ERQ Consumer Index lbits:20 reserved Reserved {} or erq_cons (Offset 010) ERQ Consumer Index <byte 10136> ulong value As longword endunion erq_cons (Offset 010) ERQ Consumer Index <byte 10140> {rsvd1[0] ((Offset 014-04F) Reserved)} <byte 10140> ulong value {} <byte 10144> {rsvd1[1] ((Offset 014-04F) Reserved)} <byte 10144> ulong value {} <byte 10148> {rsvd1[2] ((Offset 014-04F) Reserved)} <byte 10148> ulong value {} <byte 10152> {rsvd1[3] ((Offset 014-04F) Reserved)} <byte 10152> ulong value {} <byte 10156> {rsvd1[4] ((Offset 014-04F) Reserved)} <byte 10156> ulong value {} <byte 10160> {rsvd1[5] ((Offset 014-04F) Reserved)} <byte 10160> ulong value {} <byte 10164> {rsvd1[6] ((Offset 014-04F) Reserved)} <byte 10164> ulong value {}

<byte 10168> {rsvd1[7] ((Offset 014-04F) Reserved)} <byte 10168> ulong value {} <byte 10172> {rsvd1[8] ((Offset 014-04F) Reserved)} <byte 10172> ulong value {} <byte 10176> {rsvd1[9] ((Offset 014-04F) Reserved)} <byte 10176> ulong value {} <byte 10180> {rsvd1[10] ((Offset 014-04F) Reserved)} <byte 10180> ulong value {} <byte 10184> {rsvd1[11] ((Offset 014-04F) Reserved)} <byte 10184> ulong value {} <byte 10188> {rsvd1[12] ((Offset 014-04F) Reserved)} <byte 10188> ulong value {} <byte 10192> {rsvd1[13] ((Offset 014-04F) Reserved)} <byte 10192> ulong value {} <byte 10196> {rsvd1[14] ((Offset 014-04F) Reserved)} <byte 10196> ulong value {} <byte 10200> union sfq_base (Offset 050) SFQ Base (write only) <byte 10200> {field (By field)} <byte 10200> lbits:32 address SFQ Base Address {} or sfq_base (Offset 050) SFQ Base (write only) <byte 10200> ulong value As longword endunion sfq_base (Offset 050) SFQ Base (write only) <byte 10204> union sfq_len (Offset 054) SFQ Length (write only) <byte 10204> {field (By field)} <byte 10204> lbits:12 length SFQ Length lbits:20 reserved Reserved {} or sfq_len (Offset 054) SFQ Length (write only)

<byte 10204> ulong value As longword endunion sfq_len (Offset 054) SFQ Length (write only) <byte 10208> union sfq_cons (Offset 058) SFQ Consumer Index <byte 10208> {field (By field)} <byte 10208> lbits:12 index SFQ Consumer Index lbits:20 reserved Reserved {} or sfq_cons (Offset 058) SFQ Consumer Index <byte 10208> ulong value As longword endunion sfq_cons (Offset 058) SFQ Consumer Index <byte 10212> {rsvd2[0] ((Offset 05C-07B) Reserved)} <byte 10212> ulong value {} <byte 10216> {rsvd2[1] ((Offset 05C-07B) Reserved)} <byte 10216> ulong value {} <byte 10220> {rsvd2[2] ((Offset 05C-07B) Reserved)} <byte 10220> ulong value {} <byte 10224> {rsvd2[3] ((Offset 05C-07B) Reserved)} <byte 10224> ulong value {} <byte 10228> {rsvd2[4] ((Offset 05C-07B) Reserved)} <byte 10228> ulong value {} <byte 10232> {rsvd2[5] ((Offset 05C-07B) Reserved)} <byte 10232> ulong value {} <byte 10236> {rsvd2[6] ((Offset 05C-07B) Reserved)} <byte 10236> ulong value {} <byte 10240> {rsvd2[7] ((Offset 05C-07B) Reserved)} <byte 10240> ulong value {} <byte 10244> union int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 10244> {field (By field)} <byte 10244>

lbits:4 timer Interrupt Timer Value lbits:3 reserved Reserved lbits:1 ihf Interrupt when IMQ Half Full lbits:24 reserved1 Reserved {} or int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 10244> ulong value As longword endunion int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 10248> union imq_base (Offset 080) IMQ Base (write only) <byte 10248> {field (By field)} <byte 10248> lbits:32 address IMQ Base Address {} or imq_base (Offset 080) IMQ Base (write only) <byte 10248> ulong value As longword endunion imq_base (Offset 080) IMQ Base (write only) <byte 10252> union imq_len (Offset 084) IMQ Length (write only) <byte 10252> {field (By field)} <byte 10252> lbits:12 length IMQ Length lbits:20 reserved Reserved {} or imq_len (Offset 084) IMQ Length (write only) <byte 10252> ulong value As longword endunion imq_len (Offset 084) IMQ Length (write only) <byte 10256> union imq_cons (Offset 088) IMQ Consumer Index <byte 10256> {field (By field)} <byte 10256> lbits:12 index IMQ Consumer Index lbits:20 reserved Reserved {} or imq_cons (Offset 088) IMQ Consumer Index <byte 10256> ulong value As longword endunion imq_cons (Offset 088) IMQ Consumer Index <byte 10260> union imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 10260> {field (By field)} <byte 10260> lbits:32 address IMQ Producer Index Address {} or imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 10260> ulong value As longword endunion imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 10264> {rsvd3[0] ((Offset 090-0FC) Reserved)} <byte 10264> ulong value {}

<byte 10268> {rsvd3[1] ((Offset 090-0FC) Reserved)} <byte 10268> ulong value {} <byte 10272> {rsvd3[2] ((Offset 090-0FC) Reserved)} <byte 10272> ulong value {} <byte 10276> {rsvd3[3] ((Offset 090-0FC) Reserved)} <byte 10276> ulong value {} <byte 10280> {rsvd3[4] ((Offset 090-0FC) Reserved)} <byte 10280> ulong value {} <byte 10284> {rsvd3[5] ((Offset 090-0FC) Reserved)} <byte 10284> ulong value {} <byte 10288> {rsvd3[6] ((Offset 090-0FC) Reserved)} <byte 10288> ulong value {} <byte 10292> {rsvd3[7] ((Offset 090-0FC) Reserved)} <byte 10292> ulong value {} <byte 10296> {rsvd3[8] ((Offset 090-0FC) Reserved)} <byte 10296> ulong value {} <byte 10300> {rsvd3[9] ((Offset 090-0FC) Reserved)} <byte 10300> ulong value {} <byte 10304> {rsvd3[10] ((Offset 090-0FC) Reserved)} <byte 10304> ulong value {} <byte 10308> {rsvd3[11] ((Offset 090-0FC) Reserved)} <byte 10308> ulong value {} <byte 10312> {rsvd3[12] ((Offset 090-0FC) Reserved)} <byte 10312> ulong value {}

<byte 10316> {rsvd3[13] ((Offset <byte 10316> ulong value {} <byte 10320> {rsvd3[14] ((Offset <byte 10320> ulong value {} <byte 10324> {rsvd3[15] ((Offset <byte 10324> ulong value {} <byte 10328> {rsvd3[16] ((Offset <byte 10328> ulong value {} <byte 10332> {rsvd3[17] ((Offset <byte 10332> ulong value {} <byte 10336> {rsvd3[18] ((Offset <byte 10336> ulong value {} <byte 10340> {rsvd3[19] ((Offset <byte 10340> ulong value {} <byte 10344> {rsvd3[20] ((Offset <byte 10344> ulong value {} <byte 10348> {rsvd3[21] ((Offset <byte 10348> ulong value {} <byte 10352> {rsvd3[22] ((Offset <byte 10352> ulong value {} <byte 10356> {rsvd3[23] ((Offset <byte 10356> ulong value {} <byte 10360> {rsvd3[24] ((Offset <byte 10360> ulong value {}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

<byte 10364> {rsvd3[25] ((Offset 090-0FC) Reserved)} <byte 10364> ulong value {} <byte 10368> {rsvd3[26] ((Offset 090-0FC) Reserved)} <byte 10368> ulong value {} <byte 10372> {rsvd3[27] ((Offset 090-0FC) Reserved)} <byte 10372> ulong value {} <byte 10376> union fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 10376> {field (By field)} <byte 10376> lbits:6 bec Termination Receive lbits:3 reserved4 Reserved lbits:1 xrb Wrapback lbits:2 reserved Reserved lbits:3 xem Output pre-emphasis lbits:4 reserved1 Reserved lbits:1 mustbe1 Must be 1 lbits:1 stb Start BERT lbits:1 enb Enable BERT lbits:2 sdm Signal differential mode lbits:2 rxs Receiver Speed lbits:2 txs Transmitter Speed lbits:1 reserved3 Reserved lbits:1 xlr Force iTR to lock reference clock lbits:1 reserved0 Reserved lbits:1 xcv Type of Transceiver {} or fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 10376> ulong value As longword endunion fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 10380> union fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 10380> {field (By field)} <byte 10380> lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received

lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 10380> ulong value As longword endunion fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 10384> {rsvd3a[0] ((Offset 108-10f) Reserved)} <byte 10384> ulong value {} <byte 10388> {rsvd3a[1] ((Offset 108-10f) Reserved)} <byte 10388> ulong value {} <byte 10392> union sfp_cmd_status (Offset 110) SFP command and status <byte 10392> {field (No description available)} <byte 10392> lbits:1 gna Generate NACK lbits:1 rts Reset Slave lbits:1 wrc Write command lbits:1 rdc Read command lbits:1 gst Generate Stop lbits:1 sta Generate Start lbits:2 reserved1 Reserved lbits:1 rna Received NACK lbits:1 sby SFP Busy lbits:1 tip Transfer in progress lbits:9 reserved Reserved lbits:12 lp Clock Divisor {} or sfp_cmd_status (Offset 110) SFP command and status <byte 10392> ulong value endunion sfp_cmd_status (Offset 110) SFP command and status <byte 10396> union sfp_data (Offset 114) SFP data <byte 10396> {field (By field)} <byte 10396> lbits:8 sfpd SFPD Transmit lbits:24 reserved Reserved {} or sfp_data (Offset 114) SFP data <byte 10396> ulong value As longword

endunion sfp_data (Offset 114) SFP data <byte 10400> union fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 10400> {field (By field)} <byte 10400> lbits:1 tbe Transmit Link BIST error lbits:1 tlr Transmit Link BIST reset lbits:1 tle Transmit Link BIST enable lbits:1 rbe Receive Link BIST error lbits:1 rll Receive Link BIST loop-back lbits:1 rlr Receive Link BIST reset lbits:1 rle Receive Link BIST enable lbits:7 reserved3 Reserved lbits:1 ipl ITR PPL Lock lbits:1 reserved2 Reserved lbits:1 dtf Disable transceiver LOS filter lbits:1 dtl Disable transceiver LOS lbits:1 dsr Disable iTR RXLOS lbits:1 ttd Transceiver Tx Disable lbits:2 reserved1 Reserved lbits:1 rfl Receive ast Lock Disable lbits:9 reserved Reserved {} or fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 10400> ulong value As longword endunion fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 10404> union fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 10404> {field (By field)} <byte 10404> lbits:32 reserved Reserved {} or fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 10404> ulong value As longword endunion fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 10408> {rsvd3b[0] ((Offset 120-13F) Reserved)} <byte 10408> ulong value {} <byte 10412> {rsvd3b[1] ((Offset 120-13F) Reserved)} <byte 10412> ulong value {} <byte 10416> {rsvd3b[2] ((Offset 120-13F) Reserved)} <byte 10416> ulong value {} <byte 10420> {rsvd3b[3] ((Offset 120-13F) Reserved)} <byte 10420> ulong value {} <byte 10424>

{rsvd3b[4] ((Offset 120-13F) Reserved)} <byte 10424> ulong value {} <byte 10428> {rsvd3b[5] ((Offset 120-13F) Reserved)} <byte 10428> ulong value {} <byte 10432> {rsvd3b[6] ((Offset 120-13F) Reserved)} <byte 10432> ulong value {} <byte 10436> {rsvd3b[7] ((Offset 120-13F) Reserved)} <byte 10436> ulong value {} <byte 10440> union sest_base (Offset 140) SEST Base (write only) <byte 10440> {field (By field)} <byte 10440> lbits:32 address SEST Base Address {} or sest_base (Offset 140) SEST Base (write only) <byte 10440> ulong value As longword endunion sest_base (Offset 140) SEST Base (write only) <byte 10444> union sest_len (Offset 144) SEST Length (write only) <byte 10444> {field (By field)} <byte 10444> lbits:16 length SEST Length lbits:16 reserved Reserved {} or sest_len (Offset 144) SEST Length (write only) <byte 10444> ulong value As longword endunion sest_len (Offset 144) SEST Length (write only) <byte 10448> {rsvd4 ((Offset 148) Reserved)} <byte 10448> ulong value {} <byte 10452> union scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 10452> {field (By field)} <byte 10452> lbits:16 tail Tail lbits:16 head Head {} or scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 10452> ulong value As longword endunion scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 10456>

union prog_addr (Offset 150) Programmable Address register <byte 10456> {field (By field)} <byte 10456> lbits:20 ra ROM/RAM address lbits:11 reserved Reserved lbits:1 inc Increment {} or prog_addr (Offset 150) Programmable Address register <byte 10456> ulong value As longword endunion prog_addr (Offset 150) Programmable Address register <byte 10460> union prog_data (Offset 154) programmable data register <byte 10460> {field (By field)} <byte 10460> lbits:32 pdr Programmable data {} or prog_data (Offset 154) programmable data register <byte 10460> ulong value As longword endunion prog_data (Offset 154) programmable data register <byte 10464> {rsvd5[0] ((Offset 158-15F) Reserved)} <byte 10464> ulong value {} <byte 10468> {rsvd5[1] ((Offset 158-15F) Reserved)} <byte 10468> ulong value {} <byte 10472> union int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 10472> {field (By field)} <byte 10472> lbits:32 address Interrupt Message Address {} or int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 10472> ulong value As longword endunion int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 10476> union int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 10476> {field (By field)} <byte 10476> lbits:32 value Interrupt Message Value {} or int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 10476> ulong value As longword endunion int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 10480> union sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 10480> {field (By field)} <byte 10480>

lbits:8 length SGL Page Length lbits:24 reserved Reserved {} or sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 10480> ulong value As longword endunion sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 10484> union my_id (Offset 16C) My ID <byte 10484> {field (By field)} <byte 10484> lbits:24 id My ID lbits:8 reserved Reserved {} or my_id (Offset 16C) My ID <byte 10484> ulong value As longword endunion my_id (Offset 16C) My ID <byte 10488> union gpio (Offset 170) General Purpose I/O <byte 10488> {field (By field)} <byte 10488> lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:1 gc5 General Purpose Control 5 lbits:1 gc6 General Purpose Control 6 lbits:1 gc7 General Purpose Control 7 lbits:8 reserved Reserved lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose I/O 4 lbits:1 gp5 General Purpose I/O 5 lbits:1 gp6 General Purpose I/O 6 lbits:1 gp7 General Purpose I/O 7 lbits:8 reserved1 Reserved {} or gpio (Offset 170) General Purpose I/O <byte 10488> ulong value As longword endunion gpio (Offset 170) General Purpose I/O <byte 10492> {rsvd6a ((Offset 174-177) Reserved)} <byte 10492> ulong value {} <byte 10496> union edc_config (Offset 178) EDC Configuration Register <byte 10496> {field (By field)} <byte 10496> lbits:16 io_seed Starting Seed lbits:16 reserved Reserved {}

or edc_config (Offset 178) EDC Configuration Register <byte 10496> ulong value As longword endunion edc_config (Offset 178) EDC Configuration Register <byte 10500> union dx4_config3 (Offset 17C) DX4 Configuration Register 3 <byte 10500> {field (By field)} <byte 10500> lbits:9 pfs2 Programmable Frame size field 2 lbits:9 pfs3 Programmable Frame size field 3 lbits:9 pfs4 Programmable Frame size field 4 lbits:5 reserved Reserved {} or dx4_config3 (Offset 17C) DX4 Configuration Register 3 <byte 10500> ulong value As longword endunion dx4_config3 (Offset 17C) DX4 Configuration Register 3 <byte 10504> union tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 10504> {field (By field)} <byte 10504> lbits:9 pfs Programmable Frame Size lbits:15 reserved Reserved lbits:8 esi_range Exchange_ID Signaled Interrupt Range {} or tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 10504> ulong value As longword endunion tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 10508> union tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 10508> {field (By field)} <byte 10508> lbits:1 fad FCP Assist Disable lbits:1 ino In Order lbits:1 dof Discard OOO FCP Frames lbits:1 fua FCP Unassisted ACK Enable lbits:1 ime Interrupt Message Enable lbits:1 fab Fabric lbits:1 sic S_ID Copy Enable lbits:1 eqs Equal Service lbits:2 reserved Reserved lbits:1 aks Automatic ACK lbits:1 ddf Disable Delayed Freeze lbits:1 ebe Enable Big Endian Mode lbits:11 reserved1 Reserved lbits:1 fc2 FCP Class 2 Reassembly Enable lbits:1 reserved2 Reserved lbits:1 sdf Save Discarded Frames lbits:1 rde Response Detect Enable lbits:1 dam Default ACK Model lbits:2 reserved3 Reserved lbits:1 m66 66 MHz Enabled {} or tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 10508> ulong value As longword

endunion tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 10512> union tach_control (Offset 188) Tachyon DX2+ Control <byte 10512> {field (By field)} <byte 10512> lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:3 reserved Reserved lbits:1 feq Freeze ERQ lbits:1 ffa Freeze FCP Assists lbits:2 reserved1 Reserved lbits:1 fis Freeze Inbound FCP Assists When Frame Placed in SFQ lbits:1 fib Freeze Inbound FCP Assists lbits:2 reserved2 Reserved lbits:1 req Resume ERQ lbits:1 rif Resume Inbound FCP Assists lbits:1 rof Resume Outbound FCP Assists lbits:12 reserved3 Reserved lbits:1 crs Core Reset {} or tach_control (Offset 188) Tachyon DX2+ Control <byte 10512> ulong value As longword endunion tach_control (Offset 188) Tachyon DX2+ Control <byte 10516> union tach_status (Offset 18C) Tachyon DX2+ Status <byte 10516> {field (By field)} <byte 10516> lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose Input 4 lbits:5 reserved Reserved lbits:1 ipe Inbound Parity Error lbits:1 ope Outbound Parity Error lbits:4 reserved1 Reserved lbits:1 eqf ERQ Frozen lbits:1 iff Inbound FCP Assists Frozen lbits:1 off Outbound FCP Assists Frozen lbits:4 reserved2 Reserved lbits:1 ifce Inbound FIFO CRC Error lbits:1 ofce Outbound FIFO CRC Error lbits:1 m66 66 Mhz Enabled lbits:1 ile Inbound Link Control FIFO Empty lbits:1 ole Outbound Link Control List Empty lbits:1 ife Inbound FIFO Empty lbits:1 ofe Outbound FIFO Empty lbits:1 imf IMQ Full lbits:1 ssf SFQ Full {} or tach_status (Offset 18C) Tachyon DX2+ Status <byte 10516> ulong value As longword endunion tach_status (Offset 18C) Tachyon DX2+ Status

<byte 10520> {rsvd7 ((Offset 190) Reserved)} <byte 10520> ulong value {} <byte 10524> union hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 10524> {field (By field)} <byte 10524> lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 10524> ulong value As longword endunion hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 10528> union hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 10528> {field (By field)} <byte 10528> lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 10528> ulong value As longword endunion hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 10532> union inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 10532> {field (By field)} <byte 10532> lbits:24 reserved Reserved lbits:8 sest_lru_count SEST LRU Count {} or inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 10532> ulong value As longword endunion inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 10536> union inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 10536> {field (By field)} <byte 10536> lbits:8 discd_frames Discarded Frame Count lbits:24 reserved Reserved {} or inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 10536> ulong value As longword endunion inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 10540> union ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) <byte 10540>

{field (By field)} <byte 10540> lbits:28 threshold EE_Credit Zero Timer Threshold lbits:4 reserved Reserved {} or ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) <byte 10540> ulong value As longword endunion ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only ) <byte 10544> union up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 10544> {field (By field)} <byte 10544> lbits:12 reserved Reserved lbits:1 upper_addr1 Upper Data Address--44 bit data space lbits:19 upper_addr Upper Data Address {} or up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 10544> ulong value As longword endunion up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 10548> union up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 10548> {field (By field)} <byte 10548> lbits:32 upper_addr Upper Control Address {} or up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 10548> ulong value As longword endunion up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 10552> union dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 10552> {field (By field)} <byte 10552> lbits:1 ef AL_PA 0xEF DHD Login Information lbits:1 e8 AL_PA 0xE8 DHD Login Information lbits:1 e4 AL_PA 0xE4 DHD Login Information lbits:1 e2 AL_PA 0xE2 DHD Login Information lbits:1 e1 AL_PA 0xE1 DHD Login Information lbits:1 e0 AL_PA 0xE0 DHD Login Information lbits:1 dc AL_PA 0xDC DHD Login Information lbits:1 da AL_PA 0xDA DHD Login Information lbits:1 d9 AL_PA 0xD9 DHD Login Information lbits:1 d6 AL_PA 0xD6 DHD Login Information lbits:1 d5 AL_PA 0xD5 DHD Login Information lbits:1 d4 AL_PA 0xD4 DHD Login Information lbits:1 d3 AL_PA 0xD3 DHD Login Information lbits:1 d2 AL_PA 0xD2 DHD Login Information lbits:1 d1 AL_PA 0xD1 DHD Login Information lbits:1 ce AL_PA 0xCE DHD Login Information lbits:1 cd AL_PA 0xCD DHD Login Information lbits:1 cc AL_PA 0xCC DHD Login Information lbits:1 cb AL_PA 0xCB DHD Login Information lbits:1 ca AL_PA 0xCA DHD Login Information lbits:1 c9 AL_PA 0xC9 DHD Login Information

lbits:1 c7 AL_PA 0xC7 DHD Login Information lbits:1 c6 AL_PA 0xC6 DHD Login Information lbits:1 c5 AL_PA 0xC5 DHD Login Information lbits:1 c3 AL_PA 0xC3 DHD Login Information lbits:1 bc AL_PA 0xBC DHD Login Information lbits:1 ba AL_PA 0xBA DHD Login Information lbits:1 b9 AL_PA 0xB9 DHD Login Information lbits:1 b6 AL_PA 0xB6 DHD Login Information lbits:1 b5 AL_PA 0xB5 DHD Login Information lbits:1 b4 AL_PA 0xB4 DHD Login Information lbits:1 b3 AL_PA 0xB3 DHD Login Information {} or dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 10552> ulong value As longword endunion dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 10556> union dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 10556> {field (By field)} <byte 10556> lbits:1 alpab2 AL_PA 0xB2 DHD Login Information lbits:1 alpab1 AL_PA 0xB1 DHD Login Information lbits:1 alpaae AL_PA 0xAE DHD Login Information lbits:1 alpaad AL_PA 0xAD DHD Login Information lbits:1 alpaac AL_PA 0xAC DHD Login Information lbits:1 alpaab AL_PA 0xAB DHD Login Information lbits:1 alpaaa AL_PA 0xAA DHD Login Information lbits:1 alpaa9 AL_PA 0xA9 DHD Login Information lbits:1 alpaa7 AL_PA 0xA7 DHD Login Information lbits:1 alpaa6 AL_PA 0xA6 DHD Login Information lbits:1 alpaa5 AL_PA 0xA5 DHD Login Information lbits:1 alpaa3 AL_PA 0xA3 DHD Login Information lbits:1 alpa9f AL_PA 0x9F DHD Login Information lbits:1 alpa9e AL_PA 0x9E DHD Login Information lbits:1 alpa9d AL_PA 0x9D DHD Login Information lbits:1 alpa9b AL_PA 0x9B DHD Login Information lbits:1 alpa98 AL_PA 0x98 DHD Login Information lbits:1 alpa97 AL_PA 0x97 DHD Login Information lbits:1 alpa90 AL_PA 0x90 DHD Login Information lbits:1 alpa8f AL_PA 0x8F DHD Login Information lbits:1 alpa88 AL_PA 0x88 DHD Login Information lbits:1 alpa84 AL_PA 0x84 DHD Login Information lbits:1 alpa82 AL_PA 0x82 DHD Login Information lbits:1 alpa81 AL_PA 0x81 DHD Login Information lbits:1 alpa80 AL_PA 0x80 DHD Login Information lbits:1 alpa7c AL_PA 0x7C DHD Login Information lbits:1 alpa7a AL_PA 0x7A DHD Login Information lbits:1 alpa79 AL_PA 0x79 DHD Login Information lbits:1 alpa76 AL_PA 0x76 DHD Login Information lbits:1 alpa75 AL_PA 0x75 DHD Login Information lbits:1 alpa74 AL_PA 0x74 DHD Login Information lbits:1 alpa73 AL_PA 0x73 DHD Login Information {} or dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 10556> ulong value As longword endunion dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 10560> union dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1

<byte 10560> {field (By field)} <byte 10560> lbits:1 alpa72 AL_PA 0x72 DHD Login Information lbits:1 alpa71 AL_PA 0x71 DHD Login Information lbits:1 alpa6e AL_PA 0x6E DHD Login Information lbits:1 alpa6d AL_PA 0x6D DHD Login Information lbits:1 alpa6c AL_PA 0x6C DHD Login Information lbits:1 alpa6b AL_PA 0x6B DHD Login Information lbits:1 alpa6a AL_PA 0x6A DHD Login Information lbits:1 alpa69 AL_PA 0x69 DHD Login Information lbits:1 alpa67 AL_PA 0x67 DHD Login Information lbits:1 alpa66 AL_PA 0x66 DHD Login Information lbits:1 alpa65 AL_PA 0x65 DHD Login Information lbits:1 alpa63 AL_PA 0x63 DHD Login Information lbits:1 alpa5c AL_PA 0x5C DHD Login Information lbits:1 alpa5a AL_PA 0x5A DHD Login Information lbits:1 alpa59 AL_PA 0x59 DHD Login Information lbits:1 alpa56 AL_PA 0x56 DHD Login Information lbits:1 alpa55 AL_PA 0x55 DHD Login Information lbits:1 alpa54 AL_PA 0x54 DHD Login Information lbits:1 alpa53 AL_PA 0x53 DHD Login Information lbits:1 alpa52 AL_PA 0x52 DHD Login Information lbits:1 alpa51 AL_PA 0x51 DHD Login Information lbits:1 alpa4e AL_PA 0x4E DHD Login Information lbits:1 alpa4d AL_PA 0x4D DHD Login Information lbits:1 alpa4c AL_PA 0x4C DHD Login Information lbits:1 alpa4b AL_PA 0x4B DHD Login Information lbits:1 alpa4a AL_PA 0x4A DHD Login Information lbits:1 alpa49 AL_PA 0x49 DHD Login Information lbits:1 alpa47 AL_PA 0x47 DHD Login Information lbits:1 alpa46 AL_PA 0x46 DHD Login Information lbits:1 alpa45 AL_PA 0x45 DHD Login Information lbits:1 alpa43 AL_PA 0x43 DHD Login Information lbits:1 alpa3c AL_PA 0x3C DHD Login Information {} or dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 10560> ulong value As longword endunion dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 10564> union dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 10564> {field (By field)} <byte 10564> lbits:1 alpa3a AL_PA 0x3A DHD Login Information lbits:1 alpa39 AL_PA 0x39 DHD Login Information lbits:1 alpa36 AL_PA 0x36 DHD Login Information lbits:1 alpa35 AL_PA 0x35 DHD Login Information lbits:1 alpa34 AL_PA 0x34 DHD Login Information lbits:1 alpa33 AL_PA 0x33 DHD Login Information lbits:1 alpa32 AL_PA 0x32 DHD Login Information lbits:1 alpa31 AL_PA 0x31 DHD Login Information lbits:1 alpa2e AL_PA 0x2E DHD Login Information lbits:1 alpa2d AL_PA 0x2D DHD Login Information lbits:1 alpa2c AL_PA 0x2C DHD Login Information lbits:1 alpa2b AL_PA 0x2B DHD Login Information lbits:1 alpa2a AL_PA 0x2A DHD Login Information lbits:1 alpa29 AL_PA 0x29 DHD Login Information lbits:1 alpa27 AL_PA 0x27 DHD Login Information

lbits:1 alpa26 AL_PA 0x26 DHD Login Information lbits:1 alpa25 AL_PA 0x25 DHD Login Information lbits:1 alpa23 AL_PA 0x23 DHD Login Information lbits:1 alpa1f AL_PA 0x1F DHD Login Information lbits:1 alpa1e AL_PA 0x1E DHD Login Information lbits:1 alpa1d AL_PA 0x1D DHD Login Information lbits:1 alpa1b AL_PA 0x1B DHD Login Information lbits:1 alpa18 AL_PA 0x18 DHD Login Information lbits:1 alpa17 AL_PA 0x17 DHD Login Information lbits:1 alpa10 AL_PA 0x10 DHD Login Information lbits:1 alpa0f AL_PA 0x0F DHD Login Information lbits:1 alpa08 AL_PA 0x08 DHD Login Information lbits:1 alpa04 AL_PA 0x04 DHD Login Information lbits:1 alpa02 AL_PA 0x02 DHD Login Information lbits:1 alpa01 AL_PA 0x01 DHD Login Information lbits:1 alpa00 AL_PA 0x00 DHD Login Information lbits:1 reserved Reserved {} or dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 10564> ulong value As longword endunion dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 10568> union fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 10568> {field (By field)} <byte 10568> lbits:1 bli Bypass Loop Initialization lbits:1 reserved Reserved lbits:1 enp Enable N_Port Mode lbits:1 lr Login Required lbits:1 inif Initialize as Fabric lbits:1 rf Respond to Fabric Address lbits:1 blm Bypass Loop Map lbits:1 sa Acquire Soft Address lbits:1 ha Acquire Hard Address lbits:1 aq Acquire Previously Acquired Address lbits:1 fa Acquire Fabric Aquired Address lbits:1 td Timer Disable lbits:1 sap Skip Arbitration Phase lbits:1 elb External Loopback/Pad Loopback lbits:1 ilb Internal loopback lbits:1 npi Initialize as N_Port lbits:8 bb_credit BB_Credit lbits:8 al_pa Desired AL_PA {} or fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 10568> ulong value As longword endunion fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 10572> union fm_control (Offset 1C4) Frame Manager Control <byte 10572> {field (By field)} <byte 10572> lbits:3 cmd State Machine Command lbits:1 cl Close Loop Request lbits:1 reserved Reserved lbits:1 sp Send Prim_Reg lbits:1 sq Primitive Sequence

lbits:25 reserved1 Reserved {} or fm_control (Offset 1C4) Frame Manager Control <byte 10572> ulong value As longword endunion fm_control (Offset 1C4) Frame Manager Control <byte 10576> union fm_status (Offset 1C8) Frame Manager Status <byte 10576> {field (By field)} <byte 10576> lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_status (Offset 1C8) Frame Manager Status <byte 10576> ulong value As longword endunion fm_status (Offset 1C8) Frame Manager Status <byte 10580> union fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 10580> {field (By field)} <byte 10580> lbits:16 ed_tov Error Detect Time-Out lbits:9 rt_tov Receiver Transmitter Time-Out lbits:7 reserved Reserved {} or fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 10580> ulong value As longword endunion fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 10584> union fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 10584> {field (By field)} <byte 10584>

lbits:8 link_fail Link Fail Count lbits:8 loss_of_sync Loss of Synchronization Count lbits:8 bad_rx_char Bad Received Character Count lbits:8 loss_of_signal Loss of Signal Count {} or fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 10584> ulong value As longword endunion fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 10588> union fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 10588> {field (By field)} <byte 10588> lbits:8 proto_er Protocol Error Count lbits:8 bad_crc Bad CRC Count lbits:8 dis_frm Discarded Frames lbits:8 rx_eofa Received EOFa {} or fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 10588> ulong value As longword endunion fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 10592> union fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 10592> {field (By field)} <byte 10592> lbits:9 al_time Arbitrated Loop Time-Out lbits:7 reserved Reserved lbits:16 lp_tov Loop Time-Out {} or fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 10592> ulong value As longword endunion fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 10596> union fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 10596> {field (By field)} <byte 10596> lbits:24 bb0_timer BB_Credit Timer lbits:8 reserved Reserved {} or fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 10596> ulong value As longword endunion fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 10600> union fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 10600> {field (By field)} <byte 10600> lbits:32 wwn World Wide Name {} or fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 10600> ulong value As longword endunion fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 10604>

union fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 10604> {field (By field)} <byte 10604> lbits:32 wwn World Wide Name {} or fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 10604> ulong value As longword endunion fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 10608> union fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 10608> {field (By field)} <byte 10608> lbits:8 lipf_alpa AL_PA of Most Recent LIPf Received lbits:8 bad_alpa AL_PA of Most Recent OPN Sent and Returned Without Being Accept ed lbits:8 acq_alpa AL_PA Acquired During Loop Initialization lbits:8 reserved Reserved {} or fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 10608> ulong value As longword endunion fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 10612> union fm_primitive (Offset 1EC) Frame Manager Primitive <byte 10612> {field (By field)} <byte 10612> lbits:24 prim_value Primitive to be Sent lbits:8 reserved Reserved {} or fm_primitive (Offset 1EC) Frame Manager Primitive <byte 10612> ulong value As longword endunion fm_primitive (Offset 1EC) Frame Manager Primitive <byte 10616> union fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 10616> {field (By field)} <byte 10616> lbits:8 exp_frm Expired Frames lbits:24 reserved Reserved {} or fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 10616> ulong value As longword endunion fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 10620> union fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 10620> {field (By field)} <byte 10620> lbits:1 dac Disable Auto Close lbits:2 nbc Non-zero Login BB_Credit lbits:1 eei Enable ERR_INIT lbits:1 icb Ignore Close Bit lbits:2 atv Arbitration Threshold Value lbits:1 gde Garbage Deletion Enable

lbits:8 laa Lowest Allowable AL_PA lbits:5 reserved Reserved lbits:1 dao Disable 2xAL_TIME Timeout on Open lbits:3 reserved1 Reserved lbits:1 prm Promiscuous Mode lbits:1 wpe Wait For Port Enable lbits:1 fmh Force Monitor State With Hard Address lbits:1 fmn Force Monitor Non-participating State lbits:1 dlm Disable Loop Master lbits:1 dsa Disable Soft Address Selection lbits:1 ilp Ignore LPB/LPE Primitive Sequences {} or fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 10620> ulong value As longword endunion fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 10624> union pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED <byte 10624> {field (By field)} <byte 10624> {pci_rsvd1F8 ((Offset 1F8) Reserved)} <byte 10624> utiny value {} <byte 10625> {pci_rsvd1F9 ((Offset 1F9) Reserved)} <byte 10625> utiny value {} <byte 10626> union romctr (Offset 1FA) PCI ROM Control <byte 10626> {field (By field)} <byte 10626> tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or romctr (Offset 1FA) PCI ROM Control <byte 10626> utiny value As byte endunion romctr (Offset 1FA) PCI ROM Control <byte 10627> union mctr (Offset 1FB) PCI Master Control <byte 10627> {field (By field)} <byte 10627> tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or mctr (Offset 1FB) PCI Master Control <byte 10627> utiny value As byte endunion mctr (Offset 1FB) PCI Master Control {} or pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED

<byte 10624> ulong value As longword endunion pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED <byte 10628> union pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST <byte 10628> {field (By field)} <byte 10628> union softrst (Offset 1FC) PCI Interface Reset Control <byte 10628> {field (By field)} <byte 10628> tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or softrst (Offset 1FC) PCI Interface Reset Control <byte 10628> utiny value As byte endunion softrst (Offset 1FC) PCI Interface Reset Control <byte 10629> union intpend (Offset 1FD) PCI Interrupt Pending <byte 10629> {field (By field)} <byte 10629> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intpend (Offset 1FD) PCI Interrupt Pending <byte 10629> utiny value As byte endunion intpend (Offset 1FD) PCI Interrupt Pending <byte 10630> union inten (Offset 1FE) PCI Interrupt Enable <byte 10630> {field (By field)} <byte 10630> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or inten (Offset 1FE) PCI Interrupt Enable <byte 10630> utiny value As byte endunion inten (Offset 1FE) PCI Interrupt Enable <byte 10631> union intstat (Offset 1FF) PCI Interrupt Status <byte 10631> {field (By field)} <byte 10631> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved

tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intstat (Offset 1FF) PCI Interrupt Status <byte 10631> utiny value As byte endunion intstat (Offset 1FF) PCI Interrupt Status {} or pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST <byte 10628> ulong value As longword endunion pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST {} endunion csr[7] Tachyon DX2+ CSR Registers <byte 10632> union csr[8] Tachyon DX2+ CSR Registers <byte 10632> ulong[128] csra Tachyon DX2+ CSR Registers As Longwords or csr[8] Tachyon DX2+ CSR Registers <byte 10632> {csr (Tachyon DX2+ CSR Registers By Field)} <byte 10632> union erq_base (Offset 000) ERQ Base (write only) <byte 10632> {field (By field)} <byte 10632> lbits:32 address ERQ Base Address {} or erq_base (Offset 000) ERQ Base (write only) <byte 10632> ulong value As longword endunion erq_base (Offset 000) ERQ Base (write only) <byte 10636> union erq_len (Offset 004) ERQ Length (write only) <byte 10636> {field (By field)} <byte 10636> lbits:12 length ERQ Length lbits:20 reserved Reserved {} or erq_len (Offset 004) ERQ Length (write only) <byte 10636> ulong value As longword endunion erq_len (Offset 004) ERQ Length (write only) <byte 10640> union erq_prod (Offset 008) ERQ Producer Index <byte 10640> {field (By field)} <byte 10640> lbits:12 index ERQ Producer Index lbits:20 reserved Reserved {} or erq_prod (Offset 008) ERQ Producer Index <byte 10640> ulong value As longword endunion erq_prod (Offset 008) ERQ Producer Index <byte 10644> union erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 10644> {field (By field)}

<byte 10644> lbits:32 address ERQ Consumer Index Address {} or erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 10644> ulong value As longword endunion erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 10648> union erq_cons (Offset 010) ERQ Consumer Index <byte 10648> {field (By field)} <byte 10648> lbits:12 index ERQ Consumer Index lbits:20 reserved Reserved {} or erq_cons (Offset 010) ERQ Consumer Index <byte 10648> ulong value As longword endunion erq_cons (Offset 010) ERQ Consumer Index <byte 10652> {rsvd1[0] ((Offset 014-04F) Reserved)} <byte 10652> ulong value {} <byte 10656> {rsvd1[1] ((Offset 014-04F) Reserved)} <byte 10656> ulong value {} <byte 10660> {rsvd1[2] ((Offset 014-04F) Reserved)} <byte 10660> ulong value {} <byte 10664> {rsvd1[3] ((Offset 014-04F) Reserved)} <byte 10664> ulong value {} <byte 10668> {rsvd1[4] ((Offset 014-04F) Reserved)} <byte 10668> ulong value {} <byte 10672> {rsvd1[5] ((Offset 014-04F) Reserved)} <byte 10672> ulong value {} <byte 10676> {rsvd1[6] ((Offset 014-04F) Reserved)} <byte 10676> ulong value {} <byte 10680> {rsvd1[7] ((Offset 014-04F) Reserved)} <byte 10680> ulong value {} <byte 10684>

{rsvd1[8] ((Offset 014-04F) Reserved)} <byte 10684> ulong value {} <byte 10688> {rsvd1[9] ((Offset 014-04F) Reserved)} <byte 10688> ulong value {} <byte 10692> {rsvd1[10] ((Offset 014-04F) Reserved)} <byte 10692> ulong value {} <byte 10696> {rsvd1[11] ((Offset 014-04F) Reserved)} <byte 10696> ulong value {} <byte 10700> {rsvd1[12] ((Offset 014-04F) Reserved)} <byte 10700> ulong value {} <byte 10704> {rsvd1[13] ((Offset 014-04F) Reserved)} <byte 10704> ulong value {} <byte 10708> {rsvd1[14] ((Offset 014-04F) Reserved)} <byte 10708> ulong value {} <byte 10712> union sfq_base (Offset 050) SFQ Base (write only) <byte 10712> {field (By field)} <byte 10712> lbits:32 address SFQ Base Address {} or sfq_base (Offset 050) SFQ Base (write only) <byte 10712> ulong value As longword endunion sfq_base (Offset 050) SFQ Base (write only) <byte 10716> union sfq_len (Offset 054) SFQ Length (write only) <byte 10716> {field (By field)} <byte 10716> lbits:12 length SFQ Length lbits:20 reserved Reserved {} or sfq_len (Offset 054) SFQ Length (write only) <byte 10716> ulong value As longword endunion sfq_len (Offset 054) SFQ Length (write only) <byte 10720> union sfq_cons (Offset 058) SFQ Consumer Index <byte 10720>

{field (By field)} <byte 10720> lbits:12 index SFQ Consumer Index lbits:20 reserved Reserved {} or sfq_cons (Offset 058) SFQ Consumer Index <byte 10720> ulong value As longword endunion sfq_cons (Offset 058) SFQ Consumer Index <byte 10724> {rsvd2[0] ((Offset 05C-07B) Reserved)} <byte 10724> ulong value {} <byte 10728> {rsvd2[1] ((Offset 05C-07B) Reserved)} <byte 10728> ulong value {} <byte 10732> {rsvd2[2] ((Offset 05C-07B) Reserved)} <byte 10732> ulong value {} <byte 10736> {rsvd2[3] ((Offset 05C-07B) Reserved)} <byte 10736> ulong value {} <byte 10740> {rsvd2[4] ((Offset 05C-07B) Reserved)} <byte 10740> ulong value {} <byte 10744> {rsvd2[5] ((Offset 05C-07B) Reserved)} <byte 10744> ulong value {} <byte 10748> {rsvd2[6] ((Offset 05C-07B) Reserved)} <byte 10748> ulong value {} <byte 10752> {rsvd2[7] ((Offset 05C-07B) Reserved)} <byte 10752> ulong value {} <byte 10756> union int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 10756> {field (By field)} <byte 10756> lbits:4 timer Interrupt Timer Value lbits:3 reserved Reserved lbits:1 ihf Interrupt when IMQ Half Full lbits:24 reserved1 Reserved {} or int_delay_timer (Offset 07C) Interrupt Delay Timer (write only)

<byte 10756> ulong value As longword endunion int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 10760> union imq_base (Offset 080) IMQ Base (write only) <byte 10760> {field (By field)} <byte 10760> lbits:32 address IMQ Base Address {} or imq_base (Offset 080) IMQ Base (write only) <byte 10760> ulong value As longword endunion imq_base (Offset 080) IMQ Base (write only) <byte 10764> union imq_len (Offset 084) IMQ Length (write only) <byte 10764> {field (By field)} <byte 10764> lbits:12 length IMQ Length lbits:20 reserved Reserved {} or imq_len (Offset 084) IMQ Length (write only) <byte 10764> ulong value As longword endunion imq_len (Offset 084) IMQ Length (write only) <byte 10768> union imq_cons (Offset 088) IMQ Consumer Index <byte 10768> {field (By field)} <byte 10768> lbits:12 index IMQ Consumer Index lbits:20 reserved Reserved {} or imq_cons (Offset 088) IMQ Consumer Index <byte 10768> ulong value As longword endunion imq_cons (Offset 088) IMQ Consumer Index <byte 10772> union imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 10772> {field (By field)} <byte 10772> lbits:32 address IMQ Producer Index Address {} or imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 10772> ulong value As longword endunion imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 10776> {rsvd3[0] ((Offset 090-0FC) Reserved)} <byte 10776> ulong value {} <byte 10780> {rsvd3[1] ((Offset 090-0FC) Reserved)} <byte 10780> ulong value {} <byte 10784>

{rsvd3[2] ((Offset 090-0FC) Reserved)} <byte 10784> ulong value {} <byte 10788> {rsvd3[3] ((Offset 090-0FC) Reserved)} <byte 10788> ulong value {} <byte 10792> {rsvd3[4] ((Offset 090-0FC) Reserved)} <byte 10792> ulong value {} <byte 10796> {rsvd3[5] ((Offset 090-0FC) Reserved)} <byte 10796> ulong value {} <byte 10800> {rsvd3[6] ((Offset 090-0FC) Reserved)} <byte 10800> ulong value {} <byte 10804> {rsvd3[7] ((Offset 090-0FC) Reserved)} <byte 10804> ulong value {} <byte 10808> {rsvd3[8] ((Offset 090-0FC) Reserved)} <byte 10808> ulong value {} <byte 10812> {rsvd3[9] ((Offset 090-0FC) Reserved)} <byte 10812> ulong value {} <byte 10816> {rsvd3[10] ((Offset 090-0FC) Reserved)} <byte 10816> ulong value {} <byte 10820> {rsvd3[11] ((Offset 090-0FC) Reserved)} <byte 10820> ulong value {} <byte 10824> {rsvd3[12] ((Offset 090-0FC) Reserved)} <byte 10824> ulong value {} <byte 10828> {rsvd3[13] ((Offset 090-0FC) Reserved)} <byte 10828> ulong value {} <byte 10832>

{rsvd3[14] ((Offset <byte 10832> ulong value {} <byte 10836> {rsvd3[15] ((Offset <byte 10836> ulong value {} <byte 10840> {rsvd3[16] ((Offset <byte 10840> ulong value {} <byte 10844> {rsvd3[17] ((Offset <byte 10844> ulong value {} <byte 10848> {rsvd3[18] ((Offset <byte 10848> ulong value {} <byte 10852> {rsvd3[19] ((Offset <byte 10852> ulong value {} <byte 10856> {rsvd3[20] ((Offset <byte 10856> ulong value {} <byte 10860> {rsvd3[21] ((Offset <byte 10860> ulong value {} <byte 10864> {rsvd3[22] ((Offset <byte 10864> ulong value {} <byte 10868> {rsvd3[23] ((Offset <byte 10868> ulong value {} <byte 10872> {rsvd3[24] ((Offset <byte 10872> ulong value {} <byte 10876> {rsvd3[25] ((Offset <byte 10876> ulong value {} <byte 10880>

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

{rsvd3[26] ((Offset 090-0FC) Reserved)} <byte 10880> ulong value {} <byte 10884> {rsvd3[27] ((Offset 090-0FC) Reserved)} <byte 10884> ulong value {} <byte 10888> union fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 10888> {field (By field)} <byte 10888> lbits:6 bec Termination Receive lbits:3 reserved4 Reserved lbits:1 xrb Wrapback lbits:2 reserved Reserved lbits:3 xem Output pre-emphasis lbits:4 reserved1 Reserved lbits:1 mustbe1 Must be 1 lbits:1 stb Start BERT lbits:1 enb Enable BERT lbits:2 sdm Signal differential mode lbits:2 rxs Receiver Speed lbits:2 txs Transmitter Speed lbits:1 reserved3 Reserved lbits:1 xlr Force iTR to lock reference clock lbits:1 reserved0 Reserved lbits:1 xcv Type of Transceiver {} or fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 10888> ulong value As longword endunion fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 10892> union fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 10892> {field (By field)} <byte 10892> lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization

lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 10892> ulong value As longword endunion fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 10896> {rsvd3a[0] ((Offset 108-10f) Reserved)} <byte 10896> ulong value {} <byte 10900> {rsvd3a[1] ((Offset 108-10f) Reserved)} <byte 10900> ulong value {} <byte 10904> union sfp_cmd_status (Offset 110) SFP command and status <byte 10904> {field (No description available)} <byte 10904> lbits:1 gna Generate NACK lbits:1 rts Reset Slave lbits:1 wrc Write command lbits:1 rdc Read command lbits:1 gst Generate Stop lbits:1 sta Generate Start lbits:2 reserved1 Reserved lbits:1 rna Received NACK lbits:1 sby SFP Busy lbits:1 tip Transfer in progress lbits:9 reserved Reserved lbits:12 lp Clock Divisor {} or sfp_cmd_status (Offset 110) SFP command and status <byte 10904> ulong value endunion sfp_cmd_status (Offset 110) SFP command and status <byte 10908> union sfp_data (Offset 114) SFP data <byte 10908> {field (By field)} <byte 10908> lbits:8 sfpd SFPD Transmit lbits:24 reserved Reserved {} or sfp_data (Offset 114) SFP data <byte 10908> ulong value As longword endunion sfp_data (Offset 114) SFP data <byte 10912> union fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 10912> {field (By field)} <byte 10912>

lbits:1 tbe Transmit Link BIST error lbits:1 tlr Transmit Link BIST reset lbits:1 tle Transmit Link BIST enable lbits:1 rbe Receive Link BIST error lbits:1 rll Receive Link BIST loop-back lbits:1 rlr Receive Link BIST reset lbits:1 rle Receive Link BIST enable lbits:7 reserved3 Reserved lbits:1 ipl ITR PPL Lock lbits:1 reserved2 Reserved lbits:1 dtf Disable transceiver LOS filter lbits:1 dtl Disable transceiver LOS lbits:1 dsr Disable iTR RXLOS lbits:1 ttd Transceiver Tx Disable lbits:2 reserved1 Reserved lbits:1 rfl Receive ast Lock Disable lbits:9 reserved Reserved {} or fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 10912> ulong value As longword endunion fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 10916> union fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 10916> {field (By field)} <byte 10916> lbits:32 reserved Reserved {} or fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 10916> ulong value As longword endunion fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 10920> {rsvd3b[0] ((Offset 120-13F) Reserved)} <byte 10920> ulong value {} <byte 10924> {rsvd3b[1] ((Offset 120-13F) Reserved)} <byte 10924> ulong value {} <byte 10928> {rsvd3b[2] ((Offset 120-13F) Reserved)} <byte 10928> ulong value {} <byte 10932> {rsvd3b[3] ((Offset 120-13F) Reserved)} <byte 10932> ulong value {} <byte 10936> {rsvd3b[4] ((Offset 120-13F) Reserved)} <byte 10936> ulong value {} <byte 10940> {rsvd3b[5] ((Offset 120-13F) Reserved)}

<byte 10940> ulong value {} <byte 10944> {rsvd3b[6] ((Offset 120-13F) Reserved)} <byte 10944> ulong value {} <byte 10948> {rsvd3b[7] ((Offset 120-13F) Reserved)} <byte 10948> ulong value {} <byte 10952> union sest_base (Offset 140) SEST Base (write only) <byte 10952> {field (By field)} <byte 10952> lbits:32 address SEST Base Address {} or sest_base (Offset 140) SEST Base (write only) <byte 10952> ulong value As longword endunion sest_base (Offset 140) SEST Base (write only) <byte 10956> union sest_len (Offset 144) SEST Length (write only) <byte 10956> {field (By field)} <byte 10956> lbits:16 length SEST Length lbits:16 reserved Reserved {} or sest_len (Offset 144) SEST Length (write only) <byte 10956> ulong value As longword endunion sest_len (Offset 144) SEST Length (write only) <byte 10960> {rsvd4 ((Offset 148) Reserved)} <byte 10960> ulong value {} <byte 10964> union scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 10964> {field (By field)} <byte 10964> lbits:16 tail Tail lbits:16 head Head {} or scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 10964> ulong value As longword endunion scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 10968> union prog_addr (Offset 150) Programmable Address register <byte 10968> {field (By field)} <byte 10968> lbits:20 ra ROM/RAM address lbits:11 reserved Reserved

lbits:1 inc Increment {} or prog_addr (Offset 150) Programmable Address register <byte 10968> ulong value As longword endunion prog_addr (Offset 150) Programmable Address register <byte 10972> union prog_data (Offset 154) programmable data register <byte 10972> {field (By field)} <byte 10972> lbits:32 pdr Programmable data {} or prog_data (Offset 154) programmable data register <byte 10972> ulong value As longword endunion prog_data (Offset 154) programmable data register <byte 10976> {rsvd5[0] ((Offset 158-15F) Reserved)} <byte 10976> ulong value {} <byte 10980> {rsvd5[1] ((Offset 158-15F) Reserved)} <byte 10980> ulong value {} <byte 10984> union int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 10984> {field (By field)} <byte 10984> lbits:32 address Interrupt Message Address {} or int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 10984> ulong value As longword endunion int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 10988> union int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 10988> {field (By field)} <byte 10988> lbits:32 value Interrupt Message Value {} or int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 10988> ulong value As longword endunion int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 10992> union sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 10992> {field (By field)} <byte 10992> lbits:8 length SGL Page Length lbits:24 reserved Reserved {} or sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 10992> ulong value As longword

endunion sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 10996> union my_id (Offset 16C) My ID <byte 10996> {field (By field)} <byte 10996> lbits:24 id My ID lbits:8 reserved Reserved {} or my_id (Offset 16C) My ID <byte 10996> ulong value As longword endunion my_id (Offset 16C) My ID <byte 11000> union gpio (Offset 170) General Purpose I/O <byte 11000> {field (By field)} <byte 11000> lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:1 gc5 General Purpose Control 5 lbits:1 gc6 General Purpose Control 6 lbits:1 gc7 General Purpose Control 7 lbits:8 reserved Reserved lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose I/O 4 lbits:1 gp5 General Purpose I/O 5 lbits:1 gp6 General Purpose I/O 6 lbits:1 gp7 General Purpose I/O 7 lbits:8 reserved1 Reserved {} or gpio (Offset 170) General Purpose I/O <byte 11000> ulong value As longword endunion gpio (Offset 170) General Purpose I/O <byte 11004> {rsvd6a ((Offset 174-177) Reserved)} <byte 11004> ulong value {} <byte 11008> union edc_config (Offset 178) EDC Configuration Register <byte 11008> {field (By field)} <byte 11008> lbits:16 io_seed Starting Seed lbits:16 reserved Reserved {} or edc_config (Offset 178) EDC Configuration Register <byte 11008> ulong value As longword endunion edc_config (Offset 178) EDC Configuration Register <byte 11012> union dx4_config3 (Offset 17C) DX4 Configuration Register 3

<byte 11012> {field (By field)} <byte 11012> lbits:9 pfs2 Programmable Frame size field 2 lbits:9 pfs3 Programmable Frame size field 3 lbits:9 pfs4 Programmable Frame size field 4 lbits:5 reserved Reserved {} or dx4_config3 (Offset 17C) DX4 Configuration Register 3 <byte 11012> ulong value As longword endunion dx4_config3 (Offset 17C) DX4 Configuration Register 3 <byte 11016> union tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 11016> {field (By field)} <byte 11016> lbits:9 pfs Programmable Frame Size lbits:15 reserved Reserved lbits:8 esi_range Exchange_ID Signaled Interrupt Range {} or tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 11016> ulong value As longword endunion tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 11020> union tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 11020> {field (By field)} <byte 11020> lbits:1 fad FCP Assist Disable lbits:1 ino In Order lbits:1 dof Discard OOO FCP Frames lbits:1 fua FCP Unassisted ACK Enable lbits:1 ime Interrupt Message Enable lbits:1 fab Fabric lbits:1 sic S_ID Copy Enable lbits:1 eqs Equal Service lbits:2 reserved Reserved lbits:1 aks Automatic ACK lbits:1 ddf Disable Delayed Freeze lbits:1 ebe Enable Big Endian Mode lbits:11 reserved1 Reserved lbits:1 fc2 FCP Class 2 Reassembly Enable lbits:1 reserved2 Reserved lbits:1 sdf Save Discarded Frames lbits:1 rde Response Detect Enable lbits:1 dam Default ACK Model lbits:2 reserved3 Reserved lbits:1 m66 66 MHz Enabled {} or tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 11020> ulong value As longword endunion tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 11024> union tach_control (Offset 188) Tachyon DX2+ Control <byte 11024> {field (By field)} <byte 11024>

lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:3 reserved Reserved lbits:1 feq Freeze ERQ lbits:1 ffa Freeze FCP Assists lbits:2 reserved1 Reserved lbits:1 fis Freeze Inbound FCP Assists When Frame Placed in SFQ lbits:1 fib Freeze Inbound FCP Assists lbits:2 reserved2 Reserved lbits:1 req Resume ERQ lbits:1 rif Resume Inbound FCP Assists lbits:1 rof Resume Outbound FCP Assists lbits:12 reserved3 Reserved lbits:1 crs Core Reset {} or tach_control (Offset 188) Tachyon DX2+ Control <byte 11024> ulong value As longword endunion tach_control (Offset 188) Tachyon DX2+ Control <byte 11028> union tach_status (Offset 18C) Tachyon DX2+ Status <byte 11028> {field (By field)} <byte 11028> lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose Input 4 lbits:5 reserved Reserved lbits:1 ipe Inbound Parity Error lbits:1 ope Outbound Parity Error lbits:4 reserved1 Reserved lbits:1 eqf ERQ Frozen lbits:1 iff Inbound FCP Assists Frozen lbits:1 off Outbound FCP Assists Frozen lbits:4 reserved2 Reserved lbits:1 ifce Inbound FIFO CRC Error lbits:1 ofce Outbound FIFO CRC Error lbits:1 m66 66 Mhz Enabled lbits:1 ile Inbound Link Control FIFO Empty lbits:1 ole Outbound Link Control List Empty lbits:1 ife Inbound FIFO Empty lbits:1 ofe Outbound FIFO Empty lbits:1 imf IMQ Full lbits:1 ssf SFQ Full {} or tach_status (Offset 18C) Tachyon DX2+ Status <byte 11028> ulong value As longword endunion tach_status (Offset 18C) Tachyon DX2+ Status <byte 11032> {rsvd7 ((Offset 190) Reserved)} <byte 11032> ulong value {} <byte 11036>

union hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 11036> {field (By field)} <byte 11036> lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 11036> ulong value As longword endunion hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 11040> union hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 11040> {field (By field)} <byte 11040> lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 11040> ulong value As longword endunion hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 11044> union inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 11044> {field (By field)} <byte 11044> lbits:24 reserved Reserved lbits:8 sest_lru_count SEST LRU Count {} or inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 11044> ulong value As longword endunion inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 11048> union inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 11048> {field (By field)} <byte 11048> lbits:8 discd_frames Discarded Frame Count lbits:24 reserved Reserved {} or inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 11048> ulong value As longword endunion inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 11052> union ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) <byte 11052> {field (By field)} <byte 11052> lbits:28 threshold EE_Credit Zero Timer Threshold lbits:4 reserved Reserved {} or ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only)

<byte 11052> ulong value As longword endunion ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only ) <byte 11056> union up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 11056> {field (By field)} <byte 11056> lbits:12 reserved Reserved lbits:1 upper_addr1 Upper Data Address--44 bit data space lbits:19 upper_addr Upper Data Address {} or up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 11056> ulong value As longword endunion up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 11060> union up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 11060> {field (By field)} <byte 11060> lbits:32 upper_addr Upper Control Address {} or up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 11060> ulong value As longword endunion up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 11064> union dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 11064> {field (By field)} <byte 11064> lbits:1 ef AL_PA 0xEF DHD Login Information lbits:1 e8 AL_PA 0xE8 DHD Login Information lbits:1 e4 AL_PA 0xE4 DHD Login Information lbits:1 e2 AL_PA 0xE2 DHD Login Information lbits:1 e1 AL_PA 0xE1 DHD Login Information lbits:1 e0 AL_PA 0xE0 DHD Login Information lbits:1 dc AL_PA 0xDC DHD Login Information lbits:1 da AL_PA 0xDA DHD Login Information lbits:1 d9 AL_PA 0xD9 DHD Login Information lbits:1 d6 AL_PA 0xD6 DHD Login Information lbits:1 d5 AL_PA 0xD5 DHD Login Information lbits:1 d4 AL_PA 0xD4 DHD Login Information lbits:1 d3 AL_PA 0xD3 DHD Login Information lbits:1 d2 AL_PA 0xD2 DHD Login Information lbits:1 d1 AL_PA 0xD1 DHD Login Information lbits:1 ce AL_PA 0xCE DHD Login Information lbits:1 cd AL_PA 0xCD DHD Login Information lbits:1 cc AL_PA 0xCC DHD Login Information lbits:1 cb AL_PA 0xCB DHD Login Information lbits:1 ca AL_PA 0xCA DHD Login Information lbits:1 c9 AL_PA 0xC9 DHD Login Information lbits:1 c7 AL_PA 0xC7 DHD Login Information lbits:1 c6 AL_PA 0xC6 DHD Login Information lbits:1 c5 AL_PA 0xC5 DHD Login Information lbits:1 c3 AL_PA 0xC3 DHD Login Information lbits:1 bc AL_PA 0xBC DHD Login Information lbits:1 ba AL_PA 0xBA DHD Login Information

lbits:1 b9 AL_PA 0xB9 DHD Login Information lbits:1 b6 AL_PA 0xB6 DHD Login Information lbits:1 b5 AL_PA 0xB5 DHD Login Information lbits:1 b4 AL_PA 0xB4 DHD Login Information lbits:1 b3 AL_PA 0xB3 DHD Login Information {} or dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 11064> ulong value As longword endunion dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 11068> union dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 11068> {field (By field)} <byte 11068> lbits:1 alpab2 AL_PA 0xB2 DHD Login Information lbits:1 alpab1 AL_PA 0xB1 DHD Login Information lbits:1 alpaae AL_PA 0xAE DHD Login Information lbits:1 alpaad AL_PA 0xAD DHD Login Information lbits:1 alpaac AL_PA 0xAC DHD Login Information lbits:1 alpaab AL_PA 0xAB DHD Login Information lbits:1 alpaaa AL_PA 0xAA DHD Login Information lbits:1 alpaa9 AL_PA 0xA9 DHD Login Information lbits:1 alpaa7 AL_PA 0xA7 DHD Login Information lbits:1 alpaa6 AL_PA 0xA6 DHD Login Information lbits:1 alpaa5 AL_PA 0xA5 DHD Login Information lbits:1 alpaa3 AL_PA 0xA3 DHD Login Information lbits:1 alpa9f AL_PA 0x9F DHD Login Information lbits:1 alpa9e AL_PA 0x9E DHD Login Information lbits:1 alpa9d AL_PA 0x9D DHD Login Information lbits:1 alpa9b AL_PA 0x9B DHD Login Information lbits:1 alpa98 AL_PA 0x98 DHD Login Information lbits:1 alpa97 AL_PA 0x97 DHD Login Information lbits:1 alpa90 AL_PA 0x90 DHD Login Information lbits:1 alpa8f AL_PA 0x8F DHD Login Information lbits:1 alpa88 AL_PA 0x88 DHD Login Information lbits:1 alpa84 AL_PA 0x84 DHD Login Information lbits:1 alpa82 AL_PA 0x82 DHD Login Information lbits:1 alpa81 AL_PA 0x81 DHD Login Information lbits:1 alpa80 AL_PA 0x80 DHD Login Information lbits:1 alpa7c AL_PA 0x7C DHD Login Information lbits:1 alpa7a AL_PA 0x7A DHD Login Information lbits:1 alpa79 AL_PA 0x79 DHD Login Information lbits:1 alpa76 AL_PA 0x76 DHD Login Information lbits:1 alpa75 AL_PA 0x75 DHD Login Information lbits:1 alpa74 AL_PA 0x74 DHD Login Information lbits:1 alpa73 AL_PA 0x73 DHD Login Information {} or dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 11068> ulong value As longword endunion dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 11072> union dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 11072> {field (By field)} <byte 11072> lbits:1 alpa72 AL_PA 0x72 DHD Login Information lbits:1 alpa71 AL_PA 0x71 DHD Login Information lbits:1 alpa6e AL_PA 0x6E DHD Login Information

lbits:1 alpa6d AL_PA 0x6D DHD Login Information lbits:1 alpa6c AL_PA 0x6C DHD Login Information lbits:1 alpa6b AL_PA 0x6B DHD Login Information lbits:1 alpa6a AL_PA 0x6A DHD Login Information lbits:1 alpa69 AL_PA 0x69 DHD Login Information lbits:1 alpa67 AL_PA 0x67 DHD Login Information lbits:1 alpa66 AL_PA 0x66 DHD Login Information lbits:1 alpa65 AL_PA 0x65 DHD Login Information lbits:1 alpa63 AL_PA 0x63 DHD Login Information lbits:1 alpa5c AL_PA 0x5C DHD Login Information lbits:1 alpa5a AL_PA 0x5A DHD Login Information lbits:1 alpa59 AL_PA 0x59 DHD Login Information lbits:1 alpa56 AL_PA 0x56 DHD Login Information lbits:1 alpa55 AL_PA 0x55 DHD Login Information lbits:1 alpa54 AL_PA 0x54 DHD Login Information lbits:1 alpa53 AL_PA 0x53 DHD Login Information lbits:1 alpa52 AL_PA 0x52 DHD Login Information lbits:1 alpa51 AL_PA 0x51 DHD Login Information lbits:1 alpa4e AL_PA 0x4E DHD Login Information lbits:1 alpa4d AL_PA 0x4D DHD Login Information lbits:1 alpa4c AL_PA 0x4C DHD Login Information lbits:1 alpa4b AL_PA 0x4B DHD Login Information lbits:1 alpa4a AL_PA 0x4A DHD Login Information lbits:1 alpa49 AL_PA 0x49 DHD Login Information lbits:1 alpa47 AL_PA 0x47 DHD Login Information lbits:1 alpa46 AL_PA 0x46 DHD Login Information lbits:1 alpa45 AL_PA 0x45 DHD Login Information lbits:1 alpa43 AL_PA 0x43 DHD Login Information lbits:1 alpa3c AL_PA 0x3C DHD Login Information {} or dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 11072> ulong value As longword endunion dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 11076> union dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 11076> {field (By field)} <byte 11076> lbits:1 alpa3a AL_PA 0x3A DHD Login Information lbits:1 alpa39 AL_PA 0x39 DHD Login Information lbits:1 alpa36 AL_PA 0x36 DHD Login Information lbits:1 alpa35 AL_PA 0x35 DHD Login Information lbits:1 alpa34 AL_PA 0x34 DHD Login Information lbits:1 alpa33 AL_PA 0x33 DHD Login Information lbits:1 alpa32 AL_PA 0x32 DHD Login Information lbits:1 alpa31 AL_PA 0x31 DHD Login Information lbits:1 alpa2e AL_PA 0x2E DHD Login Information lbits:1 alpa2d AL_PA 0x2D DHD Login Information lbits:1 alpa2c AL_PA 0x2C DHD Login Information lbits:1 alpa2b AL_PA 0x2B DHD Login Information lbits:1 alpa2a AL_PA 0x2A DHD Login Information lbits:1 alpa29 AL_PA 0x29 DHD Login Information lbits:1 alpa27 AL_PA 0x27 DHD Login Information lbits:1 alpa26 AL_PA 0x26 DHD Login Information lbits:1 alpa25 AL_PA 0x25 DHD Login Information lbits:1 alpa23 AL_PA 0x23 DHD Login Information lbits:1 alpa1f AL_PA 0x1F DHD Login Information lbits:1 alpa1e AL_PA 0x1E DHD Login Information lbits:1 alpa1d AL_PA 0x1D DHD Login Information

lbits:1 alpa1b AL_PA 0x1B DHD Login Information lbits:1 alpa18 AL_PA 0x18 DHD Login Information lbits:1 alpa17 AL_PA 0x17 DHD Login Information lbits:1 alpa10 AL_PA 0x10 DHD Login Information lbits:1 alpa0f AL_PA 0x0F DHD Login Information lbits:1 alpa08 AL_PA 0x08 DHD Login Information lbits:1 alpa04 AL_PA 0x04 DHD Login Information lbits:1 alpa02 AL_PA 0x02 DHD Login Information lbits:1 alpa01 AL_PA 0x01 DHD Login Information lbits:1 alpa00 AL_PA 0x00 DHD Login Information lbits:1 reserved Reserved {} or dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 11076> ulong value As longword endunion dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 11080> union fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 11080> {field (By field)} <byte 11080> lbits:1 bli Bypass Loop Initialization lbits:1 reserved Reserved lbits:1 enp Enable N_Port Mode lbits:1 lr Login Required lbits:1 inif Initialize as Fabric lbits:1 rf Respond to Fabric Address lbits:1 blm Bypass Loop Map lbits:1 sa Acquire Soft Address lbits:1 ha Acquire Hard Address lbits:1 aq Acquire Previously Acquired Address lbits:1 fa Acquire Fabric Aquired Address lbits:1 td Timer Disable lbits:1 sap Skip Arbitration Phase lbits:1 elb External Loopback/Pad Loopback lbits:1 ilb Internal loopback lbits:1 npi Initialize as N_Port lbits:8 bb_credit BB_Credit lbits:8 al_pa Desired AL_PA {} or fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 11080> ulong value As longword endunion fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 11084> union fm_control (Offset 1C4) Frame Manager Control <byte 11084> {field (By field)} <byte 11084> lbits:3 cmd State Machine Command lbits:1 cl Close Loop Request lbits:1 reserved Reserved lbits:1 sp Send Prim_Reg lbits:1 sq Primitive Sequence lbits:25 reserved1 Reserved {} or fm_control (Offset 1C4) Frame Manager Control <byte 11084> ulong value As longword endunion fm_control (Offset 1C4) Frame Manager Control

<byte 11088> union fm_status (Offset 1C8) Frame Manager Status <byte 11088> {field (By field)} <byte 11088> lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_status (Offset 1C8) Frame Manager Status <byte 11088> ulong value As longword endunion fm_status (Offset 1C8) Frame Manager Status <byte 11092> union fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 11092> {field (By field)} <byte 11092> lbits:16 ed_tov Error Detect Time-Out lbits:9 rt_tov Receiver Transmitter Time-Out lbits:7 reserved Reserved {} or fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 11092> ulong value As longword endunion fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 11096> union fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 11096> {field (By field)} <byte 11096> lbits:8 link_fail Link Fail Count lbits:8 loss_of_sync Loss of Synchronization Count lbits:8 bad_rx_char Bad Received Character Count lbits:8 loss_of_signal Loss of Signal Count {} or fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1

<byte 11096> ulong value As longword endunion fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 11100> union fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 11100> {field (By field)} <byte 11100> lbits:8 proto_er Protocol Error Count lbits:8 bad_crc Bad CRC Count lbits:8 dis_frm Discarded Frames lbits:8 rx_eofa Received EOFa {} or fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 11100> ulong value As longword endunion fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 11104> union fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 11104> {field (By field)} <byte 11104> lbits:9 al_time Arbitrated Loop Time-Out lbits:7 reserved Reserved lbits:16 lp_tov Loop Time-Out {} or fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 11104> ulong value As longword endunion fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 11108> union fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 11108> {field (By field)} <byte 11108> lbits:24 bb0_timer BB_Credit Timer lbits:8 reserved Reserved {} or fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 11108> ulong value As longword endunion fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 11112> union fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 11112> {field (By field)} <byte 11112> lbits:32 wwn World Wide Name {} or fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 11112> ulong value As longword endunion fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 11116> union fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 11116> {field (By field)} <byte 11116> lbits:32 wwn World Wide Name {}

or fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 11116> ulong value As longword endunion fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 11120> union fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 11120> {field (By field)} <byte 11120> lbits:8 lipf_alpa AL_PA of Most Recent LIPf Received lbits:8 bad_alpa AL_PA of Most Recent OPN Sent and Returned Without Being Accept ed lbits:8 acq_alpa AL_PA Acquired During Loop Initialization lbits:8 reserved Reserved {} or fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 11120> ulong value As longword endunion fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 11124> union fm_primitive (Offset 1EC) Frame Manager Primitive <byte 11124> {field (By field)} <byte 11124> lbits:24 prim_value Primitive to be Sent lbits:8 reserved Reserved {} or fm_primitive (Offset 1EC) Frame Manager Primitive <byte 11124> ulong value As longword endunion fm_primitive (Offset 1EC) Frame Manager Primitive <byte 11128> union fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 11128> {field (By field)} <byte 11128> lbits:8 exp_frm Expired Frames lbits:24 reserved Reserved {} or fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 11128> ulong value As longword endunion fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 11132> union fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 11132> {field (By field)} <byte 11132> lbits:1 dac Disable Auto Close lbits:2 nbc Non-zero Login BB_Credit lbits:1 eei Enable ERR_INIT lbits:1 icb Ignore Close Bit lbits:2 atv Arbitration Threshold Value lbits:1 gde Garbage Deletion Enable lbits:8 laa Lowest Allowable AL_PA lbits:5 reserved Reserved lbits:1 dao Disable 2xAL_TIME Timeout on Open lbits:3 reserved1 Reserved lbits:1 prm Promiscuous Mode lbits:1 wpe Wait For Port Enable

lbits:1 fmh Force Monitor State With Hard Address lbits:1 fmn Force Monitor Non-participating State lbits:1 dlm Disable Loop Master lbits:1 dsa Disable Soft Address Selection lbits:1 ilp Ignore LPB/LPE Primitive Sequences {} or fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 11132> ulong value As longword endunion fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 11136> union pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED <byte 11136> {field (By field)} <byte 11136> {pci_rsvd1F8 ((Offset 1F8) Reserved)} <byte 11136> utiny value {} <byte 11137> {pci_rsvd1F9 ((Offset 1F9) Reserved)} <byte 11137> utiny value {} <byte 11138> union romctr (Offset 1FA) PCI ROM Control <byte 11138> {field (By field)} <byte 11138> tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or romctr (Offset 1FA) PCI ROM Control <byte 11138> utiny value As byte endunion romctr (Offset 1FA) PCI ROM Control <byte 11139> union mctr (Offset 1FB) PCI Master Control <byte 11139> {field (By field)} <byte 11139> tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or mctr (Offset 1FB) PCI Master Control <byte 11139> utiny value As byte endunion mctr (Offset 1FB) PCI Master Control {} or pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED <byte 11136> ulong value As longword endunion pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED <byte 11140> union pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST <byte 11140>

{field (By field)} <byte 11140> union softrst (Offset 1FC) PCI Interface Reset Control <byte 11140> {field (By field)} <byte 11140> tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or softrst (Offset 1FC) PCI Interface Reset Control <byte 11140> utiny value As byte endunion softrst (Offset 1FC) PCI Interface Reset Control <byte 11141> union intpend (Offset 1FD) PCI Interrupt Pending <byte 11141> {field (By field)} <byte 11141> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intpend (Offset 1FD) PCI Interrupt Pending <byte 11141> utiny value As byte endunion intpend (Offset 1FD) PCI Interrupt Pending <byte 11142> union inten (Offset 1FE) PCI Interrupt Enable <byte 11142> {field (By field)} <byte 11142> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or inten (Offset 1FE) PCI Interrupt Enable <byte 11142> utiny value As byte endunion inten (Offset 1FE) PCI Interrupt Enable <byte 11143> union intstat (Offset 1FF) PCI Interrupt Status <byte 11143> {field (By field)} <byte 11143> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intstat (Offset 1FF) PCI Interrupt Status <byte 11143> utiny value As byte

endunion intstat (Offset 1FF) PCI Interrupt Status {} or pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST <byte 11140> ulong value As longword endunion pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST {} endunion csr[8] Tachyon DX2+ CSR Registers <byte 11144> union csr[9] Tachyon DX2+ CSR Registers <byte 11144> ulong[128] csra Tachyon DX2+ CSR Registers As Longwords or csr[9] Tachyon DX2+ CSR Registers <byte 11144> {csr (Tachyon DX2+ CSR Registers By Field)} <byte 11144> union erq_base (Offset 000) ERQ Base (write only) <byte 11144> {field (By field)} <byte 11144> lbits:32 address ERQ Base Address {} or erq_base (Offset 000) ERQ Base (write only) <byte 11144> ulong value As longword endunion erq_base (Offset 000) ERQ Base (write only) <byte 11148> union erq_len (Offset 004) ERQ Length (write only) <byte 11148> {field (By field)} <byte 11148> lbits:12 length ERQ Length lbits:20 reserved Reserved {} or erq_len (Offset 004) ERQ Length (write only) <byte 11148> ulong value As longword endunion erq_len (Offset 004) ERQ Length (write only) <byte 11152> union erq_prod (Offset 008) ERQ Producer Index <byte 11152> {field (By field)} <byte 11152> lbits:12 index ERQ Producer Index lbits:20 reserved Reserved {} or erq_prod (Offset 008) ERQ Producer Index <byte 11152> ulong value As longword endunion erq_prod (Offset 008) ERQ Producer Index <byte 11156> union erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 11156> {field (By field)} <byte 11156> lbits:32 address ERQ Consumer Index Address {} or erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 11156> ulong value As longword

endunion erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 11160> union erq_cons (Offset 010) ERQ Consumer Index <byte 11160> {field (By field)} <byte 11160> lbits:12 index ERQ Consumer Index lbits:20 reserved Reserved {} or erq_cons (Offset 010) ERQ Consumer Index <byte 11160> ulong value As longword endunion erq_cons (Offset 010) ERQ Consumer Index <byte 11164> {rsvd1[0] ((Offset 014-04F) Reserved)} <byte 11164> ulong value {} <byte 11168> {rsvd1[1] ((Offset 014-04F) Reserved)} <byte 11168> ulong value {} <byte 11172> {rsvd1[2] ((Offset 014-04F) Reserved)} <byte 11172> ulong value {} <byte 11176> {rsvd1[3] ((Offset 014-04F) Reserved)} <byte 11176> ulong value {} <byte 11180> {rsvd1[4] ((Offset 014-04F) Reserved)} <byte 11180> ulong value {} <byte 11184> {rsvd1[5] ((Offset 014-04F) Reserved)} <byte 11184> ulong value {} <byte 11188> {rsvd1[6] ((Offset 014-04F) Reserved)} <byte 11188> ulong value {} <byte 11192> {rsvd1[7] ((Offset 014-04F) Reserved)} <byte 11192> ulong value {} <byte 11196> {rsvd1[8] ((Offset 014-04F) Reserved)} <byte 11196> ulong value {} <byte 11200> {rsvd1[9] ((Offset 014-04F) Reserved)}

<byte 11200> ulong value {} <byte 11204> {rsvd1[10] ((Offset 014-04F) Reserved)} <byte 11204> ulong value {} <byte 11208> {rsvd1[11] ((Offset 014-04F) Reserved)} <byte 11208> ulong value {} <byte 11212> {rsvd1[12] ((Offset 014-04F) Reserved)} <byte 11212> ulong value {} <byte 11216> {rsvd1[13] ((Offset 014-04F) Reserved)} <byte 11216> ulong value {} <byte 11220> {rsvd1[14] ((Offset 014-04F) Reserved)} <byte 11220> ulong value {} <byte 11224> union sfq_base (Offset 050) SFQ Base (write only) <byte 11224> {field (By field)} <byte 11224> lbits:32 address SFQ Base Address {} or sfq_base (Offset 050) SFQ Base (write only) <byte 11224> ulong value As longword endunion sfq_base (Offset 050) SFQ Base (write only) <byte 11228> union sfq_len (Offset 054) SFQ Length (write only) <byte 11228> {field (By field)} <byte 11228> lbits:12 length SFQ Length lbits:20 reserved Reserved {} or sfq_len (Offset 054) SFQ Length (write only) <byte 11228> ulong value As longword endunion sfq_len (Offset 054) SFQ Length (write only) <byte 11232> union sfq_cons (Offset 058) SFQ Consumer Index <byte 11232> {field (By field)} <byte 11232> lbits:12 index SFQ Consumer Index lbits:20 reserved Reserved {} or sfq_cons (Offset 058) SFQ Consumer Index

<byte 11232> ulong value As longword endunion sfq_cons (Offset 058) SFQ Consumer Index <byte 11236> {rsvd2[0] ((Offset 05C-07B) Reserved)} <byte 11236> ulong value {} <byte 11240> {rsvd2[1] ((Offset 05C-07B) Reserved)} <byte 11240> ulong value {} <byte 11244> {rsvd2[2] ((Offset 05C-07B) Reserved)} <byte 11244> ulong value {} <byte 11248> {rsvd2[3] ((Offset 05C-07B) Reserved)} <byte 11248> ulong value {} <byte 11252> {rsvd2[4] ((Offset 05C-07B) Reserved)} <byte 11252> ulong value {} <byte 11256> {rsvd2[5] ((Offset 05C-07B) Reserved)} <byte 11256> ulong value {} <byte 11260> {rsvd2[6] ((Offset 05C-07B) Reserved)} <byte 11260> ulong value {} <byte 11264> {rsvd2[7] ((Offset 05C-07B) Reserved)} <byte 11264> ulong value {} <byte 11268> union int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 11268> {field (By field)} <byte 11268> lbits:4 timer Interrupt Timer Value lbits:3 reserved Reserved lbits:1 ihf Interrupt when IMQ Half Full lbits:24 reserved1 Reserved {} or int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 11268> ulong value As longword endunion int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 11272> union imq_base (Offset 080) IMQ Base (write only) <byte 11272>

{field (By field)} <byte 11272> lbits:32 address IMQ Base Address {} or imq_base (Offset 080) IMQ Base (write only) <byte 11272> ulong value As longword endunion imq_base (Offset 080) IMQ Base (write only) <byte 11276> union imq_len (Offset 084) IMQ Length (write only) <byte 11276> {field (By field)} <byte 11276> lbits:12 length IMQ Length lbits:20 reserved Reserved {} or imq_len (Offset 084) IMQ Length (write only) <byte 11276> ulong value As longword endunion imq_len (Offset 084) IMQ Length (write only) <byte 11280> union imq_cons (Offset 088) IMQ Consumer Index <byte 11280> {field (By field)} <byte 11280> lbits:12 index IMQ Consumer Index lbits:20 reserved Reserved {} or imq_cons (Offset 088) IMQ Consumer Index <byte 11280> ulong value As longword endunion imq_cons (Offset 088) IMQ Consumer Index <byte 11284> union imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 11284> {field (By field)} <byte 11284> lbits:32 address IMQ Producer Index Address {} or imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 11284> ulong value As longword endunion imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 11288> {rsvd3[0] ((Offset 090-0FC) Reserved)} <byte 11288> ulong value {} <byte 11292> {rsvd3[1] ((Offset 090-0FC) Reserved)} <byte 11292> ulong value {} <byte 11296> {rsvd3[2] ((Offset 090-0FC) Reserved)} <byte 11296> ulong value {} <byte 11300> {rsvd3[3] ((Offset 090-0FC) Reserved)}

<byte 11300> ulong value {} <byte 11304> {rsvd3[4] ((Offset 090-0FC) Reserved)} <byte 11304> ulong value {} <byte 11308> {rsvd3[5] ((Offset 090-0FC) Reserved)} <byte 11308> ulong value {} <byte 11312> {rsvd3[6] ((Offset 090-0FC) Reserved)} <byte 11312> ulong value {} <byte 11316> {rsvd3[7] ((Offset 090-0FC) Reserved)} <byte 11316> ulong value {} <byte 11320> {rsvd3[8] ((Offset 090-0FC) Reserved)} <byte 11320> ulong value {} <byte 11324> {rsvd3[9] ((Offset 090-0FC) Reserved)} <byte 11324> ulong value {} <byte 11328> {rsvd3[10] ((Offset 090-0FC) Reserved)} <byte 11328> ulong value {} <byte 11332> {rsvd3[11] ((Offset 090-0FC) Reserved)} <byte 11332> ulong value {} <byte 11336> {rsvd3[12] ((Offset 090-0FC) Reserved)} <byte 11336> ulong value {} <byte 11340> {rsvd3[13] ((Offset 090-0FC) Reserved)} <byte 11340> ulong value {} <byte 11344> {rsvd3[14] ((Offset 090-0FC) Reserved)} <byte 11344> ulong value {} <byte 11348> {rsvd3[15] ((Offset 090-0FC) Reserved)}

<byte 11348> ulong value {} <byte 11352> {rsvd3[16] ((Offset <byte 11352> ulong value {} <byte 11356> {rsvd3[17] ((Offset <byte 11356> ulong value {} <byte 11360> {rsvd3[18] ((Offset <byte 11360> ulong value {} <byte 11364> {rsvd3[19] ((Offset <byte 11364> ulong value {} <byte 11368> {rsvd3[20] ((Offset <byte 11368> ulong value {} <byte 11372> {rsvd3[21] ((Offset <byte 11372> ulong value {} <byte 11376> {rsvd3[22] ((Offset <byte 11376> ulong value {} <byte 11380> {rsvd3[23] ((Offset <byte 11380> ulong value {} <byte 11384> {rsvd3[24] ((Offset <byte 11384> ulong value {} <byte 11388> {rsvd3[25] ((Offset <byte 11388> ulong value {} <byte 11392> {rsvd3[26] ((Offset <byte 11392> ulong value {} <byte 11396> {rsvd3[27] ((Offset

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

090-0FC) Reserved)}

<byte 11396> ulong value {} <byte 11400> union fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 11400> {field (By field)} <byte 11400> lbits:6 bec Termination Receive lbits:3 reserved4 Reserved lbits:1 xrb Wrapback lbits:2 reserved Reserved lbits:3 xem Output pre-emphasis lbits:4 reserved1 Reserved lbits:1 mustbe1 Must be 1 lbits:1 stb Start BERT lbits:1 enb Enable BERT lbits:2 sdm Signal differential mode lbits:2 rxs Receiver Speed lbits:2 txs Transmitter Speed lbits:1 reserved3 Reserved lbits:1 xlr Force iTR to lock reference clock lbits:1 reserved0 Reserved lbits:1 xcv Type of Transceiver {} or fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 11400> ulong value As longword endunion fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 11404> union fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 11404> {field (By field)} <byte 11404> lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop

{} or fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 11404> ulong value As longword endunion fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 11408> {rsvd3a[0] ((Offset 108-10f) Reserved)} <byte 11408> ulong value {} <byte 11412> {rsvd3a[1] ((Offset 108-10f) Reserved)} <byte 11412> ulong value {} <byte 11416> union sfp_cmd_status (Offset 110) SFP command and status <byte 11416> {field (No description available)} <byte 11416> lbits:1 gna Generate NACK lbits:1 rts Reset Slave lbits:1 wrc Write command lbits:1 rdc Read command lbits:1 gst Generate Stop lbits:1 sta Generate Start lbits:2 reserved1 Reserved lbits:1 rna Received NACK lbits:1 sby SFP Busy lbits:1 tip Transfer in progress lbits:9 reserved Reserved lbits:12 lp Clock Divisor {} or sfp_cmd_status (Offset 110) SFP command and status <byte 11416> ulong value endunion sfp_cmd_status (Offset 110) SFP command and status <byte 11420> union sfp_data (Offset 114) SFP data <byte 11420> {field (By field)} <byte 11420> lbits:8 sfpd SFPD Transmit lbits:24 reserved Reserved {} or sfp_data (Offset 114) SFP data <byte 11420> ulong value As longword endunion sfp_data (Offset 114) SFP data <byte 11424> union fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 11424> {field (By field)} <byte 11424> lbits:1 tbe Transmit Link BIST error lbits:1 tlr Transmit Link BIST reset lbits:1 tle Transmit Link BIST enable lbits:1 rbe Receive Link BIST error lbits:1 rll Receive Link BIST loop-back lbits:1 rlr Receive Link BIST reset

lbits:1 rle Receive Link BIST enable lbits:7 reserved3 Reserved lbits:1 ipl ITR PPL Lock lbits:1 reserved2 Reserved lbits:1 dtf Disable transceiver LOS filter lbits:1 dtl Disable transceiver LOS lbits:1 dsr Disable iTR RXLOS lbits:1 ttd Transceiver Tx Disable lbits:2 reserved1 Reserved lbits:1 rfl Receive ast Lock Disable lbits:9 reserved Reserved {} or fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 11424> ulong value As longword endunion fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 11428> union fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 11428> {field (By field)} <byte 11428> lbits:32 reserved Reserved {} or fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 11428> ulong value As longword endunion fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 11432> {rsvd3b[0] ((Offset 120-13F) Reserved)} <byte 11432> ulong value {} <byte 11436> {rsvd3b[1] ((Offset 120-13F) Reserved)} <byte 11436> ulong value {} <byte 11440> {rsvd3b[2] ((Offset 120-13F) Reserved)} <byte 11440> ulong value {} <byte 11444> {rsvd3b[3] ((Offset 120-13F) Reserved)} <byte 11444> ulong value {} <byte 11448> {rsvd3b[4] ((Offset 120-13F) Reserved)} <byte 11448> ulong value {} <byte 11452> {rsvd3b[5] ((Offset 120-13F) Reserved)} <byte 11452> ulong value {} <byte 11456> {rsvd3b[6] ((Offset 120-13F) Reserved)} <byte 11456>

ulong value {} <byte 11460> {rsvd3b[7] ((Offset 120-13F) Reserved)} <byte 11460> ulong value {} <byte 11464> union sest_base (Offset 140) SEST Base (write only) <byte 11464> {field (By field)} <byte 11464> lbits:32 address SEST Base Address {} or sest_base (Offset 140) SEST Base (write only) <byte 11464> ulong value As longword endunion sest_base (Offset 140) SEST Base (write only) <byte 11468> union sest_len (Offset 144) SEST Length (write only) <byte 11468> {field (By field)} <byte 11468> lbits:16 length SEST Length lbits:16 reserved Reserved {} or sest_len (Offset 144) SEST Length (write only) <byte 11468> ulong value As longword endunion sest_len (Offset 144) SEST Length (write only) <byte 11472> {rsvd4 ((Offset 148) Reserved)} <byte 11472> ulong value {} <byte 11476> union scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 11476> {field (By field)} <byte 11476> lbits:16 tail Tail lbits:16 head Head {} or scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 11476> ulong value As longword endunion scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 11480> union prog_addr (Offset 150) Programmable Address register <byte 11480> {field (By field)} <byte 11480> lbits:20 ra ROM/RAM address lbits:11 reserved Reserved lbits:1 inc Increment {} or prog_addr (Offset 150) Programmable Address register <byte 11480> ulong value As longword endunion prog_addr (Offset 150) Programmable Address register

<byte 11484> union prog_data (Offset 154) programmable data register <byte 11484> {field (By field)} <byte 11484> lbits:32 pdr Programmable data {} or prog_data (Offset 154) programmable data register <byte 11484> ulong value As longword endunion prog_data (Offset 154) programmable data register <byte 11488> {rsvd5[0] ((Offset 158-15F) Reserved)} <byte 11488> ulong value {} <byte 11492> {rsvd5[1] ((Offset 158-15F) Reserved)} <byte 11492> ulong value {} <byte 11496> union int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 11496> {field (By field)} <byte 11496> lbits:32 address Interrupt Message Address {} or int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 11496> ulong value As longword endunion int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 11500> union int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 11500> {field (By field)} <byte 11500> lbits:32 value Interrupt Message Value {} or int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 11500> ulong value As longword endunion int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 11504> union sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 11504> {field (By field)} <byte 11504> lbits:8 length SGL Page Length lbits:24 reserved Reserved {} or sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 11504> ulong value As longword endunion sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 11508> union my_id (Offset 16C) My ID <byte 11508> {field (By field)} <byte 11508>

lbits:24 id My ID lbits:8 reserved Reserved {} or my_id (Offset 16C) My ID <byte 11508> ulong value As longword endunion my_id (Offset 16C) My ID <byte 11512> union gpio (Offset 170) General Purpose I/O <byte 11512> {field (By field)} <byte 11512> lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:1 gc5 General Purpose Control 5 lbits:1 gc6 General Purpose Control 6 lbits:1 gc7 General Purpose Control 7 lbits:8 reserved Reserved lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose I/O 4 lbits:1 gp5 General Purpose I/O 5 lbits:1 gp6 General Purpose I/O 6 lbits:1 gp7 General Purpose I/O 7 lbits:8 reserved1 Reserved {} or gpio (Offset 170) General Purpose I/O <byte 11512> ulong value As longword endunion gpio (Offset 170) General Purpose I/O <byte 11516> {rsvd6a ((Offset 174-177) Reserved)} <byte 11516> ulong value {} <byte 11520> union edc_config (Offset 178) EDC Configuration Register <byte 11520> {field (By field)} <byte 11520> lbits:16 io_seed Starting Seed lbits:16 reserved Reserved {} or edc_config (Offset 178) EDC Configuration Register <byte 11520> ulong value As longword endunion edc_config (Offset 178) EDC Configuration Register <byte 11524> union dx4_config3 (Offset 17C) DX4 Configuration Register 3 <byte 11524> {field (By field)} <byte 11524> lbits:9 pfs2 Programmable Frame size field 2 lbits:9 pfs3 Programmable Frame size field 3 lbits:9 pfs4 Programmable Frame size field 4

lbits:5 reserved Reserved {} or dx4_config3 (Offset 17C) DX4 Configuration Register 3 <byte 11524> ulong value As longword endunion dx4_config3 (Offset 17C) DX4 Configuration Register 3 <byte 11528> union tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 11528> {field (By field)} <byte 11528> lbits:9 pfs Programmable Frame Size lbits:15 reserved Reserved lbits:8 esi_range Exchange_ID Signaled Interrupt Range {} or tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 11528> ulong value As longword endunion tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 11532> union tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 11532> {field (By field)} <byte 11532> lbits:1 fad FCP Assist Disable lbits:1 ino In Order lbits:1 dof Discard OOO FCP Frames lbits:1 fua FCP Unassisted ACK Enable lbits:1 ime Interrupt Message Enable lbits:1 fab Fabric lbits:1 sic S_ID Copy Enable lbits:1 eqs Equal Service lbits:2 reserved Reserved lbits:1 aks Automatic ACK lbits:1 ddf Disable Delayed Freeze lbits:1 ebe Enable Big Endian Mode lbits:11 reserved1 Reserved lbits:1 fc2 FCP Class 2 Reassembly Enable lbits:1 reserved2 Reserved lbits:1 sdf Save Discarded Frames lbits:1 rde Response Detect Enable lbits:1 dam Default ACK Model lbits:2 reserved3 Reserved lbits:1 m66 66 MHz Enabled {} or tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 11532> ulong value As longword endunion tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 11536> union tach_control (Offset 188) Tachyon DX2+ Control <byte 11536> {field (By field)} <byte 11536> lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:3 reserved Reserved

lbits:1 feq Freeze ERQ lbits:1 ffa Freeze FCP Assists lbits:2 reserved1 Reserved lbits:1 fis Freeze Inbound FCP Assists When Frame Placed in SFQ lbits:1 fib Freeze Inbound FCP Assists lbits:2 reserved2 Reserved lbits:1 req Resume ERQ lbits:1 rif Resume Inbound FCP Assists lbits:1 rof Resume Outbound FCP Assists lbits:12 reserved3 Reserved lbits:1 crs Core Reset {} or tach_control (Offset 188) Tachyon DX2+ Control <byte 11536> ulong value As longword endunion tach_control (Offset 188) Tachyon DX2+ Control <byte 11540> union tach_status (Offset 18C) Tachyon DX2+ Status <byte 11540> {field (By field)} <byte 11540> lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose Input 4 lbits:5 reserved Reserved lbits:1 ipe Inbound Parity Error lbits:1 ope Outbound Parity Error lbits:4 reserved1 Reserved lbits:1 eqf ERQ Frozen lbits:1 iff Inbound FCP Assists Frozen lbits:1 off Outbound FCP Assists Frozen lbits:4 reserved2 Reserved lbits:1 ifce Inbound FIFO CRC Error lbits:1 ofce Outbound FIFO CRC Error lbits:1 m66 66 Mhz Enabled lbits:1 ile Inbound Link Control FIFO Empty lbits:1 ole Outbound Link Control List Empty lbits:1 ife Inbound FIFO Empty lbits:1 ofe Outbound FIFO Empty lbits:1 imf IMQ Full lbits:1 ssf SFQ Full {} or tach_status (Offset 18C) Tachyon DX2+ Status <byte 11540> ulong value As longword endunion tach_status (Offset 18C) Tachyon DX2+ Status <byte 11544> {rsvd7 ((Offset 190) Reserved)} <byte 11544> ulong value {} <byte 11548> union hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 11548> {field (By field)} <byte 11548> lbits:12 length Frame Length lbits:7 reserved Reserved

lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 11548> ulong value As longword endunion hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 11552> union hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 11552> {field (By field)} <byte 11552> lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 11552> ulong value As longword endunion hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 11556> union inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 11556> {field (By field)} <byte 11556> lbits:24 reserved Reserved lbits:8 sest_lru_count SEST LRU Count {} or inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 11556> ulong value As longword endunion inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 11560> union inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 11560> {field (By field)} <byte 11560> lbits:8 discd_frames Discarded Frame Count lbits:24 reserved Reserved {} or inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 11560> ulong value As longword endunion inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 11564> union ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) <byte 11564> {field (By field)} <byte 11564> lbits:28 threshold EE_Credit Zero Timer Threshold lbits:4 reserved Reserved {} or ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) <byte 11564> ulong value As longword endunion ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only ) <byte 11568> union up_data_addr (Offset 1A8) Upper Data Address (write only)

<byte 11568> {field (By field)} <byte 11568> lbits:12 reserved Reserved lbits:1 upper_addr1 Upper Data Address--44 bit data space lbits:19 upper_addr Upper Data Address {} or up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 11568> ulong value As longword endunion up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 11572> union up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 11572> {field (By field)} <byte 11572> lbits:32 upper_addr Upper Control Address {} or up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 11572> ulong value As longword endunion up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 11576> union dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 11576> {field (By field)} <byte 11576> lbits:1 ef AL_PA 0xEF DHD Login Information lbits:1 e8 AL_PA 0xE8 DHD Login Information lbits:1 e4 AL_PA 0xE4 DHD Login Information lbits:1 e2 AL_PA 0xE2 DHD Login Information lbits:1 e1 AL_PA 0xE1 DHD Login Information lbits:1 e0 AL_PA 0xE0 DHD Login Information lbits:1 dc AL_PA 0xDC DHD Login Information lbits:1 da AL_PA 0xDA DHD Login Information lbits:1 d9 AL_PA 0xD9 DHD Login Information lbits:1 d6 AL_PA 0xD6 DHD Login Information lbits:1 d5 AL_PA 0xD5 DHD Login Information lbits:1 d4 AL_PA 0xD4 DHD Login Information lbits:1 d3 AL_PA 0xD3 DHD Login Information lbits:1 d2 AL_PA 0xD2 DHD Login Information lbits:1 d1 AL_PA 0xD1 DHD Login Information lbits:1 ce AL_PA 0xCE DHD Login Information lbits:1 cd AL_PA 0xCD DHD Login Information lbits:1 cc AL_PA 0xCC DHD Login Information lbits:1 cb AL_PA 0xCB DHD Login Information lbits:1 ca AL_PA 0xCA DHD Login Information lbits:1 c9 AL_PA 0xC9 DHD Login Information lbits:1 c7 AL_PA 0xC7 DHD Login Information lbits:1 c6 AL_PA 0xC6 DHD Login Information lbits:1 c5 AL_PA 0xC5 DHD Login Information lbits:1 c3 AL_PA 0xC3 DHD Login Information lbits:1 bc AL_PA 0xBC DHD Login Information lbits:1 ba AL_PA 0xBA DHD Login Information lbits:1 b9 AL_PA 0xB9 DHD Login Information lbits:1 b6 AL_PA 0xB6 DHD Login Information lbits:1 b5 AL_PA 0xB5 DHD Login Information lbits:1 b4 AL_PA 0xB4 DHD Login Information lbits:1 b3 AL_PA 0xB3 DHD Login Information {}

or dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 11576> ulong value As longword endunion dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 11580> union dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 11580> {field (By field)} <byte 11580> lbits:1 alpab2 AL_PA 0xB2 DHD Login Information lbits:1 alpab1 AL_PA 0xB1 DHD Login Information lbits:1 alpaae AL_PA 0xAE DHD Login Information lbits:1 alpaad AL_PA 0xAD DHD Login Information lbits:1 alpaac AL_PA 0xAC DHD Login Information lbits:1 alpaab AL_PA 0xAB DHD Login Information lbits:1 alpaaa AL_PA 0xAA DHD Login Information lbits:1 alpaa9 AL_PA 0xA9 DHD Login Information lbits:1 alpaa7 AL_PA 0xA7 DHD Login Information lbits:1 alpaa6 AL_PA 0xA6 DHD Login Information lbits:1 alpaa5 AL_PA 0xA5 DHD Login Information lbits:1 alpaa3 AL_PA 0xA3 DHD Login Information lbits:1 alpa9f AL_PA 0x9F DHD Login Information lbits:1 alpa9e AL_PA 0x9E DHD Login Information lbits:1 alpa9d AL_PA 0x9D DHD Login Information lbits:1 alpa9b AL_PA 0x9B DHD Login Information lbits:1 alpa98 AL_PA 0x98 DHD Login Information lbits:1 alpa97 AL_PA 0x97 DHD Login Information lbits:1 alpa90 AL_PA 0x90 DHD Login Information lbits:1 alpa8f AL_PA 0x8F DHD Login Information lbits:1 alpa88 AL_PA 0x88 DHD Login Information lbits:1 alpa84 AL_PA 0x84 DHD Login Information lbits:1 alpa82 AL_PA 0x82 DHD Login Information lbits:1 alpa81 AL_PA 0x81 DHD Login Information lbits:1 alpa80 AL_PA 0x80 DHD Login Information lbits:1 alpa7c AL_PA 0x7C DHD Login Information lbits:1 alpa7a AL_PA 0x7A DHD Login Information lbits:1 alpa79 AL_PA 0x79 DHD Login Information lbits:1 alpa76 AL_PA 0x76 DHD Login Information lbits:1 alpa75 AL_PA 0x75 DHD Login Information lbits:1 alpa74 AL_PA 0x74 DHD Login Information lbits:1 alpa73 AL_PA 0x73 DHD Login Information {} or dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 11580> ulong value As longword endunion dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 11584> union dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 11584> {field (By field)} <byte 11584> lbits:1 alpa72 AL_PA 0x72 DHD Login Information lbits:1 alpa71 AL_PA 0x71 DHD Login Information lbits:1 alpa6e AL_PA 0x6E DHD Login Information lbits:1 alpa6d AL_PA 0x6D DHD Login Information lbits:1 alpa6c AL_PA 0x6C DHD Login Information lbits:1 alpa6b AL_PA 0x6B DHD Login Information lbits:1 alpa6a AL_PA 0x6A DHD Login Information lbits:1 alpa69 AL_PA 0x69 DHD Login Information lbits:1 alpa67 AL_PA 0x67 DHD Login Information

lbits:1 alpa66 AL_PA 0x66 DHD Login Information lbits:1 alpa65 AL_PA 0x65 DHD Login Information lbits:1 alpa63 AL_PA 0x63 DHD Login Information lbits:1 alpa5c AL_PA 0x5C DHD Login Information lbits:1 alpa5a AL_PA 0x5A DHD Login Information lbits:1 alpa59 AL_PA 0x59 DHD Login Information lbits:1 alpa56 AL_PA 0x56 DHD Login Information lbits:1 alpa55 AL_PA 0x55 DHD Login Information lbits:1 alpa54 AL_PA 0x54 DHD Login Information lbits:1 alpa53 AL_PA 0x53 DHD Login Information lbits:1 alpa52 AL_PA 0x52 DHD Login Information lbits:1 alpa51 AL_PA 0x51 DHD Login Information lbits:1 alpa4e AL_PA 0x4E DHD Login Information lbits:1 alpa4d AL_PA 0x4D DHD Login Information lbits:1 alpa4c AL_PA 0x4C DHD Login Information lbits:1 alpa4b AL_PA 0x4B DHD Login Information lbits:1 alpa4a AL_PA 0x4A DHD Login Information lbits:1 alpa49 AL_PA 0x49 DHD Login Information lbits:1 alpa47 AL_PA 0x47 DHD Login Information lbits:1 alpa46 AL_PA 0x46 DHD Login Information lbits:1 alpa45 AL_PA 0x45 DHD Login Information lbits:1 alpa43 AL_PA 0x43 DHD Login Information lbits:1 alpa3c AL_PA 0x3C DHD Login Information {} or dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 11584> ulong value As longword endunion dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 11588> union dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 11588> {field (By field)} <byte 11588> lbits:1 alpa3a AL_PA 0x3A DHD Login Information lbits:1 alpa39 AL_PA 0x39 DHD Login Information lbits:1 alpa36 AL_PA 0x36 DHD Login Information lbits:1 alpa35 AL_PA 0x35 DHD Login Information lbits:1 alpa34 AL_PA 0x34 DHD Login Information lbits:1 alpa33 AL_PA 0x33 DHD Login Information lbits:1 alpa32 AL_PA 0x32 DHD Login Information lbits:1 alpa31 AL_PA 0x31 DHD Login Information lbits:1 alpa2e AL_PA 0x2E DHD Login Information lbits:1 alpa2d AL_PA 0x2D DHD Login Information lbits:1 alpa2c AL_PA 0x2C DHD Login Information lbits:1 alpa2b AL_PA 0x2B DHD Login Information lbits:1 alpa2a AL_PA 0x2A DHD Login Information lbits:1 alpa29 AL_PA 0x29 DHD Login Information lbits:1 alpa27 AL_PA 0x27 DHD Login Information lbits:1 alpa26 AL_PA 0x26 DHD Login Information lbits:1 alpa25 AL_PA 0x25 DHD Login Information lbits:1 alpa23 AL_PA 0x23 DHD Login Information lbits:1 alpa1f AL_PA 0x1F DHD Login Information lbits:1 alpa1e AL_PA 0x1E DHD Login Information lbits:1 alpa1d AL_PA 0x1D DHD Login Information lbits:1 alpa1b AL_PA 0x1B DHD Login Information lbits:1 alpa18 AL_PA 0x18 DHD Login Information lbits:1 alpa17 AL_PA 0x17 DHD Login Information lbits:1 alpa10 AL_PA 0x10 DHD Login Information lbits:1 alpa0f AL_PA 0x0F DHD Login Information lbits:1 alpa08 AL_PA 0x08 DHD Login Information

lbits:1 alpa04 AL_PA 0x04 DHD Login Information lbits:1 alpa02 AL_PA 0x02 DHD Login Information lbits:1 alpa01 AL_PA 0x01 DHD Login Information lbits:1 alpa00 AL_PA 0x00 DHD Login Information lbits:1 reserved Reserved {} or dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 11588> ulong value As longword endunion dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 11592> union fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 11592> {field (By field)} <byte 11592> lbits:1 bli Bypass Loop Initialization lbits:1 reserved Reserved lbits:1 enp Enable N_Port Mode lbits:1 lr Login Required lbits:1 inif Initialize as Fabric lbits:1 rf Respond to Fabric Address lbits:1 blm Bypass Loop Map lbits:1 sa Acquire Soft Address lbits:1 ha Acquire Hard Address lbits:1 aq Acquire Previously Acquired Address lbits:1 fa Acquire Fabric Aquired Address lbits:1 td Timer Disable lbits:1 sap Skip Arbitration Phase lbits:1 elb External Loopback/Pad Loopback lbits:1 ilb Internal loopback lbits:1 npi Initialize as N_Port lbits:8 bb_credit BB_Credit lbits:8 al_pa Desired AL_PA {} or fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 11592> ulong value As longword endunion fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 11596> union fm_control (Offset 1C4) Frame Manager Control <byte 11596> {field (By field)} <byte 11596> lbits:3 cmd State Machine Command lbits:1 cl Close Loop Request lbits:1 reserved Reserved lbits:1 sp Send Prim_Reg lbits:1 sq Primitive Sequence lbits:25 reserved1 Reserved {} or fm_control (Offset 1C4) Frame Manager Control <byte 11596> ulong value As longword endunion fm_control (Offset 1C4) Frame Manager Control <byte 11600> union fm_status (Offset 1C8) Frame Manager Status <byte 11600> {field (By field)} <byte 11600> lbits:4 psm Port State Machine

lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_status (Offset 1C8) Frame Manager Status <byte 11600> ulong value As longword endunion fm_status (Offset 1C8) Frame Manager Status <byte 11604> union fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 11604> {field (By field)} <byte 11604> lbits:16 ed_tov Error Detect Time-Out lbits:9 rt_tov Receiver Transmitter Time-Out lbits:7 reserved Reserved {} or fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 11604> ulong value As longword endunion fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 11608> union fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 11608> {field (By field)} <byte 11608> lbits:8 link_fail Link Fail Count lbits:8 loss_of_sync Loss of Synchronization Count lbits:8 bad_rx_char Bad Received Character Count lbits:8 loss_of_signal Loss of Signal Count {} or fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 11608> ulong value As longword endunion fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 11612> union fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 11612>

{field (By field)} <byte 11612> lbits:8 proto_er Protocol Error Count lbits:8 bad_crc Bad CRC Count lbits:8 dis_frm Discarded Frames lbits:8 rx_eofa Received EOFa {} or fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 11612> ulong value As longword endunion fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 11616> union fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 11616> {field (By field)} <byte 11616> lbits:9 al_time Arbitrated Loop Time-Out lbits:7 reserved Reserved lbits:16 lp_tov Loop Time-Out {} or fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 11616> ulong value As longword endunion fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 11620> union fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 11620> {field (By field)} <byte 11620> lbits:24 bb0_timer BB_Credit Timer lbits:8 reserved Reserved {} or fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 11620> ulong value As longword endunion fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 11624> union fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 11624> {field (By field)} <byte 11624> lbits:32 wwn World Wide Name {} or fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 11624> ulong value As longword endunion fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 11628> union fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 11628> {field (By field)} <byte 11628> lbits:32 wwn World Wide Name {} or fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 11628> ulong value As longword endunion fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 11632> union fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA

<byte 11632> {field (By field)} <byte 11632> lbits:8 lipf_alpa AL_PA of Most Recent LIPf Received lbits:8 bad_alpa AL_PA of Most Recent OPN Sent and Returned Without Being Accept ed lbits:8 acq_alpa AL_PA Acquired During Loop Initialization lbits:8 reserved Reserved {} or fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 11632> ulong value As longword endunion fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 11636> union fm_primitive (Offset 1EC) Frame Manager Primitive <byte 11636> {field (By field)} <byte 11636> lbits:24 prim_value Primitive to be Sent lbits:8 reserved Reserved {} or fm_primitive (Offset 1EC) Frame Manager Primitive <byte 11636> ulong value As longword endunion fm_primitive (Offset 1EC) Frame Manager Primitive <byte 11640> union fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 11640> {field (By field)} <byte 11640> lbits:8 exp_frm Expired Frames lbits:24 reserved Reserved {} or fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 11640> ulong value As longword endunion fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 11644> union fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 11644> {field (By field)} <byte 11644> lbits:1 dac Disable Auto Close lbits:2 nbc Non-zero Login BB_Credit lbits:1 eei Enable ERR_INIT lbits:1 icb Ignore Close Bit lbits:2 atv Arbitration Threshold Value lbits:1 gde Garbage Deletion Enable lbits:8 laa Lowest Allowable AL_PA lbits:5 reserved Reserved lbits:1 dao Disable 2xAL_TIME Timeout on Open lbits:3 reserved1 Reserved lbits:1 prm Promiscuous Mode lbits:1 wpe Wait For Port Enable lbits:1 fmh Force Monitor State With Hard Address lbits:1 fmn Force Monitor Non-participating State lbits:1 dlm Disable Loop Master lbits:1 dsa Disable Soft Address Selection lbits:1 ilp Ignore LPB/LPE Primitive Sequences {}

or fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 11644> ulong value As longword endunion fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 11648> union pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED <byte 11648> {field (By field)} <byte 11648> {pci_rsvd1F8 ((Offset 1F8) Reserved)} <byte 11648> utiny value {} <byte 11649> {pci_rsvd1F9 ((Offset 1F9) Reserved)} <byte 11649> utiny value {} <byte 11650> union romctr (Offset 1FA) PCI ROM Control <byte 11650> {field (By field)} <byte 11650> tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or romctr (Offset 1FA) PCI ROM Control <byte 11650> utiny value As byte endunion romctr (Offset 1FA) PCI ROM Control <byte 11651> union mctr (Offset 1FB) PCI Master Control <byte 11651> {field (By field)} <byte 11651> tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or mctr (Offset 1FB) PCI Master Control <byte 11651> utiny value As byte endunion mctr (Offset 1FB) PCI Master Control {} or pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED <byte 11648> ulong value As longword endunion pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED <byte 11652> union pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST <byte 11652> {field (By field)} <byte 11652> union softrst (Offset 1FC) PCI Interface Reset Control <byte 11652> {field (By field)} <byte 11652>

tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or softrst (Offset 1FC) PCI Interface Reset Control <byte 11652> utiny value As byte endunion softrst (Offset 1FC) PCI Interface Reset Control <byte 11653> union intpend (Offset 1FD) PCI Interrupt Pending <byte 11653> {field (By field)} <byte 11653> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intpend (Offset 1FD) PCI Interrupt Pending <byte 11653> utiny value As byte endunion intpend (Offset 1FD) PCI Interrupt Pending <byte 11654> union inten (Offset 1FE) PCI Interrupt Enable <byte 11654> {field (By field)} <byte 11654> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or inten (Offset 1FE) PCI Interrupt Enable <byte 11654> utiny value As byte endunion inten (Offset 1FE) PCI Interrupt Enable <byte 11655> union intstat (Offset 1FF) PCI Interrupt Status <byte 11655> {field (By field)} <byte 11655> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intstat (Offset 1FF) PCI Interrupt Status <byte 11655> utiny value As byte endunion intstat (Offset 1FF) PCI Interrupt Status {} or pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST <byte 11652> ulong value As longword endunion pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST

{} endunion csr[9] Tachyon DX2+ CSR Registers <byte 11656> union csr[10] Tachyon DX2+ CSR Registers <byte 11656> ulong[128] csra Tachyon DX2+ CSR Registers As Longwords or csr[10] Tachyon DX2+ CSR Registers <byte 11656> {csr (Tachyon DX2+ CSR Registers By Field)} <byte 11656> union erq_base (Offset 000) ERQ Base (write only) <byte 11656> {field (By field)} <byte 11656> lbits:32 address ERQ Base Address {} or erq_base (Offset 000) ERQ Base (write only) <byte 11656> ulong value As longword endunion erq_base (Offset 000) ERQ Base (write only) <byte 11660> union erq_len (Offset 004) ERQ Length (write only) <byte 11660> {field (By field)} <byte 11660> lbits:12 length ERQ Length lbits:20 reserved Reserved {} or erq_len (Offset 004) ERQ Length (write only) <byte 11660> ulong value As longword endunion erq_len (Offset 004) ERQ Length (write only) <byte 11664> union erq_prod (Offset 008) ERQ Producer Index <byte 11664> {field (By field)} <byte 11664> lbits:12 index ERQ Producer Index lbits:20 reserved Reserved {} or erq_prod (Offset 008) ERQ Producer Index <byte 11664> ulong value As longword endunion erq_prod (Offset 008) ERQ Producer Index <byte 11668> union erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 11668> {field (By field)} <byte 11668> lbits:32 address ERQ Consumer Index Address {} or erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 11668> ulong value As longword endunion erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 11672> union erq_cons (Offset 010) ERQ Consumer Index <byte 11672> {field (By field)} <byte 11672>

lbits:12 index ERQ Consumer Index lbits:20 reserved Reserved {} or erq_cons (Offset 010) ERQ Consumer Index <byte 11672> ulong value As longword endunion erq_cons (Offset 010) ERQ Consumer Index <byte 11676> {rsvd1[0] ((Offset 014-04F) Reserved)} <byte 11676> ulong value {} <byte 11680> {rsvd1[1] ((Offset 014-04F) Reserved)} <byte 11680> ulong value {} <byte 11684> {rsvd1[2] ((Offset 014-04F) Reserved)} <byte 11684> ulong value {} <byte 11688> {rsvd1[3] ((Offset 014-04F) Reserved)} <byte 11688> ulong value {} <byte 11692> {rsvd1[4] ((Offset 014-04F) Reserved)} <byte 11692> ulong value {} <byte 11696> {rsvd1[5] ((Offset 014-04F) Reserved)} <byte 11696> ulong value {} <byte 11700> {rsvd1[6] ((Offset 014-04F) Reserved)} <byte 11700> ulong value {} <byte 11704> {rsvd1[7] ((Offset 014-04F) Reserved)} <byte 11704> ulong value {} <byte 11708> {rsvd1[8] ((Offset 014-04F) Reserved)} <byte 11708> ulong value {} <byte 11712> {rsvd1[9] ((Offset 014-04F) Reserved)} <byte 11712> ulong value {} <byte 11716> {rsvd1[10] ((Offset 014-04F) Reserved)} <byte 11716>

ulong value {} <byte 11720> {rsvd1[11] ((Offset 014-04F) Reserved)} <byte 11720> ulong value {} <byte 11724> {rsvd1[12] ((Offset 014-04F) Reserved)} <byte 11724> ulong value {} <byte 11728> {rsvd1[13] ((Offset 014-04F) Reserved)} <byte 11728> ulong value {} <byte 11732> {rsvd1[14] ((Offset 014-04F) Reserved)} <byte 11732> ulong value {} <byte 11736> union sfq_base (Offset 050) SFQ Base (write only) <byte 11736> {field (By field)} <byte 11736> lbits:32 address SFQ Base Address {} or sfq_base (Offset 050) SFQ Base (write only) <byte 11736> ulong value As longword endunion sfq_base (Offset 050) SFQ Base (write only) <byte 11740> union sfq_len (Offset 054) SFQ Length (write only) <byte 11740> {field (By field)} <byte 11740> lbits:12 length SFQ Length lbits:20 reserved Reserved {} or sfq_len (Offset 054) SFQ Length (write only) <byte 11740> ulong value As longword endunion sfq_len (Offset 054) SFQ Length (write only) <byte 11744> union sfq_cons (Offset 058) SFQ Consumer Index <byte 11744> {field (By field)} <byte 11744> lbits:12 index SFQ Consumer Index lbits:20 reserved Reserved {} or sfq_cons (Offset 058) SFQ Consumer Index <byte 11744> ulong value As longword endunion sfq_cons (Offset 058) SFQ Consumer Index <byte 11748> {rsvd2[0] ((Offset 05C-07B) Reserved)} <byte 11748>

ulong value {} <byte 11752> {rsvd2[1] ((Offset 05C-07B) Reserved)} <byte 11752> ulong value {} <byte 11756> {rsvd2[2] ((Offset 05C-07B) Reserved)} <byte 11756> ulong value {} <byte 11760> {rsvd2[3] ((Offset 05C-07B) Reserved)} <byte 11760> ulong value {} <byte 11764> {rsvd2[4] ((Offset 05C-07B) Reserved)} <byte 11764> ulong value {} <byte 11768> {rsvd2[5] ((Offset 05C-07B) Reserved)} <byte 11768> ulong value {} <byte 11772> {rsvd2[6] ((Offset 05C-07B) Reserved)} <byte 11772> ulong value {} <byte 11776> {rsvd2[7] ((Offset 05C-07B) Reserved)} <byte 11776> ulong value {} <byte 11780> union int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 11780> {field (By field)} <byte 11780> lbits:4 timer Interrupt Timer Value lbits:3 reserved Reserved lbits:1 ihf Interrupt when IMQ Half Full lbits:24 reserved1 Reserved {} or int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 11780> ulong value As longword endunion int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 11784> union imq_base (Offset 080) IMQ Base (write only) <byte 11784> {field (By field)} <byte 11784> lbits:32 address IMQ Base Address {} or imq_base (Offset 080) IMQ Base (write only) <byte 11784>

ulong value As longword endunion imq_base (Offset 080) IMQ Base (write only) <byte 11788> union imq_len (Offset 084) IMQ Length (write only) <byte 11788> {field (By field)} <byte 11788> lbits:12 length IMQ Length lbits:20 reserved Reserved {} or imq_len (Offset 084) IMQ Length (write only) <byte 11788> ulong value As longword endunion imq_len (Offset 084) IMQ Length (write only) <byte 11792> union imq_cons (Offset 088) IMQ Consumer Index <byte 11792> {field (By field)} <byte 11792> lbits:12 index IMQ Consumer Index lbits:20 reserved Reserved {} or imq_cons (Offset 088) IMQ Consumer Index <byte 11792> ulong value As longword endunion imq_cons (Offset 088) IMQ Consumer Index <byte 11796> union imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 11796> {field (By field)} <byte 11796> lbits:32 address IMQ Producer Index Address {} or imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 11796> ulong value As longword endunion imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 11800> {rsvd3[0] ((Offset 090-0FC) Reserved)} <byte 11800> ulong value {} <byte 11804> {rsvd3[1] ((Offset 090-0FC) Reserved)} <byte 11804> ulong value {} <byte 11808> {rsvd3[2] ((Offset 090-0FC) Reserved)} <byte 11808> ulong value {} <byte 11812> {rsvd3[3] ((Offset 090-0FC) Reserved)} <byte 11812> ulong value {} <byte 11816> {rsvd3[4] ((Offset 090-0FC) Reserved)} <byte 11816>

ulong value {} <byte 11820> {rsvd3[5] ((Offset 090-0FC) Reserved)} <byte 11820> ulong value {} <byte 11824> {rsvd3[6] ((Offset 090-0FC) Reserved)} <byte 11824> ulong value {} <byte 11828> {rsvd3[7] ((Offset 090-0FC) Reserved)} <byte 11828> ulong value {} <byte 11832> {rsvd3[8] ((Offset 090-0FC) Reserved)} <byte 11832> ulong value {} <byte 11836> {rsvd3[9] ((Offset 090-0FC) Reserved)} <byte 11836> ulong value {} <byte 11840> {rsvd3[10] ((Offset 090-0FC) Reserved)} <byte 11840> ulong value {} <byte 11844> {rsvd3[11] ((Offset 090-0FC) Reserved)} <byte 11844> ulong value {} <byte 11848> {rsvd3[12] ((Offset 090-0FC) Reserved)} <byte 11848> ulong value {} <byte 11852> {rsvd3[13] ((Offset 090-0FC) Reserved)} <byte 11852> ulong value {} <byte 11856> {rsvd3[14] ((Offset 090-0FC) Reserved)} <byte 11856> ulong value {} <byte 11860> {rsvd3[15] ((Offset 090-0FC) Reserved)} <byte 11860> ulong value {} <byte 11864> {rsvd3[16] ((Offset 090-0FC) Reserved)} <byte 11864>

ulong value {} <byte 11868> {rsvd3[17] ((Offset 090-0FC) Reserved)} <byte 11868> ulong value {} <byte 11872> {rsvd3[18] ((Offset 090-0FC) Reserved)} <byte 11872> ulong value {} <byte 11876> {rsvd3[19] ((Offset 090-0FC) Reserved)} <byte 11876> ulong value {} <byte 11880> {rsvd3[20] ((Offset 090-0FC) Reserved)} <byte 11880> ulong value {} <byte 11884> {rsvd3[21] ((Offset 090-0FC) Reserved)} <byte 11884> ulong value {} <byte 11888> {rsvd3[22] ((Offset 090-0FC) Reserved)} <byte 11888> ulong value {} <byte 11892> {rsvd3[23] ((Offset 090-0FC) Reserved)} <byte 11892> ulong value {} <byte 11896> {rsvd3[24] ((Offset 090-0FC) Reserved)} <byte 11896> ulong value {} <byte 11900> {rsvd3[25] ((Offset 090-0FC) Reserved)} <byte 11900> ulong value {} <byte 11904> {rsvd3[26] ((Offset 090-0FC) Reserved)} <byte 11904> ulong value {} <byte 11908> {rsvd3[27] ((Offset 090-0FC) Reserved)} <byte 11908> ulong value {} <byte 11912> union fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 11912>

{field (By field)} <byte 11912> lbits:6 bec Termination Receive lbits:3 reserved4 Reserved lbits:1 xrb Wrapback lbits:2 reserved Reserved lbits:3 xem Output pre-emphasis lbits:4 reserved1 Reserved lbits:1 mustbe1 Must be 1 lbits:1 stb Start BERT lbits:1 enb Enable BERT lbits:2 sdm Signal differential mode lbits:2 rxs Receiver Speed lbits:2 txs Transmitter Speed lbits:1 reserved3 Reserved lbits:1 xlr Force iTR to lock reference clock lbits:1 reserved0 Reserved lbits:1 xcv Type of Transceiver {} or fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 11912> ulong value As longword endunion fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 11916> union fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 11916> {field (By field)} <byte 11916> lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 11916> ulong value As longword endunion fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 11920>

{rsvd3a[0] ((Offset 108-10f) Reserved)} <byte 11920> ulong value {} <byte 11924> {rsvd3a[1] ((Offset 108-10f) Reserved)} <byte 11924> ulong value {} <byte 11928> union sfp_cmd_status (Offset 110) SFP command and status <byte 11928> {field (No description available)} <byte 11928> lbits:1 gna Generate NACK lbits:1 rts Reset Slave lbits:1 wrc Write command lbits:1 rdc Read command lbits:1 gst Generate Stop lbits:1 sta Generate Start lbits:2 reserved1 Reserved lbits:1 rna Received NACK lbits:1 sby SFP Busy lbits:1 tip Transfer in progress lbits:9 reserved Reserved lbits:12 lp Clock Divisor {} or sfp_cmd_status (Offset 110) SFP command and status <byte 11928> ulong value endunion sfp_cmd_status (Offset 110) SFP command and status <byte 11932> union sfp_data (Offset 114) SFP data <byte 11932> {field (By field)} <byte 11932> lbits:8 sfpd SFPD Transmit lbits:24 reserved Reserved {} or sfp_data (Offset 114) SFP data <byte 11932> ulong value As longword endunion sfp_data (Offset 114) SFP data <byte 11936> union fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 11936> {field (By field)} <byte 11936> lbits:1 tbe Transmit Link BIST error lbits:1 tlr Transmit Link BIST reset lbits:1 tle Transmit Link BIST enable lbits:1 rbe Receive Link BIST error lbits:1 rll Receive Link BIST loop-back lbits:1 rlr Receive Link BIST reset lbits:1 rle Receive Link BIST enable lbits:7 reserved3 Reserved lbits:1 ipl ITR PPL Lock lbits:1 reserved2 Reserved lbits:1 dtf Disable transceiver LOS filter lbits:1 dtl Disable transceiver LOS

lbits:1 dsr Disable iTR RXLOS lbits:1 ttd Transceiver Tx Disable lbits:2 reserved1 Reserved lbits:1 rfl Receive ast Lock Disable lbits:9 reserved Reserved {} or fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 11936> ulong value As longword endunion fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 11940> union fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 11940> {field (By field)} <byte 11940> lbits:32 reserved Reserved {} or fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 11940> ulong value As longword endunion fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 11944> {rsvd3b[0] ((Offset 120-13F) Reserved)} <byte 11944> ulong value {} <byte 11948> {rsvd3b[1] ((Offset 120-13F) Reserved)} <byte 11948> ulong value {} <byte 11952> {rsvd3b[2] ((Offset 120-13F) Reserved)} <byte 11952> ulong value {} <byte 11956> {rsvd3b[3] ((Offset 120-13F) Reserved)} <byte 11956> ulong value {} <byte 11960> {rsvd3b[4] ((Offset 120-13F) Reserved)} <byte 11960> ulong value {} <byte 11964> {rsvd3b[5] ((Offset 120-13F) Reserved)} <byte 11964> ulong value {} <byte 11968> {rsvd3b[6] ((Offset 120-13F) Reserved)} <byte 11968> ulong value {} <byte 11972> {rsvd3b[7] ((Offset 120-13F) Reserved)} <byte 11972> ulong value

{} <byte 11976> union sest_base (Offset 140) SEST Base (write only) <byte 11976> {field (By field)} <byte 11976> lbits:32 address SEST Base Address {} or sest_base (Offset 140) SEST Base (write only) <byte 11976> ulong value As longword endunion sest_base (Offset 140) SEST Base (write only) <byte 11980> union sest_len (Offset 144) SEST Length (write only) <byte 11980> {field (By field)} <byte 11980> lbits:16 length SEST Length lbits:16 reserved Reserved {} or sest_len (Offset 144) SEST Length (write only) <byte 11980> ulong value As longword endunion sest_len (Offset 144) SEST Length (write only) <byte 11984> {rsvd4 ((Offset 148) Reserved)} <byte 11984> ulong value {} <byte 11988> union scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 11988> {field (By field)} <byte 11988> lbits:16 tail Tail lbits:16 head Head {} or scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 11988> ulong value As longword endunion scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 11992> union prog_addr (Offset 150) Programmable Address register <byte 11992> {field (By field)} <byte 11992> lbits:20 ra ROM/RAM address lbits:11 reserved Reserved lbits:1 inc Increment {} or prog_addr (Offset 150) Programmable Address register <byte 11992> ulong value As longword endunion prog_addr (Offset 150) Programmable Address register <byte 11996> union prog_data (Offset 154) programmable data register <byte 11996> {field (By field)} <byte 11996> lbits:32 pdr Programmable data

{} or prog_data (Offset 154) programmable data register <byte 11996> ulong value As longword endunion prog_data (Offset 154) programmable data register <byte 12000> {rsvd5[0] ((Offset 158-15F) Reserved)} <byte 12000> ulong value {} <byte 12004> {rsvd5[1] ((Offset 158-15F) Reserved)} <byte 12004> ulong value {} <byte 12008> union int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 12008> {field (By field)} <byte 12008> lbits:32 address Interrupt Message Address {} or int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 12008> ulong value As longword endunion int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 12012> union int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 12012> {field (By field)} <byte 12012> lbits:32 value Interrupt Message Value {} or int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 12012> ulong value As longword endunion int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 12016> union sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 12016> {field (By field)} <byte 12016> lbits:8 length SGL Page Length lbits:24 reserved Reserved {} or sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 12016> ulong value As longword endunion sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 12020> union my_id (Offset 16C) My ID <byte 12020> {field (By field)} <byte 12020> lbits:24 id My ID lbits:8 reserved Reserved {} or my_id (Offset 16C) My ID <byte 12020> ulong value As longword

endunion my_id (Offset 16C) My ID <byte 12024> union gpio (Offset 170) General Purpose I/O <byte 12024> {field (By field)} <byte 12024> lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:1 gc5 General Purpose Control 5 lbits:1 gc6 General Purpose Control 6 lbits:1 gc7 General Purpose Control 7 lbits:8 reserved Reserved lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose I/O 4 lbits:1 gp5 General Purpose I/O 5 lbits:1 gp6 General Purpose I/O 6 lbits:1 gp7 General Purpose I/O 7 lbits:8 reserved1 Reserved {} or gpio (Offset 170) General Purpose I/O <byte 12024> ulong value As longword endunion gpio (Offset 170) General Purpose I/O <byte 12028> {rsvd6a ((Offset 174-177) Reserved)} <byte 12028> ulong value {} <byte 12032> union edc_config (Offset 178) EDC Configuration Register <byte 12032> {field (By field)} <byte 12032> lbits:16 io_seed Starting Seed lbits:16 reserved Reserved {} or edc_config (Offset 178) EDC Configuration Register <byte 12032> ulong value As longword endunion edc_config (Offset 178) EDC Configuration Register <byte 12036> union dx4_config3 (Offset 17C) DX4 Configuration Register 3 <byte 12036> {field (By field)} <byte 12036> lbits:9 pfs2 Programmable Frame size field 2 lbits:9 pfs3 Programmable Frame size field 3 lbits:9 pfs4 Programmable Frame size field 4 lbits:5 reserved Reserved {} or dx4_config3 (Offset 17C) DX4 Configuration Register 3 <byte 12036> ulong value As longword endunion dx4_config3 (Offset 17C) DX4 Configuration Register 3

<byte 12040> union tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 12040> {field (By field)} <byte 12040> lbits:9 pfs Programmable Frame Size lbits:15 reserved Reserved lbits:8 esi_range Exchange_ID Signaled Interrupt Range {} or tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 12040> ulong value As longword endunion tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 12044> union tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 12044> {field (By field)} <byte 12044> lbits:1 fad FCP Assist Disable lbits:1 ino In Order lbits:1 dof Discard OOO FCP Frames lbits:1 fua FCP Unassisted ACK Enable lbits:1 ime Interrupt Message Enable lbits:1 fab Fabric lbits:1 sic S_ID Copy Enable lbits:1 eqs Equal Service lbits:2 reserved Reserved lbits:1 aks Automatic ACK lbits:1 ddf Disable Delayed Freeze lbits:1 ebe Enable Big Endian Mode lbits:11 reserved1 Reserved lbits:1 fc2 FCP Class 2 Reassembly Enable lbits:1 reserved2 Reserved lbits:1 sdf Save Discarded Frames lbits:1 rde Response Detect Enable lbits:1 dam Default ACK Model lbits:2 reserved3 Reserved lbits:1 m66 66 MHz Enabled {} or tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 12044> ulong value As longword endunion tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 12048> union tach_control (Offset 188) Tachyon DX2+ Control <byte 12048> {field (By field)} <byte 12048> lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:3 reserved Reserved lbits:1 feq Freeze ERQ lbits:1 ffa Freeze FCP Assists lbits:2 reserved1 Reserved lbits:1 fis Freeze Inbound FCP Assists When Frame Placed in SFQ lbits:1 fib Freeze Inbound FCP Assists lbits:2 reserved2 Reserved

lbits:1 req Resume ERQ lbits:1 rif Resume Inbound FCP Assists lbits:1 rof Resume Outbound FCP Assists lbits:12 reserved3 Reserved lbits:1 crs Core Reset {} or tach_control (Offset 188) Tachyon DX2+ Control <byte 12048> ulong value As longword endunion tach_control (Offset 188) Tachyon DX2+ Control <byte 12052> union tach_status (Offset 18C) Tachyon DX2+ Status <byte 12052> {field (By field)} <byte 12052> lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose Input 4 lbits:5 reserved Reserved lbits:1 ipe Inbound Parity Error lbits:1 ope Outbound Parity Error lbits:4 reserved1 Reserved lbits:1 eqf ERQ Frozen lbits:1 iff Inbound FCP Assists Frozen lbits:1 off Outbound FCP Assists Frozen lbits:4 reserved2 Reserved lbits:1 ifce Inbound FIFO CRC Error lbits:1 ofce Outbound FIFO CRC Error lbits:1 m66 66 Mhz Enabled lbits:1 ile Inbound Link Control FIFO Empty lbits:1 ole Outbound Link Control List Empty lbits:1 ife Inbound FIFO Empty lbits:1 ofe Outbound FIFO Empty lbits:1 imf IMQ Full lbits:1 ssf SFQ Full {} or tach_status (Offset 18C) Tachyon DX2+ Status <byte 12052> ulong value As longword endunion tach_status (Offset 18C) Tachyon DX2+ Status <byte 12056> {rsvd7 ((Offset 190) Reserved)} <byte 12056> ulong value {} <byte 12060> union hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 12060> {field (By field)} <byte 12060> lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 12060> ulong value As longword

endunion hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 12064> union hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 12064> {field (By field)} <byte 12064> lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 12064> ulong value As longword endunion hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 12068> union inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 12068> {field (By field)} <byte 12068> lbits:24 reserved Reserved lbits:8 sest_lru_count SEST LRU Count {} or inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 12068> ulong value As longword endunion inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 12072> union inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 12072> {field (By field)} <byte 12072> lbits:8 discd_frames Discarded Frame Count lbits:24 reserved Reserved {} or inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 12072> ulong value As longword endunion inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 12076> union ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) <byte 12076> {field (By field)} <byte 12076> lbits:28 threshold EE_Credit Zero Timer Threshold lbits:4 reserved Reserved {} or ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) <byte 12076> ulong value As longword endunion ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only ) <byte 12080> union up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 12080> {field (By field)} <byte 12080> lbits:12 reserved Reserved lbits:1 upper_addr1 Upper Data Address--44 bit data space lbits:19 upper_addr Upper Data Address

{} or up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 12080> ulong value As longword endunion up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 12084> union up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 12084> {field (By field)} <byte 12084> lbits:32 upper_addr Upper Control Address {} or up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 12084> ulong value As longword endunion up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 12088> union dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 12088> {field (By field)} <byte 12088> lbits:1 ef AL_PA 0xEF DHD Login Information lbits:1 e8 AL_PA 0xE8 DHD Login Information lbits:1 e4 AL_PA 0xE4 DHD Login Information lbits:1 e2 AL_PA 0xE2 DHD Login Information lbits:1 e1 AL_PA 0xE1 DHD Login Information lbits:1 e0 AL_PA 0xE0 DHD Login Information lbits:1 dc AL_PA 0xDC DHD Login Information lbits:1 da AL_PA 0xDA DHD Login Information lbits:1 d9 AL_PA 0xD9 DHD Login Information lbits:1 d6 AL_PA 0xD6 DHD Login Information lbits:1 d5 AL_PA 0xD5 DHD Login Information lbits:1 d4 AL_PA 0xD4 DHD Login Information lbits:1 d3 AL_PA 0xD3 DHD Login Information lbits:1 d2 AL_PA 0xD2 DHD Login Information lbits:1 d1 AL_PA 0xD1 DHD Login Information lbits:1 ce AL_PA 0xCE DHD Login Information lbits:1 cd AL_PA 0xCD DHD Login Information lbits:1 cc AL_PA 0xCC DHD Login Information lbits:1 cb AL_PA 0xCB DHD Login Information lbits:1 ca AL_PA 0xCA DHD Login Information lbits:1 c9 AL_PA 0xC9 DHD Login Information lbits:1 c7 AL_PA 0xC7 DHD Login Information lbits:1 c6 AL_PA 0xC6 DHD Login Information lbits:1 c5 AL_PA 0xC5 DHD Login Information lbits:1 c3 AL_PA 0xC3 DHD Login Information lbits:1 bc AL_PA 0xBC DHD Login Information lbits:1 ba AL_PA 0xBA DHD Login Information lbits:1 b9 AL_PA 0xB9 DHD Login Information lbits:1 b6 AL_PA 0xB6 DHD Login Information lbits:1 b5 AL_PA 0xB5 DHD Login Information lbits:1 b4 AL_PA 0xB4 DHD Login Information lbits:1 b3 AL_PA 0xB3 DHD Login Information {} or dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 12088> ulong value As longword endunion dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 12092> union dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2

<byte 12092> {field (By field)} <byte 12092> lbits:1 alpab2 AL_PA 0xB2 DHD Login Information lbits:1 alpab1 AL_PA 0xB1 DHD Login Information lbits:1 alpaae AL_PA 0xAE DHD Login Information lbits:1 alpaad AL_PA 0xAD DHD Login Information lbits:1 alpaac AL_PA 0xAC DHD Login Information lbits:1 alpaab AL_PA 0xAB DHD Login Information lbits:1 alpaaa AL_PA 0xAA DHD Login Information lbits:1 alpaa9 AL_PA 0xA9 DHD Login Information lbits:1 alpaa7 AL_PA 0xA7 DHD Login Information lbits:1 alpaa6 AL_PA 0xA6 DHD Login Information lbits:1 alpaa5 AL_PA 0xA5 DHD Login Information lbits:1 alpaa3 AL_PA 0xA3 DHD Login Information lbits:1 alpa9f AL_PA 0x9F DHD Login Information lbits:1 alpa9e AL_PA 0x9E DHD Login Information lbits:1 alpa9d AL_PA 0x9D DHD Login Information lbits:1 alpa9b AL_PA 0x9B DHD Login Information lbits:1 alpa98 AL_PA 0x98 DHD Login Information lbits:1 alpa97 AL_PA 0x97 DHD Login Information lbits:1 alpa90 AL_PA 0x90 DHD Login Information lbits:1 alpa8f AL_PA 0x8F DHD Login Information lbits:1 alpa88 AL_PA 0x88 DHD Login Information lbits:1 alpa84 AL_PA 0x84 DHD Login Information lbits:1 alpa82 AL_PA 0x82 DHD Login Information lbits:1 alpa81 AL_PA 0x81 DHD Login Information lbits:1 alpa80 AL_PA 0x80 DHD Login Information lbits:1 alpa7c AL_PA 0x7C DHD Login Information lbits:1 alpa7a AL_PA 0x7A DHD Login Information lbits:1 alpa79 AL_PA 0x79 DHD Login Information lbits:1 alpa76 AL_PA 0x76 DHD Login Information lbits:1 alpa75 AL_PA 0x75 DHD Login Information lbits:1 alpa74 AL_PA 0x74 DHD Login Information lbits:1 alpa73 AL_PA 0x73 DHD Login Information {} or dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 12092> ulong value As longword endunion dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 12096> union dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 12096> {field (By field)} <byte 12096> lbits:1 alpa72 AL_PA 0x72 DHD Login Information lbits:1 alpa71 AL_PA 0x71 DHD Login Information lbits:1 alpa6e AL_PA 0x6E DHD Login Information lbits:1 alpa6d AL_PA 0x6D DHD Login Information lbits:1 alpa6c AL_PA 0x6C DHD Login Information lbits:1 alpa6b AL_PA 0x6B DHD Login Information lbits:1 alpa6a AL_PA 0x6A DHD Login Information lbits:1 alpa69 AL_PA 0x69 DHD Login Information lbits:1 alpa67 AL_PA 0x67 DHD Login Information lbits:1 alpa66 AL_PA 0x66 DHD Login Information lbits:1 alpa65 AL_PA 0x65 DHD Login Information lbits:1 alpa63 AL_PA 0x63 DHD Login Information lbits:1 alpa5c AL_PA 0x5C DHD Login Information lbits:1 alpa5a AL_PA 0x5A DHD Login Information lbits:1 alpa59 AL_PA 0x59 DHD Login Information

lbits:1 alpa56 AL_PA 0x56 DHD Login Information lbits:1 alpa55 AL_PA 0x55 DHD Login Information lbits:1 alpa54 AL_PA 0x54 DHD Login Information lbits:1 alpa53 AL_PA 0x53 DHD Login Information lbits:1 alpa52 AL_PA 0x52 DHD Login Information lbits:1 alpa51 AL_PA 0x51 DHD Login Information lbits:1 alpa4e AL_PA 0x4E DHD Login Information lbits:1 alpa4d AL_PA 0x4D DHD Login Information lbits:1 alpa4c AL_PA 0x4C DHD Login Information lbits:1 alpa4b AL_PA 0x4B DHD Login Information lbits:1 alpa4a AL_PA 0x4A DHD Login Information lbits:1 alpa49 AL_PA 0x49 DHD Login Information lbits:1 alpa47 AL_PA 0x47 DHD Login Information lbits:1 alpa46 AL_PA 0x46 DHD Login Information lbits:1 alpa45 AL_PA 0x45 DHD Login Information lbits:1 alpa43 AL_PA 0x43 DHD Login Information lbits:1 alpa3c AL_PA 0x3C DHD Login Information {} or dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 12096> ulong value As longword endunion dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 12100> union dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 12100> {field (By field)} <byte 12100> lbits:1 alpa3a AL_PA 0x3A DHD Login Information lbits:1 alpa39 AL_PA 0x39 DHD Login Information lbits:1 alpa36 AL_PA 0x36 DHD Login Information lbits:1 alpa35 AL_PA 0x35 DHD Login Information lbits:1 alpa34 AL_PA 0x34 DHD Login Information lbits:1 alpa33 AL_PA 0x33 DHD Login Information lbits:1 alpa32 AL_PA 0x32 DHD Login Information lbits:1 alpa31 AL_PA 0x31 DHD Login Information lbits:1 alpa2e AL_PA 0x2E DHD Login Information lbits:1 alpa2d AL_PA 0x2D DHD Login Information lbits:1 alpa2c AL_PA 0x2C DHD Login Information lbits:1 alpa2b AL_PA 0x2B DHD Login Information lbits:1 alpa2a AL_PA 0x2A DHD Login Information lbits:1 alpa29 AL_PA 0x29 DHD Login Information lbits:1 alpa27 AL_PA 0x27 DHD Login Information lbits:1 alpa26 AL_PA 0x26 DHD Login Information lbits:1 alpa25 AL_PA 0x25 DHD Login Information lbits:1 alpa23 AL_PA 0x23 DHD Login Information lbits:1 alpa1f AL_PA 0x1F DHD Login Information lbits:1 alpa1e AL_PA 0x1E DHD Login Information lbits:1 alpa1d AL_PA 0x1D DHD Login Information lbits:1 alpa1b AL_PA 0x1B DHD Login Information lbits:1 alpa18 AL_PA 0x18 DHD Login Information lbits:1 alpa17 AL_PA 0x17 DHD Login Information lbits:1 alpa10 AL_PA 0x10 DHD Login Information lbits:1 alpa0f AL_PA 0x0F DHD Login Information lbits:1 alpa08 AL_PA 0x08 DHD Login Information lbits:1 alpa04 AL_PA 0x04 DHD Login Information lbits:1 alpa02 AL_PA 0x02 DHD Login Information lbits:1 alpa01 AL_PA 0x01 DHD Login Information lbits:1 alpa00 AL_PA 0x00 DHD Login Information lbits:1 reserved Reserved {}

or dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 12100> ulong value As longword endunion dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 12104> union fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 12104> {field (By field)} <byte 12104> lbits:1 bli Bypass Loop Initialization lbits:1 reserved Reserved lbits:1 enp Enable N_Port Mode lbits:1 lr Login Required lbits:1 inif Initialize as Fabric lbits:1 rf Respond to Fabric Address lbits:1 blm Bypass Loop Map lbits:1 sa Acquire Soft Address lbits:1 ha Acquire Hard Address lbits:1 aq Acquire Previously Acquired Address lbits:1 fa Acquire Fabric Aquired Address lbits:1 td Timer Disable lbits:1 sap Skip Arbitration Phase lbits:1 elb External Loopback/Pad Loopback lbits:1 ilb Internal loopback lbits:1 npi Initialize as N_Port lbits:8 bb_credit BB_Credit lbits:8 al_pa Desired AL_PA {} or fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 12104> ulong value As longword endunion fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 12108> union fm_control (Offset 1C4) Frame Manager Control <byte 12108> {field (By field)} <byte 12108> lbits:3 cmd State Machine Command lbits:1 cl Close Loop Request lbits:1 reserved Reserved lbits:1 sp Send Prim_Reg lbits:1 sq Primitive Sequence lbits:25 reserved1 Reserved {} or fm_control (Offset 1C4) Frame Manager Control <byte 12108> ulong value As longword endunion fm_control (Offset 1C4) Frame Manager Control <byte 12112> union fm_status (Offset 1C8) Frame Manager Status <byte 12112> {field (By field)} <byte 12112> lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure

lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_status (Offset 1C8) Frame Manager Status <byte 12112> ulong value As longword endunion fm_status (Offset 1C8) Frame Manager Status <byte 12116> union fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 12116> {field (By field)} <byte 12116> lbits:16 ed_tov Error Detect Time-Out lbits:9 rt_tov Receiver Transmitter Time-Out lbits:7 reserved Reserved {} or fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 12116> ulong value As longword endunion fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 12120> union fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 12120> {field (By field)} <byte 12120> lbits:8 link_fail Link Fail Count lbits:8 loss_of_sync Loss of Synchronization Count lbits:8 bad_rx_char Bad Received Character Count lbits:8 loss_of_signal Loss of Signal Count {} or fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 12120> ulong value As longword endunion fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 12124> union fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 12124> {field (By field)} <byte 12124> lbits:8 proto_er Protocol Error Count lbits:8 bad_crc Bad CRC Count lbits:8 dis_frm Discarded Frames lbits:8 rx_eofa Received EOFa

{} or fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 12124> ulong value As longword endunion fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 12128> union fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 12128> {field (By field)} <byte 12128> lbits:9 al_time Arbitrated Loop Time-Out lbits:7 reserved Reserved lbits:16 lp_tov Loop Time-Out {} or fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 12128> ulong value As longword endunion fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 12132> union fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 12132> {field (By field)} <byte 12132> lbits:24 bb0_timer BB_Credit Timer lbits:8 reserved Reserved {} or fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 12132> ulong value As longword endunion fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 12136> union fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 12136> {field (By field)} <byte 12136> lbits:32 wwn World Wide Name {} or fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 12136> ulong value As longword endunion fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 12140> union fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 12140> {field (By field)} <byte 12140> lbits:32 wwn World Wide Name {} or fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 12140> ulong value As longword endunion fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 12144> union fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 12144> {field (By field)} <byte 12144> lbits:8 lipf_alpa AL_PA of Most Recent LIPf Received lbits:8 bad_alpa AL_PA of Most Recent OPN Sent and Returned Without Being Accept ed

lbits:8 acq_alpa AL_PA Acquired During Loop Initialization lbits:8 reserved Reserved {} or fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 12144> ulong value As longword endunion fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 12148> union fm_primitive (Offset 1EC) Frame Manager Primitive <byte 12148> {field (By field)} <byte 12148> lbits:24 prim_value Primitive to be Sent lbits:8 reserved Reserved {} or fm_primitive (Offset 1EC) Frame Manager Primitive <byte 12148> ulong value As longword endunion fm_primitive (Offset 1EC) Frame Manager Primitive <byte 12152> union fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 12152> {field (By field)} <byte 12152> lbits:8 exp_frm Expired Frames lbits:24 reserved Reserved {} or fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 12152> ulong value As longword endunion fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 12156> union fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 12156> {field (By field)} <byte 12156> lbits:1 dac Disable Auto Close lbits:2 nbc Non-zero Login BB_Credit lbits:1 eei Enable ERR_INIT lbits:1 icb Ignore Close Bit lbits:2 atv Arbitration Threshold Value lbits:1 gde Garbage Deletion Enable lbits:8 laa Lowest Allowable AL_PA lbits:5 reserved Reserved lbits:1 dao Disable 2xAL_TIME Timeout on Open lbits:3 reserved1 Reserved lbits:1 prm Promiscuous Mode lbits:1 wpe Wait For Port Enable lbits:1 fmh Force Monitor State With Hard Address lbits:1 fmn Force Monitor Non-participating State lbits:1 dlm Disable Loop Master lbits:1 dsa Disable Soft Address Selection lbits:1 ilp Ignore LPB/LPE Primitive Sequences {} or fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 12156> ulong value As longword endunion fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 12160> union pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED

<byte 12160> {field (By field)} <byte 12160> {pci_rsvd1F8 ((Offset 1F8) Reserved)} <byte 12160> utiny value {} <byte 12161> {pci_rsvd1F9 ((Offset 1F9) Reserved)} <byte 12161> utiny value {} <byte 12162> union romctr (Offset 1FA) PCI ROM Control <byte 12162> {field (By field)} <byte 12162> tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or romctr (Offset 1FA) PCI ROM Control <byte 12162> utiny value As byte endunion romctr (Offset 1FA) PCI ROM Control <byte 12163> union mctr (Offset 1FB) PCI Master Control <byte 12163> {field (By field)} <byte 12163> tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or mctr (Offset 1FB) PCI Master Control <byte 12163> utiny value As byte endunion mctr (Offset 1FB) PCI Master Control {} or pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED <byte 12160> ulong value As longword endunion pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED <byte 12164> union pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST <byte 12164> {field (By field)} <byte 12164> union softrst (Offset 1FC) PCI Interface Reset Control <byte 12164> {field (By field)} <byte 12164> tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or softrst (Offset 1FC) PCI Interface Reset Control <byte 12164> utiny value As byte

endunion softrst (Offset 1FC) PCI Interface Reset Control <byte 12165> union intpend (Offset 1FD) PCI Interrupt Pending <byte 12165> {field (By field)} <byte 12165> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intpend (Offset 1FD) PCI Interrupt Pending <byte 12165> utiny value As byte endunion intpend (Offset 1FD) PCI Interrupt Pending <byte 12166> union inten (Offset 1FE) PCI Interrupt Enable <byte 12166> {field (By field)} <byte 12166> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or inten (Offset 1FE) PCI Interrupt Enable <byte 12166> utiny value As byte endunion inten (Offset 1FE) PCI Interrupt Enable <byte 12167> union intstat (Offset 1FF) PCI Interrupt Status <byte 12167> {field (By field)} <byte 12167> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intstat (Offset 1FF) PCI Interrupt Status <byte 12167> utiny value As byte endunion intstat (Offset 1FF) PCI Interrupt Status {} or pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST <byte 12164> ulong value As longword endunion pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST {} endunion csr[10] Tachyon DX2+ CSR Registers <byte 12168> union csr[11] Tachyon DX2+ CSR Registers <byte 12168> ulong[128] csra Tachyon DX2+ CSR Registers As Longwords

or csr[11] Tachyon DX2+ CSR Registers <byte 12168> {csr (Tachyon DX2+ CSR Registers By Field)} <byte 12168> union erq_base (Offset 000) ERQ Base (write only) <byte 12168> {field (By field)} <byte 12168> lbits:32 address ERQ Base Address {} or erq_base (Offset 000) ERQ Base (write only) <byte 12168> ulong value As longword endunion erq_base (Offset 000) ERQ Base (write only) <byte 12172> union erq_len (Offset 004) ERQ Length (write only) <byte 12172> {field (By field)} <byte 12172> lbits:12 length ERQ Length lbits:20 reserved Reserved {} or erq_len (Offset 004) ERQ Length (write only) <byte 12172> ulong value As longword endunion erq_len (Offset 004) ERQ Length (write only) <byte 12176> union erq_prod (Offset 008) ERQ Producer Index <byte 12176> {field (By field)} <byte 12176> lbits:12 index ERQ Producer Index lbits:20 reserved Reserved {} or erq_prod (Offset 008) ERQ Producer Index <byte 12176> ulong value As longword endunion erq_prod (Offset 008) ERQ Producer Index <byte 12180> union erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 12180> {field (By field)} <byte 12180> lbits:32 address ERQ Consumer Index Address {} or erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 12180> ulong value As longword endunion erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only) <byte 12184> union erq_cons (Offset 010) ERQ Consumer Index <byte 12184> {field (By field)} <byte 12184> lbits:12 index ERQ Consumer Index lbits:20 reserved Reserved {} or erq_cons (Offset 010) ERQ Consumer Index <byte 12184> ulong value As longword

endunion erq_cons (Offset 010) ERQ Consumer Index <byte 12188> {rsvd1[0] ((Offset 014-04F) Reserved)} <byte 12188> ulong value {} <byte 12192> {rsvd1[1] ((Offset 014-04F) Reserved)} <byte 12192> ulong value {} <byte 12196> {rsvd1[2] ((Offset 014-04F) Reserved)} <byte 12196> ulong value {} <byte 12200> {rsvd1[3] ((Offset 014-04F) Reserved)} <byte 12200> ulong value {} <byte 12204> {rsvd1[4] ((Offset 014-04F) Reserved)} <byte 12204> ulong value {} <byte 12208> {rsvd1[5] ((Offset 014-04F) Reserved)} <byte 12208> ulong value {} <byte 12212> {rsvd1[6] ((Offset 014-04F) Reserved)} <byte 12212> ulong value {} <byte 12216> {rsvd1[7] ((Offset 014-04F) Reserved)} <byte 12216> ulong value {} <byte 12220> {rsvd1[8] ((Offset 014-04F) Reserved)} <byte 12220> ulong value {} <byte 12224> {rsvd1[9] ((Offset 014-04F) Reserved)} <byte 12224> ulong value {} <byte 12228> {rsvd1[10] ((Offset 014-04F) Reserved)} <byte 12228> ulong value {} <byte 12232> {rsvd1[11] ((Offset 014-04F) Reserved)} <byte 12232> ulong value

{} <byte 12236> {rsvd1[12] ((Offset 014-04F) Reserved)} <byte 12236> ulong value {} <byte 12240> {rsvd1[13] ((Offset 014-04F) Reserved)} <byte 12240> ulong value {} <byte 12244> {rsvd1[14] ((Offset 014-04F) Reserved)} <byte 12244> ulong value {} <byte 12248> union sfq_base (Offset 050) SFQ Base (write only) <byte 12248> {field (By field)} <byte 12248> lbits:32 address SFQ Base Address {} or sfq_base (Offset 050) SFQ Base (write only) <byte 12248> ulong value As longword endunion sfq_base (Offset 050) SFQ Base (write only) <byte 12252> union sfq_len (Offset 054) SFQ Length (write only) <byte 12252> {field (By field)} <byte 12252> lbits:12 length SFQ Length lbits:20 reserved Reserved {} or sfq_len (Offset 054) SFQ Length (write only) <byte 12252> ulong value As longword endunion sfq_len (Offset 054) SFQ Length (write only) <byte 12256> union sfq_cons (Offset 058) SFQ Consumer Index <byte 12256> {field (By field)} <byte 12256> lbits:12 index SFQ Consumer Index lbits:20 reserved Reserved {} or sfq_cons (Offset 058) SFQ Consumer Index <byte 12256> ulong value As longword endunion sfq_cons (Offset 058) SFQ Consumer Index <byte 12260> {rsvd2[0] ((Offset 05C-07B) Reserved)} <byte 12260> ulong value {} <byte 12264> {rsvd2[1] ((Offset 05C-07B) Reserved)} <byte 12264> ulong value

{} <byte 12268> {rsvd2[2] ((Offset 05C-07B) Reserved)} <byte 12268> ulong value {} <byte 12272> {rsvd2[3] ((Offset 05C-07B) Reserved)} <byte 12272> ulong value {} <byte 12276> {rsvd2[4] ((Offset 05C-07B) Reserved)} <byte 12276> ulong value {} <byte 12280> {rsvd2[5] ((Offset 05C-07B) Reserved)} <byte 12280> ulong value {} <byte 12284> {rsvd2[6] ((Offset 05C-07B) Reserved)} <byte 12284> ulong value {} <byte 12288> {rsvd2[7] ((Offset 05C-07B) Reserved)} <byte 12288> ulong value {} <byte 12292> union int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 12292> {field (By field)} <byte 12292> lbits:4 timer Interrupt Timer Value lbits:3 reserved Reserved lbits:1 ihf Interrupt when IMQ Half Full lbits:24 reserved1 Reserved {} or int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 12292> ulong value As longword endunion int_delay_timer (Offset 07C) Interrupt Delay Timer (write only) <byte 12296> union imq_base (Offset 080) IMQ Base (write only) <byte 12296> {field (By field)} <byte 12296> lbits:32 address IMQ Base Address {} or imq_base (Offset 080) IMQ Base (write only) <byte 12296> ulong value As longword endunion imq_base (Offset 080) IMQ Base (write only) <byte 12300> union imq_len (Offset 084) IMQ Length (write only) <byte 12300> {field (By field)}

<byte 12300> lbits:12 length IMQ Length lbits:20 reserved Reserved {} or imq_len (Offset 084) IMQ Length (write only) <byte 12300> ulong value As longword endunion imq_len (Offset 084) IMQ Length (write only) <byte 12304> union imq_cons (Offset 088) IMQ Consumer Index <byte 12304> {field (By field)} <byte 12304> lbits:12 index IMQ Consumer Index lbits:20 reserved Reserved {} or imq_cons (Offset 088) IMQ Consumer Index <byte 12304> ulong value As longword endunion imq_cons (Offset 088) IMQ Consumer Index <byte 12308> union imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 12308> {field (By field)} <byte 12308> lbits:32 address IMQ Producer Index Address {} or imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 12308> ulong value As longword endunion imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only) <byte 12312> {rsvd3[0] ((Offset 090-0FC) Reserved)} <byte 12312> ulong value {} <byte 12316> {rsvd3[1] ((Offset 090-0FC) Reserved)} <byte 12316> ulong value {} <byte 12320> {rsvd3[2] ((Offset 090-0FC) Reserved)} <byte 12320> ulong value {} <byte 12324> {rsvd3[3] ((Offset 090-0FC) Reserved)} <byte 12324> ulong value {} <byte 12328> {rsvd3[4] ((Offset 090-0FC) Reserved)} <byte 12328> ulong value {} <byte 12332> {rsvd3[5] ((Offset 090-0FC) Reserved)} <byte 12332> ulong value

{} <byte 12336> {rsvd3[6] ((Offset 090-0FC) Reserved)} <byte 12336> ulong value {} <byte 12340> {rsvd3[7] ((Offset 090-0FC) Reserved)} <byte 12340> ulong value {} <byte 12344> {rsvd3[8] ((Offset 090-0FC) Reserved)} <byte 12344> ulong value {} <byte 12348> {rsvd3[9] ((Offset 090-0FC) Reserved)} <byte 12348> ulong value {} <byte 12352> {rsvd3[10] ((Offset 090-0FC) Reserved)} <byte 12352> ulong value {} <byte 12356> {rsvd3[11] ((Offset 090-0FC) Reserved)} <byte 12356> ulong value {} <byte 12360> {rsvd3[12] ((Offset 090-0FC) Reserved)} <byte 12360> ulong value {} <byte 12364> {rsvd3[13] ((Offset 090-0FC) Reserved)} <byte 12364> ulong value {} <byte 12368> {rsvd3[14] ((Offset 090-0FC) Reserved)} <byte 12368> ulong value {} <byte 12372> {rsvd3[15] ((Offset 090-0FC) Reserved)} <byte 12372> ulong value {} <byte 12376> {rsvd3[16] ((Offset 090-0FC) Reserved)} <byte 12376> ulong value {} <byte 12380> {rsvd3[17] ((Offset 090-0FC) Reserved)} <byte 12380> ulong value

{} <byte 12384> {rsvd3[18] ((Offset 090-0FC) Reserved)} <byte 12384> ulong value {} <byte 12388> {rsvd3[19] ((Offset 090-0FC) Reserved)} <byte 12388> ulong value {} <byte 12392> {rsvd3[20] ((Offset 090-0FC) Reserved)} <byte 12392> ulong value {} <byte 12396> {rsvd3[21] ((Offset 090-0FC) Reserved)} <byte 12396> ulong value {} <byte 12400> {rsvd3[22] ((Offset 090-0FC) Reserved)} <byte 12400> ulong value {} <byte 12404> {rsvd3[23] ((Offset 090-0FC) Reserved)} <byte 12404> ulong value {} <byte 12408> {rsvd3[24] ((Offset 090-0FC) Reserved)} <byte 12408> ulong value {} <byte 12412> {rsvd3[25] ((Offset 090-0FC) Reserved)} <byte 12412> ulong value {} <byte 12416> {rsvd3[26] ((Offset 090-0FC) Reserved)} <byte 12416> ulong value {} <byte 12420> {rsvd3[27] ((Offset 090-0FC) Reserved)} <byte 12420> ulong value {} <byte 12424> union fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 12424> {field (By field)} <byte 12424> lbits:6 bec Termination Receive lbits:3 reserved4 Reserved lbits:1 xrb Wrapback lbits:2 reserved Reserved

lbits:3 xem Output pre-emphasis lbits:4 reserved1 Reserved lbits:1 mustbe1 Must be 1 lbits:1 stb Start BERT lbits:1 enb Enable BERT lbits:2 sdm Signal differential mode lbits:2 rxs Receiver Speed lbits:2 txs Transmitter Speed lbits:1 reserved3 Reserved lbits:1 xlr Force iTR to lock reference clock lbits:1 reserved0 Reserved lbits:1 xcv Type of Transceiver {} or fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 12424> ulong value As longword endunion fm_config3 (Offset 100) Frame Manager Configuration 3 <byte 12428> union fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 12428> {field (By field)} <byte 12428> lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 12428> ulong value As longword endunion fm_statuss (Offset 104) Frame Manager Status Shadow (read only) <byte 12432> {rsvd3a[0] ((Offset 108-10f) Reserved)} <byte 12432> ulong value {} <byte 12436> {rsvd3a[1] ((Offset 108-10f) Reserved)}

<byte 12436> ulong value {} <byte 12440> union sfp_cmd_status (Offset 110) SFP command and status <byte 12440> {field (No description available)} <byte 12440> lbits:1 gna Generate NACK lbits:1 rts Reset Slave lbits:1 wrc Write command lbits:1 rdc Read command lbits:1 gst Generate Stop lbits:1 sta Generate Start lbits:2 reserved1 Reserved lbits:1 rna Received NACK lbits:1 sby SFP Busy lbits:1 tip Transfer in progress lbits:9 reserved Reserved lbits:12 lp Clock Divisor {} or sfp_cmd_status (Offset 110) SFP command and status <byte 12440> ulong value endunion sfp_cmd_status (Offset 110) SFP command and status <byte 12444> union sfp_data (Offset 114) SFP data <byte 12444> {field (By field)} <byte 12444> lbits:8 sfpd SFPD Transmit lbits:24 reserved Reserved {} or sfp_data (Offset 114) SFP data <byte 12444> ulong value As longword endunion sfp_data (Offset 114) SFP data <byte 12448> union fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 12448> {field (By field)} <byte 12448> lbits:1 tbe Transmit Link BIST error lbits:1 tlr Transmit Link BIST reset lbits:1 tle Transmit Link BIST enable lbits:1 rbe Receive Link BIST error lbits:1 rll Receive Link BIST loop-back lbits:1 rlr Receive Link BIST reset lbits:1 rle Receive Link BIST enable lbits:7 reserved3 Reserved lbits:1 ipl ITR PPL Lock lbits:1 reserved2 Reserved lbits:1 dtf Disable transceiver LOS filter lbits:1 dtl Disable transceiver LOS lbits:1 dsr Disable iTR RXLOS lbits:1 ttd Transceiver Tx Disable lbits:2 reserved1 Reserved lbits:1 rfl Receive ast Lock Disable lbits:9 reserved Reserved {}

or fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 12448> ulong value As longword endunion fm_config4 (Offset 118) Frame Manager Configuration 4 <byte 12452> union fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 12452> {field (By field)} <byte 12452> lbits:32 reserved Reserved {} or fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 12452> ulong value As longword endunion fm_config5 (Offset 11C) Frame Manager Configuration 5 <byte 12456> {rsvd3b[0] ((Offset 120-13F) Reserved)} <byte 12456> ulong value {} <byte 12460> {rsvd3b[1] ((Offset 120-13F) Reserved)} <byte 12460> ulong value {} <byte 12464> {rsvd3b[2] ((Offset 120-13F) Reserved)} <byte 12464> ulong value {} <byte 12468> {rsvd3b[3] ((Offset 120-13F) Reserved)} <byte 12468> ulong value {} <byte 12472> {rsvd3b[4] ((Offset 120-13F) Reserved)} <byte 12472> ulong value {} <byte 12476> {rsvd3b[5] ((Offset 120-13F) Reserved)} <byte 12476> ulong value {} <byte 12480> {rsvd3b[6] ((Offset 120-13F) Reserved)} <byte 12480> ulong value {} <byte 12484> {rsvd3b[7] ((Offset 120-13F) Reserved)} <byte 12484> ulong value {} <byte 12488> union sest_base (Offset 140) SEST Base (write only) <byte 12488> {field (By field)} <byte 12488>

lbits:32 address SEST Base Address {} or sest_base (Offset 140) SEST Base (write only) <byte 12488> ulong value As longword endunion sest_base (Offset 140) SEST Base (write only) <byte 12492> union sest_len (Offset 144) SEST Length (write only) <byte 12492> {field (By field)} <byte 12492> lbits:16 length SEST Length lbits:16 reserved Reserved {} or sest_len (Offset 144) SEST Length (write only) <byte 12492> ulong value As longword endunion sest_len (Offset 144) SEST Length (write only) <byte 12496> {rsvd4 ((Offset 148) Reserved)} <byte 12496> ulong value {} <byte 12500> union scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 12500> {field (By field)} <byte 12500> lbits:16 tail Tail lbits:16 head Head {} or scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 12500> ulong value As longword endunion scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail <byte 12504> union prog_addr (Offset 150) Programmable Address register <byte 12504> {field (By field)} <byte 12504> lbits:20 ra ROM/RAM address lbits:11 reserved Reserved lbits:1 inc Increment {} or prog_addr (Offset 150) Programmable Address register <byte 12504> ulong value As longword endunion prog_addr (Offset 150) Programmable Address register <byte 12508> union prog_data (Offset 154) programmable data register <byte 12508> {field (By field)} <byte 12508> lbits:32 pdr Programmable data {} or prog_data (Offset 154) programmable data register <byte 12508> ulong value As longword endunion prog_data (Offset 154) programmable data register <byte 12512>

{rsvd5[0] ((Offset 158-15F) Reserved)} <byte 12512> ulong value {} <byte 12516> {rsvd5[1] ((Offset 158-15F) Reserved)} <byte 12516> ulong value {} <byte 12520> union int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 12520> {field (By field)} <byte 12520> lbits:32 address Interrupt Message Address {} or int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 12520> ulong value As longword endunion int_mess_adr (Offset 160) Interrupt Message Address (write only) <byte 12524> union int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 12524> {field (By field)} <byte 12524> lbits:32 value Interrupt Message Value {} or int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 12524> ulong value As longword endunion int_mess_value (Offset 164) Interrupt Message Value (write only) <byte 12528> union sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 12528> {field (By field)} <byte 12528> lbits:8 length SGL Page Length lbits:24 reserved Reserved {} or sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 12528> ulong value As longword endunion sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only) <byte 12532> union my_id (Offset 16C) My ID <byte 12532> {field (By field)} <byte 12532> lbits:24 id My ID lbits:8 reserved Reserved {} or my_id (Offset 16C) My ID <byte 12532> ulong value As longword endunion my_id (Offset 16C) My ID <byte 12536> union gpio (Offset 170) General Purpose I/O <byte 12536> {field (By field)} <byte 12536>

lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:1 gc5 General Purpose Control 5 lbits:1 gc6 General Purpose Control 6 lbits:1 gc7 General Purpose Control 7 lbits:8 reserved Reserved lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose I/O 4 lbits:1 gp5 General Purpose I/O 5 lbits:1 gp6 General Purpose I/O 6 lbits:1 gp7 General Purpose I/O 7 lbits:8 reserved1 Reserved {} or gpio (Offset 170) General Purpose I/O <byte 12536> ulong value As longword endunion gpio (Offset 170) General Purpose I/O <byte 12540> {rsvd6a ((Offset 174-177) Reserved)} <byte 12540> ulong value {} <byte 12544> union edc_config (Offset 178) EDC Configuration Register <byte 12544> {field (By field)} <byte 12544> lbits:16 io_seed Starting Seed lbits:16 reserved Reserved {} or edc_config (Offset 178) EDC Configuration Register <byte 12544> ulong value As longword endunion edc_config (Offset 178) EDC Configuration Register <byte 12548> union dx4_config3 (Offset 17C) DX4 Configuration Register 3 <byte 12548> {field (By field)} <byte 12548> lbits:9 pfs2 Programmable Frame size field 2 lbits:9 pfs3 Programmable Frame size field 3 lbits:9 pfs4 Programmable Frame size field 4 lbits:5 reserved Reserved {} or dx4_config3 (Offset 17C) DX4 Configuration Register 3 <byte 12548> ulong value As longword endunion dx4_config3 (Offset 17C) DX4 Configuration Register 3 <byte 12552> union tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 12552> {field (By field)} <byte 12552> lbits:9 pfs Programmable Frame Size

lbits:15 reserved Reserved lbits:8 esi_range Exchange_ID Signaled Interrupt Range {} or tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 12552> ulong value As longword endunion tach_config2 (Offset 180) Tachyon DX2+ Configuration 2 <byte 12556> union tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 12556> {field (By field)} <byte 12556> lbits:1 fad FCP Assist Disable lbits:1 ino In Order lbits:1 dof Discard OOO FCP Frames lbits:1 fua FCP Unassisted ACK Enable lbits:1 ime Interrupt Message Enable lbits:1 fab Fabric lbits:1 sic S_ID Copy Enable lbits:1 eqs Equal Service lbits:2 reserved Reserved lbits:1 aks Automatic ACK lbits:1 ddf Disable Delayed Freeze lbits:1 ebe Enable Big Endian Mode lbits:11 reserved1 Reserved lbits:1 fc2 FCP Class 2 Reassembly Enable lbits:1 reserved2 Reserved lbits:1 sdf Save Discarded Frames lbits:1 rde Response Detect Enable lbits:1 dam Default ACK Model lbits:2 reserved3 Reserved lbits:1 m66 66 MHz Enabled {} or tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 12556> ulong value As longword endunion tach_config (Offset 184) Tachyon DX2+ Configuration 1 <byte 12560> union tach_control (Offset 188) Tachyon DX2+ Control <byte 12560> {field (By field)} <byte 12560> lbits:1 gc0 General Purpose Control 0 lbits:1 gc1 General Purpose Control 1 lbits:1 gc2 General Purpose Control 2 lbits:1 gc3 General Purpose Control 3 lbits:1 gc4 General Purpose Control 4 lbits:3 reserved Reserved lbits:1 feq Freeze ERQ lbits:1 ffa Freeze FCP Assists lbits:2 reserved1 Reserved lbits:1 fis Freeze Inbound FCP Assists When Frame Placed in SFQ lbits:1 fib Freeze Inbound FCP Assists lbits:2 reserved2 Reserved lbits:1 req Resume ERQ lbits:1 rif Resume Inbound FCP Assists lbits:1 rof Resume Outbound FCP Assists lbits:12 reserved3 Reserved lbits:1 crs Core Reset {}

or tach_control (Offset 188) Tachyon DX2+ Control <byte 12560> ulong value As longword endunion tach_control (Offset 188) Tachyon DX2+ Control <byte 12564> union tach_status (Offset 18C) Tachyon DX2+ Status <byte 12564> {field (By field)} <byte 12564> lbits:1 gp0 General Purpose I/O 0 lbits:1 gp1 General Purpose I/O 1 lbits:1 gp2 General Purpose I/O 2 lbits:1 gp3 General Purpose I/O 3 lbits:1 gp4 General Purpose Input 4 lbits:5 reserved Reserved lbits:1 ipe Inbound Parity Error lbits:1 ope Outbound Parity Error lbits:4 reserved1 Reserved lbits:1 eqf ERQ Frozen lbits:1 iff Inbound FCP Assists Frozen lbits:1 off Outbound FCP Assists Frozen lbits:4 reserved2 Reserved lbits:1 ifce Inbound FIFO CRC Error lbits:1 ofce Outbound FIFO CRC Error lbits:1 m66 66 Mhz Enabled lbits:1 ile Inbound Link Control FIFO Empty lbits:1 ole Outbound Link Control List Empty lbits:1 ife Inbound FIFO Empty lbits:1 ofe Outbound FIFO Empty lbits:1 imf IMQ Full lbits:1 ssf SFQ Full {} or tach_status (Offset 18C) Tachyon DX2+ Status <byte 12564> ulong value As longword endunion tach_status (Offset 18C) Tachyon DX2+ Status <byte 12568> {rsvd7 ((Offset 190) Reserved)} <byte 12568> ulong value {} <byte 12572> union hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 12572> {field (By field)} <byte 12572> lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 12572> ulong value As longword endunion hi_pri_send1 (Offset 194) High Priority Send 1 (write only) <byte 12576> union hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 12576> {field (By field)} <byte 12576>

lbits:12 length Frame Length lbits:7 reserved Reserved lbits:12 upper_addr Frame Upper Address lbits:1 reserved1 Reserved {} or hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 12576> ulong value As longword endunion hi_pri_send2 (Offset 198) High Priority Send 2 (write only) <byte 12580> union inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 12580> {field (By field)} <byte 12580> lbits:24 reserved Reserved lbits:8 sest_lru_count SEST LRU Count {} or inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 12580> ulong value As longword endunion inbound_rstat1 (Offset 19C) Inbound Resource Status 1 <byte 12584> union inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 12584> {field (By field)} <byte 12584> lbits:8 discd_frames Discarded Frame Count lbits:24 reserved Reserved {} or inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 12584> ulong value As longword endunion inbound_rstat2 (Offset 1A0) Inbound Resource Status 2 <byte 12588> union ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) <byte 12588> {field (By field)} <byte 12588> lbits:28 threshold EE_Credit Zero Timer Threshold lbits:4 reserved Reserved {} or ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only) <byte 12588> ulong value As longword endunion ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only ) <byte 12592> union up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 12592> {field (By field)} <byte 12592> lbits:12 reserved Reserved lbits:1 upper_addr1 Upper Data Address--44 bit data space lbits:19 upper_addr Upper Data Address {} or up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 12592> ulong value As longword endunion up_data_addr (Offset 1A8) Upper Data Address (write only) <byte 12596>

union up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 12596> {field (By field)} <byte 12596> lbits:32 upper_addr Upper Control Address {} or up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 12596> ulong value As longword endunion up_ctrl_addr (Offset 1AC) Upper Control Address (write only) <byte 12600> union dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 12600> {field (By field)} <byte 12600> lbits:1 ef AL_PA 0xEF DHD Login Information lbits:1 e8 AL_PA 0xE8 DHD Login Information lbits:1 e4 AL_PA 0xE4 DHD Login Information lbits:1 e2 AL_PA 0xE2 DHD Login Information lbits:1 e1 AL_PA 0xE1 DHD Login Information lbits:1 e0 AL_PA 0xE0 DHD Login Information lbits:1 dc AL_PA 0xDC DHD Login Information lbits:1 da AL_PA 0xDA DHD Login Information lbits:1 d9 AL_PA 0xD9 DHD Login Information lbits:1 d6 AL_PA 0xD6 DHD Login Information lbits:1 d5 AL_PA 0xD5 DHD Login Information lbits:1 d4 AL_PA 0xD4 DHD Login Information lbits:1 d3 AL_PA 0xD3 DHD Login Information lbits:1 d2 AL_PA 0xD2 DHD Login Information lbits:1 d1 AL_PA 0xD1 DHD Login Information lbits:1 ce AL_PA 0xCE DHD Login Information lbits:1 cd AL_PA 0xCD DHD Login Information lbits:1 cc AL_PA 0xCC DHD Login Information lbits:1 cb AL_PA 0xCB DHD Login Information lbits:1 ca AL_PA 0xCA DHD Login Information lbits:1 c9 AL_PA 0xC9 DHD Login Information lbits:1 c7 AL_PA 0xC7 DHD Login Information lbits:1 c6 AL_PA 0xC6 DHD Login Information lbits:1 c5 AL_PA 0xC5 DHD Login Information lbits:1 c3 AL_PA 0xC3 DHD Login Information lbits:1 bc AL_PA 0xBC DHD Login Information lbits:1 ba AL_PA 0xBA DHD Login Information lbits:1 b9 AL_PA 0xB9 DHD Login Information lbits:1 b6 AL_PA 0xB6 DHD Login Information lbits:1 b5 AL_PA 0xB5 DHD Login Information lbits:1 b4 AL_PA 0xB4 DHD Login Information lbits:1 b3 AL_PA 0xB3 DHD Login Information {} or dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 12600> ulong value As longword endunion dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3 <byte 12604> union dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 12604> {field (By field)} <byte 12604> lbits:1 alpab2 AL_PA 0xB2 DHD Login Information lbits:1 alpab1 AL_PA 0xB1 DHD Login Information lbits:1 alpaae AL_PA 0xAE DHD Login Information

lbits:1 alpaad AL_PA 0xAD DHD Login Information lbits:1 alpaac AL_PA 0xAC DHD Login Information lbits:1 alpaab AL_PA 0xAB DHD Login Information lbits:1 alpaaa AL_PA 0xAA DHD Login Information lbits:1 alpaa9 AL_PA 0xA9 DHD Login Information lbits:1 alpaa7 AL_PA 0xA7 DHD Login Information lbits:1 alpaa6 AL_PA 0xA6 DHD Login Information lbits:1 alpaa5 AL_PA 0xA5 DHD Login Information lbits:1 alpaa3 AL_PA 0xA3 DHD Login Information lbits:1 alpa9f AL_PA 0x9F DHD Login Information lbits:1 alpa9e AL_PA 0x9E DHD Login Information lbits:1 alpa9d AL_PA 0x9D DHD Login Information lbits:1 alpa9b AL_PA 0x9B DHD Login Information lbits:1 alpa98 AL_PA 0x98 DHD Login Information lbits:1 alpa97 AL_PA 0x97 DHD Login Information lbits:1 alpa90 AL_PA 0x90 DHD Login Information lbits:1 alpa8f AL_PA 0x8F DHD Login Information lbits:1 alpa88 AL_PA 0x88 DHD Login Information lbits:1 alpa84 AL_PA 0x84 DHD Login Information lbits:1 alpa82 AL_PA 0x82 DHD Login Information lbits:1 alpa81 AL_PA 0x81 DHD Login Information lbits:1 alpa80 AL_PA 0x80 DHD Login Information lbits:1 alpa7c AL_PA 0x7C DHD Login Information lbits:1 alpa7a AL_PA 0x7A DHD Login Information lbits:1 alpa79 AL_PA 0x79 DHD Login Information lbits:1 alpa76 AL_PA 0x76 DHD Login Information lbits:1 alpa75 AL_PA 0x75 DHD Login Information lbits:1 alpa74 AL_PA 0x74 DHD Login Information lbits:1 alpa73 AL_PA 0x73 DHD Login Information {} or dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 12604> ulong value As longword endunion dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2 <byte 12608> union dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 12608> {field (By field)} <byte 12608> lbits:1 alpa72 AL_PA 0x72 DHD Login Information lbits:1 alpa71 AL_PA 0x71 DHD Login Information lbits:1 alpa6e AL_PA 0x6E DHD Login Information lbits:1 alpa6d AL_PA 0x6D DHD Login Information lbits:1 alpa6c AL_PA 0x6C DHD Login Information lbits:1 alpa6b AL_PA 0x6B DHD Login Information lbits:1 alpa6a AL_PA 0x6A DHD Login Information lbits:1 alpa69 AL_PA 0x69 DHD Login Information lbits:1 alpa67 AL_PA 0x67 DHD Login Information lbits:1 alpa66 AL_PA 0x66 DHD Login Information lbits:1 alpa65 AL_PA 0x65 DHD Login Information lbits:1 alpa63 AL_PA 0x63 DHD Login Information lbits:1 alpa5c AL_PA 0x5C DHD Login Information lbits:1 alpa5a AL_PA 0x5A DHD Login Information lbits:1 alpa59 AL_PA 0x59 DHD Login Information lbits:1 alpa56 AL_PA 0x56 DHD Login Information lbits:1 alpa55 AL_PA 0x55 DHD Login Information lbits:1 alpa54 AL_PA 0x54 DHD Login Information lbits:1 alpa53 AL_PA 0x53 DHD Login Information lbits:1 alpa52 AL_PA 0x52 DHD Login Information lbits:1 alpa51 AL_PA 0x51 DHD Login Information

lbits:1 alpa4e AL_PA 0x4E DHD Login Information lbits:1 alpa4d AL_PA 0x4D DHD Login Information lbits:1 alpa4c AL_PA 0x4C DHD Login Information lbits:1 alpa4b AL_PA 0x4B DHD Login Information lbits:1 alpa4a AL_PA 0x4A DHD Login Information lbits:1 alpa49 AL_PA 0x49 DHD Login Information lbits:1 alpa47 AL_PA 0x47 DHD Login Information lbits:1 alpa46 AL_PA 0x46 DHD Login Information lbits:1 alpa45 AL_PA 0x45 DHD Login Information lbits:1 alpa43 AL_PA 0x43 DHD Login Information lbits:1 alpa3c AL_PA 0x3C DHD Login Information {} or dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 12608> ulong value As longword endunion dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1 <byte 12612> union dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 12612> {field (By field)} <byte 12612> lbits:1 alpa3a AL_PA 0x3A DHD Login Information lbits:1 alpa39 AL_PA 0x39 DHD Login Information lbits:1 alpa36 AL_PA 0x36 DHD Login Information lbits:1 alpa35 AL_PA 0x35 DHD Login Information lbits:1 alpa34 AL_PA 0x34 DHD Login Information lbits:1 alpa33 AL_PA 0x33 DHD Login Information lbits:1 alpa32 AL_PA 0x32 DHD Login Information lbits:1 alpa31 AL_PA 0x31 DHD Login Information lbits:1 alpa2e AL_PA 0x2E DHD Login Information lbits:1 alpa2d AL_PA 0x2D DHD Login Information lbits:1 alpa2c AL_PA 0x2C DHD Login Information lbits:1 alpa2b AL_PA 0x2B DHD Login Information lbits:1 alpa2a AL_PA 0x2A DHD Login Information lbits:1 alpa29 AL_PA 0x29 DHD Login Information lbits:1 alpa27 AL_PA 0x27 DHD Login Information lbits:1 alpa26 AL_PA 0x26 DHD Login Information lbits:1 alpa25 AL_PA 0x25 DHD Login Information lbits:1 alpa23 AL_PA 0x23 DHD Login Information lbits:1 alpa1f AL_PA 0x1F DHD Login Information lbits:1 alpa1e AL_PA 0x1E DHD Login Information lbits:1 alpa1d AL_PA 0x1D DHD Login Information lbits:1 alpa1b AL_PA 0x1B DHD Login Information lbits:1 alpa18 AL_PA 0x18 DHD Login Information lbits:1 alpa17 AL_PA 0x17 DHD Login Information lbits:1 alpa10 AL_PA 0x10 DHD Login Information lbits:1 alpa0f AL_PA 0x0F DHD Login Information lbits:1 alpa08 AL_PA 0x08 DHD Login Information lbits:1 alpa04 AL_PA 0x04 DHD Login Information lbits:1 alpa02 AL_PA 0x02 DHD Login Information lbits:1 alpa01 AL_PA 0x01 DHD Login Information lbits:1 alpa00 AL_PA 0x00 DHD Login Information lbits:1 reserved Reserved {} or dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 12612> ulong value As longword endunion dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0 <byte 12616> union fm_config1 (Offset 1C0) Frame Manager Configuration 1

<byte 12616> {field (By field)} <byte 12616> lbits:1 bli Bypass Loop Initialization lbits:1 reserved Reserved lbits:1 enp Enable N_Port Mode lbits:1 lr Login Required lbits:1 inif Initialize as Fabric lbits:1 rf Respond to Fabric Address lbits:1 blm Bypass Loop Map lbits:1 sa Acquire Soft Address lbits:1 ha Acquire Hard Address lbits:1 aq Acquire Previously Acquired Address lbits:1 fa Acquire Fabric Aquired Address lbits:1 td Timer Disable lbits:1 sap Skip Arbitration Phase lbits:1 elb External Loopback/Pad Loopback lbits:1 ilb Internal loopback lbits:1 npi Initialize as N_Port lbits:8 bb_credit BB_Credit lbits:8 al_pa Desired AL_PA {} or fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 12616> ulong value As longword endunion fm_config1 (Offset 1C0) Frame Manager Configuration 1 <byte 12620> union fm_control (Offset 1C4) Frame Manager Control <byte 12620> {field (By field)} <byte 12620> lbits:3 cmd State Machine Command lbits:1 cl Close Loop Request lbits:1 reserved Reserved lbits:1 sp Send Prim_Reg lbits:1 sq Primitive Sequence lbits:25 reserved1 Reserved {} or fm_control (Offset 1C4) Frame Manager Control <byte 12620> ulong value As longword endunion fm_control (Offset 1C4) Frame Manager Control <byte 12624> union fm_status (Offset 1C8) Frame Manager Status <byte 12624> {field (By field)} <byte 12624> lbits:4 psm Port State Machine lbits:4 lsm Loop State Machine lbits:1 ldn Link Down lbits:1 lup Link Up lbits:1 es Elastic Store Error lbits:1 ce Credit Error lbits:1 lf Link Failure lbits:1 lg Login Required lbits:1 ptx Primitive Transmitted lbits:1 prx Primitive Received lbits:1 ba Bad AL_PA lbits:1 lpf LIPf lbits:1 sto State Time-out

lbits:1 ols OLS/NOS Received lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received lbits:1 drs Directed LIP Sequence Received lbits:1 reserved Reserved lbits:1 ls Loss of Signal lbits:1 os Out of Synchronization lbits:1 flt Link Fault lbits:1 reserved1 Reserved lbits:1 byp Node Bypassed lbits:1 np Non-Participating lbits:1 tp Transmit Parity Error lbits:1 lp Loop {} or fm_status (Offset 1C8) Frame Manager Status <byte 12624> ulong value As longword endunion fm_status (Offset 1C8) Frame Manager Status <byte 12628> union fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 12628> {field (By field)} <byte 12628> lbits:16 ed_tov Error Detect Time-Out lbits:9 rt_tov Receiver Transmitter Time-Out lbits:7 reserved Reserved {} or fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 12628> ulong value As longword endunion fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1 <byte 12632> union fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 12632> {field (By field)} <byte 12632> lbits:8 link_fail Link Fail Count lbits:8 loss_of_sync Loss of Synchronization Count lbits:8 bad_rx_char Bad Received Character Count lbits:8 loss_of_signal Loss of Signal Count {} or fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 12632> ulong value As longword endunion fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1 <byte 12636> union fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 12636> {field (By field)} <byte 12636> lbits:8 proto_er Protocol Error Count lbits:8 bad_crc Bad CRC Count lbits:8 dis_frm Discarded Frames lbits:8 rx_eofa Received EOFa {} or fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 12636> ulong value As longword endunion fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2 <byte 12640>

union fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 12640> {field (By field)} <byte 12640> lbits:9 al_time Arbitrated Loop Time-Out lbits:7 reserved Reserved lbits:16 lp_tov Loop Time-Out {} or fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 12640> ulong value As longword endunion fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2 <byte 12644> union fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 12644> {field (By field)} <byte 12644> lbits:24 bb0_timer BB_Credit Timer lbits:8 reserved Reserved {} or fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 12644> ulong value As longword endunion fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer <byte 12648> union fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 12648> {field (By field)} <byte 12648> lbits:32 wwn World Wide Name {} or fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 12648> ulong value As longword endunion fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High <byte 12652> union fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 12652> {field (By field)} <byte 12652> lbits:32 wwn World Wide Name {} or fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 12652> ulong value As longword endunion fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low <byte 12656> union fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 12656> {field (By field)} <byte 12656> lbits:8 lipf_alpa AL_PA of Most Recent LIPf Received lbits:8 bad_alpa AL_PA of Most Recent OPN Sent and Returned Without Being Accept ed lbits:8 acq_alpa AL_PA Acquired During Loop Initialization lbits:8 reserved Reserved {} or fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 12656> ulong value As longword

endunion fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA <byte 12660> union fm_primitive (Offset 1EC) Frame Manager Primitive <byte 12660> {field (By field)} <byte 12660> lbits:24 prim_value Primitive to be Sent lbits:8 reserved Reserved {} or fm_primitive (Offset 1EC) Frame Manager Primitive <byte 12660> ulong value As longword endunion fm_primitive (Offset 1EC) Frame Manager Primitive <byte 12664> union fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 12664> {field (By field)} <byte 12664> lbits:8 exp_frm Expired Frames lbits:24 reserved Reserved {} or fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 12664> ulong value As longword endunion fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3 <byte 12668> union fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 12668> {field (By field)} <byte 12668> lbits:1 dac Disable Auto Close lbits:2 nbc Non-zero Login BB_Credit lbits:1 eei Enable ERR_INIT lbits:1 icb Ignore Close Bit lbits:2 atv Arbitration Threshold Value lbits:1 gde Garbage Deletion Enable lbits:8 laa Lowest Allowable AL_PA lbits:5 reserved Reserved lbits:1 dao Disable 2xAL_TIME Timeout on Open lbits:3 reserved1 Reserved lbits:1 prm Promiscuous Mode lbits:1 wpe Wait For Port Enable lbits:1 fmh Force Monitor State With Hard Address lbits:1 fmn Force Monitor Non-participating State lbits:1 dlm Disable Loop Master lbits:1 dsa Disable Soft Address Selection lbits:1 ilp Ignore LPB/LPE Primitive Sequences {} or fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 12668> ulong value As longword endunion fm_config2 (Offset 1F4) Frame Manager Configuration 2 <byte 12672> union pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED <byte 12672> {field (By field)} <byte 12672> {pci_rsvd1F8 ((Offset 1F8) Reserved)} <byte 12672> utiny value

{} <byte 12673> {pci_rsvd1F9 ((Offset 1F9) Reserved)} <byte 12673> utiny value {} <byte 12674> union romctr (Offset 1FA) PCI ROM Control <byte 12674> {field (By field)} <byte 12674> tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or romctr (Offset 1FA) PCI ROM Control <byte 12674> utiny value As byte endunion romctr (Offset 1FA) PCI ROM Control <byte 12675> union mctr (Offset 1FB) PCI Master Control <byte 12675> {field (By field)} <byte 12675> tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or mctr (Offset 1FB) PCI Master Control <byte 12675> utiny value As byte endunion mctr (Offset 1FB) PCI Master Control {} or pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED <byte 12672> ulong value As longword endunion pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED <byte 12676> union pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST <byte 12676> {field (By field)} <byte 12676> union softrst (Offset 1FC) PCI Interface Reset Control <byte 12676> {field (By field)} <byte 12676> tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or softrst (Offset 1FC) PCI Interface Reset Control <byte 12676> utiny value As byte endunion softrst (Offset 1FC) PCI Interface Reset Control <byte 12677> union intpend (Offset 1FD) PCI Interrupt Pending <byte 12677> {field (By field)} <byte 12677>

tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intpend (Offset 1FD) PCI Interrupt Pending <byte 12677> utiny value As byte endunion intpend (Offset 1FD) PCI Interrupt Pending <byte 12678> union inten (Offset 1FE) PCI Interrupt Enable <byte 12678> {field (By field)} <byte 12678> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or inten (Offset 1FE) PCI Interrupt Enable <byte 12678> utiny value As byte endunion inten (Offset 1FE) PCI Interrupt Enable <byte 12679> union intstat (Offset 1FF) PCI Interrupt Status <byte 12679> {field (By field)} <byte 12679> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or intstat (Offset 1FF) PCI Interrupt Status <byte 12679> utiny value As byte endunion intstat (Offset 1FF) PCI Interrupt Status {} or pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST <byte 12676> ulong value As longword endunion pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST {} endunion csr[11] Tachyon DX2+ CSR Registers <byte 12680> union ncfglo[0] Tachyon DX2+ PCI Non-Configuration Registers Low <byte 12680> ulong[3] ncfgloa Tachyon DX2+ PCI Non-Configuration Registers -- Low As Longword s or ncfglo[0] Tachyon DX2+ PCI Non-Configuration Registers Low <byte 12680> {ncfglo (Tachyon DX2+ PCI Non-Configuration Registers -- Low By Field)} <byte 12680> union ncfglo_fcr (Offset 0x200) Function Control Register

<byte 12680> {field (By field)} <byte 12680> lbits:3 mrbl Maximum Read Burst Length lbits:3 mwbl Maximum Write Burst Length lbits:26 rsvd1 Reserved {} or ncfglo_fcr (Offset 0x200) Function Control Register <byte 12680> ulong value As longword endunion ncfglo_fcr (Offset 0x200) Function Control Register <byte 12684> union ncfglo_fsr (Offset 0x204) Function Status Register <byte 12684> {field (By field)} <byte 12684> lbits:2 sro Split Reads Outstanding lbits:1 ssdr Servicing Split or Delayed Read lbits:1 mie Message Interrupt Error lbits:1 dte Discard Timer Expired lbits:1 rbce Read Byte Count Excessive lbits:1 sbce Split Completion Byte Count Excessive lbits:1 madr59 MADDR5/MADDR9 status on reset deassertion for function_0/function _1 lbits:1 ape Attribute Parity Error lbits:1 peod Parity Error on Outgoing Data lbits:1 peid Parity Error on Incoming Data lbits:1 pesc Parity Error on Split Completion lbits:1 rfe Read fifo Empty lbits:1 rff Read fifo Full lbits:1 wfe Write fifo Empty lbits:1 wff Write fifo Full lbits:1 wfpe Write fifo Parity Error lbits:1 rfpe Read fifo Parity Error lbits:1 npt No Pending Transaction lbits:1 pes Parity Error on Split Related Transaction lbits:1 llos Live Loss of Signal lbits:1 ftl Function Fatal lbits:10 reserved Reserved {} or ncfglo_fsr (Offset 0x204) Function Status Register <byte 12684> ulong value As longword endunion ncfglo_fsr (Offset 0x204) Function Status Register <byte 12688> union ncfglo_escr (Offset 0x208) Error Split Completion Register <byte 12688> {field (By field)} <byte 12688> lbits:12 rbc Remaining Byte Count lbits:7 rla Remaining Lower Address lbits:1 reserved Reserved lbits:8 mi Message Index lbits:4 mc Message Class {} or ncfglo_escr (Offset 0x208) Error Split Completion Register <byte 12688> ulong value As longword endunion ncfglo_escr (Offset 0x208) Error Split Completion Register {}

endunion ncfglo[0] Tachyon DX2+ PCI Non-Configuration Registers Low <byte 12692> union ncfglo[1] Tachyon DX2+ PCI Non-Configuration Registers Low <byte 12692> ulong[3] ncfgloa Tachyon DX2+ PCI Non-Configuration Registers -- Low As Longword s or ncfglo[1] Tachyon DX2+ PCI Non-Configuration Registers Low <byte 12692> {ncfglo (Tachyon DX2+ PCI Non-Configuration Registers -- Low By Field)} <byte 12692> union ncfglo_fcr (Offset 0x200) Function Control Register <byte 12692> {field (By field)} <byte 12692> lbits:3 mrbl Maximum Read Burst Length lbits:3 mwbl Maximum Write Burst Length lbits:26 rsvd1 Reserved {} or ncfglo_fcr (Offset 0x200) Function Control Register <byte 12692> ulong value As longword endunion ncfglo_fcr (Offset 0x200) Function Control Register <byte 12696> union ncfglo_fsr (Offset 0x204) Function Status Register <byte 12696> {field (By field)} <byte 12696> lbits:2 sro Split Reads Outstanding lbits:1 ssdr Servicing Split or Delayed Read lbits:1 mie Message Interrupt Error lbits:1 dte Discard Timer Expired lbits:1 rbce Read Byte Count Excessive lbits:1 sbce Split Completion Byte Count Excessive lbits:1 madr59 MADDR5/MADDR9 status on reset deassertion for function_0/function _1 lbits:1 ape Attribute Parity Error lbits:1 peod Parity Error on Outgoing Data lbits:1 peid Parity Error on Incoming Data lbits:1 pesc Parity Error on Split Completion lbits:1 rfe Read fifo Empty lbits:1 rff Read fifo Full lbits:1 wfe Write fifo Empty lbits:1 wff Write fifo Full lbits:1 wfpe Write fifo Parity Error lbits:1 rfpe Read fifo Parity Error lbits:1 npt No Pending Transaction lbits:1 pes Parity Error on Split Related Transaction lbits:1 llos Live Loss of Signal lbits:1 ftl Function Fatal lbits:10 reserved Reserved {} or ncfglo_fsr (Offset 0x204) Function Status Register <byte 12696> ulong value As longword endunion ncfglo_fsr (Offset 0x204) Function Status Register <byte 12700> union ncfglo_escr (Offset 0x208) Error Split Completion Register <byte 12700> {field (By field)} <byte 12700>

lbits:12 rbc Remaining Byte Count lbits:7 rla Remaining Lower Address lbits:1 reserved Reserved lbits:8 mi Message Index lbits:4 mc Message Class {} or ncfglo_escr (Offset 0x208) Error Split Completion Register <byte 12700> ulong value As longword endunion ncfglo_escr (Offset 0x208) Error Split Completion Register {} endunion ncfglo[1] Tachyon DX2+ PCI Non-Configuration Registers Low <byte 12704> union ncfglo[2] Tachyon DX2+ PCI Non-Configuration Registers Low <byte 12704> ulong[3] ncfgloa Tachyon DX2+ PCI Non-Configuration Registers -- Low As Longword s or ncfglo[2] Tachyon DX2+ PCI Non-Configuration Registers Low <byte 12704> {ncfglo (Tachyon DX2+ PCI Non-Configuration Registers -- Low By Field)} <byte 12704> union ncfglo_fcr (Offset 0x200) Function Control Register <byte 12704> {field (By field)} <byte 12704> lbits:3 mrbl Maximum Read Burst Length lbits:3 mwbl Maximum Write Burst Length lbits:26 rsvd1 Reserved {} or ncfglo_fcr (Offset 0x200) Function Control Register <byte 12704> ulong value As longword endunion ncfglo_fcr (Offset 0x200) Function Control Register <byte 12708> union ncfglo_fsr (Offset 0x204) Function Status Register <byte 12708> {field (By field)} <byte 12708> lbits:2 sro Split Reads Outstanding lbits:1 ssdr Servicing Split or Delayed Read lbits:1 mie Message Interrupt Error lbits:1 dte Discard Timer Expired lbits:1 rbce Read Byte Count Excessive lbits:1 sbce Split Completion Byte Count Excessive lbits:1 madr59 MADDR5/MADDR9 status on reset deassertion for function_0/function _1 lbits:1 ape Attribute Parity Error lbits:1 peod Parity Error on Outgoing Data lbits:1 peid Parity Error on Incoming Data lbits:1 pesc Parity Error on Split Completion lbits:1 rfe Read fifo Empty lbits:1 rff Read fifo Full lbits:1 wfe Write fifo Empty lbits:1 wff Write fifo Full lbits:1 wfpe Write fifo Parity Error lbits:1 rfpe Read fifo Parity Error lbits:1 npt No Pending Transaction lbits:1 pes Parity Error on Split Related Transaction lbits:1 llos Live Loss of Signal lbits:1 ftl Function Fatal

lbits:10 reserved Reserved {} or ncfglo_fsr (Offset 0x204) Function Status Register <byte 12708> ulong value As longword endunion ncfglo_fsr (Offset 0x204) Function Status Register <byte 12712> union ncfglo_escr (Offset 0x208) Error Split Completion Register <byte 12712> {field (By field)} <byte 12712> lbits:12 rbc Remaining Byte Count lbits:7 rla Remaining Lower Address lbits:1 reserved Reserved lbits:8 mi Message Index lbits:4 mc Message Class {} or ncfglo_escr (Offset 0x208) Error Split Completion Register <byte 12712> ulong value As longword endunion ncfglo_escr (Offset 0x208) Error Split Completion Register {} endunion ncfglo[2] Tachyon DX2+ PCI Non-Configuration Registers Low <byte 12716> union ncfglo[3] Tachyon DX2+ PCI Non-Configuration Registers Low <byte 12716> ulong[3] ncfgloa Tachyon DX2+ PCI Non-Configuration Registers -- Low As Longword s or ncfglo[3] Tachyon DX2+ PCI Non-Configuration Registers Low <byte 12716> {ncfglo (Tachyon DX2+ PCI Non-Configuration Registers -- Low By Field)} <byte 12716> union ncfglo_fcr (Offset 0x200) Function Control Register <byte 12716> {field (By field)} <byte 12716> lbits:3 mrbl Maximum Read Burst Length lbits:3 mwbl Maximum Write Burst Length lbits:26 rsvd1 Reserved {} or ncfglo_fcr (Offset 0x200) Function Control Register <byte 12716> ulong value As longword endunion ncfglo_fcr (Offset 0x200) Function Control Register <byte 12720> union ncfglo_fsr (Offset 0x204) Function Status Register <byte 12720> {field (By field)} <byte 12720> lbits:2 sro Split Reads Outstanding lbits:1 ssdr Servicing Split or Delayed Read lbits:1 mie Message Interrupt Error lbits:1 dte Discard Timer Expired lbits:1 rbce Read Byte Count Excessive lbits:1 sbce Split Completion Byte Count Excessive lbits:1 madr59 MADDR5/MADDR9 status on reset deassertion for function_0/function _1 lbits:1 ape Attribute Parity Error lbits:1 peod Parity Error on Outgoing Data lbits:1 peid Parity Error on Incoming Data

lbits:1 pesc Parity Error on Split Completion lbits:1 rfe Read fifo Empty lbits:1 rff Read fifo Full lbits:1 wfe Write fifo Empty lbits:1 wff Write fifo Full lbits:1 wfpe Write fifo Parity Error lbits:1 rfpe Read fifo Parity Error lbits:1 npt No Pending Transaction lbits:1 pes Parity Error on Split Related Transaction lbits:1 llos Live Loss of Signal lbits:1 ftl Function Fatal lbits:10 reserved Reserved {} or ncfglo_fsr (Offset 0x204) Function Status Register <byte 12720> ulong value As longword endunion ncfglo_fsr (Offset 0x204) Function Status Register <byte 12724> union ncfglo_escr (Offset 0x208) Error Split Completion Register <byte 12724> {field (By field)} <byte 12724> lbits:12 rbc Remaining Byte Count lbits:7 rla Remaining Lower Address lbits:1 reserved Reserved lbits:8 mi Message Index lbits:4 mc Message Class {} or ncfglo_escr (Offset 0x208) Error Split Completion Register <byte 12724> ulong value As longword endunion ncfglo_escr (Offset 0x208) Error Split Completion Register {} endunion ncfglo[3] Tachyon DX2+ PCI Non-Configuration Registers Low <byte 12728> union ncfglo[4] Tachyon DX2+ PCI Non-Configuration Registers Low <byte 12728> ulong[3] ncfgloa Tachyon DX2+ PCI Non-Configuration Registers -- Low As Longword s or ncfglo[4] Tachyon DX2+ PCI Non-Configuration Registers Low <byte 12728> {ncfglo (Tachyon DX2+ PCI Non-Configuration Registers -- Low By Field)} <byte 12728> union ncfglo_fcr (Offset 0x200) Function Control Register <byte 12728> {field (By field)} <byte 12728> lbits:3 mrbl Maximum Read Burst Length lbits:3 mwbl Maximum Write Burst Length lbits:26 rsvd1 Reserved {} or ncfglo_fcr (Offset 0x200) Function Control Register <byte 12728> ulong value As longword endunion ncfglo_fcr (Offset 0x200) Function Control Register <byte 12732> union ncfglo_fsr (Offset 0x204) Function Status Register <byte 12732> {field (By field)} <byte 12732>

lbits:2 sro Split Reads Outstanding lbits:1 ssdr Servicing Split or Delayed Read lbits:1 mie Message Interrupt Error lbits:1 dte Discard Timer Expired lbits:1 rbce Read Byte Count Excessive lbits:1 sbce Split Completion Byte Count Excessive lbits:1 madr59 MADDR5/MADDR9 status on reset deassertion for function_0/function _1 lbits:1 ape Attribute Parity Error lbits:1 peod Parity Error on Outgoing Data lbits:1 peid Parity Error on Incoming Data lbits:1 pesc Parity Error on Split Completion lbits:1 rfe Read fifo Empty lbits:1 rff Read fifo Full lbits:1 wfe Write fifo Empty lbits:1 wff Write fifo Full lbits:1 wfpe Write fifo Parity Error lbits:1 rfpe Read fifo Parity Error lbits:1 npt No Pending Transaction lbits:1 pes Parity Error on Split Related Transaction lbits:1 llos Live Loss of Signal lbits:1 ftl Function Fatal lbits:10 reserved Reserved {} or ncfglo_fsr (Offset 0x204) Function Status Register <byte 12732> ulong value As longword endunion ncfglo_fsr (Offset 0x204) Function Status Register <byte 12736> union ncfglo_escr (Offset 0x208) Error Split Completion Register <byte 12736> {field (By field)} <byte 12736> lbits:12 rbc Remaining Byte Count lbits:7 rla Remaining Lower Address lbits:1 reserved Reserved lbits:8 mi Message Index lbits:4 mc Message Class {} or ncfglo_escr (Offset 0x208) Error Split Completion Register <byte 12736> ulong value As longword endunion ncfglo_escr (Offset 0x208) Error Split Completion Register {} endunion ncfglo[4] Tachyon DX2+ PCI Non-Configuration Registers Low <byte 12740> union ncfglo[5] Tachyon DX2+ PCI Non-Configuration Registers Low <byte 12740> ulong[3] ncfgloa Tachyon DX2+ PCI Non-Configuration Registers -- Low As Longword s or ncfglo[5] Tachyon DX2+ PCI Non-Configuration Registers Low <byte 12740> {ncfglo (Tachyon DX2+ PCI Non-Configuration Registers -- Low By Field)} <byte 12740> union ncfglo_fcr (Offset 0x200) Function Control Register <byte 12740> {field (By field)} <byte 12740> lbits:3 mrbl Maximum Read Burst Length lbits:3 mwbl Maximum Write Burst Length

lbits:26 rsvd1 Reserved {} or ncfglo_fcr (Offset 0x200) Function Control Register <byte 12740> ulong value As longword endunion ncfglo_fcr (Offset 0x200) Function Control Register <byte 12744> union ncfglo_fsr (Offset 0x204) Function Status Register <byte 12744> {field (By field)} <byte 12744> lbits:2 sro Split Reads Outstanding lbits:1 ssdr Servicing Split or Delayed Read lbits:1 mie Message Interrupt Error lbits:1 dte Discard Timer Expired lbits:1 rbce Read Byte Count Excessive lbits:1 sbce Split Completion Byte Count Excessive lbits:1 madr59 MADDR5/MADDR9 status on reset deassertion for function_0/function _1 lbits:1 ape Attribute Parity Error lbits:1 peod Parity Error on Outgoing Data lbits:1 peid Parity Error on Incoming Data lbits:1 pesc Parity Error on Split Completion lbits:1 rfe Read fifo Empty lbits:1 rff Read fifo Full lbits:1 wfe Write fifo Empty lbits:1 wff Write fifo Full lbits:1 wfpe Write fifo Parity Error lbits:1 rfpe Read fifo Parity Error lbits:1 npt No Pending Transaction lbits:1 pes Parity Error on Split Related Transaction lbits:1 llos Live Loss of Signal lbits:1 ftl Function Fatal lbits:10 reserved Reserved {} or ncfglo_fsr (Offset 0x204) Function Status Register <byte 12744> ulong value As longword endunion ncfglo_fsr (Offset 0x204) Function Status Register <byte 12748> union ncfglo_escr (Offset 0x208) Error Split Completion Register <byte 12748> {field (By field)} <byte 12748> lbits:12 rbc Remaining Byte Count lbits:7 rla Remaining Lower Address lbits:1 reserved Reserved lbits:8 mi Message Index lbits:4 mc Message Class {} or ncfglo_escr (Offset 0x208) Error Split Completion Register <byte 12748> ulong value As longword endunion ncfglo_escr (Offset 0x208) Error Split Completion Register {} endunion ncfglo[5] Tachyon DX2+ PCI Non-Configuration Registers Low <byte 12752> union ncfglo[6] Tachyon DX2+ PCI Non-Configuration Registers Low <byte 12752> ulong[3] ncfgloa Tachyon DX2+ PCI Non-Configuration Registers -- Low As Longword

s or ncfglo[6] Tachyon DX2+ PCI Non-Configuration Registers Low <byte 12752> {ncfglo (Tachyon DX2+ PCI Non-Configuration Registers -- Low By Field)} <byte 12752> union ncfglo_fcr (Offset 0x200) Function Control Register <byte 12752> {field (By field)} <byte 12752> lbits:3 mrbl Maximum Read Burst Length lbits:3 mwbl Maximum Write Burst Length lbits:26 rsvd1 Reserved {} or ncfglo_fcr (Offset 0x200) Function Control Register <byte 12752> ulong value As longword endunion ncfglo_fcr (Offset 0x200) Function Control Register <byte 12756> union ncfglo_fsr (Offset 0x204) Function Status Register <byte 12756> {field (By field)} <byte 12756> lbits:2 sro Split Reads Outstanding lbits:1 ssdr Servicing Split or Delayed Read lbits:1 mie Message Interrupt Error lbits:1 dte Discard Timer Expired lbits:1 rbce Read Byte Count Excessive lbits:1 sbce Split Completion Byte Count Excessive lbits:1 madr59 MADDR5/MADDR9 status on reset deassertion for function_0/function _1 lbits:1 ape Attribute Parity Error lbits:1 peod Parity Error on Outgoing Data lbits:1 peid Parity Error on Incoming Data lbits:1 pesc Parity Error on Split Completion lbits:1 rfe Read fifo Empty lbits:1 rff Read fifo Full lbits:1 wfe Write fifo Empty lbits:1 wff Write fifo Full lbits:1 wfpe Write fifo Parity Error lbits:1 rfpe Read fifo Parity Error lbits:1 npt No Pending Transaction lbits:1 pes Parity Error on Split Related Transaction lbits:1 llos Live Loss of Signal lbits:1 ftl Function Fatal lbits:10 reserved Reserved {} or ncfglo_fsr (Offset 0x204) Function Status Register <byte 12756> ulong value As longword endunion ncfglo_fsr (Offset 0x204) Function Status Register <byte 12760> union ncfglo_escr (Offset 0x208) Error Split Completion Register <byte 12760> {field (By field)} <byte 12760> lbits:12 rbc Remaining Byte Count lbits:7 rla Remaining Lower Address lbits:1 reserved Reserved lbits:8 mi Message Index lbits:4 mc Message Class

{} or ncfglo_escr (Offset 0x208) Error Split Completion Register <byte 12760> ulong value As longword endunion ncfglo_escr (Offset 0x208) Error Split Completion Register {} endunion ncfglo[6] Tachyon DX2+ PCI Non-Configuration Registers Low <byte 12764> union ncfglo[7] Tachyon DX2+ PCI Non-Configuration Registers Low <byte 12764> ulong[3] ncfgloa Tachyon DX2+ PCI Non-Configuration Registers -- Low As Longword s or ncfglo[7] Tachyon DX2+ PCI Non-Configuration Registers Low <byte 12764> {ncfglo (Tachyon DX2+ PCI Non-Configuration Registers -- Low By Field)} <byte 12764> union ncfglo_fcr (Offset 0x200) Function Control Register <byte 12764> {field (By field)} <byte 12764> lbits:3 mrbl Maximum Read Burst Length lbits:3 mwbl Maximum Write Burst Length lbits:26 rsvd1 Reserved {} or ncfglo_fcr (Offset 0x200) Function Control Register <byte 12764> ulong value As longword endunion ncfglo_fcr (Offset 0x200) Function Control Register <byte 12768> union ncfglo_fsr (Offset 0x204) Function Status Register <byte 12768> {field (By field)} <byte 12768> lbits:2 sro Split Reads Outstanding lbits:1 ssdr Servicing Split or Delayed Read lbits:1 mie Message Interrupt Error lbits:1 dte Discard Timer Expired lbits:1 rbce Read Byte Count Excessive lbits:1 sbce Split Completion Byte Count Excessive lbits:1 madr59 MADDR5/MADDR9 status on reset deassertion for function_0/function _1 lbits:1 ape Attribute Parity Error lbits:1 peod Parity Error on Outgoing Data lbits:1 peid Parity Error on Incoming Data lbits:1 pesc Parity Error on Split Completion lbits:1 rfe Read fifo Empty lbits:1 rff Read fifo Full lbits:1 wfe Write fifo Empty lbits:1 wff Write fifo Full lbits:1 wfpe Write fifo Parity Error lbits:1 rfpe Read fifo Parity Error lbits:1 npt No Pending Transaction lbits:1 pes Parity Error on Split Related Transaction lbits:1 llos Live Loss of Signal lbits:1 ftl Function Fatal lbits:10 reserved Reserved {} or ncfglo_fsr (Offset 0x204) Function Status Register <byte 12768> ulong value As longword

endunion ncfglo_fsr (Offset 0x204) Function Status Register <byte 12772> union ncfglo_escr (Offset 0x208) Error Split Completion Register <byte 12772> {field (By field)} <byte 12772> lbits:12 rbc Remaining Byte Count lbits:7 rla Remaining Lower Address lbits:1 reserved Reserved lbits:8 mi Message Index lbits:4 mc Message Class {} or ncfglo_escr (Offset 0x208) Error Split Completion Register <byte 12772> ulong value As longword endunion ncfglo_escr (Offset 0x208) Error Split Completion Register {} endunion ncfglo[7] Tachyon DX2+ PCI Non-Configuration Registers Low <byte 12776> union ncfglo[8] Tachyon DX2+ PCI Non-Configuration Registers Low <byte 12776> ulong[3] ncfgloa Tachyon DX2+ PCI Non-Configuration Registers -- Low As Longword s or ncfglo[8] Tachyon DX2+ PCI Non-Configuration Registers Low <byte 12776> {ncfglo (Tachyon DX2+ PCI Non-Configuration Registers -- Low By Field)} <byte 12776> union ncfglo_fcr (Offset 0x200) Function Control Register <byte 12776> {field (By field)} <byte 12776> lbits:3 mrbl Maximum Read Burst Length lbits:3 mwbl Maximum Write Burst Length lbits:26 rsvd1 Reserved {} or ncfglo_fcr (Offset 0x200) Function Control Register <byte 12776> ulong value As longword endunion ncfglo_fcr (Offset 0x200) Function Control Register <byte 12780> union ncfglo_fsr (Offset 0x204) Function Status Register <byte 12780> {field (By field)} <byte 12780> lbits:2 sro Split Reads Outstanding lbits:1 ssdr Servicing Split or Delayed Read lbits:1 mie Message Interrupt Error lbits:1 dte Discard Timer Expired lbits:1 rbce Read Byte Count Excessive lbits:1 sbce Split Completion Byte Count Excessive lbits:1 madr59 MADDR5/MADDR9 status on reset deassertion for function_0/function _1 lbits:1 ape Attribute Parity Error lbits:1 peod Parity Error on Outgoing Data lbits:1 peid Parity Error on Incoming Data lbits:1 pesc Parity Error on Split Completion lbits:1 rfe Read fifo Empty lbits:1 rff Read fifo Full lbits:1 wfe Write fifo Empty lbits:1 wff Write fifo Full

lbits:1 wfpe Write fifo Parity Error lbits:1 rfpe Read fifo Parity Error lbits:1 npt No Pending Transaction lbits:1 pes Parity Error on Split Related Transaction lbits:1 llos Live Loss of Signal lbits:1 ftl Function Fatal lbits:10 reserved Reserved {} or ncfglo_fsr (Offset 0x204) Function Status Register <byte 12780> ulong value As longword endunion ncfglo_fsr (Offset 0x204) Function Status Register <byte 12784> union ncfglo_escr (Offset 0x208) Error Split Completion Register <byte 12784> {field (By field)} <byte 12784> lbits:12 rbc Remaining Byte Count lbits:7 rla Remaining Lower Address lbits:1 reserved Reserved lbits:8 mi Message Index lbits:4 mc Message Class {} or ncfglo_escr (Offset 0x208) Error Split Completion Register <byte 12784> ulong value As longword endunion ncfglo_escr (Offset 0x208) Error Split Completion Register {} endunion ncfglo[8] Tachyon DX2+ PCI Non-Configuration Registers Low <byte 12788> union ncfglo[9] Tachyon DX2+ PCI Non-Configuration Registers Low <byte 12788> ulong[3] ncfgloa Tachyon DX2+ PCI Non-Configuration Registers -- Low As Longword s or ncfglo[9] Tachyon DX2+ PCI Non-Configuration Registers Low <byte 12788> {ncfglo (Tachyon DX2+ PCI Non-Configuration Registers -- Low By Field)} <byte 12788> union ncfglo_fcr (Offset 0x200) Function Control Register <byte 12788> {field (By field)} <byte 12788> lbits:3 mrbl Maximum Read Burst Length lbits:3 mwbl Maximum Write Burst Length lbits:26 rsvd1 Reserved {} or ncfglo_fcr (Offset 0x200) Function Control Register <byte 12788> ulong value As longword endunion ncfglo_fcr (Offset 0x200) Function Control Register <byte 12792> union ncfglo_fsr (Offset 0x204) Function Status Register <byte 12792> {field (By field)} <byte 12792> lbits:2 sro Split Reads Outstanding lbits:1 ssdr Servicing Split or Delayed Read lbits:1 mie Message Interrupt Error lbits:1 dte Discard Timer Expired lbits:1 rbce Read Byte Count Excessive

lbits:1 sbce Split Completion Byte Count Excessive lbits:1 madr59 MADDR5/MADDR9 status on reset deassertion for function_0/function _1 lbits:1 ape Attribute Parity Error lbits:1 peod Parity Error on Outgoing Data lbits:1 peid Parity Error on Incoming Data lbits:1 pesc Parity Error on Split Completion lbits:1 rfe Read fifo Empty lbits:1 rff Read fifo Full lbits:1 wfe Write fifo Empty lbits:1 wff Write fifo Full lbits:1 wfpe Write fifo Parity Error lbits:1 rfpe Read fifo Parity Error lbits:1 npt No Pending Transaction lbits:1 pes Parity Error on Split Related Transaction lbits:1 llos Live Loss of Signal lbits:1 ftl Function Fatal lbits:10 reserved Reserved {} or ncfglo_fsr (Offset 0x204) Function Status Register <byte 12792> ulong value As longword endunion ncfglo_fsr (Offset 0x204) Function Status Register <byte 12796> union ncfglo_escr (Offset 0x208) Error Split Completion Register <byte 12796> {field (By field)} <byte 12796> lbits:12 rbc Remaining Byte Count lbits:7 rla Remaining Lower Address lbits:1 reserved Reserved lbits:8 mi Message Index lbits:4 mc Message Class {} or ncfglo_escr (Offset 0x208) Error Split Completion Register <byte 12796> ulong value As longword endunion ncfglo_escr (Offset 0x208) Error Split Completion Register {} endunion ncfglo[9] Tachyon DX2+ PCI Non-Configuration Registers Low <byte 12800> union ncfglo[10] Tachyon DX2+ PCI Non-Configuration Registers Low <byte 12800> ulong[3] ncfgloa Tachyon DX2+ PCI Non-Configuration Registers -- Low As Longword s or ncfglo[10] Tachyon DX2+ PCI Non-Configuration Registers Low <byte 12800> {ncfglo (Tachyon DX2+ PCI Non-Configuration Registers -- Low By Field)} <byte 12800> union ncfglo_fcr (Offset 0x200) Function Control Register <byte 12800> {field (By field)} <byte 12800> lbits:3 mrbl Maximum Read Burst Length lbits:3 mwbl Maximum Write Burst Length lbits:26 rsvd1 Reserved {} or ncfglo_fcr (Offset 0x200) Function Control Register <byte 12800> ulong value As longword

endunion ncfglo_fcr (Offset 0x200) Function Control Register <byte 12804> union ncfglo_fsr (Offset 0x204) Function Status Register <byte 12804> {field (By field)} <byte 12804> lbits:2 sro Split Reads Outstanding lbits:1 ssdr Servicing Split or Delayed Read lbits:1 mie Message Interrupt Error lbits:1 dte Discard Timer Expired lbits:1 rbce Read Byte Count Excessive lbits:1 sbce Split Completion Byte Count Excessive lbits:1 madr59 MADDR5/MADDR9 status on reset deassertion for function_0/function _1 lbits:1 ape Attribute Parity Error lbits:1 peod Parity Error on Outgoing Data lbits:1 peid Parity Error on Incoming Data lbits:1 pesc Parity Error on Split Completion lbits:1 rfe Read fifo Empty lbits:1 rff Read fifo Full lbits:1 wfe Write fifo Empty lbits:1 wff Write fifo Full lbits:1 wfpe Write fifo Parity Error lbits:1 rfpe Read fifo Parity Error lbits:1 npt No Pending Transaction lbits:1 pes Parity Error on Split Related Transaction lbits:1 llos Live Loss of Signal lbits:1 ftl Function Fatal lbits:10 reserved Reserved {} or ncfglo_fsr (Offset 0x204) Function Status Register <byte 12804> ulong value As longword endunion ncfglo_fsr (Offset 0x204) Function Status Register <byte 12808> union ncfglo_escr (Offset 0x208) Error Split Completion Register <byte 12808> {field (By field)} <byte 12808> lbits:12 rbc Remaining Byte Count lbits:7 rla Remaining Lower Address lbits:1 reserved Reserved lbits:8 mi Message Index lbits:4 mc Message Class {} or ncfglo_escr (Offset 0x208) Error Split Completion Register <byte 12808> ulong value As longword endunion ncfglo_escr (Offset 0x208) Error Split Completion Register {} endunion ncfglo[10] Tachyon DX2+ PCI Non-Configuration Registers Low <byte 12812> union ncfglo[11] Tachyon DX2+ PCI Non-Configuration Registers Low <byte 12812> ulong[3] ncfgloa Tachyon DX2+ PCI Non-Configuration Registers -- Low As Longword s or ncfglo[11] Tachyon DX2+ PCI Non-Configuration Registers Low <byte 12812> {ncfglo (Tachyon DX2+ PCI Non-Configuration Registers -- Low By Field)} <byte 12812>

union ncfglo_fcr (Offset 0x200) Function Control Register <byte 12812> {field (By field)} <byte 12812> lbits:3 mrbl Maximum Read Burst Length lbits:3 mwbl Maximum Write Burst Length lbits:26 rsvd1 Reserved {} or ncfglo_fcr (Offset 0x200) Function Control Register <byte 12812> ulong value As longword endunion ncfglo_fcr (Offset 0x200) Function Control Register <byte 12816> union ncfglo_fsr (Offset 0x204) Function Status Register <byte 12816> {field (By field)} <byte 12816> lbits:2 sro Split Reads Outstanding lbits:1 ssdr Servicing Split or Delayed Read lbits:1 mie Message Interrupt Error lbits:1 dte Discard Timer Expired lbits:1 rbce Read Byte Count Excessive lbits:1 sbce Split Completion Byte Count Excessive lbits:1 madr59 MADDR5/MADDR9 status on reset deassertion for function_0/function _1 lbits:1 ape Attribute Parity Error lbits:1 peod Parity Error on Outgoing Data lbits:1 peid Parity Error on Incoming Data lbits:1 pesc Parity Error on Split Completion lbits:1 rfe Read fifo Empty lbits:1 rff Read fifo Full lbits:1 wfe Write fifo Empty lbits:1 wff Write fifo Full lbits:1 wfpe Write fifo Parity Error lbits:1 rfpe Read fifo Parity Error lbits:1 npt No Pending Transaction lbits:1 pes Parity Error on Split Related Transaction lbits:1 llos Live Loss of Signal lbits:1 ftl Function Fatal lbits:10 reserved Reserved {} or ncfglo_fsr (Offset 0x204) Function Status Register <byte 12816> ulong value As longword endunion ncfglo_fsr (Offset 0x204) Function Status Register <byte 12820> union ncfglo_escr (Offset 0x208) Error Split Completion Register <byte 12820> {field (By field)} <byte 12820> lbits:12 rbc Remaining Byte Count lbits:7 rla Remaining Lower Address lbits:1 reserved Reserved lbits:8 mi Message Index lbits:4 mc Message Class {} or ncfglo_escr (Offset 0x208) Error Split Completion Register <byte 12820> ulong value As longword endunion ncfglo_escr (Offset 0x208) Error Split Completion Register

{} endunion ncfglo[11] Tachyon DX2+ PCI Non-Configuration Registers Low <byte 12824> union pcicfg[0] Tachyon DX2+ PCI Configuration Registers <byte 12824> ulong[31] pcicfga Tachyon DX2+ PCI Configuration Registers As Longwords or pcicfg[0] Tachyon DX2+ PCI Configuration Registers <byte 12824> {pcicfg (Tachyon DX2+ PCI Configuration Registers By Field)} <byte 12824> union pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID <byte 12824> {field (By field)} <byte 12824> union pci_vendor_id (Offset 00) PCI Vendor ID <byte 12824> {field (By field)} <byte 12824> bits:16 id ID {} or pci_vendor_id (Offset 00) PCI Vendor ID <byte 12824> ushort value As word endunion pci_vendor_id (Offset 00) PCI Vendor ID <byte 12826> union pci_device_id (Offset 02) PCI Device ID <byte 12826> {field (By field)} <byte 12826> bits:16 id ID {} or pci_device_id (Offset 02) PCI Device ID <byte 12826> ushort value As word endunion pci_device_id (Offset 02) PCI Device ID {} or pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID <byte 12824> ulong value As longword endunion pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID <byte 12828> union pcicfg_reg_04 (Offset 04) PCI CMD/STATUS <byte 12828> {field (By field)} <byte 12828> union pci_cmd (Offset 04) PCI Command <byte 12828> {field (By field)} <byte 12828> bits:1 io_access I/O Access Control bits:1 mem_access Memory Access Control bits:1 pcim_en PCI Master Enable bits:1 scycle_en Special Cycle Enable (read only, always returns 0) bits:1 memwinv Memory Write & Invalidate bits:1 paltsnp_en Palette Snooping Enable (read only, always returns 0) bits:1 perrrsp Parity Error Response bits:1 waitcycctrl Wait Cycle Control bits:1 serrx_en SERR# Enable bits:1 fbbw_en Fast Back-to-Back Write enable (read only, always returns 0) bits:6 rsvd Reserved

{} or pci_cmd (Offset 04) PCI Command <byte 12828> ushort value As word endunion pci_cmd (Offset 04) PCI Command <byte 12830> union pci_status (Offset 06) PCI Status <byte 12830> {field (By field)} <byte 12830> bits:4 rsvd Reserved bits:1 cpl New Capabilities bits:1 cap66mhz 66MHz Capable bits:1 udfsup UDF Supported (read only, always returns 0) bits:1 capfbbw Fast Back-to-Back Capable (read only, always returns 0) bits:1 dperr Data Parity Error Detected bits:2 devsel_time PCI_DEVSEL# response timing (read only, always returns 1) bits:1 sgnltabrt Signaled Target Abort bits:1 rcvdtabrt Received Target Abort bits:1 rcvdmabrt Received Master Abort bits:1 sgnlsyserr Signaled System Error bits:1 perr Detected Parity Error {} or pci_status (Offset 06) PCI Status <byte 12830> ushort value As word endunion pci_status (Offset 06) PCI Status {} or pcicfg_reg_04 (Offset 04) PCI CMD/STATUS <byte 12828> ulong value As longword endunion pcicfg_reg_04 (Offset 04) PCI CMD/STATUS <byte 12832> union pcicfg_reg_08 (Offset 08) PCI REVID/CLASS <byte 12832> {field (By field)} <byte 12832> union pci_revid (Offset 08) PCI Revision <byte 12832> {field (By field)} <byte 12832> tbits:2 minor Minor tbits:3 major Major tbits:3 res Reserved {} or pci_revid (Offset 08) PCI Revision <byte 12832> utiny value As byte endunion pci_revid (Offset 08) PCI Revision <byte 12833> union pci_class (Offset 09) PCI Class <byte 12833> {field (By field)} <byte 12833> tbits:8 baseclcode Base Class Code <byte 12834> tbits:8 subclcode Subclass Code <byte 12835> tbits:8 reglevpi Register Level Programming Interface {}

or pci_class (Offset 09) PCI Class <byte 12833> utiny[3] value As byte array endunion pci_class (Offset 09) PCI Class {} or pcicfg_reg_08 (Offset 08) PCI REVID/CLASS <byte 12832> ulong value As longword endunion pcicfg_reg_08 (Offset 08) PCI REVID/CLASS <byte 12836> union pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST <byte 12836> {field (By field)} <byte 12836> union pci_clsize (Offset 0C) PCI Cache Line Size <byte 12836> {field (By field)} <byte 12836> tbits:8 size PCI cache line size {} or pci_clsize (Offset 0C) PCI Cache Line Size <byte 12836> utiny value As byte endunion pci_clsize (Offset 0C) PCI Cache Line Size <byte 12837> union pci_lattmr (Offset 0D) PCI Latency Timer <byte 12837> {field (By field)} <byte 12837> tbits:8 tmr PCI latency timer {} or pci_lattmr (Offset 0D) PCI Latency Timer <byte 12837> utiny value As byte endunion pci_lattmr (Offset 0D) PCI Latency Timer <byte 12838> union pci_hdrtype (Offset 0E) PCI Header Type <byte 12838> {field (By field)} <byte 12838> tbits:8 type PCI header type (read only) {} or pci_hdrtype (Offset 0E) PCI Header Type <byte 12838> utiny value As byte endunion pci_hdrtype (Offset 0E) PCI Header Type <byte 12839> {pci_rsvd0f ((Offset 0F) Reserved (BIST))} <byte 12839> utiny value {} {} or pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST <byte 12836> ulong value As longword endunion pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST <byte 12840> {pci_rsvd10_13 ((Offset 10) Reserved (RSVBAR))} <byte 12840> ulong value

{} <byte 12844> {pci_rsvd14_17 ((Offset 14) Reserved (RSVBAR))} <byte 12844> ulong value {} <byte 12848> union pci_iobasel (Offset 18) PCI Lower I/O Base Address <byte 12848> {field (By field)} <byte 12848> lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobasel (Offset 18) PCI Lower I/O Base Address <byte 12848> ulong value As longword endunion pci_iobasel (Offset 18) PCI Lower I/O Base Address <byte 12852> union pci_iobaseu (Offset 1C) PCI Upper I/O Base Address <byte 12852> {field (By field)} <byte 12852> lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobaseu (Offset 1C) PCI Upper I/O Base Address <byte 12852> ulong value As longword endunion pci_iobaseu (Offset 1C) PCI Upper I/O Base Address <byte 12856> union pci_membasel (Offset 20) PCI Lower Memory Address Base <byte 12856> {field (By field)} <byte 12856> lbits:1 memspace Memory Space Indicator lbits:2 loctype Location Type lbits:1 prefetch Prefetchable lbits:9 alwayszero Always read as zero lbits:19 baseaddr Lower Base Address {} or pci_membasel (Offset 20) PCI Lower Memory Address Base <byte 12856> ulong value As longword (Bits 31:0) endunion pci_membasel (Offset 20) PCI Lower Memory Address Base <byte 12860> union pci_membaseu (Offset 24) PCI Upper Memory Address Base <byte 12860> {field (By field)} <byte 12860> lbits:32 baseaddr Upper Base Address {} or pci_membaseu (Offset 24) PCI Upper Memory Address Base <byte 12860> ulong value As longword (Bits 63:32) endunion pci_membaseu (Offset 24) PCI Upper Memory Address Base <byte 12864> {pci_rsrvd28_2b ((Offset 28) Reserved)}

<byte 12864> ulong value {} <byte 12868> union pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID <byte 12868> {field (By field)} <byte 12868> union pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID <byte 12868> {field (By field)} <byte 12868> bits:16 id ID {} or pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID <byte 12868> ushort value As word endunion pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID <byte 12870> union pci_subsys_id (Offset 2E) PCI Subsystem ID <byte 12870> {field (By field)} <byte 12870> bits:16 id ID {} or pci_subsys_id (Offset 2E) PCI Subsystem ID <byte 12870> ushort value As word endunion pci_subsys_id (Offset 2E) PCI Subsystem ID {} or pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID <byte 12868> ulong value As longword endunion pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID <byte 12872> union pci_rombase (Offset 30) PCI ROM Base Address <byte 12872> {field (By field)} <byte 12872> lbits:1 decode_en Decode enable lbits:16 rsvd Reserved - always zero lbits:15 address Address Decoding {} or pci_rombase (Offset 30) PCI ROM Base Address <byte 12872> ulong value As longword endunion pci_rombase (Offset 30) PCI ROM Base Address <byte 12876> union pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED <byte 12876> {field (By field)} <byte 12876> union pci_cap_ptr (Offset 34) PCI Capabilities Pointer <byte 12876> {field (By field)} <byte 12876> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_ptr (Offset 34) PCI Capabilities Pointer <byte 12876>

utiny value As byte endunion pci_cap_ptr (Offset 34) PCI Capabilities Pointer <byte 12877> {pci_rsvd35 ((Offset 35) Reserved)} <byte 12877> utiny value {} <byte 12878> {pci_rsvd36_37 ((Offset 36) Reserved)} <byte 12878> ushort value {} {} or pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED <byte 12876> ulong value As longword endunion pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED <byte 12880> {pci_rsvd38_3b ((Offset 38) Reserved)} <byte 12880> ulong value {} <byte 12884> union pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED <byte 12884> {field (By field)} <byte 12884> union pci_int_line (Offset 3C) PCI Interrupt Line <byte 12884> {field (By field)} <byte 12884> tbits:8 line PCI Interrupt Line {} or pci_int_line (Offset 3C) PCI Interrupt Line <byte 12884> utiny value As byte endunion pci_int_line (Offset 3C) PCI Interrupt Line <byte 12885> union pci_int_pin (Offset 3D) PCI Interrupt Pin <byte 12885> {field (By field)} <byte 12885> tbits:8 pin PCI Interrupt Pin (read only) {} or pci_int_pin (Offset 3D) PCI Interrupt Pin <byte 12885> utiny value As byte endunion pci_int_pin (Offset 3D) PCI Interrupt Pin <byte 12886> union pci_min_gnt (Offset 3E) PCI Minimum Grant <byte 12886> {field (By field)} <byte 12886> tbits:8 grant PCI Minimum Grant (read only) {} or pci_min_gnt (Offset 3E) PCI Minimum Grant <byte 12886> utiny value As byte endunion pci_min_gnt (Offset 3E) PCI Minimum Grant <byte 12887>

{reserved ((Offset 3F) Reserved)} <byte 12887> utiny value {} {} or pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED <byte 12884> ulong value As longword endunion pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED <byte 12888> union pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR <byte 12888> {field (By field)} <byte 12888> {pci_rsvd40 ((Offset 40) Reserved)} <byte 12888> utiny value {} <byte 12889> {pci_rsvd41 ((Offset 41) Reserved)} <byte 12889> utiny value {} <byte 12890> union pci_romctr (Offset 42) PCI ROM Control <byte 12890> {field (By field)} <byte 12890> tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or pci_romctr (Offset 42) PCI ROM Control <byte 12890> utiny value As byte endunion pci_romctr (Offset 42) PCI ROM Control <byte 12891> union pci_mctr (Offset 43) PCI Master Control <byte 12891> {field (By field)} <byte 12891> tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or pci_mctr (Offset 43) PCI Master Control <byte 12891> utiny value As byte endunion pci_mctr (Offset 43) PCI Master Control {} or pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR <byte 12888> ulong value As longword endunion pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR <byte 12892> union pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT <byte 12892> {field (By field)}

<byte 12892> union pci_softrst (Offset 44) PCI Interface Reset Control <byte 12892> {field (By field)} <byte 12892> tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or pci_softrst (Offset 44) PCI Interface Reset Control <byte 12892> utiny value As byte endunion pci_softrst (Offset 44) PCI Interface Reset Control <byte 12893> union pci_intpend (Offset 45) PCI Interrupt <byte 12893> {field (By field)} <byte 12893> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_intpend (Offset 45) PCI Interrupt <byte 12893> utiny value As byte endunion pci_intpend (Offset 45) PCI Interrupt <byte 12894> union pci_inten (Offset 46) PCI Interrupt Enable Pending <byte 12894> {field (By field)} <byte 12894> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_inten (Offset 46) PCI Interrupt Enable Pending <byte 12894> utiny value As byte endunion pci_inten (Offset 46) PCI Interrupt Enable Pending <byte 12895> union pci_instat (Offset 47) PCI Interrupt Status <byte 12895> {field (By field)} <byte 12895> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_instat (Offset 47) PCI Interrupt Status <byte 12895> utiny value As byte endunion pci_instat (Offset 47) PCI Interrupt Status

{} or pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT <byte 12892> ulong value As longword endunion pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT <byte 12896> {pci_rsvd48_4b ((Offset 48) Reserved)} <byte 12896> ulong value {} <byte 12900> {pci_rsvd4c_4f ((Offset 4C) Reserved)} <byte 12900> ulong value {} <byte 12904> union pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC <byte 12904> {field (By field)} <byte 12904> union pci_cap_id (Offset 50) PCI Capabilities Identifier <byte 12904> {field (By field)} <byte 12904> tbits:8 cap_id Capability structure identifier. {} or pci_cap_id (Offset 50) PCI Capabilities Identifier <byte 12904> utiny value As byte endunion pci_cap_id (Offset 50) PCI Capabilities Identifier <byte 12905> union pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities <byte 12905> {field (By field)} <byte 12905> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities <byte 12905> utiny value As byte endunion pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities <byte 12906> union pci_pmc (Offset 52) PCI Power Management Capabilities <byte 12906> {field (By field)} <byte 12906> bits:3 ver PCI Power Management Specification Version bits:1 clk PME Clock bits:1 aps Auxilliary Power Source bits:1 dsi Device Specific Initialization bits:3 rsvd Reserved bits:1 d1 D1 Support bits:1 d2 D2 Support bits:5 pme PME Support {} or pci_pmc (Offset 52) PCI Power Management Capabilities <byte 12906> ushort value As word endunion pci_pmc (Offset 52) PCI Power Management Capabilities {}

or pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC <byte 12904> ulong value As longword endunion pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC <byte 12908> union pci_pmcs (Offset 54) PCI Power Management Control and Status <byte 12908> {field (By field)} <byte 12908> lbits:2 pst Power State lbits:6 reserved1 Reserved lbits:1 pen PME Enable lbits:4 sel Data Select lbits:2 scl Data Scale lbits:1 pme PME Status lbits:16 reserved Reserved {} or pci_pmcs (Offset 54) PCI Power Management Control and Status <byte 12908> ulong value As word endunion pci_pmcs (Offset 54) PCI Power Management Control and Status <byte 12912> union pci_par (Offset 58) PCI Programmable Address Register <byte 12912> {field (By field)} <byte 12912> lbits:20 ra ROM/RAM Address lbits:11 rsvd Reserved lbits:1 inc Increment For DWord aligned addresses {} or pci_par (Offset 58) PCI Programmable Address Register <byte 12912> ulong value As longword endunion pci_par (Offset 58) PCI Programmable Address Register <byte 12916> union pci_dar (Offset 5C) PCI Programmable Data Register <byte 12916> {field (By field)} <byte 12916> lbits:32 data Read/Write Data {} or pci_dar (Offset 5C) PCI Programmable Data Register <byte 12916> ulong value As longword endunion pci_dar (Offset 5C) PCI Programmable Data Register <byte 12920> {pci_rsvd60_6f ((Offset 60) Reserved)} <byte 12920> ulong value {} <byte 12924> union pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC <byte 12924> {field (By field)} <byte 12924> union pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Id entifier <byte 12924> {field (By field)} <byte 12924>

tbits:8 cap_id Capability structure identifier. {} or pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Ident ifier <byte 12924> utiny value As byte endunion pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier <byte 12925> union pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capabili ty <byte 12925> {field (By field)} <byte 12925> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability <byte 12925> utiny value As byte endunion pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capab ility <byte 12926> union pci_mc (Offset 66) PCI Message Control Register <byte 12926> {field (By field)} <byte 12926> bits:1 men Message Signaled Interrupts Enable bits:3 mmc Multiple Message Capable bits:3 mme Multiple Message Enable bits:1 c64 64 Bit Address Capable Read bits:8 rsvd Reserved {} or pci_mc (Offset 66) PCI Message Control Register <byte 12926> ushort value As word endunion pci_mc (Offset 66) PCI Message Control Register {} or pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC <byte 12924> ulong value As longword endunion pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC <byte 12928> union pci_ma (Offset 68) PCI Message Address <byte 12928> {field (By field)} <byte 12928> lbits:2 rsvd Reserved lbits:30 address Message Address {} or pci_ma (Offset 68) PCI Message Address <byte 12928> ulong value As longword endunion pci_ma (Offset 68) PCI Message Address <byte 12932> union pci_mua (Offset 6C) PCI Message Upper Address <byte 12932> {field (By field)} <byte 12932> lbits:32 address Message Upper Address {}

or pci_mua (Offset 6C) PCI Message Upper Address <byte 12932> ulong value As longword endunion pci_mua (Offset 6C) PCI Message Upper Address <byte 12936> union pci_md (Offset 70) PCI Message Data <byte 12936> {field (By field)} <byte 12936> lbits:16 mid Message ID lbits:16 rsvd Reserved {} or pci_md (Offset 70) PCI Message Data <byte 12936> ulong value As longword endunion pci_md (Offset 70) PCI Message Data <byte 12940> union pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD <byte 12940> {field (By field)} <byte 12940> union pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier <byte 12940> {field (By field)} <byte 12940> tbits:8 cap_id Capability structure identifier. {} or pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier <byte 12940> utiny value As byte endunion pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier <byte 12941> union pci_x_next_cap (Offset 75) PCI Next Capability Register <byte 12941> {field (By field)} <byte 12941> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_x_next_cap (Offset 75) PCI Next Capability Register <byte 12941> utiny value As byte endunion pci_x_next_cap (Offset 75) PCI Next Capability Register <byte 12942> union pci_x_cmd (Offset 76) PCI-X Command Register <byte 12942> {field (By field)} <byte 12942> bits:1 dper Data Parity Error Recovery bits:1 ero Enable Relaxed Ordering bits:2 mbc Maximum Memory Read Byte Count bits:3 mos Maximum Outstanding Split Transactions bits:9 rsvd Reserved {} or pci_x_cmd (Offset 76) PCI-X Command Register <byte 12942> ushort value As word endunion pci_x_cmd (Offset 76) PCI-X Command Register {} or pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD <byte 12940>

ulong value As longword endunion pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD <byte 12944> union pci_x_s (Offset 78) PCI-X Status Register <byte 12944> {field (By field)} <byte 12944> lbits:3 fn Function Number lbits:5 dn Device Number lbits:8 bn Bus Number lbits:1 d64 64-bit Device lbits:1 c133 133 MHz Capable lbits:1 scd Split Completion Discarded lbits:1 usc Unexpected Split Completion lbits:1 dc Device Complexity lbits:2 dmbc Designed Maximum Memory Read Byte Count lbits:3 dmos Designed Maximum Outstanding Split Transactions lbits:3 dmcr Designed Maximum Cumulative Read Size lbits:1 rcse Received Split Completion Error Message lbits:2 rsvd Reserved {} or pci_x_s (Offset 78) PCI-X Status Register <byte 12944> ulong value As longword endunion pci_x_s (Offset 78) PCI-X Status Register {} endunion pcicfg[0] Tachyon DX2+ PCI Configuration Registers <byte 12948> union pcicfg[1] Tachyon DX2+ PCI Configuration Registers <byte 12948> ulong[31] pcicfga Tachyon DX2+ PCI Configuration Registers As Longwords or pcicfg[1] Tachyon DX2+ PCI Configuration Registers <byte 12948> {pcicfg (Tachyon DX2+ PCI Configuration Registers By Field)} <byte 12948> union pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID <byte 12948> {field (By field)} <byte 12948> union pci_vendor_id (Offset 00) PCI Vendor ID <byte 12948> {field (By field)} <byte 12948> bits:16 id ID {} or pci_vendor_id (Offset 00) PCI Vendor ID <byte 12948> ushort value As word endunion pci_vendor_id (Offset 00) PCI Vendor ID <byte 12950> union pci_device_id (Offset 02) PCI Device ID <byte 12950> {field (By field)} <byte 12950> bits:16 id ID {} or pci_device_id (Offset 02) PCI Device ID <byte 12950> ushort value As word endunion pci_device_id (Offset 02) PCI Device ID

{} or pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID <byte 12948> ulong value As longword endunion pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID <byte 12952> union pcicfg_reg_04 (Offset 04) PCI CMD/STATUS <byte 12952> {field (By field)} <byte 12952> union pci_cmd (Offset 04) PCI Command <byte 12952> {field (By field)} <byte 12952> bits:1 io_access I/O Access Control bits:1 mem_access Memory Access Control bits:1 pcim_en PCI Master Enable bits:1 scycle_en Special Cycle Enable (read only, always returns 0) bits:1 memwinv Memory Write & Invalidate bits:1 paltsnp_en Palette Snooping Enable (read only, always returns 0) bits:1 perrrsp Parity Error Response bits:1 waitcycctrl Wait Cycle Control bits:1 serrx_en SERR# Enable bits:1 fbbw_en Fast Back-to-Back Write enable (read only, always returns 0) bits:6 rsvd Reserved {} or pci_cmd (Offset 04) PCI Command <byte 12952> ushort value As word endunion pci_cmd (Offset 04) PCI Command <byte 12954> union pci_status (Offset 06) PCI Status <byte 12954> {field (By field)} <byte 12954> bits:4 rsvd Reserved bits:1 cpl New Capabilities bits:1 cap66mhz 66MHz Capable bits:1 udfsup UDF Supported (read only, always returns 0) bits:1 capfbbw Fast Back-to-Back Capable (read only, always returns 0) bits:1 dperr Data Parity Error Detected bits:2 devsel_time PCI_DEVSEL# response timing (read only, always returns 1) bits:1 sgnltabrt Signaled Target Abort bits:1 rcvdtabrt Received Target Abort bits:1 rcvdmabrt Received Master Abort bits:1 sgnlsyserr Signaled System Error bits:1 perr Detected Parity Error {} or pci_status (Offset 06) PCI Status <byte 12954> ushort value As word endunion pci_status (Offset 06) PCI Status {} or pcicfg_reg_04 (Offset 04) PCI CMD/STATUS <byte 12952> ulong value As longword endunion pcicfg_reg_04 (Offset 04) PCI CMD/STATUS <byte 12956> union pcicfg_reg_08 (Offset 08) PCI REVID/CLASS <byte 12956>

{field (By field)} <byte 12956> union pci_revid (Offset 08) PCI Revision <byte 12956> {field (By field)} <byte 12956> tbits:2 minor Minor tbits:3 major Major tbits:3 res Reserved {} or pci_revid (Offset 08) PCI Revision <byte 12956> utiny value As byte endunion pci_revid (Offset 08) PCI Revision <byte 12957> union pci_class (Offset 09) PCI Class <byte 12957> {field (By field)} <byte 12957> tbits:8 baseclcode Base Class Code <byte 12958> tbits:8 subclcode Subclass Code <byte 12959> tbits:8 reglevpi Register Level Programming Interface {} or pci_class (Offset 09) PCI Class <byte 12957> utiny[3] value As byte array endunion pci_class (Offset 09) PCI Class {} or pcicfg_reg_08 (Offset 08) PCI REVID/CLASS <byte 12956> ulong value As longword endunion pcicfg_reg_08 (Offset 08) PCI REVID/CLASS <byte 12960> union pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST <byte 12960> {field (By field)} <byte 12960> union pci_clsize (Offset 0C) PCI Cache Line Size <byte 12960> {field (By field)} <byte 12960> tbits:8 size PCI cache line size {} or pci_clsize (Offset 0C) PCI Cache Line Size <byte 12960> utiny value As byte endunion pci_clsize (Offset 0C) PCI Cache Line Size <byte 12961> union pci_lattmr (Offset 0D) PCI Latency Timer <byte 12961> {field (By field)} <byte 12961> tbits:8 tmr PCI latency timer {} or pci_lattmr (Offset 0D) PCI Latency Timer <byte 12961> utiny value As byte endunion pci_lattmr (Offset 0D) PCI Latency Timer

<byte 12962> union pci_hdrtype (Offset 0E) PCI Header Type <byte 12962> {field (By field)} <byte 12962> tbits:8 type PCI header type (read only) {} or pci_hdrtype (Offset 0E) PCI Header Type <byte 12962> utiny value As byte endunion pci_hdrtype (Offset 0E) PCI Header Type <byte 12963> {pci_rsvd0f ((Offset 0F) Reserved (BIST))} <byte 12963> utiny value {} {} or pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST <byte 12960> ulong value As longword endunion pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST <byte 12964> {pci_rsvd10_13 ((Offset 10) Reserved (RSVBAR))} <byte 12964> ulong value {} <byte 12968> {pci_rsvd14_17 ((Offset 14) Reserved (RSVBAR))} <byte 12968> ulong value {} <byte 12972> union pci_iobasel (Offset 18) PCI Lower I/O Base Address <byte 12972> {field (By field)} <byte 12972> lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobasel (Offset 18) PCI Lower I/O Base Address <byte 12972> ulong value As longword endunion pci_iobasel (Offset 18) PCI Lower I/O Base Address <byte 12976> union pci_iobaseu (Offset 1C) PCI Upper I/O Base Address <byte 12976> {field (By field)} <byte 12976> lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobaseu (Offset 1C) PCI Upper I/O Base Address <byte 12976> ulong value As longword endunion pci_iobaseu (Offset 1C) PCI Upper I/O Base Address <byte 12980> union pci_membasel (Offset 20) PCI Lower Memory Address Base <byte 12980>

{field (By field)} <byte 12980> lbits:1 memspace Memory Space Indicator lbits:2 loctype Location Type lbits:1 prefetch Prefetchable lbits:9 alwayszero Always read as zero lbits:19 baseaddr Lower Base Address {} or pci_membasel (Offset 20) PCI Lower Memory Address Base <byte 12980> ulong value As longword (Bits 31:0) endunion pci_membasel (Offset 20) PCI Lower Memory Address Base <byte 12984> union pci_membaseu (Offset 24) PCI Upper Memory Address Base <byte 12984> {field (By field)} <byte 12984> lbits:32 baseaddr Upper Base Address {} or pci_membaseu (Offset 24) PCI Upper Memory Address Base <byte 12984> ulong value As longword (Bits 63:32) endunion pci_membaseu (Offset 24) PCI Upper Memory Address Base <byte 12988> {pci_rsrvd28_2b ((Offset 28) Reserved)} <byte 12988> ulong value {} <byte 12992> union pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID <byte 12992> {field (By field)} <byte 12992> union pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID <byte 12992> {field (By field)} <byte 12992> bits:16 id ID {} or pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID <byte 12992> ushort value As word endunion pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID <byte 12994> union pci_subsys_id (Offset 2E) PCI Subsystem ID <byte 12994> {field (By field)} <byte 12994> bits:16 id ID {} or pci_subsys_id (Offset 2E) PCI Subsystem ID <byte 12994> ushort value As word endunion pci_subsys_id (Offset 2E) PCI Subsystem ID {} or pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID <byte 12992> ulong value As longword endunion pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID <byte 12996>

union pci_rombase (Offset 30) PCI ROM Base Address <byte 12996> {field (By field)} <byte 12996> lbits:1 decode_en Decode enable lbits:16 rsvd Reserved - always zero lbits:15 address Address Decoding {} or pci_rombase (Offset 30) PCI ROM Base Address <byte 12996> ulong value As longword endunion pci_rombase (Offset 30) PCI ROM Base Address <byte 13000> union pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED <byte 13000> {field (By field)} <byte 13000> union pci_cap_ptr (Offset 34) PCI Capabilities Pointer <byte 13000> {field (By field)} <byte 13000> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_ptr (Offset 34) PCI Capabilities Pointer <byte 13000> utiny value As byte endunion pci_cap_ptr (Offset 34) PCI Capabilities Pointer <byte 13001> {pci_rsvd35 ((Offset 35) Reserved)} <byte 13001> utiny value {} <byte 13002> {pci_rsvd36_37 ((Offset 36) Reserved)} <byte 13002> ushort value {} {} or pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED <byte 13000> ulong value As longword endunion pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED <byte 13004> {pci_rsvd38_3b ((Offset 38) Reserved)} <byte 13004> ulong value {} <byte 13008> union pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED <byte 13008> {field (By field)} <byte 13008> union pci_int_line (Offset 3C) PCI Interrupt Line <byte 13008> {field (By field)} <byte 13008> tbits:8 line PCI Interrupt Line {} or pci_int_line (Offset 3C) PCI Interrupt Line <byte 13008>

utiny value As byte endunion pci_int_line (Offset 3C) PCI Interrupt Line <byte 13009> union pci_int_pin (Offset 3D) PCI Interrupt Pin <byte 13009> {field (By field)} <byte 13009> tbits:8 pin PCI Interrupt Pin (read only) {} or pci_int_pin (Offset 3D) PCI Interrupt Pin <byte 13009> utiny value As byte endunion pci_int_pin (Offset 3D) PCI Interrupt Pin <byte 13010> union pci_min_gnt (Offset 3E) PCI Minimum Grant <byte 13010> {field (By field)} <byte 13010> tbits:8 grant PCI Minimum Grant (read only) {} or pci_min_gnt (Offset 3E) PCI Minimum Grant <byte 13010> utiny value As byte endunion pci_min_gnt (Offset 3E) PCI Minimum Grant <byte 13011> {reserved ((Offset 3F) Reserved)} <byte 13011> utiny value {} {} or pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED <byte 13008> ulong value As longword endunion pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED <byte 13012> union pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR <byte 13012> {field (By field)} <byte 13012> {pci_rsvd40 ((Offset 40) Reserved)} <byte 13012> utiny value {} <byte 13013> {pci_rsvd41 ((Offset 41) Reserved)} <byte 13013> utiny value {} <byte 13014> union pci_romctr (Offset 42) PCI ROM Control <byte 13014> {field (By field)} <byte 13014> tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or pci_romctr (Offset 42) PCI ROM Control <byte 13014>

utiny value As byte endunion pci_romctr (Offset 42) PCI ROM Control <byte 13015> union pci_mctr (Offset 43) PCI Master Control <byte 13015> {field (By field)} <byte 13015> tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or pci_mctr (Offset 43) PCI Master Control <byte 13015> utiny value As byte endunion pci_mctr (Offset 43) PCI Master Control {} or pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR <byte 13012> ulong value As longword endunion pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR <byte 13016> union pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT <byte 13016> {field (By field)} <byte 13016> union pci_softrst (Offset 44) PCI Interface Reset Control <byte 13016> {field (By field)} <byte 13016> tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or pci_softrst (Offset 44) PCI Interface Reset Control <byte 13016> utiny value As byte endunion pci_softrst (Offset 44) PCI Interface Reset Control <byte 13017> union pci_intpend (Offset 45) PCI Interrupt <byte 13017> {field (By field)} <byte 13017> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_intpend (Offset 45) PCI Interrupt <byte 13017> utiny value As byte endunion pci_intpend (Offset 45) PCI Interrupt <byte 13018> union pci_inten (Offset 46) PCI Interrupt Enable Pending <byte 13018> {field (By field)} <byte 13018> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt

tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_inten (Offset 46) PCI Interrupt Enable Pending <byte 13018> utiny value As byte endunion pci_inten (Offset 46) PCI Interrupt Enable Pending <byte 13019> union pci_instat (Offset 47) PCI Interrupt Status <byte 13019> {field (By field)} <byte 13019> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_instat (Offset 47) PCI Interrupt Status <byte 13019> utiny value As byte endunion pci_instat (Offset 47) PCI Interrupt Status {} or pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT <byte 13016> ulong value As longword endunion pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT <byte 13020> {pci_rsvd48_4b ((Offset 48) Reserved)} <byte 13020> ulong value {} <byte 13024> {pci_rsvd4c_4f ((Offset 4C) Reserved)} <byte 13024> ulong value {} <byte 13028> union pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC <byte 13028> {field (By field)} <byte 13028> union pci_cap_id (Offset 50) PCI Capabilities Identifier <byte 13028> {field (By field)} <byte 13028> tbits:8 cap_id Capability structure identifier. {} or pci_cap_id (Offset 50) PCI Capabilities Identifier <byte 13028> utiny value As byte endunion pci_cap_id (Offset 50) PCI Capabilities Identifier <byte 13029> union pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities <byte 13029> {field (By field)} <byte 13029>

tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities <byte 13029> utiny value As byte endunion pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities <byte 13030> union pci_pmc (Offset 52) PCI Power Management Capabilities <byte 13030> {field (By field)} <byte 13030> bits:3 ver PCI Power Management Specification Version bits:1 clk PME Clock bits:1 aps Auxilliary Power Source bits:1 dsi Device Specific Initialization bits:3 rsvd Reserved bits:1 d1 D1 Support bits:1 d2 D2 Support bits:5 pme PME Support {} or pci_pmc (Offset 52) PCI Power Management Capabilities <byte 13030> ushort value As word endunion pci_pmc (Offset 52) PCI Power Management Capabilities {} or pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC <byte 13028> ulong value As longword endunion pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC <byte 13032> union pci_pmcs (Offset 54) PCI Power Management Control and Status <byte 13032> {field (By field)} <byte 13032> lbits:2 pst Power State lbits:6 reserved1 Reserved lbits:1 pen PME Enable lbits:4 sel Data Select lbits:2 scl Data Scale lbits:1 pme PME Status lbits:16 reserved Reserved {} or pci_pmcs (Offset 54) PCI Power Management Control and Status <byte 13032> ulong value As word endunion pci_pmcs (Offset 54) PCI Power Management Control and Status <byte 13036> union pci_par (Offset 58) PCI Programmable Address Register <byte 13036> {field (By field)} <byte 13036> lbits:20 ra ROM/RAM Address lbits:11 rsvd Reserved lbits:1 inc Increment For DWord aligned addresses {} or pci_par (Offset 58) PCI Programmable Address Register <byte 13036> ulong value As longword endunion pci_par (Offset 58) PCI Programmable Address Register <byte 13040>

union pci_dar (Offset 5C) PCI Programmable Data Register <byte 13040> {field (By field)} <byte 13040> lbits:32 data Read/Write Data {} or pci_dar (Offset 5C) PCI Programmable Data Register <byte 13040> ulong value As longword endunion pci_dar (Offset 5C) PCI Programmable Data Register <byte 13044> {pci_rsvd60_6f ((Offset 60) Reserved)} <byte 13044> ulong value {} <byte 13048> union pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC <byte 13048> {field (By field)} <byte 13048> union pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Id entifier <byte 13048> {field (By field)} <byte 13048> tbits:8 cap_id Capability structure identifier. {} or pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Ident ifier <byte 13048> utiny value As byte endunion pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier <byte 13049> union pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capabili ty <byte 13049> {field (By field)} <byte 13049> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability <byte 13049> utiny value As byte endunion pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capab ility <byte 13050> union pci_mc (Offset 66) PCI Message Control Register <byte 13050> {field (By field)} <byte 13050> bits:1 men Message Signaled Interrupts Enable bits:3 mmc Multiple Message Capable bits:3 mme Multiple Message Enable bits:1 c64 64 Bit Address Capable Read bits:8 rsvd Reserved {} or pci_mc (Offset 66) PCI Message Control Register <byte 13050> ushort value As word

endunion pci_mc (Offset 66) PCI Message Control Register {} or pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC <byte 13048> ulong value As longword endunion pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC <byte 13052> union pci_ma (Offset 68) PCI Message Address <byte 13052> {field (By field)} <byte 13052> lbits:2 rsvd Reserved lbits:30 address Message Address {} or pci_ma (Offset 68) PCI Message Address <byte 13052> ulong value As longword endunion pci_ma (Offset 68) PCI Message Address <byte 13056> union pci_mua (Offset 6C) PCI Message Upper Address <byte 13056> {field (By field)} <byte 13056> lbits:32 address Message Upper Address {} or pci_mua (Offset 6C) PCI Message Upper Address <byte 13056> ulong value As longword endunion pci_mua (Offset 6C) PCI Message Upper Address <byte 13060> union pci_md (Offset 70) PCI Message Data <byte 13060> {field (By field)} <byte 13060> lbits:16 mid Message ID lbits:16 rsvd Reserved {} or pci_md (Offset 70) PCI Message Data <byte 13060> ulong value As longword endunion pci_md (Offset 70) PCI Message Data <byte 13064> union pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD <byte 13064> {field (By field)} <byte 13064> union pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier <byte 13064> {field (By field)} <byte 13064> tbits:8 cap_id Capability structure identifier. {} or pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier <byte 13064> utiny value As byte endunion pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier <byte 13065> union pci_x_next_cap (Offset 75) PCI Next Capability Register <byte 13065> {field (By field)}

<byte 13065> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_x_next_cap (Offset 75) PCI Next Capability Register <byte 13065> utiny value As byte endunion pci_x_next_cap (Offset 75) PCI Next Capability Register <byte 13066> union pci_x_cmd (Offset 76) PCI-X Command Register <byte 13066> {field (By field)} <byte 13066> bits:1 dper Data Parity Error Recovery bits:1 ero Enable Relaxed Ordering bits:2 mbc Maximum Memory Read Byte Count bits:3 mos Maximum Outstanding Split Transactions bits:9 rsvd Reserved {} or pci_x_cmd (Offset 76) PCI-X Command Register <byte 13066> ushort value As word endunion pci_x_cmd (Offset 76) PCI-X Command Register {} or pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD <byte 13064> ulong value As longword endunion pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD <byte 13068> union pci_x_s (Offset 78) PCI-X Status Register <byte 13068> {field (By field)} <byte 13068> lbits:3 fn Function Number lbits:5 dn Device Number lbits:8 bn Bus Number lbits:1 d64 64-bit Device lbits:1 c133 133 MHz Capable lbits:1 scd Split Completion Discarded lbits:1 usc Unexpected Split Completion lbits:1 dc Device Complexity lbits:2 dmbc Designed Maximum Memory Read Byte Count lbits:3 dmos Designed Maximum Outstanding Split Transactions lbits:3 dmcr Designed Maximum Cumulative Read Size lbits:1 rcse Received Split Completion Error Message lbits:2 rsvd Reserved {} or pci_x_s (Offset 78) PCI-X Status Register <byte 13068> ulong value As longword endunion pci_x_s (Offset 78) PCI-X Status Register {} endunion pcicfg[1] Tachyon DX2+ PCI Configuration Registers <byte 13072> union pcicfg[2] Tachyon DX2+ PCI Configuration Registers <byte 13072> ulong[31] pcicfga Tachyon DX2+ PCI Configuration Registers As Longwords or pcicfg[2] Tachyon DX2+ PCI Configuration Registers <byte 13072> {pcicfg (Tachyon DX2+ PCI Configuration Registers By Field)} <byte 13072>

union pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID <byte 13072> {field (By field)} <byte 13072> union pci_vendor_id (Offset 00) PCI Vendor ID <byte 13072> {field (By field)} <byte 13072> bits:16 id ID {} or pci_vendor_id (Offset 00) PCI Vendor ID <byte 13072> ushort value As word endunion pci_vendor_id (Offset 00) PCI Vendor ID <byte 13074> union pci_device_id (Offset 02) PCI Device ID <byte 13074> {field (By field)} <byte 13074> bits:16 id ID {} or pci_device_id (Offset 02) PCI Device ID <byte 13074> ushort value As word endunion pci_device_id (Offset 02) PCI Device ID {} or pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID <byte 13072> ulong value As longword endunion pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID <byte 13076> union pcicfg_reg_04 (Offset 04) PCI CMD/STATUS <byte 13076> {field (By field)} <byte 13076> union pci_cmd (Offset 04) PCI Command <byte 13076> {field (By field)} <byte 13076> bits:1 io_access I/O Access Control bits:1 mem_access Memory Access Control bits:1 pcim_en PCI Master Enable bits:1 scycle_en Special Cycle Enable (read only, always returns 0) bits:1 memwinv Memory Write & Invalidate bits:1 paltsnp_en Palette Snooping Enable (read only, always returns 0) bits:1 perrrsp Parity Error Response bits:1 waitcycctrl Wait Cycle Control bits:1 serrx_en SERR# Enable bits:1 fbbw_en Fast Back-to-Back Write enable (read only, always returns 0) bits:6 rsvd Reserved {} or pci_cmd (Offset 04) PCI Command <byte 13076> ushort value As word endunion pci_cmd (Offset 04) PCI Command <byte 13078> union pci_status (Offset 06) PCI Status <byte 13078> {field (By field)} <byte 13078>

bits:4 rsvd Reserved bits:1 cpl New Capabilities bits:1 cap66mhz 66MHz Capable bits:1 udfsup UDF Supported (read only, always returns 0) bits:1 capfbbw Fast Back-to-Back Capable (read only, always returns 0) bits:1 dperr Data Parity Error Detected bits:2 devsel_time PCI_DEVSEL# response timing (read only, always returns 1) bits:1 sgnltabrt Signaled Target Abort bits:1 rcvdtabrt Received Target Abort bits:1 rcvdmabrt Received Master Abort bits:1 sgnlsyserr Signaled System Error bits:1 perr Detected Parity Error {} or pci_status (Offset 06) PCI Status <byte 13078> ushort value As word endunion pci_status (Offset 06) PCI Status {} or pcicfg_reg_04 (Offset 04) PCI CMD/STATUS <byte 13076> ulong value As longword endunion pcicfg_reg_04 (Offset 04) PCI CMD/STATUS <byte 13080> union pcicfg_reg_08 (Offset 08) PCI REVID/CLASS <byte 13080> {field (By field)} <byte 13080> union pci_revid (Offset 08) PCI Revision <byte 13080> {field (By field)} <byte 13080> tbits:2 minor Minor tbits:3 major Major tbits:3 res Reserved {} or pci_revid (Offset 08) PCI Revision <byte 13080> utiny value As byte endunion pci_revid (Offset 08) PCI Revision <byte 13081> union pci_class (Offset 09) PCI Class <byte 13081> {field (By field)} <byte 13081> tbits:8 baseclcode Base Class Code <byte 13082> tbits:8 subclcode Subclass Code <byte 13083> tbits:8 reglevpi Register Level Programming Interface {} or pci_class (Offset 09) PCI Class <byte 13081> utiny[3] value As byte array endunion pci_class (Offset 09) PCI Class {} or pcicfg_reg_08 (Offset 08) PCI REVID/CLASS <byte 13080> ulong value As longword endunion pcicfg_reg_08 (Offset 08) PCI REVID/CLASS <byte 13084>

union pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST <byte 13084> {field (By field)} <byte 13084> union pci_clsize (Offset 0C) PCI Cache Line Size <byte 13084> {field (By field)} <byte 13084> tbits:8 size PCI cache line size {} or pci_clsize (Offset 0C) PCI Cache Line Size <byte 13084> utiny value As byte endunion pci_clsize (Offset 0C) PCI Cache Line Size <byte 13085> union pci_lattmr (Offset 0D) PCI Latency Timer <byte 13085> {field (By field)} <byte 13085> tbits:8 tmr PCI latency timer {} or pci_lattmr (Offset 0D) PCI Latency Timer <byte 13085> utiny value As byte endunion pci_lattmr (Offset 0D) PCI Latency Timer <byte 13086> union pci_hdrtype (Offset 0E) PCI Header Type <byte 13086> {field (By field)} <byte 13086> tbits:8 type PCI header type (read only) {} or pci_hdrtype (Offset 0E) PCI Header Type <byte 13086> utiny value As byte endunion pci_hdrtype (Offset 0E) PCI Header Type <byte 13087> {pci_rsvd0f ((Offset 0F) Reserved (BIST))} <byte 13087> utiny value {} {} or pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST <byte 13084> ulong value As longword endunion pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST <byte 13088> {pci_rsvd10_13 ((Offset 10) Reserved (RSVBAR))} <byte 13088> ulong value {} <byte 13092> {pci_rsvd14_17 ((Offset 14) Reserved (RSVBAR))} <byte 13092> ulong value {} <byte 13096> union pci_iobasel (Offset 18) PCI Lower I/O Base Address <byte 13096> {field (By field)}

<byte 13096> lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobasel (Offset 18) PCI Lower I/O Base Address <byte 13096> ulong value As longword endunion pci_iobasel (Offset 18) PCI Lower I/O Base Address <byte 13100> union pci_iobaseu (Offset 1C) PCI Upper I/O Base Address <byte 13100> {field (By field)} <byte 13100> lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobaseu (Offset 1C) PCI Upper I/O Base Address <byte 13100> ulong value As longword endunion pci_iobaseu (Offset 1C) PCI Upper I/O Base Address <byte 13104> union pci_membasel (Offset 20) PCI Lower Memory Address Base <byte 13104> {field (By field)} <byte 13104> lbits:1 memspace Memory Space Indicator lbits:2 loctype Location Type lbits:1 prefetch Prefetchable lbits:9 alwayszero Always read as zero lbits:19 baseaddr Lower Base Address {} or pci_membasel (Offset 20) PCI Lower Memory Address Base <byte 13104> ulong value As longword (Bits 31:0) endunion pci_membasel (Offset 20) PCI Lower Memory Address Base <byte 13108> union pci_membaseu (Offset 24) PCI Upper Memory Address Base <byte 13108> {field (By field)} <byte 13108> lbits:32 baseaddr Upper Base Address {} or pci_membaseu (Offset 24) PCI Upper Memory Address Base <byte 13108> ulong value As longword (Bits 63:32) endunion pci_membaseu (Offset 24) PCI Upper Memory Address Base <byte 13112> {pci_rsrvd28_2b ((Offset 28) Reserved)} <byte 13112> ulong value {} <byte 13116> union pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID <byte 13116> {field (By field)} <byte 13116> union pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID <byte 13116>

{field (By field)} <byte 13116> bits:16 id ID {} or pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID <byte 13116> ushort value As word endunion pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID <byte 13118> union pci_subsys_id (Offset 2E) PCI Subsystem ID <byte 13118> {field (By field)} <byte 13118> bits:16 id ID {} or pci_subsys_id (Offset 2E) PCI Subsystem ID <byte 13118> ushort value As word endunion pci_subsys_id (Offset 2E) PCI Subsystem ID {} or pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID <byte 13116> ulong value As longword endunion pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID <byte 13120> union pci_rombase (Offset 30) PCI ROM Base Address <byte 13120> {field (By field)} <byte 13120> lbits:1 decode_en Decode enable lbits:16 rsvd Reserved - always zero lbits:15 address Address Decoding {} or pci_rombase (Offset 30) PCI ROM Base Address <byte 13120> ulong value As longword endunion pci_rombase (Offset 30) PCI ROM Base Address <byte 13124> union pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED <byte 13124> {field (By field)} <byte 13124> union pci_cap_ptr (Offset 34) PCI Capabilities Pointer <byte 13124> {field (By field)} <byte 13124> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_ptr (Offset 34) PCI Capabilities Pointer <byte 13124> utiny value As byte endunion pci_cap_ptr (Offset 34) PCI Capabilities Pointer <byte 13125> {pci_rsvd35 ((Offset 35) Reserved)} <byte 13125> utiny value {} <byte 13126> {pci_rsvd36_37 ((Offset 36) Reserved)} <byte 13126>

ushort value {} {} or pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED <byte 13124> ulong value As longword endunion pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED <byte 13128> {pci_rsvd38_3b ((Offset 38) Reserved)} <byte 13128> ulong value {} <byte 13132> union pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED <byte 13132> {field (By field)} <byte 13132> union pci_int_line (Offset 3C) PCI Interrupt Line <byte 13132> {field (By field)} <byte 13132> tbits:8 line PCI Interrupt Line {} or pci_int_line (Offset 3C) PCI Interrupt Line <byte 13132> utiny value As byte endunion pci_int_line (Offset 3C) PCI Interrupt Line <byte 13133> union pci_int_pin (Offset 3D) PCI Interrupt Pin <byte 13133> {field (By field)} <byte 13133> tbits:8 pin PCI Interrupt Pin (read only) {} or pci_int_pin (Offset 3D) PCI Interrupt Pin <byte 13133> utiny value As byte endunion pci_int_pin (Offset 3D) PCI Interrupt Pin <byte 13134> union pci_min_gnt (Offset 3E) PCI Minimum Grant <byte 13134> {field (By field)} <byte 13134> tbits:8 grant PCI Minimum Grant (read only) {} or pci_min_gnt (Offset 3E) PCI Minimum Grant <byte 13134> utiny value As byte endunion pci_min_gnt (Offset 3E) PCI Minimum Grant <byte 13135> {reserved ((Offset 3F) Reserved)} <byte 13135> utiny value {} {} or pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED <byte 13132> ulong value As longword endunion pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED <byte 13136>

union pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR <byte 13136> {field (By field)} <byte 13136> {pci_rsvd40 ((Offset 40) Reserved)} <byte 13136> utiny value {} <byte 13137> {pci_rsvd41 ((Offset 41) Reserved)} <byte 13137> utiny value {} <byte 13138> union pci_romctr (Offset 42) PCI ROM Control <byte 13138> {field (By field)} <byte 13138> tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or pci_romctr (Offset 42) PCI ROM Control <byte 13138> utiny value As byte endunion pci_romctr (Offset 42) PCI ROM Control <byte 13139> union pci_mctr (Offset 43) PCI Master Control <byte 13139> {field (By field)} <byte 13139> tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or pci_mctr (Offset 43) PCI Master Control <byte 13139> utiny value As byte endunion pci_mctr (Offset 43) PCI Master Control {} or pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR <byte 13136> ulong value As longword endunion pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR <byte 13140> union pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT <byte 13140> {field (By field)} <byte 13140> union pci_softrst (Offset 44) PCI Interface Reset Control <byte 13140> {field (By field)} <byte 13140> tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or pci_softrst (Offset 44) PCI Interface Reset Control <byte 13140>

utiny value As byte endunion pci_softrst (Offset 44) PCI Interface Reset Control <byte 13141> union pci_intpend (Offset 45) PCI Interrupt <byte 13141> {field (By field)} <byte 13141> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_intpend (Offset 45) PCI Interrupt <byte 13141> utiny value As byte endunion pci_intpend (Offset 45) PCI Interrupt <byte 13142> union pci_inten (Offset 46) PCI Interrupt Enable Pending <byte 13142> {field (By field)} <byte 13142> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_inten (Offset 46) PCI Interrupt Enable Pending <byte 13142> utiny value As byte endunion pci_inten (Offset 46) PCI Interrupt Enable Pending <byte 13143> union pci_instat (Offset 47) PCI Interrupt Status <byte 13143> {field (By field)} <byte 13143> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_instat (Offset 47) PCI Interrupt Status <byte 13143> utiny value As byte endunion pci_instat (Offset 47) PCI Interrupt Status {} or pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT <byte 13140> ulong value As longword endunion pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT <byte 13144> {pci_rsvd48_4b ((Offset 48) Reserved)} <byte 13144> ulong value {}

<byte 13148> {pci_rsvd4c_4f ((Offset 4C) Reserved)} <byte 13148> ulong value {} <byte 13152> union pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC <byte 13152> {field (By field)} <byte 13152> union pci_cap_id (Offset 50) PCI Capabilities Identifier <byte 13152> {field (By field)} <byte 13152> tbits:8 cap_id Capability structure identifier. {} or pci_cap_id (Offset 50) PCI Capabilities Identifier <byte 13152> utiny value As byte endunion pci_cap_id (Offset 50) PCI Capabilities Identifier <byte 13153> union pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities <byte 13153> {field (By field)} <byte 13153> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities <byte 13153> utiny value As byte endunion pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities <byte 13154> union pci_pmc (Offset 52) PCI Power Management Capabilities <byte 13154> {field (By field)} <byte 13154> bits:3 ver PCI Power Management Specification Version bits:1 clk PME Clock bits:1 aps Auxilliary Power Source bits:1 dsi Device Specific Initialization bits:3 rsvd Reserved bits:1 d1 D1 Support bits:1 d2 D2 Support bits:5 pme PME Support {} or pci_pmc (Offset 52) PCI Power Management Capabilities <byte 13154> ushort value As word endunion pci_pmc (Offset 52) PCI Power Management Capabilities {} or pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC <byte 13152> ulong value As longword endunion pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC <byte 13156> union pci_pmcs (Offset 54) PCI Power Management Control and Status <byte 13156> {field (By field)} <byte 13156> lbits:2 pst Power State

lbits:6 reserved1 Reserved lbits:1 pen PME Enable lbits:4 sel Data Select lbits:2 scl Data Scale lbits:1 pme PME Status lbits:16 reserved Reserved {} or pci_pmcs (Offset 54) PCI Power Management Control and Status <byte 13156> ulong value As word endunion pci_pmcs (Offset 54) PCI Power Management Control and Status <byte 13160> union pci_par (Offset 58) PCI Programmable Address Register <byte 13160> {field (By field)} <byte 13160> lbits:20 ra ROM/RAM Address lbits:11 rsvd Reserved lbits:1 inc Increment For DWord aligned addresses {} or pci_par (Offset 58) PCI Programmable Address Register <byte 13160> ulong value As longword endunion pci_par (Offset 58) PCI Programmable Address Register <byte 13164> union pci_dar (Offset 5C) PCI Programmable Data Register <byte 13164> {field (By field)} <byte 13164> lbits:32 data Read/Write Data {} or pci_dar (Offset 5C) PCI Programmable Data Register <byte 13164> ulong value As longword endunion pci_dar (Offset 5C) PCI Programmable Data Register <byte 13168> {pci_rsvd60_6f ((Offset 60) Reserved)} <byte 13168> ulong value {} <byte 13172> union pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC <byte 13172> {field (By field)} <byte 13172> union pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Id entifier <byte 13172> {field (By field)} <byte 13172> tbits:8 cap_id Capability structure identifier. {} or pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Ident ifier <byte 13172> utiny value As byte endunion pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier <byte 13173> union pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capabili

ty <byte 13173> {field (By field)} <byte 13173> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability <byte 13173> utiny value As byte endunion pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capab ility <byte 13174> union pci_mc (Offset 66) PCI Message Control Register <byte 13174> {field (By field)} <byte 13174> bits:1 men Message Signaled Interrupts Enable bits:3 mmc Multiple Message Capable bits:3 mme Multiple Message Enable bits:1 c64 64 Bit Address Capable Read bits:8 rsvd Reserved {} or pci_mc (Offset 66) PCI Message Control Register <byte 13174> ushort value As word endunion pci_mc (Offset 66) PCI Message Control Register {} or pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC <byte 13172> ulong value As longword endunion pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC <byte 13176> union pci_ma (Offset 68) PCI Message Address <byte 13176> {field (By field)} <byte 13176> lbits:2 rsvd Reserved lbits:30 address Message Address {} or pci_ma (Offset 68) PCI Message Address <byte 13176> ulong value As longword endunion pci_ma (Offset 68) PCI Message Address <byte 13180> union pci_mua (Offset 6C) PCI Message Upper Address <byte 13180> {field (By field)} <byte 13180> lbits:32 address Message Upper Address {} or pci_mua (Offset 6C) PCI Message Upper Address <byte 13180> ulong value As longword endunion pci_mua (Offset 6C) PCI Message Upper Address <byte 13184> union pci_md (Offset 70) PCI Message Data <byte 13184> {field (By field)} <byte 13184> lbits:16 mid Message ID

lbits:16 rsvd Reserved {} or pci_md (Offset 70) PCI Message Data <byte 13184> ulong value As longword endunion pci_md (Offset 70) PCI Message Data <byte 13188> union pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD <byte 13188> {field (By field)} <byte 13188> union pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier <byte 13188> {field (By field)} <byte 13188> tbits:8 cap_id Capability structure identifier. {} or pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier <byte 13188> utiny value As byte endunion pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier <byte 13189> union pci_x_next_cap (Offset 75) PCI Next Capability Register <byte 13189> {field (By field)} <byte 13189> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_x_next_cap (Offset 75) PCI Next Capability Register <byte 13189> utiny value As byte endunion pci_x_next_cap (Offset 75) PCI Next Capability Register <byte 13190> union pci_x_cmd (Offset 76) PCI-X Command Register <byte 13190> {field (By field)} <byte 13190> bits:1 dper Data Parity Error Recovery bits:1 ero Enable Relaxed Ordering bits:2 mbc Maximum Memory Read Byte Count bits:3 mos Maximum Outstanding Split Transactions bits:9 rsvd Reserved {} or pci_x_cmd (Offset 76) PCI-X Command Register <byte 13190> ushort value As word endunion pci_x_cmd (Offset 76) PCI-X Command Register {} or pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD <byte 13188> ulong value As longword endunion pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD <byte 13192> union pci_x_s (Offset 78) PCI-X Status Register <byte 13192> {field (By field)} <byte 13192> lbits:3 fn Function Number lbits:5 dn Device Number lbits:8 bn Bus Number

lbits:1 d64 64-bit Device lbits:1 c133 133 MHz Capable lbits:1 scd Split Completion Discarded lbits:1 usc Unexpected Split Completion lbits:1 dc Device Complexity lbits:2 dmbc Designed Maximum Memory Read Byte Count lbits:3 dmos Designed Maximum Outstanding Split Transactions lbits:3 dmcr Designed Maximum Cumulative Read Size lbits:1 rcse Received Split Completion Error Message lbits:2 rsvd Reserved {} or pci_x_s (Offset 78) PCI-X Status Register <byte 13192> ulong value As longword endunion pci_x_s (Offset 78) PCI-X Status Register {} endunion pcicfg[2] Tachyon DX2+ PCI Configuration Registers <byte 13196> union pcicfg[3] Tachyon DX2+ PCI Configuration Registers <byte 13196> ulong[31] pcicfga Tachyon DX2+ PCI Configuration Registers As Longwords or pcicfg[3] Tachyon DX2+ PCI Configuration Registers <byte 13196> {pcicfg (Tachyon DX2+ PCI Configuration Registers By Field)} <byte 13196> union pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID <byte 13196> {field (By field)} <byte 13196> union pci_vendor_id (Offset 00) PCI Vendor ID <byte 13196> {field (By field)} <byte 13196> bits:16 id ID {} or pci_vendor_id (Offset 00) PCI Vendor ID <byte 13196> ushort value As word endunion pci_vendor_id (Offset 00) PCI Vendor ID <byte 13198> union pci_device_id (Offset 02) PCI Device ID <byte 13198> {field (By field)} <byte 13198> bits:16 id ID {} or pci_device_id (Offset 02) PCI Device ID <byte 13198> ushort value As word endunion pci_device_id (Offset 02) PCI Device ID {} or pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID <byte 13196> ulong value As longword endunion pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID <byte 13200> union pcicfg_reg_04 (Offset 04) PCI CMD/STATUS <byte 13200> {field (By field)} <byte 13200>

union pci_cmd (Offset 04) PCI Command <byte 13200> {field (By field)} <byte 13200> bits:1 io_access I/O Access Control bits:1 mem_access Memory Access Control bits:1 pcim_en PCI Master Enable bits:1 scycle_en Special Cycle Enable (read only, always returns 0) bits:1 memwinv Memory Write & Invalidate bits:1 paltsnp_en Palette Snooping Enable (read only, always returns 0) bits:1 perrrsp Parity Error Response bits:1 waitcycctrl Wait Cycle Control bits:1 serrx_en SERR# Enable bits:1 fbbw_en Fast Back-to-Back Write enable (read only, always returns 0) bits:6 rsvd Reserved {} or pci_cmd (Offset 04) PCI Command <byte 13200> ushort value As word endunion pci_cmd (Offset 04) PCI Command <byte 13202> union pci_status (Offset 06) PCI Status <byte 13202> {field (By field)} <byte 13202> bits:4 rsvd Reserved bits:1 cpl New Capabilities bits:1 cap66mhz 66MHz Capable bits:1 udfsup UDF Supported (read only, always returns 0) bits:1 capfbbw Fast Back-to-Back Capable (read only, always returns 0) bits:1 dperr Data Parity Error Detected bits:2 devsel_time PCI_DEVSEL# response timing (read only, always returns 1) bits:1 sgnltabrt Signaled Target Abort bits:1 rcvdtabrt Received Target Abort bits:1 rcvdmabrt Received Master Abort bits:1 sgnlsyserr Signaled System Error bits:1 perr Detected Parity Error {} or pci_status (Offset 06) PCI Status <byte 13202> ushort value As word endunion pci_status (Offset 06) PCI Status {} or pcicfg_reg_04 (Offset 04) PCI CMD/STATUS <byte 13200> ulong value As longword endunion pcicfg_reg_04 (Offset 04) PCI CMD/STATUS <byte 13204> union pcicfg_reg_08 (Offset 08) PCI REVID/CLASS <byte 13204> {field (By field)} <byte 13204> union pci_revid (Offset 08) PCI Revision <byte 13204> {field (By field)} <byte 13204> tbits:2 minor Minor tbits:3 major Major tbits:3 res Reserved {}

or pci_revid (Offset 08) PCI Revision <byte 13204> utiny value As byte endunion pci_revid (Offset 08) PCI Revision <byte 13205> union pci_class (Offset 09) PCI Class <byte 13205> {field (By field)} <byte 13205> tbits:8 baseclcode Base Class Code <byte 13206> tbits:8 subclcode Subclass Code <byte 13207> tbits:8 reglevpi Register Level Programming Interface {} or pci_class (Offset 09) PCI Class <byte 13205> utiny[3] value As byte array endunion pci_class (Offset 09) PCI Class {} or pcicfg_reg_08 (Offset 08) PCI REVID/CLASS <byte 13204> ulong value As longword endunion pcicfg_reg_08 (Offset 08) PCI REVID/CLASS <byte 13208> union pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST <byte 13208> {field (By field)} <byte 13208> union pci_clsize (Offset 0C) PCI Cache Line Size <byte 13208> {field (By field)} <byte 13208> tbits:8 size PCI cache line size {} or pci_clsize (Offset 0C) PCI Cache Line Size <byte 13208> utiny value As byte endunion pci_clsize (Offset 0C) PCI Cache Line Size <byte 13209> union pci_lattmr (Offset 0D) PCI Latency Timer <byte 13209> {field (By field)} <byte 13209> tbits:8 tmr PCI latency timer {} or pci_lattmr (Offset 0D) PCI Latency Timer <byte 13209> utiny value As byte endunion pci_lattmr (Offset 0D) PCI Latency Timer <byte 13210> union pci_hdrtype (Offset 0E) PCI Header Type <byte 13210> {field (By field)} <byte 13210> tbits:8 type PCI header type (read only) {} or pci_hdrtype (Offset 0E) PCI Header Type <byte 13210> utiny value As byte

endunion pci_hdrtype (Offset 0E) PCI Header Type <byte 13211> {pci_rsvd0f ((Offset 0F) Reserved (BIST))} <byte 13211> utiny value {} {} or pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST <byte 13208> ulong value As longword endunion pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST <byte 13212> {pci_rsvd10_13 ((Offset 10) Reserved (RSVBAR))} <byte 13212> ulong value {} <byte 13216> {pci_rsvd14_17 ((Offset 14) Reserved (RSVBAR))} <byte 13216> ulong value {} <byte 13220> union pci_iobasel (Offset 18) PCI Lower I/O Base Address <byte 13220> {field (By field)} <byte 13220> lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobasel (Offset 18) PCI Lower I/O Base Address <byte 13220> ulong value As longword endunion pci_iobasel (Offset 18) PCI Lower I/O Base Address <byte 13224> union pci_iobaseu (Offset 1C) PCI Upper I/O Base Address <byte 13224> {field (By field)} <byte 13224> lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobaseu (Offset 1C) PCI Upper I/O Base Address <byte 13224> ulong value As longword endunion pci_iobaseu (Offset 1C) PCI Upper I/O Base Address <byte 13228> union pci_membasel (Offset 20) PCI Lower Memory Address Base <byte 13228> {field (By field)} <byte 13228> lbits:1 memspace Memory Space Indicator lbits:2 loctype Location Type lbits:1 prefetch Prefetchable lbits:9 alwayszero Always read as zero lbits:19 baseaddr Lower Base Address {} or pci_membasel (Offset 20) PCI Lower Memory Address Base <byte 13228>

ulong value As longword (Bits 31:0) endunion pci_membasel (Offset 20) PCI Lower Memory Address Base <byte 13232> union pci_membaseu (Offset 24) PCI Upper Memory Address Base <byte 13232> {field (By field)} <byte 13232> lbits:32 baseaddr Upper Base Address {} or pci_membaseu (Offset 24) PCI Upper Memory Address Base <byte 13232> ulong value As longword (Bits 63:32) endunion pci_membaseu (Offset 24) PCI Upper Memory Address Base <byte 13236> {pci_rsrvd28_2b ((Offset 28) Reserved)} <byte 13236> ulong value {} <byte 13240> union pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID <byte 13240> {field (By field)} <byte 13240> union pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID <byte 13240> {field (By field)} <byte 13240> bits:16 id ID {} or pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID <byte 13240> ushort value As word endunion pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID <byte 13242> union pci_subsys_id (Offset 2E) PCI Subsystem ID <byte 13242> {field (By field)} <byte 13242> bits:16 id ID {} or pci_subsys_id (Offset 2E) PCI Subsystem ID <byte 13242> ushort value As word endunion pci_subsys_id (Offset 2E) PCI Subsystem ID {} or pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID <byte 13240> ulong value As longword endunion pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID <byte 13244> union pci_rombase (Offset 30) PCI ROM Base Address <byte 13244> {field (By field)} <byte 13244> lbits:1 decode_en Decode enable lbits:16 rsvd Reserved - always zero lbits:15 address Address Decoding {} or pci_rombase (Offset 30) PCI ROM Base Address <byte 13244>

ulong value As longword endunion pci_rombase (Offset 30) PCI ROM Base Address <byte 13248> union pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED <byte 13248> {field (By field)} <byte 13248> union pci_cap_ptr (Offset 34) PCI Capabilities Pointer <byte 13248> {field (By field)} <byte 13248> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_ptr (Offset 34) PCI Capabilities Pointer <byte 13248> utiny value As byte endunion pci_cap_ptr (Offset 34) PCI Capabilities Pointer <byte 13249> {pci_rsvd35 ((Offset 35) Reserved)} <byte 13249> utiny value {} <byte 13250> {pci_rsvd36_37 ((Offset 36) Reserved)} <byte 13250> ushort value {} {} or pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED <byte 13248> ulong value As longword endunion pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED <byte 13252> {pci_rsvd38_3b ((Offset 38) Reserved)} <byte 13252> ulong value {} <byte 13256> union pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED <byte 13256> {field (By field)} <byte 13256> union pci_int_line (Offset 3C) PCI Interrupt Line <byte 13256> {field (By field)} <byte 13256> tbits:8 line PCI Interrupt Line {} or pci_int_line (Offset 3C) PCI Interrupt Line <byte 13256> utiny value As byte endunion pci_int_line (Offset 3C) PCI Interrupt Line <byte 13257> union pci_int_pin (Offset 3D) PCI Interrupt Pin <byte 13257> {field (By field)} <byte 13257> tbits:8 pin PCI Interrupt Pin (read only) {} or pci_int_pin (Offset 3D) PCI Interrupt Pin

<byte 13257> utiny value As byte endunion pci_int_pin (Offset 3D) PCI Interrupt Pin <byte 13258> union pci_min_gnt (Offset 3E) PCI Minimum Grant <byte 13258> {field (By field)} <byte 13258> tbits:8 grant PCI Minimum Grant (read only) {} or pci_min_gnt (Offset 3E) PCI Minimum Grant <byte 13258> utiny value As byte endunion pci_min_gnt (Offset 3E) PCI Minimum Grant <byte 13259> {reserved ((Offset 3F) Reserved)} <byte 13259> utiny value {} {} or pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED <byte 13256> ulong value As longword endunion pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED <byte 13260> union pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR <byte 13260> {field (By field)} <byte 13260> {pci_rsvd40 ((Offset 40) Reserved)} <byte 13260> utiny value {} <byte 13261> {pci_rsvd41 ((Offset 41) Reserved)} <byte 13261> utiny value {} <byte 13262> union pci_romctr (Offset 42) PCI ROM Control <byte 13262> {field (By field)} <byte 13262> tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or pci_romctr (Offset 42) PCI ROM Control <byte 13262> utiny value As byte endunion pci_romctr (Offset 42) PCI ROM Control <byte 13263> union pci_mctr (Offset 43) PCI Master Control <byte 13263> {field (By field)} <byte 13263> tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved

tbits:1 dlt Disable Latency Timer {} or pci_mctr (Offset 43) PCI Master Control <byte 13263> utiny value As byte endunion pci_mctr (Offset 43) PCI Master Control {} or pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR <byte 13260> ulong value As longword endunion pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR <byte 13264> union pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT <byte 13264> {field (By field)} <byte 13264> union pci_softrst (Offset 44) PCI Interface Reset Control <byte 13264> {field (By field)} <byte 13264> tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or pci_softrst (Offset 44) PCI Interface Reset Control <byte 13264> utiny value As byte endunion pci_softrst (Offset 44) PCI Interface Reset Control <byte 13265> union pci_intpend (Offset 45) PCI Interrupt <byte 13265> {field (By field)} <byte 13265> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_intpend (Offset 45) PCI Interrupt <byte 13265> utiny value As byte endunion pci_intpend (Offset 45) PCI Interrupt <byte 13266> union pci_inten (Offset 46) PCI Interrupt Enable Pending <byte 13266> {field (By field)} <byte 13266> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_inten (Offset 46) PCI Interrupt Enable Pending <byte 13266> utiny value As byte endunion pci_inten (Offset 46) PCI Interrupt Enable Pending <byte 13267>

union pci_instat (Offset 47) PCI Interrupt Status <byte 13267> {field (By field)} <byte 13267> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_instat (Offset 47) PCI Interrupt Status <byte 13267> utiny value As byte endunion pci_instat (Offset 47) PCI Interrupt Status {} or pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT <byte 13264> ulong value As longword endunion pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT <byte 13268> {pci_rsvd48_4b ((Offset 48) Reserved)} <byte 13268> ulong value {} <byte 13272> {pci_rsvd4c_4f ((Offset 4C) Reserved)} <byte 13272> ulong value {} <byte 13276> union pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC <byte 13276> {field (By field)} <byte 13276> union pci_cap_id (Offset 50) PCI Capabilities Identifier <byte 13276> {field (By field)} <byte 13276> tbits:8 cap_id Capability structure identifier. {} or pci_cap_id (Offset 50) PCI Capabilities Identifier <byte 13276> utiny value As byte endunion pci_cap_id (Offset 50) PCI Capabilities Identifier <byte 13277> union pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities <byte 13277> {field (By field)} <byte 13277> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities <byte 13277> utiny value As byte endunion pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities <byte 13278> union pci_pmc (Offset 52) PCI Power Management Capabilities <byte 13278> {field (By field)}

<byte 13278> bits:3 ver PCI Power Management Specification Version bits:1 clk PME Clock bits:1 aps Auxilliary Power Source bits:1 dsi Device Specific Initialization bits:3 rsvd Reserved bits:1 d1 D1 Support bits:1 d2 D2 Support bits:5 pme PME Support {} or pci_pmc (Offset 52) PCI Power Management Capabilities <byte 13278> ushort value As word endunion pci_pmc (Offset 52) PCI Power Management Capabilities {} or pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC <byte 13276> ulong value As longword endunion pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC <byte 13280> union pci_pmcs (Offset 54) PCI Power Management Control and Status <byte 13280> {field (By field)} <byte 13280> lbits:2 pst Power State lbits:6 reserved1 Reserved lbits:1 pen PME Enable lbits:4 sel Data Select lbits:2 scl Data Scale lbits:1 pme PME Status lbits:16 reserved Reserved {} or pci_pmcs (Offset 54) PCI Power Management Control and Status <byte 13280> ulong value As word endunion pci_pmcs (Offset 54) PCI Power Management Control and Status <byte 13284> union pci_par (Offset 58) PCI Programmable Address Register <byte 13284> {field (By field)} <byte 13284> lbits:20 ra ROM/RAM Address lbits:11 rsvd Reserved lbits:1 inc Increment For DWord aligned addresses {} or pci_par (Offset 58) PCI Programmable Address Register <byte 13284> ulong value As longword endunion pci_par (Offset 58) PCI Programmable Address Register <byte 13288> union pci_dar (Offset 5C) PCI Programmable Data Register <byte 13288> {field (By field)} <byte 13288> lbits:32 data Read/Write Data {} or pci_dar (Offset 5C) PCI Programmable Data Register <byte 13288> ulong value As longword endunion pci_dar (Offset 5C) PCI Programmable Data Register

<byte 13292> {pci_rsvd60_6f ((Offset 60) Reserved)} <byte 13292> ulong value {} <byte 13296> union pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC <byte 13296> {field (By field)} <byte 13296> union pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Id entifier <byte 13296> {field (By field)} <byte 13296> tbits:8 cap_id Capability structure identifier. {} or pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Ident ifier <byte 13296> utiny value As byte endunion pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier <byte 13297> union pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capabili ty <byte 13297> {field (By field)} <byte 13297> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability <byte 13297> utiny value As byte endunion pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capab ility <byte 13298> union pci_mc (Offset 66) PCI Message Control Register <byte 13298> {field (By field)} <byte 13298> bits:1 men Message Signaled Interrupts Enable bits:3 mmc Multiple Message Capable bits:3 mme Multiple Message Enable bits:1 c64 64 Bit Address Capable Read bits:8 rsvd Reserved {} or pci_mc (Offset 66) PCI Message Control Register <byte 13298> ushort value As word endunion pci_mc (Offset 66) PCI Message Control Register {} or pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC <byte 13296> ulong value As longword endunion pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC <byte 13300> union pci_ma (Offset 68) PCI Message Address <byte 13300> {field (By field)}

<byte 13300> lbits:2 rsvd Reserved lbits:30 address Message Address {} or pci_ma (Offset 68) PCI Message Address <byte 13300> ulong value As longword endunion pci_ma (Offset 68) PCI Message Address <byte 13304> union pci_mua (Offset 6C) PCI Message Upper Address <byte 13304> {field (By field)} <byte 13304> lbits:32 address Message Upper Address {} or pci_mua (Offset 6C) PCI Message Upper Address <byte 13304> ulong value As longword endunion pci_mua (Offset 6C) PCI Message Upper Address <byte 13308> union pci_md (Offset 70) PCI Message Data <byte 13308> {field (By field)} <byte 13308> lbits:16 mid Message ID lbits:16 rsvd Reserved {} or pci_md (Offset 70) PCI Message Data <byte 13308> ulong value As longword endunion pci_md (Offset 70) PCI Message Data <byte 13312> union pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD <byte 13312> {field (By field)} <byte 13312> union pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier <byte 13312> {field (By field)} <byte 13312> tbits:8 cap_id Capability structure identifier. {} or pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier <byte 13312> utiny value As byte endunion pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier <byte 13313> union pci_x_next_cap (Offset 75) PCI Next Capability Register <byte 13313> {field (By field)} <byte 13313> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_x_next_cap (Offset 75) PCI Next Capability Register <byte 13313> utiny value As byte endunion pci_x_next_cap (Offset 75) PCI Next Capability Register <byte 13314> union pci_x_cmd (Offset 76) PCI-X Command Register <byte 13314>

{field (By field)} <byte 13314> bits:1 dper Data Parity Error Recovery bits:1 ero Enable Relaxed Ordering bits:2 mbc Maximum Memory Read Byte Count bits:3 mos Maximum Outstanding Split Transactions bits:9 rsvd Reserved {} or pci_x_cmd (Offset 76) PCI-X Command Register <byte 13314> ushort value As word endunion pci_x_cmd (Offset 76) PCI-X Command Register {} or pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD <byte 13312> ulong value As longword endunion pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD <byte 13316> union pci_x_s (Offset 78) PCI-X Status Register <byte 13316> {field (By field)} <byte 13316> lbits:3 fn Function Number lbits:5 dn Device Number lbits:8 bn Bus Number lbits:1 d64 64-bit Device lbits:1 c133 133 MHz Capable lbits:1 scd Split Completion Discarded lbits:1 usc Unexpected Split Completion lbits:1 dc Device Complexity lbits:2 dmbc Designed Maximum Memory Read Byte Count lbits:3 dmos Designed Maximum Outstanding Split Transactions lbits:3 dmcr Designed Maximum Cumulative Read Size lbits:1 rcse Received Split Completion Error Message lbits:2 rsvd Reserved {} or pci_x_s (Offset 78) PCI-X Status Register <byte 13316> ulong value As longword endunion pci_x_s (Offset 78) PCI-X Status Register {} endunion pcicfg[3] Tachyon DX2+ PCI Configuration Registers <byte 13320> union pcicfg[4] Tachyon DX2+ PCI Configuration Registers <byte 13320> ulong[31] pcicfga Tachyon DX2+ PCI Configuration Registers As Longwords or pcicfg[4] Tachyon DX2+ PCI Configuration Registers <byte 13320> {pcicfg (Tachyon DX2+ PCI Configuration Registers By Field)} <byte 13320> union pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID <byte 13320> {field (By field)} <byte 13320> union pci_vendor_id (Offset 00) PCI Vendor ID <byte 13320> {field (By field)} <byte 13320> bits:16 id ID {}

or pci_vendor_id (Offset 00) PCI Vendor ID <byte 13320> ushort value As word endunion pci_vendor_id (Offset 00) PCI Vendor ID <byte 13322> union pci_device_id (Offset 02) PCI Device ID <byte 13322> {field (By field)} <byte 13322> bits:16 id ID {} or pci_device_id (Offset 02) PCI Device ID <byte 13322> ushort value As word endunion pci_device_id (Offset 02) PCI Device ID {} or pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID <byte 13320> ulong value As longword endunion pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID <byte 13324> union pcicfg_reg_04 (Offset 04) PCI CMD/STATUS <byte 13324> {field (By field)} <byte 13324> union pci_cmd (Offset 04) PCI Command <byte 13324> {field (By field)} <byte 13324> bits:1 io_access I/O Access Control bits:1 mem_access Memory Access Control bits:1 pcim_en PCI Master Enable bits:1 scycle_en Special Cycle Enable (read only, always returns 0) bits:1 memwinv Memory Write & Invalidate bits:1 paltsnp_en Palette Snooping Enable (read only, always returns 0) bits:1 perrrsp Parity Error Response bits:1 waitcycctrl Wait Cycle Control bits:1 serrx_en SERR# Enable bits:1 fbbw_en Fast Back-to-Back Write enable (read only, always returns 0) bits:6 rsvd Reserved {} or pci_cmd (Offset 04) PCI Command <byte 13324> ushort value As word endunion pci_cmd (Offset 04) PCI Command <byte 13326> union pci_status (Offset 06) PCI Status <byte 13326> {field (By field)} <byte 13326> bits:4 rsvd Reserved bits:1 cpl New Capabilities bits:1 cap66mhz 66MHz Capable bits:1 udfsup UDF Supported (read only, always returns 0) bits:1 capfbbw Fast Back-to-Back Capable (read only, always returns 0) bits:1 dperr Data Parity Error Detected bits:2 devsel_time PCI_DEVSEL# response timing (read only, always returns 1) bits:1 sgnltabrt Signaled Target Abort bits:1 rcvdtabrt Received Target Abort bits:1 rcvdmabrt Received Master Abort

bits:1 sgnlsyserr Signaled System Error bits:1 perr Detected Parity Error {} or pci_status (Offset 06) PCI Status <byte 13326> ushort value As word endunion pci_status (Offset 06) PCI Status {} or pcicfg_reg_04 (Offset 04) PCI CMD/STATUS <byte 13324> ulong value As longword endunion pcicfg_reg_04 (Offset 04) PCI CMD/STATUS <byte 13328> union pcicfg_reg_08 (Offset 08) PCI REVID/CLASS <byte 13328> {field (By field)} <byte 13328> union pci_revid (Offset 08) PCI Revision <byte 13328> {field (By field)} <byte 13328> tbits:2 minor Minor tbits:3 major Major tbits:3 res Reserved {} or pci_revid (Offset 08) PCI Revision <byte 13328> utiny value As byte endunion pci_revid (Offset 08) PCI Revision <byte 13329> union pci_class (Offset 09) PCI Class <byte 13329> {field (By field)} <byte 13329> tbits:8 baseclcode Base Class Code <byte 13330> tbits:8 subclcode Subclass Code <byte 13331> tbits:8 reglevpi Register Level Programming Interface {} or pci_class (Offset 09) PCI Class <byte 13329> utiny[3] value As byte array endunion pci_class (Offset 09) PCI Class {} or pcicfg_reg_08 (Offset 08) PCI REVID/CLASS <byte 13328> ulong value As longword endunion pcicfg_reg_08 (Offset 08) PCI REVID/CLASS <byte 13332> union pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST <byte 13332> {field (By field)} <byte 13332> union pci_clsize (Offset 0C) PCI Cache Line Size <byte 13332> {field (By field)} <byte 13332> tbits:8 size PCI cache line size {}

or pci_clsize (Offset 0C) PCI Cache Line Size <byte 13332> utiny value As byte endunion pci_clsize (Offset 0C) PCI Cache Line Size <byte 13333> union pci_lattmr (Offset 0D) PCI Latency Timer <byte 13333> {field (By field)} <byte 13333> tbits:8 tmr PCI latency timer {} or pci_lattmr (Offset 0D) PCI Latency Timer <byte 13333> utiny value As byte endunion pci_lattmr (Offset 0D) PCI Latency Timer <byte 13334> union pci_hdrtype (Offset 0E) PCI Header Type <byte 13334> {field (By field)} <byte 13334> tbits:8 type PCI header type (read only) {} or pci_hdrtype (Offset 0E) PCI Header Type <byte 13334> utiny value As byte endunion pci_hdrtype (Offset 0E) PCI Header Type <byte 13335> {pci_rsvd0f ((Offset 0F) Reserved (BIST))} <byte 13335> utiny value {} {} or pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST <byte 13332> ulong value As longword endunion pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST <byte 13336> {pci_rsvd10_13 ((Offset 10) Reserved (RSVBAR))} <byte 13336> ulong value {} <byte 13340> {pci_rsvd14_17 ((Offset 14) Reserved (RSVBAR))} <byte 13340> ulong value {} <byte 13344> union pci_iobasel (Offset 18) PCI Lower I/O Base Address <byte 13344> {field (By field)} <byte 13344> lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobasel (Offset 18) PCI Lower I/O Base Address <byte 13344> ulong value As longword endunion pci_iobasel (Offset 18) PCI Lower I/O Base Address <byte 13348>

union pci_iobaseu (Offset 1C) PCI Upper I/O Base Address <byte 13348> {field (By field)} <byte 13348> lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobaseu (Offset 1C) PCI Upper I/O Base Address <byte 13348> ulong value As longword endunion pci_iobaseu (Offset 1C) PCI Upper I/O Base Address <byte 13352> union pci_membasel (Offset 20) PCI Lower Memory Address Base <byte 13352> {field (By field)} <byte 13352> lbits:1 memspace Memory Space Indicator lbits:2 loctype Location Type lbits:1 prefetch Prefetchable lbits:9 alwayszero Always read as zero lbits:19 baseaddr Lower Base Address {} or pci_membasel (Offset 20) PCI Lower Memory Address Base <byte 13352> ulong value As longword (Bits 31:0) endunion pci_membasel (Offset 20) PCI Lower Memory Address Base <byte 13356> union pci_membaseu (Offset 24) PCI Upper Memory Address Base <byte 13356> {field (By field)} <byte 13356> lbits:32 baseaddr Upper Base Address {} or pci_membaseu (Offset 24) PCI Upper Memory Address Base <byte 13356> ulong value As longword (Bits 63:32) endunion pci_membaseu (Offset 24) PCI Upper Memory Address Base <byte 13360> {pci_rsrvd28_2b ((Offset 28) Reserved)} <byte 13360> ulong value {} <byte 13364> union pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID <byte 13364> {field (By field)} <byte 13364> union pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID <byte 13364> {field (By field)} <byte 13364> bits:16 id ID {} or pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID <byte 13364> ushort value As word endunion pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID <byte 13366> union pci_subsys_id (Offset 2E) PCI Subsystem ID

<byte 13366> {field (By field)} <byte 13366> bits:16 id ID {} or pci_subsys_id (Offset 2E) PCI Subsystem ID <byte 13366> ushort value As word endunion pci_subsys_id (Offset 2E) PCI Subsystem ID {} or pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID <byte 13364> ulong value As longword endunion pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID <byte 13368> union pci_rombase (Offset 30) PCI ROM Base Address <byte 13368> {field (By field)} <byte 13368> lbits:1 decode_en Decode enable lbits:16 rsvd Reserved - always zero lbits:15 address Address Decoding {} or pci_rombase (Offset 30) PCI ROM Base Address <byte 13368> ulong value As longword endunion pci_rombase (Offset 30) PCI ROM Base Address <byte 13372> union pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED <byte 13372> {field (By field)} <byte 13372> union pci_cap_ptr (Offset 34) PCI Capabilities Pointer <byte 13372> {field (By field)} <byte 13372> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_ptr (Offset 34) PCI Capabilities Pointer <byte 13372> utiny value As byte endunion pci_cap_ptr (Offset 34) PCI Capabilities Pointer <byte 13373> {pci_rsvd35 ((Offset 35) Reserved)} <byte 13373> utiny value {} <byte 13374> {pci_rsvd36_37 ((Offset 36) Reserved)} <byte 13374> ushort value {} {} or pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED <byte 13372> ulong value As longword endunion pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED <byte 13376> {pci_rsvd38_3b ((Offset 38) Reserved)} <byte 13376>

ulong value {} <byte 13380> union pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED <byte 13380> {field (By field)} <byte 13380> union pci_int_line (Offset 3C) PCI Interrupt Line <byte 13380> {field (By field)} <byte 13380> tbits:8 line PCI Interrupt Line {} or pci_int_line (Offset 3C) PCI Interrupt Line <byte 13380> utiny value As byte endunion pci_int_line (Offset 3C) PCI Interrupt Line <byte 13381> union pci_int_pin (Offset 3D) PCI Interrupt Pin <byte 13381> {field (By field)} <byte 13381> tbits:8 pin PCI Interrupt Pin (read only) {} or pci_int_pin (Offset 3D) PCI Interrupt Pin <byte 13381> utiny value As byte endunion pci_int_pin (Offset 3D) PCI Interrupt Pin <byte 13382> union pci_min_gnt (Offset 3E) PCI Minimum Grant <byte 13382> {field (By field)} <byte 13382> tbits:8 grant PCI Minimum Grant (read only) {} or pci_min_gnt (Offset 3E) PCI Minimum Grant <byte 13382> utiny value As byte endunion pci_min_gnt (Offset 3E) PCI Minimum Grant <byte 13383> {reserved ((Offset 3F) Reserved)} <byte 13383> utiny value {} {} or pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED <byte 13380> ulong value As longword endunion pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED <byte 13384> union pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR <byte 13384> {field (By field)} <byte 13384> {pci_rsvd40 ((Offset 40) Reserved)} <byte 13384> utiny value {} <byte 13385> {pci_rsvd41 ((Offset 41) Reserved)}

<byte 13385> utiny value {} <byte 13386> union pci_romctr (Offset 42) PCI ROM Control <byte 13386> {field (By field)} <byte 13386> tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or pci_romctr (Offset 42) PCI ROM Control <byte 13386> utiny value As byte endunion pci_romctr (Offset 42) PCI ROM Control <byte 13387> union pci_mctr (Offset 43) PCI Master Control <byte 13387> {field (By field)} <byte 13387> tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or pci_mctr (Offset 43) PCI Master Control <byte 13387> utiny value As byte endunion pci_mctr (Offset 43) PCI Master Control {} or pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR <byte 13384> ulong value As longword endunion pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR <byte 13388> union pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT <byte 13388> {field (By field)} <byte 13388> union pci_softrst (Offset 44) PCI Interface Reset Control <byte 13388> {field (By field)} <byte 13388> tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or pci_softrst (Offset 44) PCI Interface Reset Control <byte 13388> utiny value As byte endunion pci_softrst (Offset 44) PCI Interface Reset Control <byte 13389> union pci_intpend (Offset 45) PCI Interrupt <byte 13389> {field (By field)} <byte 13389> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt

tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_intpend (Offset 45) PCI Interrupt <byte 13389> utiny value As byte endunion pci_intpend (Offset 45) PCI Interrupt <byte 13390> union pci_inten (Offset 46) PCI Interrupt Enable Pending <byte 13390> {field (By field)} <byte 13390> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_inten (Offset 46) PCI Interrupt Enable Pending <byte 13390> utiny value As byte endunion pci_inten (Offset 46) PCI Interrupt Enable Pending <byte 13391> union pci_instat (Offset 47) PCI Interrupt Status <byte 13391> {field (By field)} <byte 13391> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_instat (Offset 47) PCI Interrupt Status <byte 13391> utiny value As byte endunion pci_instat (Offset 47) PCI Interrupt Status {} or pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT <byte 13388> ulong value As longword endunion pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT <byte 13392> {pci_rsvd48_4b ((Offset 48) Reserved)} <byte 13392> ulong value {} <byte 13396> {pci_rsvd4c_4f ((Offset 4C) Reserved)} <byte 13396> ulong value {} <byte 13400> union pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC <byte 13400> {field (By field)} <byte 13400>

union pci_cap_id (Offset 50) PCI Capabilities Identifier <byte 13400> {field (By field)} <byte 13400> tbits:8 cap_id Capability structure identifier. {} or pci_cap_id (Offset 50) PCI Capabilities Identifier <byte 13400> utiny value As byte endunion pci_cap_id (Offset 50) PCI Capabilities Identifier <byte 13401> union pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities <byte 13401> {field (By field)} <byte 13401> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities <byte 13401> utiny value As byte endunion pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities <byte 13402> union pci_pmc (Offset 52) PCI Power Management Capabilities <byte 13402> {field (By field)} <byte 13402> bits:3 ver PCI Power Management Specification Version bits:1 clk PME Clock bits:1 aps Auxilliary Power Source bits:1 dsi Device Specific Initialization bits:3 rsvd Reserved bits:1 d1 D1 Support bits:1 d2 D2 Support bits:5 pme PME Support {} or pci_pmc (Offset 52) PCI Power Management Capabilities <byte 13402> ushort value As word endunion pci_pmc (Offset 52) PCI Power Management Capabilities {} or pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC <byte 13400> ulong value As longword endunion pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC <byte 13404> union pci_pmcs (Offset 54) PCI Power Management Control and Status <byte 13404> {field (By field)} <byte 13404> lbits:2 pst Power State lbits:6 reserved1 Reserved lbits:1 pen PME Enable lbits:4 sel Data Select lbits:2 scl Data Scale lbits:1 pme PME Status lbits:16 reserved Reserved {} or pci_pmcs (Offset 54) PCI Power Management Control and Status <byte 13404> ulong value As word

endunion pci_pmcs (Offset 54) PCI Power Management Control and Status <byte 13408> union pci_par (Offset 58) PCI Programmable Address Register <byte 13408> {field (By field)} <byte 13408> lbits:20 ra ROM/RAM Address lbits:11 rsvd Reserved lbits:1 inc Increment For DWord aligned addresses {} or pci_par (Offset 58) PCI Programmable Address Register <byte 13408> ulong value As longword endunion pci_par (Offset 58) PCI Programmable Address Register <byte 13412> union pci_dar (Offset 5C) PCI Programmable Data Register <byte 13412> {field (By field)} <byte 13412> lbits:32 data Read/Write Data {} or pci_dar (Offset 5C) PCI Programmable Data Register <byte 13412> ulong value As longword endunion pci_dar (Offset 5C) PCI Programmable Data Register <byte 13416> {pci_rsvd60_6f ((Offset 60) Reserved)} <byte 13416> ulong value {} <byte 13420> union pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC <byte 13420> {field (By field)} <byte 13420> union pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Id entifier <byte 13420> {field (By field)} <byte 13420> tbits:8 cap_id Capability structure identifier. {} or pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Ident ifier <byte 13420> utiny value As byte endunion pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier <byte 13421> union pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capabili ty <byte 13421> {field (By field)} <byte 13421> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability <byte 13421> utiny value As byte endunion pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capab

ility <byte 13422> union pci_mc (Offset 66) PCI Message Control Register <byte 13422> {field (By field)} <byte 13422> bits:1 men Message Signaled Interrupts Enable bits:3 mmc Multiple Message Capable bits:3 mme Multiple Message Enable bits:1 c64 64 Bit Address Capable Read bits:8 rsvd Reserved {} or pci_mc (Offset 66) PCI Message Control Register <byte 13422> ushort value As word endunion pci_mc (Offset 66) PCI Message Control Register {} or pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC <byte 13420> ulong value As longword endunion pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC <byte 13424> union pci_ma (Offset 68) PCI Message Address <byte 13424> {field (By field)} <byte 13424> lbits:2 rsvd Reserved lbits:30 address Message Address {} or pci_ma (Offset 68) PCI Message Address <byte 13424> ulong value As longword endunion pci_ma (Offset 68) PCI Message Address <byte 13428> union pci_mua (Offset 6C) PCI Message Upper Address <byte 13428> {field (By field)} <byte 13428> lbits:32 address Message Upper Address {} or pci_mua (Offset 6C) PCI Message Upper Address <byte 13428> ulong value As longword endunion pci_mua (Offset 6C) PCI Message Upper Address <byte 13432> union pci_md (Offset 70) PCI Message Data <byte 13432> {field (By field)} <byte 13432> lbits:16 mid Message ID lbits:16 rsvd Reserved {} or pci_md (Offset 70) PCI Message Data <byte 13432> ulong value As longword endunion pci_md (Offset 70) PCI Message Data <byte 13436> union pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD <byte 13436> {field (By field)}

<byte 13436> union pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier <byte 13436> {field (By field)} <byte 13436> tbits:8 cap_id Capability structure identifier. {} or pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier <byte 13436> utiny value As byte endunion pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier <byte 13437> union pci_x_next_cap (Offset 75) PCI Next Capability Register <byte 13437> {field (By field)} <byte 13437> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_x_next_cap (Offset 75) PCI Next Capability Register <byte 13437> utiny value As byte endunion pci_x_next_cap (Offset 75) PCI Next Capability Register <byte 13438> union pci_x_cmd (Offset 76) PCI-X Command Register <byte 13438> {field (By field)} <byte 13438> bits:1 dper Data Parity Error Recovery bits:1 ero Enable Relaxed Ordering bits:2 mbc Maximum Memory Read Byte Count bits:3 mos Maximum Outstanding Split Transactions bits:9 rsvd Reserved {} or pci_x_cmd (Offset 76) PCI-X Command Register <byte 13438> ushort value As word endunion pci_x_cmd (Offset 76) PCI-X Command Register {} or pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD <byte 13436> ulong value As longword endunion pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD <byte 13440> union pci_x_s (Offset 78) PCI-X Status Register <byte 13440> {field (By field)} <byte 13440> lbits:3 fn Function Number lbits:5 dn Device Number lbits:8 bn Bus Number lbits:1 d64 64-bit Device lbits:1 c133 133 MHz Capable lbits:1 scd Split Completion Discarded lbits:1 usc Unexpected Split Completion lbits:1 dc Device Complexity lbits:2 dmbc Designed Maximum Memory Read Byte Count lbits:3 dmos Designed Maximum Outstanding Split Transactions lbits:3 dmcr Designed Maximum Cumulative Read Size lbits:1 rcse Received Split Completion Error Message lbits:2 rsvd Reserved

{} or pci_x_s (Offset 78) PCI-X Status Register <byte 13440> ulong value As longword endunion pci_x_s (Offset 78) PCI-X Status Register {} endunion pcicfg[4] Tachyon DX2+ PCI Configuration Registers <byte 13444> union pcicfg[5] Tachyon DX2+ PCI Configuration Registers <byte 13444> ulong[31] pcicfga Tachyon DX2+ PCI Configuration Registers As Longwords or pcicfg[5] Tachyon DX2+ PCI Configuration Registers <byte 13444> {pcicfg (Tachyon DX2+ PCI Configuration Registers By Field)} <byte 13444> union pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID <byte 13444> {field (By field)} <byte 13444> union pci_vendor_id (Offset 00) PCI Vendor ID <byte 13444> {field (By field)} <byte 13444> bits:16 id ID {} or pci_vendor_id (Offset 00) PCI Vendor ID <byte 13444> ushort value As word endunion pci_vendor_id (Offset 00) PCI Vendor ID <byte 13446> union pci_device_id (Offset 02) PCI Device ID <byte 13446> {field (By field)} <byte 13446> bits:16 id ID {} or pci_device_id (Offset 02) PCI Device ID <byte 13446> ushort value As word endunion pci_device_id (Offset 02) PCI Device ID {} or pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID <byte 13444> ulong value As longword endunion pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID <byte 13448> union pcicfg_reg_04 (Offset 04) PCI CMD/STATUS <byte 13448> {field (By field)} <byte 13448> union pci_cmd (Offset 04) PCI Command <byte 13448> {field (By field)} <byte 13448> bits:1 io_access I/O Access Control bits:1 mem_access Memory Access Control bits:1 pcim_en PCI Master Enable bits:1 scycle_en Special Cycle Enable (read only, always returns 0) bits:1 memwinv Memory Write & Invalidate bits:1 paltsnp_en Palette Snooping Enable (read only, always returns 0)

bits:1 perrrsp Parity Error Response bits:1 waitcycctrl Wait Cycle Control bits:1 serrx_en SERR# Enable bits:1 fbbw_en Fast Back-to-Back Write enable (read only, always returns 0) bits:6 rsvd Reserved {} or pci_cmd (Offset 04) PCI Command <byte 13448> ushort value As word endunion pci_cmd (Offset 04) PCI Command <byte 13450> union pci_status (Offset 06) PCI Status <byte 13450> {field (By field)} <byte 13450> bits:4 rsvd Reserved bits:1 cpl New Capabilities bits:1 cap66mhz 66MHz Capable bits:1 udfsup UDF Supported (read only, always returns 0) bits:1 capfbbw Fast Back-to-Back Capable (read only, always returns 0) bits:1 dperr Data Parity Error Detected bits:2 devsel_time PCI_DEVSEL# response timing (read only, always returns 1) bits:1 sgnltabrt Signaled Target Abort bits:1 rcvdtabrt Received Target Abort bits:1 rcvdmabrt Received Master Abort bits:1 sgnlsyserr Signaled System Error bits:1 perr Detected Parity Error {} or pci_status (Offset 06) PCI Status <byte 13450> ushort value As word endunion pci_status (Offset 06) PCI Status {} or pcicfg_reg_04 (Offset 04) PCI CMD/STATUS <byte 13448> ulong value As longword endunion pcicfg_reg_04 (Offset 04) PCI CMD/STATUS <byte 13452> union pcicfg_reg_08 (Offset 08) PCI REVID/CLASS <byte 13452> {field (By field)} <byte 13452> union pci_revid (Offset 08) PCI Revision <byte 13452> {field (By field)} <byte 13452> tbits:2 minor Minor tbits:3 major Major tbits:3 res Reserved {} or pci_revid (Offset 08) PCI Revision <byte 13452> utiny value As byte endunion pci_revid (Offset 08) PCI Revision <byte 13453> union pci_class (Offset 09) PCI Class <byte 13453> {field (By field)} <byte 13453> tbits:8 baseclcode Base Class Code

<byte 13454> tbits:8 subclcode Subclass Code <byte 13455> tbits:8 reglevpi Register Level Programming Interface {} or pci_class (Offset 09) PCI Class <byte 13453> utiny[3] value As byte array endunion pci_class (Offset 09) PCI Class {} or pcicfg_reg_08 (Offset 08) PCI REVID/CLASS <byte 13452> ulong value As longword endunion pcicfg_reg_08 (Offset 08) PCI REVID/CLASS <byte 13456> union pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST <byte 13456> {field (By field)} <byte 13456> union pci_clsize (Offset 0C) PCI Cache Line Size <byte 13456> {field (By field)} <byte 13456> tbits:8 size PCI cache line size {} or pci_clsize (Offset 0C) PCI Cache Line Size <byte 13456> utiny value As byte endunion pci_clsize (Offset 0C) PCI Cache Line Size <byte 13457> union pci_lattmr (Offset 0D) PCI Latency Timer <byte 13457> {field (By field)} <byte 13457> tbits:8 tmr PCI latency timer {} or pci_lattmr (Offset 0D) PCI Latency Timer <byte 13457> utiny value As byte endunion pci_lattmr (Offset 0D) PCI Latency Timer <byte 13458> union pci_hdrtype (Offset 0E) PCI Header Type <byte 13458> {field (By field)} <byte 13458> tbits:8 type PCI header type (read only) {} or pci_hdrtype (Offset 0E) PCI Header Type <byte 13458> utiny value As byte endunion pci_hdrtype (Offset 0E) PCI Header Type <byte 13459> {pci_rsvd0f ((Offset 0F) Reserved (BIST))} <byte 13459> utiny value {} {} or pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST <byte 13456> ulong value As longword

endunion pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST <byte 13460> {pci_rsvd10_13 ((Offset 10) Reserved (RSVBAR))} <byte 13460> ulong value {} <byte 13464> {pci_rsvd14_17 ((Offset 14) Reserved (RSVBAR))} <byte 13464> ulong value {} <byte 13468> union pci_iobasel (Offset 18) PCI Lower I/O Base Address <byte 13468> {field (By field)} <byte 13468> lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobasel (Offset 18) PCI Lower I/O Base Address <byte 13468> ulong value As longword endunion pci_iobasel (Offset 18) PCI Lower I/O Base Address <byte 13472> union pci_iobaseu (Offset 1C) PCI Upper I/O Base Address <byte 13472> {field (By field)} <byte 13472> lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobaseu (Offset 1C) PCI Upper I/O Base Address <byte 13472> ulong value As longword endunion pci_iobaseu (Offset 1C) PCI Upper I/O Base Address <byte 13476> union pci_membasel (Offset 20) PCI Lower Memory Address Base <byte 13476> {field (By field)} <byte 13476> lbits:1 memspace Memory Space Indicator lbits:2 loctype Location Type lbits:1 prefetch Prefetchable lbits:9 alwayszero Always read as zero lbits:19 baseaddr Lower Base Address {} or pci_membasel (Offset 20) PCI Lower Memory Address Base <byte 13476> ulong value As longword (Bits 31:0) endunion pci_membasel (Offset 20) PCI Lower Memory Address Base <byte 13480> union pci_membaseu (Offset 24) PCI Upper Memory Address Base <byte 13480> {field (By field)} <byte 13480> lbits:32 baseaddr Upper Base Address {} or pci_membaseu (Offset 24) PCI Upper Memory Address Base

<byte 13480> ulong value As longword (Bits 63:32) endunion pci_membaseu (Offset 24) PCI Upper Memory Address Base <byte 13484> {pci_rsrvd28_2b ((Offset 28) Reserved)} <byte 13484> ulong value {} <byte 13488> union pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID <byte 13488> {field (By field)} <byte 13488> union pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID <byte 13488> {field (By field)} <byte 13488> bits:16 id ID {} or pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID <byte 13488> ushort value As word endunion pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID <byte 13490> union pci_subsys_id (Offset 2E) PCI Subsystem ID <byte 13490> {field (By field)} <byte 13490> bits:16 id ID {} or pci_subsys_id (Offset 2E) PCI Subsystem ID <byte 13490> ushort value As word endunion pci_subsys_id (Offset 2E) PCI Subsystem ID {} or pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID <byte 13488> ulong value As longword endunion pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID <byte 13492> union pci_rombase (Offset 30) PCI ROM Base Address <byte 13492> {field (By field)} <byte 13492> lbits:1 decode_en Decode enable lbits:16 rsvd Reserved - always zero lbits:15 address Address Decoding {} or pci_rombase (Offset 30) PCI ROM Base Address <byte 13492> ulong value As longword endunion pci_rombase (Offset 30) PCI ROM Base Address <byte 13496> union pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED <byte 13496> {field (By field)} <byte 13496> union pci_cap_ptr (Offset 34) PCI Capabilities Pointer <byte 13496> {field (By field)}

<byte 13496> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_ptr (Offset 34) PCI Capabilities Pointer <byte 13496> utiny value As byte endunion pci_cap_ptr (Offset 34) PCI Capabilities Pointer <byte 13497> {pci_rsvd35 ((Offset 35) Reserved)} <byte 13497> utiny value {} <byte 13498> {pci_rsvd36_37 ((Offset 36) Reserved)} <byte 13498> ushort value {} {} or pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED <byte 13496> ulong value As longword endunion pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED <byte 13500> {pci_rsvd38_3b ((Offset 38) Reserved)} <byte 13500> ulong value {} <byte 13504> union pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED <byte 13504> {field (By field)} <byte 13504> union pci_int_line (Offset 3C) PCI Interrupt Line <byte 13504> {field (By field)} <byte 13504> tbits:8 line PCI Interrupt Line {} or pci_int_line (Offset 3C) PCI Interrupt Line <byte 13504> utiny value As byte endunion pci_int_line (Offset 3C) PCI Interrupt Line <byte 13505> union pci_int_pin (Offset 3D) PCI Interrupt Pin <byte 13505> {field (By field)} <byte 13505> tbits:8 pin PCI Interrupt Pin (read only) {} or pci_int_pin (Offset 3D) PCI Interrupt Pin <byte 13505> utiny value As byte endunion pci_int_pin (Offset 3D) PCI Interrupt Pin <byte 13506> union pci_min_gnt (Offset 3E) PCI Minimum Grant <byte 13506> {field (By field)} <byte 13506> tbits:8 grant PCI Minimum Grant (read only) {}

or pci_min_gnt (Offset 3E) PCI Minimum Grant <byte 13506> utiny value As byte endunion pci_min_gnt (Offset 3E) PCI Minimum Grant <byte 13507> {reserved ((Offset 3F) Reserved)} <byte 13507> utiny value {} {} or pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED <byte 13504> ulong value As longword endunion pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED <byte 13508> union pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR <byte 13508> {field (By field)} <byte 13508> {pci_rsvd40 ((Offset 40) Reserved)} <byte 13508> utiny value {} <byte 13509> {pci_rsvd41 ((Offset 41) Reserved)} <byte 13509> utiny value {} <byte 13510> union pci_romctr (Offset 42) PCI ROM Control <byte 13510> {field (By field)} <byte 13510> tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or pci_romctr (Offset 42) PCI ROM Control <byte 13510> utiny value As byte endunion pci_romctr (Offset 42) PCI ROM Control <byte 13511> union pci_mctr (Offset 43) PCI Master Control <byte 13511> {field (By field)} <byte 13511> tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or pci_mctr (Offset 43) PCI Master Control <byte 13511> utiny value As byte endunion pci_mctr (Offset 43) PCI Master Control {} or pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR <byte 13508> ulong value As longword

endunion pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR <byte 13512> union pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT <byte 13512> {field (By field)} <byte 13512> union pci_softrst (Offset 44) PCI Interface Reset Control <byte 13512> {field (By field)} <byte 13512> tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or pci_softrst (Offset 44) PCI Interface Reset Control <byte 13512> utiny value As byte endunion pci_softrst (Offset 44) PCI Interface Reset Control <byte 13513> union pci_intpend (Offset 45) PCI Interrupt <byte 13513> {field (By field)} <byte 13513> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_intpend (Offset 45) PCI Interrupt <byte 13513> utiny value As byte endunion pci_intpend (Offset 45) PCI Interrupt <byte 13514> union pci_inten (Offset 46) PCI Interrupt Enable Pending <byte 13514> {field (By field)} <byte 13514> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_inten (Offset 46) PCI Interrupt Enable Pending <byte 13514> utiny value As byte endunion pci_inten (Offset 46) PCI Interrupt Enable Pending <byte 13515> union pci_instat (Offset 47) PCI Interrupt Status <byte 13515> {field (By field)} <byte 13515> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved

{} or pci_instat (Offset 47) PCI Interrupt Status <byte 13515> utiny value As byte endunion pci_instat (Offset 47) PCI Interrupt Status {} or pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT <byte 13512> ulong value As longword endunion pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT <byte 13516> {pci_rsvd48_4b ((Offset 48) Reserved)} <byte 13516> ulong value {} <byte 13520> {pci_rsvd4c_4f ((Offset 4C) Reserved)} <byte 13520> ulong value {} <byte 13524> union pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC <byte 13524> {field (By field)} <byte 13524> union pci_cap_id (Offset 50) PCI Capabilities Identifier <byte 13524> {field (By field)} <byte 13524> tbits:8 cap_id Capability structure identifier. {} or pci_cap_id (Offset 50) PCI Capabilities Identifier <byte 13524> utiny value As byte endunion pci_cap_id (Offset 50) PCI Capabilities Identifier <byte 13525> union pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities <byte 13525> {field (By field)} <byte 13525> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities <byte 13525> utiny value As byte endunion pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities <byte 13526> union pci_pmc (Offset 52) PCI Power Management Capabilities <byte 13526> {field (By field)} <byte 13526> bits:3 ver PCI Power Management Specification Version bits:1 clk PME Clock bits:1 aps Auxilliary Power Source bits:1 dsi Device Specific Initialization bits:3 rsvd Reserved bits:1 d1 D1 Support bits:1 d2 D2 Support bits:5 pme PME Support {}

or pci_pmc (Offset 52) PCI Power Management Capabilities <byte 13526> ushort value As word endunion pci_pmc (Offset 52) PCI Power Management Capabilities {} or pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC <byte 13524> ulong value As longword endunion pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC <byte 13528> union pci_pmcs (Offset 54) PCI Power Management Control and Status <byte 13528> {field (By field)} <byte 13528> lbits:2 pst Power State lbits:6 reserved1 Reserved lbits:1 pen PME Enable lbits:4 sel Data Select lbits:2 scl Data Scale lbits:1 pme PME Status lbits:16 reserved Reserved {} or pci_pmcs (Offset 54) PCI Power Management Control and Status <byte 13528> ulong value As word endunion pci_pmcs (Offset 54) PCI Power Management Control and Status <byte 13532> union pci_par (Offset 58) PCI Programmable Address Register <byte 13532> {field (By field)} <byte 13532> lbits:20 ra ROM/RAM Address lbits:11 rsvd Reserved lbits:1 inc Increment For DWord aligned addresses {} or pci_par (Offset 58) PCI Programmable Address Register <byte 13532> ulong value As longword endunion pci_par (Offset 58) PCI Programmable Address Register <byte 13536> union pci_dar (Offset 5C) PCI Programmable Data Register <byte 13536> {field (By field)} <byte 13536> lbits:32 data Read/Write Data {} or pci_dar (Offset 5C) PCI Programmable Data Register <byte 13536> ulong value As longword endunion pci_dar (Offset 5C) PCI Programmable Data Register <byte 13540> {pci_rsvd60_6f ((Offset 60) Reserved)} <byte 13540> ulong value {} <byte 13544> union pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC <byte 13544> {field (By field)} <byte 13544>

union pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Id entifier <byte 13544> {field (By field)} <byte 13544> tbits:8 cap_id Capability structure identifier. {} or pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Ident ifier <byte 13544> utiny value As byte endunion pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier <byte 13545> union pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capabili ty <byte 13545> {field (By field)} <byte 13545> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability <byte 13545> utiny value As byte endunion pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capab ility <byte 13546> union pci_mc (Offset 66) PCI Message Control Register <byte 13546> {field (By field)} <byte 13546> bits:1 men Message Signaled Interrupts Enable bits:3 mmc Multiple Message Capable bits:3 mme Multiple Message Enable bits:1 c64 64 Bit Address Capable Read bits:8 rsvd Reserved {} or pci_mc (Offset 66) PCI Message Control Register <byte 13546> ushort value As word endunion pci_mc (Offset 66) PCI Message Control Register {} or pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC <byte 13544> ulong value As longword endunion pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC <byte 13548> union pci_ma (Offset 68) PCI Message Address <byte 13548> {field (By field)} <byte 13548> lbits:2 rsvd Reserved lbits:30 address Message Address {} or pci_ma (Offset 68) PCI Message Address <byte 13548> ulong value As longword endunion pci_ma (Offset 68) PCI Message Address <byte 13552> union pci_mua (Offset 6C) PCI Message Upper Address

<byte 13552> {field (By field)} <byte 13552> lbits:32 address Message Upper Address {} or pci_mua (Offset 6C) PCI Message Upper Address <byte 13552> ulong value As longword endunion pci_mua (Offset 6C) PCI Message Upper Address <byte 13556> union pci_md (Offset 70) PCI Message Data <byte 13556> {field (By field)} <byte 13556> lbits:16 mid Message ID lbits:16 rsvd Reserved {} or pci_md (Offset 70) PCI Message Data <byte 13556> ulong value As longword endunion pci_md (Offset 70) PCI Message Data <byte 13560> union pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD <byte 13560> {field (By field)} <byte 13560> union pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier <byte 13560> {field (By field)} <byte 13560> tbits:8 cap_id Capability structure identifier. {} or pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier <byte 13560> utiny value As byte endunion pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier <byte 13561> union pci_x_next_cap (Offset 75) PCI Next Capability Register <byte 13561> {field (By field)} <byte 13561> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_x_next_cap (Offset 75) PCI Next Capability Register <byte 13561> utiny value As byte endunion pci_x_next_cap (Offset 75) PCI Next Capability Register <byte 13562> union pci_x_cmd (Offset 76) PCI-X Command Register <byte 13562> {field (By field)} <byte 13562> bits:1 dper Data Parity Error Recovery bits:1 ero Enable Relaxed Ordering bits:2 mbc Maximum Memory Read Byte Count bits:3 mos Maximum Outstanding Split Transactions bits:9 rsvd Reserved {} or pci_x_cmd (Offset 76) PCI-X Command Register <byte 13562>

ushort value As word endunion pci_x_cmd (Offset 76) PCI-X Command Register {} or pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD <byte 13560> ulong value As longword endunion pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD <byte 13564> union pci_x_s (Offset 78) PCI-X Status Register <byte 13564> {field (By field)} <byte 13564> lbits:3 fn Function Number lbits:5 dn Device Number lbits:8 bn Bus Number lbits:1 d64 64-bit Device lbits:1 c133 133 MHz Capable lbits:1 scd Split Completion Discarded lbits:1 usc Unexpected Split Completion lbits:1 dc Device Complexity lbits:2 dmbc Designed Maximum Memory Read Byte Count lbits:3 dmos Designed Maximum Outstanding Split Transactions lbits:3 dmcr Designed Maximum Cumulative Read Size lbits:1 rcse Received Split Completion Error Message lbits:2 rsvd Reserved {} or pci_x_s (Offset 78) PCI-X Status Register <byte 13564> ulong value As longword endunion pci_x_s (Offset 78) PCI-X Status Register {} endunion pcicfg[5] Tachyon DX2+ PCI Configuration Registers <byte 13568> union pcicfg[6] Tachyon DX2+ PCI Configuration Registers <byte 13568> ulong[31] pcicfga Tachyon DX2+ PCI Configuration Registers As Longwords or pcicfg[6] Tachyon DX2+ PCI Configuration Registers <byte 13568> {pcicfg (Tachyon DX2+ PCI Configuration Registers By Field)} <byte 13568> union pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID <byte 13568> {field (By field)} <byte 13568> union pci_vendor_id (Offset 00) PCI Vendor ID <byte 13568> {field (By field)} <byte 13568> bits:16 id ID {} or pci_vendor_id (Offset 00) PCI Vendor ID <byte 13568> ushort value As word endunion pci_vendor_id (Offset 00) PCI Vendor ID <byte 13570> union pci_device_id (Offset 02) PCI Device ID <byte 13570> {field (By field)} <byte 13570> bits:16 id ID

{} or pci_device_id (Offset 02) PCI Device ID <byte 13570> ushort value As word endunion pci_device_id (Offset 02) PCI Device ID {} or pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID <byte 13568> ulong value As longword endunion pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID <byte 13572> union pcicfg_reg_04 (Offset 04) PCI CMD/STATUS <byte 13572> {field (By field)} <byte 13572> union pci_cmd (Offset 04) PCI Command <byte 13572> {field (By field)} <byte 13572> bits:1 io_access I/O Access Control bits:1 mem_access Memory Access Control bits:1 pcim_en PCI Master Enable bits:1 scycle_en Special Cycle Enable (read only, always returns 0) bits:1 memwinv Memory Write & Invalidate bits:1 paltsnp_en Palette Snooping Enable (read only, always returns 0) bits:1 perrrsp Parity Error Response bits:1 waitcycctrl Wait Cycle Control bits:1 serrx_en SERR# Enable bits:1 fbbw_en Fast Back-to-Back Write enable (read only, always returns 0) bits:6 rsvd Reserved {} or pci_cmd (Offset 04) PCI Command <byte 13572> ushort value As word endunion pci_cmd (Offset 04) PCI Command <byte 13574> union pci_status (Offset 06) PCI Status <byte 13574> {field (By field)} <byte 13574> bits:4 rsvd Reserved bits:1 cpl New Capabilities bits:1 cap66mhz 66MHz Capable bits:1 udfsup UDF Supported (read only, always returns 0) bits:1 capfbbw Fast Back-to-Back Capable (read only, always returns 0) bits:1 dperr Data Parity Error Detected bits:2 devsel_time PCI_DEVSEL# response timing (read only, always returns 1) bits:1 sgnltabrt Signaled Target Abort bits:1 rcvdtabrt Received Target Abort bits:1 rcvdmabrt Received Master Abort bits:1 sgnlsyserr Signaled System Error bits:1 perr Detected Parity Error {} or pci_status (Offset 06) PCI Status <byte 13574> ushort value As word endunion pci_status (Offset 06) PCI Status {} or pcicfg_reg_04 (Offset 04) PCI CMD/STATUS <byte 13572>

ulong value As longword endunion pcicfg_reg_04 (Offset 04) PCI CMD/STATUS <byte 13576> union pcicfg_reg_08 (Offset 08) PCI REVID/CLASS <byte 13576> {field (By field)} <byte 13576> union pci_revid (Offset 08) PCI Revision <byte 13576> {field (By field)} <byte 13576> tbits:2 minor Minor tbits:3 major Major tbits:3 res Reserved {} or pci_revid (Offset 08) PCI Revision <byte 13576> utiny value As byte endunion pci_revid (Offset 08) PCI Revision <byte 13577> union pci_class (Offset 09) PCI Class <byte 13577> {field (By field)} <byte 13577> tbits:8 baseclcode Base Class Code <byte 13578> tbits:8 subclcode Subclass Code <byte 13579> tbits:8 reglevpi Register Level Programming Interface {} or pci_class (Offset 09) PCI Class <byte 13577> utiny[3] value As byte array endunion pci_class (Offset 09) PCI Class {} or pcicfg_reg_08 (Offset 08) PCI REVID/CLASS <byte 13576> ulong value As longword endunion pcicfg_reg_08 (Offset 08) PCI REVID/CLASS <byte 13580> union pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST <byte 13580> {field (By field)} <byte 13580> union pci_clsize (Offset 0C) PCI Cache Line Size <byte 13580> {field (By field)} <byte 13580> tbits:8 size PCI cache line size {} or pci_clsize (Offset 0C) PCI Cache Line Size <byte 13580> utiny value As byte endunion pci_clsize (Offset 0C) PCI Cache Line Size <byte 13581> union pci_lattmr (Offset 0D) PCI Latency Timer <byte 13581> {field (By field)} <byte 13581> tbits:8 tmr PCI latency timer

{} or pci_lattmr (Offset 0D) PCI Latency Timer <byte 13581> utiny value As byte endunion pci_lattmr (Offset 0D) PCI Latency Timer <byte 13582> union pci_hdrtype (Offset 0E) PCI Header Type <byte 13582> {field (By field)} <byte 13582> tbits:8 type PCI header type (read only) {} or pci_hdrtype (Offset 0E) PCI Header Type <byte 13582> utiny value As byte endunion pci_hdrtype (Offset 0E) PCI Header Type <byte 13583> {pci_rsvd0f ((Offset 0F) Reserved (BIST))} <byte 13583> utiny value {} {} or pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST <byte 13580> ulong value As longword endunion pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST <byte 13584> {pci_rsvd10_13 ((Offset 10) Reserved (RSVBAR))} <byte 13584> ulong value {} <byte 13588> {pci_rsvd14_17 ((Offset 14) Reserved (RSVBAR))} <byte 13588> ulong value {} <byte 13592> union pci_iobasel (Offset 18) PCI Lower I/O Base Address <byte 13592> {field (By field)} <byte 13592> lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobasel (Offset 18) PCI Lower I/O Base Address <byte 13592> ulong value As longword endunion pci_iobasel (Offset 18) PCI Lower I/O Base Address <byte 13596> union pci_iobaseu (Offset 1C) PCI Upper I/O Base Address <byte 13596> {field (By field)} <byte 13596> lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobaseu (Offset 1C) PCI Upper I/O Base Address <byte 13596>

ulong value As longword endunion pci_iobaseu (Offset 1C) PCI Upper I/O Base Address <byte 13600> union pci_membasel (Offset 20) PCI Lower Memory Address Base <byte 13600> {field (By field)} <byte 13600> lbits:1 memspace Memory Space Indicator lbits:2 loctype Location Type lbits:1 prefetch Prefetchable lbits:9 alwayszero Always read as zero lbits:19 baseaddr Lower Base Address {} or pci_membasel (Offset 20) PCI Lower Memory Address Base <byte 13600> ulong value As longword (Bits 31:0) endunion pci_membasel (Offset 20) PCI Lower Memory Address Base <byte 13604> union pci_membaseu (Offset 24) PCI Upper Memory Address Base <byte 13604> {field (By field)} <byte 13604> lbits:32 baseaddr Upper Base Address {} or pci_membaseu (Offset 24) PCI Upper Memory Address Base <byte 13604> ulong value As longword (Bits 63:32) endunion pci_membaseu (Offset 24) PCI Upper Memory Address Base <byte 13608> {pci_rsrvd28_2b ((Offset 28) Reserved)} <byte 13608> ulong value {} <byte 13612> union pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID <byte 13612> {field (By field)} <byte 13612> union pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID <byte 13612> {field (By field)} <byte 13612> bits:16 id ID {} or pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID <byte 13612> ushort value As word endunion pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID <byte 13614> union pci_subsys_id (Offset 2E) PCI Subsystem ID <byte 13614> {field (By field)} <byte 13614> bits:16 id ID {} or pci_subsys_id (Offset 2E) PCI Subsystem ID <byte 13614> ushort value As word endunion pci_subsys_id (Offset 2E) PCI Subsystem ID {}

or pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID <byte 13612> ulong value As longword endunion pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID <byte 13616> union pci_rombase (Offset 30) PCI ROM Base Address <byte 13616> {field (By field)} <byte 13616> lbits:1 decode_en Decode enable lbits:16 rsvd Reserved - always zero lbits:15 address Address Decoding {} or pci_rombase (Offset 30) PCI ROM Base Address <byte 13616> ulong value As longword endunion pci_rombase (Offset 30) PCI ROM Base Address <byte 13620> union pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED <byte 13620> {field (By field)} <byte 13620> union pci_cap_ptr (Offset 34) PCI Capabilities Pointer <byte 13620> {field (By field)} <byte 13620> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_ptr (Offset 34) PCI Capabilities Pointer <byte 13620> utiny value As byte endunion pci_cap_ptr (Offset 34) PCI Capabilities Pointer <byte 13621> {pci_rsvd35 ((Offset 35) Reserved)} <byte 13621> utiny value {} <byte 13622> {pci_rsvd36_37 ((Offset 36) Reserved)} <byte 13622> ushort value {} {} or pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED <byte 13620> ulong value As longword endunion pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED <byte 13624> {pci_rsvd38_3b ((Offset 38) Reserved)} <byte 13624> ulong value {} <byte 13628> union pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED <byte 13628> {field (By field)} <byte 13628> union pci_int_line (Offset 3C) PCI Interrupt Line <byte 13628> {field (By field)}

<byte 13628> tbits:8 line PCI Interrupt Line {} or pci_int_line (Offset 3C) PCI Interrupt Line <byte 13628> utiny value As byte endunion pci_int_line (Offset 3C) PCI Interrupt Line <byte 13629> union pci_int_pin (Offset 3D) PCI Interrupt Pin <byte 13629> {field (By field)} <byte 13629> tbits:8 pin PCI Interrupt Pin (read only) {} or pci_int_pin (Offset 3D) PCI Interrupt Pin <byte 13629> utiny value As byte endunion pci_int_pin (Offset 3D) PCI Interrupt Pin <byte 13630> union pci_min_gnt (Offset 3E) PCI Minimum Grant <byte 13630> {field (By field)} <byte 13630> tbits:8 grant PCI Minimum Grant (read only) {} or pci_min_gnt (Offset 3E) PCI Minimum Grant <byte 13630> utiny value As byte endunion pci_min_gnt (Offset 3E) PCI Minimum Grant <byte 13631> {reserved ((Offset 3F) Reserved)} <byte 13631> utiny value {} {} or pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED <byte 13628> ulong value As longword endunion pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED <byte 13632> union pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR <byte 13632> {field (By field)} <byte 13632> {pci_rsvd40 ((Offset 40) Reserved)} <byte 13632> utiny value {} <byte 13633> {pci_rsvd41 ((Offset 41) Reserved)} <byte 13633> utiny value {} <byte 13634> union pci_romctr (Offset 42) PCI ROM Control <byte 13634> {field (By field)} <byte 13634> tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only)

tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or pci_romctr (Offset 42) PCI ROM Control <byte 13634> utiny value As byte endunion pci_romctr (Offset 42) PCI ROM Control <byte 13635> union pci_mctr (Offset 43) PCI Master Control <byte 13635> {field (By field)} <byte 13635> tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or pci_mctr (Offset 43) PCI Master Control <byte 13635> utiny value As byte endunion pci_mctr (Offset 43) PCI Master Control {} or pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR <byte 13632> ulong value As longword endunion pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR <byte 13636> union pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT <byte 13636> {field (By field)} <byte 13636> union pci_softrst (Offset 44) PCI Interface Reset Control <byte 13636> {field (By field)} <byte 13636> tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or pci_softrst (Offset 44) PCI Interface Reset Control <byte 13636> utiny value As byte endunion pci_softrst (Offset 44) PCI Interface Reset Control <byte 13637> union pci_intpend (Offset 45) PCI Interrupt <byte 13637> {field (By field)} <byte 13637> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_intpend (Offset 45) PCI Interrupt <byte 13637> utiny value As byte endunion pci_intpend (Offset 45) PCI Interrupt <byte 13638> union pci_inten (Offset 46) PCI Interrupt Enable Pending

<byte 13638> {field (By field)} <byte 13638> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_inten (Offset 46) PCI Interrupt Enable Pending <byte 13638> utiny value As byte endunion pci_inten (Offset 46) PCI Interrupt Enable Pending <byte 13639> union pci_instat (Offset 47) PCI Interrupt Status <byte 13639> {field (By field)} <byte 13639> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_instat (Offset 47) PCI Interrupt Status <byte 13639> utiny value As byte endunion pci_instat (Offset 47) PCI Interrupt Status {} or pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT <byte 13636> ulong value As longword endunion pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT <byte 13640> {pci_rsvd48_4b ((Offset 48) Reserved)} <byte 13640> ulong value {} <byte 13644> {pci_rsvd4c_4f ((Offset 4C) Reserved)} <byte 13644> ulong value {} <byte 13648> union pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC <byte 13648> {field (By field)} <byte 13648> union pci_cap_id (Offset 50) PCI Capabilities Identifier <byte 13648> {field (By field)} <byte 13648> tbits:8 cap_id Capability structure identifier. {} or pci_cap_id (Offset 50) PCI Capabilities Identifier <byte 13648> utiny value As byte endunion pci_cap_id (Offset 50) PCI Capabilities Identifier

<byte 13649> union pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities <byte 13649> {field (By field)} <byte 13649> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities <byte 13649> utiny value As byte endunion pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities <byte 13650> union pci_pmc (Offset 52) PCI Power Management Capabilities <byte 13650> {field (By field)} <byte 13650> bits:3 ver PCI Power Management Specification Version bits:1 clk PME Clock bits:1 aps Auxilliary Power Source bits:1 dsi Device Specific Initialization bits:3 rsvd Reserved bits:1 d1 D1 Support bits:1 d2 D2 Support bits:5 pme PME Support {} or pci_pmc (Offset 52) PCI Power Management Capabilities <byte 13650> ushort value As word endunion pci_pmc (Offset 52) PCI Power Management Capabilities {} or pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC <byte 13648> ulong value As longword endunion pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC <byte 13652> union pci_pmcs (Offset 54) PCI Power Management Control and Status <byte 13652> {field (By field)} <byte 13652> lbits:2 pst Power State lbits:6 reserved1 Reserved lbits:1 pen PME Enable lbits:4 sel Data Select lbits:2 scl Data Scale lbits:1 pme PME Status lbits:16 reserved Reserved {} or pci_pmcs (Offset 54) PCI Power Management Control and Status <byte 13652> ulong value As word endunion pci_pmcs (Offset 54) PCI Power Management Control and Status <byte 13656> union pci_par (Offset 58) PCI Programmable Address Register <byte 13656> {field (By field)} <byte 13656> lbits:20 ra ROM/RAM Address lbits:11 rsvd Reserved lbits:1 inc Increment For DWord aligned addresses {}

or pci_par (Offset 58) PCI Programmable Address Register <byte 13656> ulong value As longword endunion pci_par (Offset 58) PCI Programmable Address Register <byte 13660> union pci_dar (Offset 5C) PCI Programmable Data Register <byte 13660> {field (By field)} <byte 13660> lbits:32 data Read/Write Data {} or pci_dar (Offset 5C) PCI Programmable Data Register <byte 13660> ulong value As longword endunion pci_dar (Offset 5C) PCI Programmable Data Register <byte 13664> {pci_rsvd60_6f ((Offset 60) Reserved)} <byte 13664> ulong value {} <byte 13668> union pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC <byte 13668> {field (By field)} <byte 13668> union pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Id entifier <byte 13668> {field (By field)} <byte 13668> tbits:8 cap_id Capability structure identifier. {} or pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Ident ifier <byte 13668> utiny value As byte endunion pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier <byte 13669> union pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capabili ty <byte 13669> {field (By field)} <byte 13669> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability <byte 13669> utiny value As byte endunion pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capab ility <byte 13670> union pci_mc (Offset 66) PCI Message Control Register <byte 13670> {field (By field)} <byte 13670> bits:1 men Message Signaled Interrupts Enable bits:3 mmc Multiple Message Capable bits:3 mme Multiple Message Enable bits:1 c64 64 Bit Address Capable Read

bits:8 rsvd Reserved {} or pci_mc (Offset 66) PCI Message Control Register <byte 13670> ushort value As word endunion pci_mc (Offset 66) PCI Message Control Register {} or pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC <byte 13668> ulong value As longword endunion pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC <byte 13672> union pci_ma (Offset 68) PCI Message Address <byte 13672> {field (By field)} <byte 13672> lbits:2 rsvd Reserved lbits:30 address Message Address {} or pci_ma (Offset 68) PCI Message Address <byte 13672> ulong value As longword endunion pci_ma (Offset 68) PCI Message Address <byte 13676> union pci_mua (Offset 6C) PCI Message Upper Address <byte 13676> {field (By field)} <byte 13676> lbits:32 address Message Upper Address {} or pci_mua (Offset 6C) PCI Message Upper Address <byte 13676> ulong value As longword endunion pci_mua (Offset 6C) PCI Message Upper Address <byte 13680> union pci_md (Offset 70) PCI Message Data <byte 13680> {field (By field)} <byte 13680> lbits:16 mid Message ID lbits:16 rsvd Reserved {} or pci_md (Offset 70) PCI Message Data <byte 13680> ulong value As longword endunion pci_md (Offset 70) PCI Message Data <byte 13684> union pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD <byte 13684> {field (By field)} <byte 13684> union pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier <byte 13684> {field (By field)} <byte 13684> tbits:8 cap_id Capability structure identifier. {} or pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier <byte 13684> utiny value As byte

endunion pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier <byte 13685> union pci_x_next_cap (Offset 75) PCI Next Capability Register <byte 13685> {field (By field)} <byte 13685> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_x_next_cap (Offset 75) PCI Next Capability Register <byte 13685> utiny value As byte endunion pci_x_next_cap (Offset 75) PCI Next Capability Register <byte 13686> union pci_x_cmd (Offset 76) PCI-X Command Register <byte 13686> {field (By field)} <byte 13686> bits:1 dper Data Parity Error Recovery bits:1 ero Enable Relaxed Ordering bits:2 mbc Maximum Memory Read Byte Count bits:3 mos Maximum Outstanding Split Transactions bits:9 rsvd Reserved {} or pci_x_cmd (Offset 76) PCI-X Command Register <byte 13686> ushort value As word endunion pci_x_cmd (Offset 76) PCI-X Command Register {} or pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD <byte 13684> ulong value As longword endunion pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD <byte 13688> union pci_x_s (Offset 78) PCI-X Status Register <byte 13688> {field (By field)} <byte 13688> lbits:3 fn Function Number lbits:5 dn Device Number lbits:8 bn Bus Number lbits:1 d64 64-bit Device lbits:1 c133 133 MHz Capable lbits:1 scd Split Completion Discarded lbits:1 usc Unexpected Split Completion lbits:1 dc Device Complexity lbits:2 dmbc Designed Maximum Memory Read Byte Count lbits:3 dmos Designed Maximum Outstanding Split Transactions lbits:3 dmcr Designed Maximum Cumulative Read Size lbits:1 rcse Received Split Completion Error Message lbits:2 rsvd Reserved {} or pci_x_s (Offset 78) PCI-X Status Register <byte 13688> ulong value As longword endunion pci_x_s (Offset 78) PCI-X Status Register {} endunion pcicfg[6] Tachyon DX2+ PCI Configuration Registers <byte 13692> union pcicfg[7] Tachyon DX2+ PCI Configuration Registers <byte 13692>

ulong[31] pcicfga Tachyon DX2+ PCI Configuration Registers As Longwords or pcicfg[7] Tachyon DX2+ PCI Configuration Registers <byte 13692> {pcicfg (Tachyon DX2+ PCI Configuration Registers By Field)} <byte 13692> union pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID <byte 13692> {field (By field)} <byte 13692> union pci_vendor_id (Offset 00) PCI Vendor ID <byte 13692> {field (By field)} <byte 13692> bits:16 id ID {} or pci_vendor_id (Offset 00) PCI Vendor ID <byte 13692> ushort value As word endunion pci_vendor_id (Offset 00) PCI Vendor ID <byte 13694> union pci_device_id (Offset 02) PCI Device ID <byte 13694> {field (By field)} <byte 13694> bits:16 id ID {} or pci_device_id (Offset 02) PCI Device ID <byte 13694> ushort value As word endunion pci_device_id (Offset 02) PCI Device ID {} or pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID <byte 13692> ulong value As longword endunion pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID <byte 13696> union pcicfg_reg_04 (Offset 04) PCI CMD/STATUS <byte 13696> {field (By field)} <byte 13696> union pci_cmd (Offset 04) PCI Command <byte 13696> {field (By field)} <byte 13696> bits:1 io_access I/O Access Control bits:1 mem_access Memory Access Control bits:1 pcim_en PCI Master Enable bits:1 scycle_en Special Cycle Enable (read only, always returns 0) bits:1 memwinv Memory Write & Invalidate bits:1 paltsnp_en Palette Snooping Enable (read only, always returns 0) bits:1 perrrsp Parity Error Response bits:1 waitcycctrl Wait Cycle Control bits:1 serrx_en SERR# Enable bits:1 fbbw_en Fast Back-to-Back Write enable (read only, always returns 0) bits:6 rsvd Reserved {} or pci_cmd (Offset 04) PCI Command <byte 13696> ushort value As word endunion pci_cmd (Offset 04) PCI Command

<byte 13698> union pci_status (Offset 06) PCI Status <byte 13698> {field (By field)} <byte 13698> bits:4 rsvd Reserved bits:1 cpl New Capabilities bits:1 cap66mhz 66MHz Capable bits:1 udfsup UDF Supported (read only, always returns 0) bits:1 capfbbw Fast Back-to-Back Capable (read only, always returns 0) bits:1 dperr Data Parity Error Detected bits:2 devsel_time PCI_DEVSEL# response timing (read only, always returns 1) bits:1 sgnltabrt Signaled Target Abort bits:1 rcvdtabrt Received Target Abort bits:1 rcvdmabrt Received Master Abort bits:1 sgnlsyserr Signaled System Error bits:1 perr Detected Parity Error {} or pci_status (Offset 06) PCI Status <byte 13698> ushort value As word endunion pci_status (Offset 06) PCI Status {} or pcicfg_reg_04 (Offset 04) PCI CMD/STATUS <byte 13696> ulong value As longword endunion pcicfg_reg_04 (Offset 04) PCI CMD/STATUS <byte 13700> union pcicfg_reg_08 (Offset 08) PCI REVID/CLASS <byte 13700> {field (By field)} <byte 13700> union pci_revid (Offset 08) PCI Revision <byte 13700> {field (By field)} <byte 13700> tbits:2 minor Minor tbits:3 major Major tbits:3 res Reserved {} or pci_revid (Offset 08) PCI Revision <byte 13700> utiny value As byte endunion pci_revid (Offset 08) PCI Revision <byte 13701> union pci_class (Offset 09) PCI Class <byte 13701> {field (By field)} <byte 13701> tbits:8 baseclcode Base Class Code <byte 13702> tbits:8 subclcode Subclass Code <byte 13703> tbits:8 reglevpi Register Level Programming Interface {} or pci_class (Offset 09) PCI Class <byte 13701> utiny[3] value As byte array endunion pci_class (Offset 09) PCI Class {}

or pcicfg_reg_08 (Offset 08) PCI REVID/CLASS <byte 13700> ulong value As longword endunion pcicfg_reg_08 (Offset 08) PCI REVID/CLASS <byte 13704> union pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST <byte 13704> {field (By field)} <byte 13704> union pci_clsize (Offset 0C) PCI Cache Line Size <byte 13704> {field (By field)} <byte 13704> tbits:8 size PCI cache line size {} or pci_clsize (Offset 0C) PCI Cache Line Size <byte 13704> utiny value As byte endunion pci_clsize (Offset 0C) PCI Cache Line Size <byte 13705> union pci_lattmr (Offset 0D) PCI Latency Timer <byte 13705> {field (By field)} <byte 13705> tbits:8 tmr PCI latency timer {} or pci_lattmr (Offset 0D) PCI Latency Timer <byte 13705> utiny value As byte endunion pci_lattmr (Offset 0D) PCI Latency Timer <byte 13706> union pci_hdrtype (Offset 0E) PCI Header Type <byte 13706> {field (By field)} <byte 13706> tbits:8 type PCI header type (read only) {} or pci_hdrtype (Offset 0E) PCI Header Type <byte 13706> utiny value As byte endunion pci_hdrtype (Offset 0E) PCI Header Type <byte 13707> {pci_rsvd0f ((Offset 0F) Reserved (BIST))} <byte 13707> utiny value {} {} or pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST <byte 13704> ulong value As longword endunion pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST <byte 13708> {pci_rsvd10_13 ((Offset 10) Reserved (RSVBAR))} <byte 13708> ulong value {} <byte 13712> {pci_rsvd14_17 ((Offset 14) Reserved (RSVBAR))} <byte 13712> ulong value

{} <byte 13716> union pci_iobasel (Offset 18) PCI Lower I/O Base Address <byte 13716> {field (By field)} <byte 13716> lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobasel (Offset 18) PCI Lower I/O Base Address <byte 13716> ulong value As longword endunion pci_iobasel (Offset 18) PCI Lower I/O Base Address <byte 13720> union pci_iobaseu (Offset 1C) PCI Upper I/O Base Address <byte 13720> {field (By field)} <byte 13720> lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobaseu (Offset 1C) PCI Upper I/O Base Address <byte 13720> ulong value As longword endunion pci_iobaseu (Offset 1C) PCI Upper I/O Base Address <byte 13724> union pci_membasel (Offset 20) PCI Lower Memory Address Base <byte 13724> {field (By field)} <byte 13724> lbits:1 memspace Memory Space Indicator lbits:2 loctype Location Type lbits:1 prefetch Prefetchable lbits:9 alwayszero Always read as zero lbits:19 baseaddr Lower Base Address {} or pci_membasel (Offset 20) PCI Lower Memory Address Base <byte 13724> ulong value As longword (Bits 31:0) endunion pci_membasel (Offset 20) PCI Lower Memory Address Base <byte 13728> union pci_membaseu (Offset 24) PCI Upper Memory Address Base <byte 13728> {field (By field)} <byte 13728> lbits:32 baseaddr Upper Base Address {} or pci_membaseu (Offset 24) PCI Upper Memory Address Base <byte 13728> ulong value As longword (Bits 63:32) endunion pci_membaseu (Offset 24) PCI Upper Memory Address Base <byte 13732> {pci_rsrvd28_2b ((Offset 28) Reserved)} <byte 13732> ulong value {} <byte 13736> union pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID

<byte 13736> {field (By field)} <byte 13736> union pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID <byte 13736> {field (By field)} <byte 13736> bits:16 id ID {} or pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID <byte 13736> ushort value As word endunion pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID <byte 13738> union pci_subsys_id (Offset 2E) PCI Subsystem ID <byte 13738> {field (By field)} <byte 13738> bits:16 id ID {} or pci_subsys_id (Offset 2E) PCI Subsystem ID <byte 13738> ushort value As word endunion pci_subsys_id (Offset 2E) PCI Subsystem ID {} or pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID <byte 13736> ulong value As longword endunion pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID <byte 13740> union pci_rombase (Offset 30) PCI ROM Base Address <byte 13740> {field (By field)} <byte 13740> lbits:1 decode_en Decode enable lbits:16 rsvd Reserved - always zero lbits:15 address Address Decoding {} or pci_rombase (Offset 30) PCI ROM Base Address <byte 13740> ulong value As longword endunion pci_rombase (Offset 30) PCI ROM Base Address <byte 13744> union pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED <byte 13744> {field (By field)} <byte 13744> union pci_cap_ptr (Offset 34) PCI Capabilities Pointer <byte 13744> {field (By field)} <byte 13744> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_ptr (Offset 34) PCI Capabilities Pointer <byte 13744> utiny value As byte endunion pci_cap_ptr (Offset 34) PCI Capabilities Pointer <byte 13745> {pci_rsvd35 ((Offset 35) Reserved)} <byte 13745>

utiny value {} <byte 13746> {pci_rsvd36_37 ((Offset 36) Reserved)} <byte 13746> ushort value {} {} or pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED <byte 13744> ulong value As longword endunion pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED <byte 13748> {pci_rsvd38_3b ((Offset 38) Reserved)} <byte 13748> ulong value {} <byte 13752> union pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED <byte 13752> {field (By field)} <byte 13752> union pci_int_line (Offset 3C) PCI Interrupt Line <byte 13752> {field (By field)} <byte 13752> tbits:8 line PCI Interrupt Line {} or pci_int_line (Offset 3C) PCI Interrupt Line <byte 13752> utiny value As byte endunion pci_int_line (Offset 3C) PCI Interrupt Line <byte 13753> union pci_int_pin (Offset 3D) PCI Interrupt Pin <byte 13753> {field (By field)} <byte 13753> tbits:8 pin PCI Interrupt Pin (read only) {} or pci_int_pin (Offset 3D) PCI Interrupt Pin <byte 13753> utiny value As byte endunion pci_int_pin (Offset 3D) PCI Interrupt Pin <byte 13754> union pci_min_gnt (Offset 3E) PCI Minimum Grant <byte 13754> {field (By field)} <byte 13754> tbits:8 grant PCI Minimum Grant (read only) {} or pci_min_gnt (Offset 3E) PCI Minimum Grant <byte 13754> utiny value As byte endunion pci_min_gnt (Offset 3E) PCI Minimum Grant <byte 13755> {reserved ((Offset 3F) Reserved)} <byte 13755> utiny value {} {}

or pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED <byte 13752> ulong value As longword endunion pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED <byte 13756> union pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR <byte 13756> {field (By field)} <byte 13756> {pci_rsvd40 ((Offset 40) Reserved)} <byte 13756> utiny value {} <byte 13757> {pci_rsvd41 ((Offset 41) Reserved)} <byte 13757> utiny value {} <byte 13758> union pci_romctr (Offset 42) PCI ROM Control <byte 13758> {field (By field)} <byte 13758> tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or pci_romctr (Offset 42) PCI ROM Control <byte 13758> utiny value As byte endunion pci_romctr (Offset 42) PCI ROM Control <byte 13759> union pci_mctr (Offset 43) PCI Master Control <byte 13759> {field (By field)} <byte 13759> tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or pci_mctr (Offset 43) PCI Master Control <byte 13759> utiny value As byte endunion pci_mctr (Offset 43) PCI Master Control {} or pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR <byte 13756> ulong value As longword endunion pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR <byte 13760> union pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT <byte 13760> {field (By field)} <byte 13760> union pci_softrst (Offset 44) PCI Interface Reset Control <byte 13760> {field (By field)} <byte 13760>

tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or pci_softrst (Offset 44) PCI Interface Reset Control <byte 13760> utiny value As byte endunion pci_softrst (Offset 44) PCI Interface Reset Control <byte 13761> union pci_intpend (Offset 45) PCI Interrupt <byte 13761> {field (By field)} <byte 13761> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_intpend (Offset 45) PCI Interrupt <byte 13761> utiny value As byte endunion pci_intpend (Offset 45) PCI Interrupt <byte 13762> union pci_inten (Offset 46) PCI Interrupt Enable Pending <byte 13762> {field (By field)} <byte 13762> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_inten (Offset 46) PCI Interrupt Enable Pending <byte 13762> utiny value As byte endunion pci_inten (Offset 46) PCI Interrupt Enable Pending <byte 13763> union pci_instat (Offset 47) PCI Interrupt Status <byte 13763> {field (By field)} <byte 13763> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_instat (Offset 47) PCI Interrupt Status <byte 13763> utiny value As byte endunion pci_instat (Offset 47) PCI Interrupt Status {} or pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT <byte 13760> ulong value As longword endunion pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT

<byte 13764> {pci_rsvd48_4b ((Offset 48) Reserved)} <byte 13764> ulong value {} <byte 13768> {pci_rsvd4c_4f ((Offset 4C) Reserved)} <byte 13768> ulong value {} <byte 13772> union pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC <byte 13772> {field (By field)} <byte 13772> union pci_cap_id (Offset 50) PCI Capabilities Identifier <byte 13772> {field (By field)} <byte 13772> tbits:8 cap_id Capability structure identifier. {} or pci_cap_id (Offset 50) PCI Capabilities Identifier <byte 13772> utiny value As byte endunion pci_cap_id (Offset 50) PCI Capabilities Identifier <byte 13773> union pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities <byte 13773> {field (By field)} <byte 13773> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities <byte 13773> utiny value As byte endunion pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities <byte 13774> union pci_pmc (Offset 52) PCI Power Management Capabilities <byte 13774> {field (By field)} <byte 13774> bits:3 ver PCI Power Management Specification Version bits:1 clk PME Clock bits:1 aps Auxilliary Power Source bits:1 dsi Device Specific Initialization bits:3 rsvd Reserved bits:1 d1 D1 Support bits:1 d2 D2 Support bits:5 pme PME Support {} or pci_pmc (Offset 52) PCI Power Management Capabilities <byte 13774> ushort value As word endunion pci_pmc (Offset 52) PCI Power Management Capabilities {} or pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC <byte 13772> ulong value As longword endunion pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC <byte 13776>

union pci_pmcs (Offset 54) PCI Power Management Control and Status <byte 13776> {field (By field)} <byte 13776> lbits:2 pst Power State lbits:6 reserved1 Reserved lbits:1 pen PME Enable lbits:4 sel Data Select lbits:2 scl Data Scale lbits:1 pme PME Status lbits:16 reserved Reserved {} or pci_pmcs (Offset 54) PCI Power Management Control and Status <byte 13776> ulong value As word endunion pci_pmcs (Offset 54) PCI Power Management Control and Status <byte 13780> union pci_par (Offset 58) PCI Programmable Address Register <byte 13780> {field (By field)} <byte 13780> lbits:20 ra ROM/RAM Address lbits:11 rsvd Reserved lbits:1 inc Increment For DWord aligned addresses {} or pci_par (Offset 58) PCI Programmable Address Register <byte 13780> ulong value As longword endunion pci_par (Offset 58) PCI Programmable Address Register <byte 13784> union pci_dar (Offset 5C) PCI Programmable Data Register <byte 13784> {field (By field)} <byte 13784> lbits:32 data Read/Write Data {} or pci_dar (Offset 5C) PCI Programmable Data Register <byte 13784> ulong value As longword endunion pci_dar (Offset 5C) PCI Programmable Data Register <byte 13788> {pci_rsvd60_6f ((Offset 60) Reserved)} <byte 13788> ulong value {} <byte 13792> union pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC <byte 13792> {field (By field)} <byte 13792> union pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Id entifier <byte 13792> {field (By field)} <byte 13792> tbits:8 cap_id Capability structure identifier. {} or pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Ident ifier <byte 13792>

utiny value As byte endunion pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier <byte 13793> union pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capabili ty <byte 13793> {field (By field)} <byte 13793> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability <byte 13793> utiny value As byte endunion pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capab ility <byte 13794> union pci_mc (Offset 66) PCI Message Control Register <byte 13794> {field (By field)} <byte 13794> bits:1 men Message Signaled Interrupts Enable bits:3 mmc Multiple Message Capable bits:3 mme Multiple Message Enable bits:1 c64 64 Bit Address Capable Read bits:8 rsvd Reserved {} or pci_mc (Offset 66) PCI Message Control Register <byte 13794> ushort value As word endunion pci_mc (Offset 66) PCI Message Control Register {} or pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC <byte 13792> ulong value As longword endunion pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC <byte 13796> union pci_ma (Offset 68) PCI Message Address <byte 13796> {field (By field)} <byte 13796> lbits:2 rsvd Reserved lbits:30 address Message Address {} or pci_ma (Offset 68) PCI Message Address <byte 13796> ulong value As longword endunion pci_ma (Offset 68) PCI Message Address <byte 13800> union pci_mua (Offset 6C) PCI Message Upper Address <byte 13800> {field (By field)} <byte 13800> lbits:32 address Message Upper Address {} or pci_mua (Offset 6C) PCI Message Upper Address <byte 13800> ulong value As longword endunion pci_mua (Offset 6C) PCI Message Upper Address <byte 13804>

union pci_md (Offset 70) PCI Message Data <byte 13804> {field (By field)} <byte 13804> lbits:16 mid Message ID lbits:16 rsvd Reserved {} or pci_md (Offset 70) PCI Message Data <byte 13804> ulong value As longword endunion pci_md (Offset 70) PCI Message Data <byte 13808> union pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD <byte 13808> {field (By field)} <byte 13808> union pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier <byte 13808> {field (By field)} <byte 13808> tbits:8 cap_id Capability structure identifier. {} or pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier <byte 13808> utiny value As byte endunion pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier <byte 13809> union pci_x_next_cap (Offset 75) PCI Next Capability Register <byte 13809> {field (By field)} <byte 13809> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_x_next_cap (Offset 75) PCI Next Capability Register <byte 13809> utiny value As byte endunion pci_x_next_cap (Offset 75) PCI Next Capability Register <byte 13810> union pci_x_cmd (Offset 76) PCI-X Command Register <byte 13810> {field (By field)} <byte 13810> bits:1 dper Data Parity Error Recovery bits:1 ero Enable Relaxed Ordering bits:2 mbc Maximum Memory Read Byte Count bits:3 mos Maximum Outstanding Split Transactions bits:9 rsvd Reserved {} or pci_x_cmd (Offset 76) PCI-X Command Register <byte 13810> ushort value As word endunion pci_x_cmd (Offset 76) PCI-X Command Register {} or pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD <byte 13808> ulong value As longword endunion pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD <byte 13812> union pci_x_s (Offset 78) PCI-X Status Register <byte 13812>

{field (By field)} <byte 13812> lbits:3 fn Function Number lbits:5 dn Device Number lbits:8 bn Bus Number lbits:1 d64 64-bit Device lbits:1 c133 133 MHz Capable lbits:1 scd Split Completion Discarded lbits:1 usc Unexpected Split Completion lbits:1 dc Device Complexity lbits:2 dmbc Designed Maximum Memory Read Byte Count lbits:3 dmos Designed Maximum Outstanding Split Transactions lbits:3 dmcr Designed Maximum Cumulative Read Size lbits:1 rcse Received Split Completion Error Message lbits:2 rsvd Reserved {} or pci_x_s (Offset 78) PCI-X Status Register <byte 13812> ulong value As longword endunion pci_x_s (Offset 78) PCI-X Status Register {} endunion pcicfg[7] Tachyon DX2+ PCI Configuration Registers <byte 13816> union pcicfg[8] Tachyon DX2+ PCI Configuration Registers <byte 13816> ulong[31] pcicfga Tachyon DX2+ PCI Configuration Registers As Longwords or pcicfg[8] Tachyon DX2+ PCI Configuration Registers <byte 13816> {pcicfg (Tachyon DX2+ PCI Configuration Registers By Field)} <byte 13816> union pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID <byte 13816> {field (By field)} <byte 13816> union pci_vendor_id (Offset 00) PCI Vendor ID <byte 13816> {field (By field)} <byte 13816> bits:16 id ID {} or pci_vendor_id (Offset 00) PCI Vendor ID <byte 13816> ushort value As word endunion pci_vendor_id (Offset 00) PCI Vendor ID <byte 13818> union pci_device_id (Offset 02) PCI Device ID <byte 13818> {field (By field)} <byte 13818> bits:16 id ID {} or pci_device_id (Offset 02) PCI Device ID <byte 13818> ushort value As word endunion pci_device_id (Offset 02) PCI Device ID {} or pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID <byte 13816> ulong value As longword endunion pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID

<byte 13820> union pcicfg_reg_04 (Offset 04) PCI CMD/STATUS <byte 13820> {field (By field)} <byte 13820> union pci_cmd (Offset 04) PCI Command <byte 13820> {field (By field)} <byte 13820> bits:1 io_access I/O Access Control bits:1 mem_access Memory Access Control bits:1 pcim_en PCI Master Enable bits:1 scycle_en Special Cycle Enable (read only, always returns 0) bits:1 memwinv Memory Write & Invalidate bits:1 paltsnp_en Palette Snooping Enable (read only, always returns 0) bits:1 perrrsp Parity Error Response bits:1 waitcycctrl Wait Cycle Control bits:1 serrx_en SERR# Enable bits:1 fbbw_en Fast Back-to-Back Write enable (read only, always returns 0) bits:6 rsvd Reserved {} or pci_cmd (Offset 04) PCI Command <byte 13820> ushort value As word endunion pci_cmd (Offset 04) PCI Command <byte 13822> union pci_status (Offset 06) PCI Status <byte 13822> {field (By field)} <byte 13822> bits:4 rsvd Reserved bits:1 cpl New Capabilities bits:1 cap66mhz 66MHz Capable bits:1 udfsup UDF Supported (read only, always returns 0) bits:1 capfbbw Fast Back-to-Back Capable (read only, always returns 0) bits:1 dperr Data Parity Error Detected bits:2 devsel_time PCI_DEVSEL# response timing (read only, always returns 1) bits:1 sgnltabrt Signaled Target Abort bits:1 rcvdtabrt Received Target Abort bits:1 rcvdmabrt Received Master Abort bits:1 sgnlsyserr Signaled System Error bits:1 perr Detected Parity Error {} or pci_status (Offset 06) PCI Status <byte 13822> ushort value As word endunion pci_status (Offset 06) PCI Status {} or pcicfg_reg_04 (Offset 04) PCI CMD/STATUS <byte 13820> ulong value As longword endunion pcicfg_reg_04 (Offset 04) PCI CMD/STATUS <byte 13824> union pcicfg_reg_08 (Offset 08) PCI REVID/CLASS <byte 13824> {field (By field)} <byte 13824> union pci_revid (Offset 08) PCI Revision <byte 13824> {field (By field)}

<byte 13824> tbits:2 minor Minor tbits:3 major Major tbits:3 res Reserved {} or pci_revid (Offset 08) PCI Revision <byte 13824> utiny value As byte endunion pci_revid (Offset 08) PCI Revision <byte 13825> union pci_class (Offset 09) PCI Class <byte 13825> {field (By field)} <byte 13825> tbits:8 baseclcode Base Class Code <byte 13826> tbits:8 subclcode Subclass Code <byte 13827> tbits:8 reglevpi Register Level Programming Interface {} or pci_class (Offset 09) PCI Class <byte 13825> utiny[3] value As byte array endunion pci_class (Offset 09) PCI Class {} or pcicfg_reg_08 (Offset 08) PCI REVID/CLASS <byte 13824> ulong value As longword endunion pcicfg_reg_08 (Offset 08) PCI REVID/CLASS <byte 13828> union pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST <byte 13828> {field (By field)} <byte 13828> union pci_clsize (Offset 0C) PCI Cache Line Size <byte 13828> {field (By field)} <byte 13828> tbits:8 size PCI cache line size {} or pci_clsize (Offset 0C) PCI Cache Line Size <byte 13828> utiny value As byte endunion pci_clsize (Offset 0C) PCI Cache Line Size <byte 13829> union pci_lattmr (Offset 0D) PCI Latency Timer <byte 13829> {field (By field)} <byte 13829> tbits:8 tmr PCI latency timer {} or pci_lattmr (Offset 0D) PCI Latency Timer <byte 13829> utiny value As byte endunion pci_lattmr (Offset 0D) PCI Latency Timer <byte 13830> union pci_hdrtype (Offset 0E) PCI Header Type <byte 13830> {field (By field)} <byte 13830>

tbits:8 type PCI header type (read only) {} or pci_hdrtype (Offset 0E) PCI Header Type <byte 13830> utiny value As byte endunion pci_hdrtype (Offset 0E) PCI Header Type <byte 13831> {pci_rsvd0f ((Offset 0F) Reserved (BIST))} <byte 13831> utiny value {} {} or pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST <byte 13828> ulong value As longword endunion pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST <byte 13832> {pci_rsvd10_13 ((Offset 10) Reserved (RSVBAR))} <byte 13832> ulong value {} <byte 13836> {pci_rsvd14_17 ((Offset 14) Reserved (RSVBAR))} <byte 13836> ulong value {} <byte 13840> union pci_iobasel (Offset 18) PCI Lower I/O Base Address <byte 13840> {field (By field)} <byte 13840> lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobasel (Offset 18) PCI Lower I/O Base Address <byte 13840> ulong value As longword endunion pci_iobasel (Offset 18) PCI Lower I/O Base Address <byte 13844> union pci_iobaseu (Offset 1C) PCI Upper I/O Base Address <byte 13844> {field (By field)} <byte 13844> lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobaseu (Offset 1C) PCI Upper I/O Base Address <byte 13844> ulong value As longword endunion pci_iobaseu (Offset 1C) PCI Upper I/O Base Address <byte 13848> union pci_membasel (Offset 20) PCI Lower Memory Address Base <byte 13848> {field (By field)} <byte 13848> lbits:1 memspace Memory Space Indicator lbits:2 loctype Location Type lbits:1 prefetch Prefetchable

lbits:9 alwayszero Always read as zero lbits:19 baseaddr Lower Base Address {} or pci_membasel (Offset 20) PCI Lower Memory Address Base <byte 13848> ulong value As longword (Bits 31:0) endunion pci_membasel (Offset 20) PCI Lower Memory Address Base <byte 13852> union pci_membaseu (Offset 24) PCI Upper Memory Address Base <byte 13852> {field (By field)} <byte 13852> lbits:32 baseaddr Upper Base Address {} or pci_membaseu (Offset 24) PCI Upper Memory Address Base <byte 13852> ulong value As longword (Bits 63:32) endunion pci_membaseu (Offset 24) PCI Upper Memory Address Base <byte 13856> {pci_rsrvd28_2b ((Offset 28) Reserved)} <byte 13856> ulong value {} <byte 13860> union pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID <byte 13860> {field (By field)} <byte 13860> union pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID <byte 13860> {field (By field)} <byte 13860> bits:16 id ID {} or pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID <byte 13860> ushort value As word endunion pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID <byte 13862> union pci_subsys_id (Offset 2E) PCI Subsystem ID <byte 13862> {field (By field)} <byte 13862> bits:16 id ID {} or pci_subsys_id (Offset 2E) PCI Subsystem ID <byte 13862> ushort value As word endunion pci_subsys_id (Offset 2E) PCI Subsystem ID {} or pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID <byte 13860> ulong value As longword endunion pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID <byte 13864> union pci_rombase (Offset 30) PCI ROM Base Address <byte 13864> {field (By field)} <byte 13864> lbits:1 decode_en Decode enable

lbits:16 rsvd Reserved - always zero lbits:15 address Address Decoding {} or pci_rombase (Offset 30) PCI ROM Base Address <byte 13864> ulong value As longword endunion pci_rombase (Offset 30) PCI ROM Base Address <byte 13868> union pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED <byte 13868> {field (By field)} <byte 13868> union pci_cap_ptr (Offset 34) PCI Capabilities Pointer <byte 13868> {field (By field)} <byte 13868> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_ptr (Offset 34) PCI Capabilities Pointer <byte 13868> utiny value As byte endunion pci_cap_ptr (Offset 34) PCI Capabilities Pointer <byte 13869> {pci_rsvd35 ((Offset 35) Reserved)} <byte 13869> utiny value {} <byte 13870> {pci_rsvd36_37 ((Offset 36) Reserved)} <byte 13870> ushort value {} {} or pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED <byte 13868> ulong value As longword endunion pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED <byte 13872> {pci_rsvd38_3b ((Offset 38) Reserved)} <byte 13872> ulong value {} <byte 13876> union pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED <byte 13876> {field (By field)} <byte 13876> union pci_int_line (Offset 3C) PCI Interrupt Line <byte 13876> {field (By field)} <byte 13876> tbits:8 line PCI Interrupt Line {} or pci_int_line (Offset 3C) PCI Interrupt Line <byte 13876> utiny value As byte endunion pci_int_line (Offset 3C) PCI Interrupt Line <byte 13877> union pci_int_pin (Offset 3D) PCI Interrupt Pin <byte 13877>

{field (By field)} <byte 13877> tbits:8 pin PCI Interrupt Pin (read only) {} or pci_int_pin (Offset 3D) PCI Interrupt Pin <byte 13877> utiny value As byte endunion pci_int_pin (Offset 3D) PCI Interrupt Pin <byte 13878> union pci_min_gnt (Offset 3E) PCI Minimum Grant <byte 13878> {field (By field)} <byte 13878> tbits:8 grant PCI Minimum Grant (read only) {} or pci_min_gnt (Offset 3E) PCI Minimum Grant <byte 13878> utiny value As byte endunion pci_min_gnt (Offset 3E) PCI Minimum Grant <byte 13879> {reserved ((Offset 3F) Reserved)} <byte 13879> utiny value {} {} or pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED <byte 13876> ulong value As longword endunion pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED <byte 13880> union pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR <byte 13880> {field (By field)} <byte 13880> {pci_rsvd40 ((Offset 40) Reserved)} <byte 13880> utiny value {} <byte 13881> {pci_rsvd41 ((Offset 41) Reserved)} <byte 13881> utiny value {} <byte 13882> union pci_romctr (Offset 42) PCI ROM Control <byte 13882> {field (By field)} <byte 13882> tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or pci_romctr (Offset 42) PCI ROM Control <byte 13882> utiny value As byte endunion pci_romctr (Offset 42) PCI ROM Control <byte 13883> union pci_mctr (Offset 43) PCI Master Control <byte 13883>

{field (By field)} <byte 13883> tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or pci_mctr (Offset 43) PCI Master Control <byte 13883> utiny value As byte endunion pci_mctr (Offset 43) PCI Master Control {} or pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR <byte 13880> ulong value As longword endunion pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR <byte 13884> union pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT <byte 13884> {field (By field)} <byte 13884> union pci_softrst (Offset 44) PCI Interface Reset Control <byte 13884> {field (By field)} <byte 13884> tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or pci_softrst (Offset 44) PCI Interface Reset Control <byte 13884> utiny value As byte endunion pci_softrst (Offset 44) PCI Interface Reset Control <byte 13885> union pci_intpend (Offset 45) PCI Interrupt <byte 13885> {field (By field)} <byte 13885> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_intpend (Offset 45) PCI Interrupt <byte 13885> utiny value As byte endunion pci_intpend (Offset 45) PCI Interrupt <byte 13886> union pci_inten (Offset 46) PCI Interrupt Enable Pending <byte 13886> {field (By field)} <byte 13886> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {}

or pci_inten (Offset 46) PCI Interrupt Enable Pending <byte 13886> utiny value As byte endunion pci_inten (Offset 46) PCI Interrupt Enable Pending <byte 13887> union pci_instat (Offset 47) PCI Interrupt Status <byte 13887> {field (By field)} <byte 13887> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_instat (Offset 47) PCI Interrupt Status <byte 13887> utiny value As byte endunion pci_instat (Offset 47) PCI Interrupt Status {} or pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT <byte 13884> ulong value As longword endunion pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT <byte 13888> {pci_rsvd48_4b ((Offset 48) Reserved)} <byte 13888> ulong value {} <byte 13892> {pci_rsvd4c_4f ((Offset 4C) Reserved)} <byte 13892> ulong value {} <byte 13896> union pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC <byte 13896> {field (By field)} <byte 13896> union pci_cap_id (Offset 50) PCI Capabilities Identifier <byte 13896> {field (By field)} <byte 13896> tbits:8 cap_id Capability structure identifier. {} or pci_cap_id (Offset 50) PCI Capabilities Identifier <byte 13896> utiny value As byte endunion pci_cap_id (Offset 50) PCI Capabilities Identifier <byte 13897> union pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities <byte 13897> {field (By field)} <byte 13897> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities <byte 13897> utiny value As byte

endunion pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities <byte 13898> union pci_pmc (Offset 52) PCI Power Management Capabilities <byte 13898> {field (By field)} <byte 13898> bits:3 ver PCI Power Management Specification Version bits:1 clk PME Clock bits:1 aps Auxilliary Power Source bits:1 dsi Device Specific Initialization bits:3 rsvd Reserved bits:1 d1 D1 Support bits:1 d2 D2 Support bits:5 pme PME Support {} or pci_pmc (Offset 52) PCI Power Management Capabilities <byte 13898> ushort value As word endunion pci_pmc (Offset 52) PCI Power Management Capabilities {} or pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC <byte 13896> ulong value As longword endunion pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC <byte 13900> union pci_pmcs (Offset 54) PCI Power Management Control and Status <byte 13900> {field (By field)} <byte 13900> lbits:2 pst Power State lbits:6 reserved1 Reserved lbits:1 pen PME Enable lbits:4 sel Data Select lbits:2 scl Data Scale lbits:1 pme PME Status lbits:16 reserved Reserved {} or pci_pmcs (Offset 54) PCI Power Management Control and Status <byte 13900> ulong value As word endunion pci_pmcs (Offset 54) PCI Power Management Control and Status <byte 13904> union pci_par (Offset 58) PCI Programmable Address Register <byte 13904> {field (By field)} <byte 13904> lbits:20 ra ROM/RAM Address lbits:11 rsvd Reserved lbits:1 inc Increment For DWord aligned addresses {} or pci_par (Offset 58) PCI Programmable Address Register <byte 13904> ulong value As longword endunion pci_par (Offset 58) PCI Programmable Address Register <byte 13908> union pci_dar (Offset 5C) PCI Programmable Data Register <byte 13908> {field (By field)} <byte 13908> lbits:32 data Read/Write Data

{} or pci_dar (Offset 5C) PCI Programmable Data Register <byte 13908> ulong value As longword endunion pci_dar (Offset 5C) PCI Programmable Data Register <byte 13912> {pci_rsvd60_6f ((Offset 60) Reserved)} <byte 13912> ulong value {} <byte 13916> union pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC <byte 13916> {field (By field)} <byte 13916> union pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Id entifier <byte 13916> {field (By field)} <byte 13916> tbits:8 cap_id Capability structure identifier. {} or pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Ident ifier <byte 13916> utiny value As byte endunion pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier <byte 13917> union pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capabili ty <byte 13917> {field (By field)} <byte 13917> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability <byte 13917> utiny value As byte endunion pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capab ility <byte 13918> union pci_mc (Offset 66) PCI Message Control Register <byte 13918> {field (By field)} <byte 13918> bits:1 men Message Signaled Interrupts Enable bits:3 mmc Multiple Message Capable bits:3 mme Multiple Message Enable bits:1 c64 64 Bit Address Capable Read bits:8 rsvd Reserved {} or pci_mc (Offset 66) PCI Message Control Register <byte 13918> ushort value As word endunion pci_mc (Offset 66) PCI Message Control Register {} or pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC <byte 13916> ulong value As longword

endunion pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC <byte 13920> union pci_ma (Offset 68) PCI Message Address <byte 13920> {field (By field)} <byte 13920> lbits:2 rsvd Reserved lbits:30 address Message Address {} or pci_ma (Offset 68) PCI Message Address <byte 13920> ulong value As longword endunion pci_ma (Offset 68) PCI Message Address <byte 13924> union pci_mua (Offset 6C) PCI Message Upper Address <byte 13924> {field (By field)} <byte 13924> lbits:32 address Message Upper Address {} or pci_mua (Offset 6C) PCI Message Upper Address <byte 13924> ulong value As longword endunion pci_mua (Offset 6C) PCI Message Upper Address <byte 13928> union pci_md (Offset 70) PCI Message Data <byte 13928> {field (By field)} <byte 13928> lbits:16 mid Message ID lbits:16 rsvd Reserved {} or pci_md (Offset 70) PCI Message Data <byte 13928> ulong value As longword endunion pci_md (Offset 70) PCI Message Data <byte 13932> union pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD <byte 13932> {field (By field)} <byte 13932> union pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier <byte 13932> {field (By field)} <byte 13932> tbits:8 cap_id Capability structure identifier. {} or pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier <byte 13932> utiny value As byte endunion pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier <byte 13933> union pci_x_next_cap (Offset 75) PCI Next Capability Register <byte 13933> {field (By field)} <byte 13933> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_x_next_cap (Offset 75) PCI Next Capability Register <byte 13933>

utiny value As byte endunion pci_x_next_cap (Offset 75) PCI Next Capability Register <byte 13934> union pci_x_cmd (Offset 76) PCI-X Command Register <byte 13934> {field (By field)} <byte 13934> bits:1 dper Data Parity Error Recovery bits:1 ero Enable Relaxed Ordering bits:2 mbc Maximum Memory Read Byte Count bits:3 mos Maximum Outstanding Split Transactions bits:9 rsvd Reserved {} or pci_x_cmd (Offset 76) PCI-X Command Register <byte 13934> ushort value As word endunion pci_x_cmd (Offset 76) PCI-X Command Register {} or pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD <byte 13932> ulong value As longword endunion pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD <byte 13936> union pci_x_s (Offset 78) PCI-X Status Register <byte 13936> {field (By field)} <byte 13936> lbits:3 fn Function Number lbits:5 dn Device Number lbits:8 bn Bus Number lbits:1 d64 64-bit Device lbits:1 c133 133 MHz Capable lbits:1 scd Split Completion Discarded lbits:1 usc Unexpected Split Completion lbits:1 dc Device Complexity lbits:2 dmbc Designed Maximum Memory Read Byte Count lbits:3 dmos Designed Maximum Outstanding Split Transactions lbits:3 dmcr Designed Maximum Cumulative Read Size lbits:1 rcse Received Split Completion Error Message lbits:2 rsvd Reserved {} or pci_x_s (Offset 78) PCI-X Status Register <byte 13936> ulong value As longword endunion pci_x_s (Offset 78) PCI-X Status Register {} endunion pcicfg[8] Tachyon DX2+ PCI Configuration Registers <byte 13940> union pcicfg[9] Tachyon DX2+ PCI Configuration Registers <byte 13940> ulong[31] pcicfga Tachyon DX2+ PCI Configuration Registers As Longwords or pcicfg[9] Tachyon DX2+ PCI Configuration Registers <byte 13940> {pcicfg (Tachyon DX2+ PCI Configuration Registers By Field)} <byte 13940> union pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID <byte 13940> {field (By field)} <byte 13940> union pci_vendor_id (Offset 00) PCI Vendor ID

<byte 13940> {field (By field)} <byte 13940> bits:16 id ID {} or pci_vendor_id (Offset 00) PCI Vendor ID <byte 13940> ushort value As word endunion pci_vendor_id (Offset 00) PCI Vendor ID <byte 13942> union pci_device_id (Offset 02) PCI Device ID <byte 13942> {field (By field)} <byte 13942> bits:16 id ID {} or pci_device_id (Offset 02) PCI Device ID <byte 13942> ushort value As word endunion pci_device_id (Offset 02) PCI Device ID {} or pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID <byte 13940> ulong value As longword endunion pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID <byte 13944> union pcicfg_reg_04 (Offset 04) PCI CMD/STATUS <byte 13944> {field (By field)} <byte 13944> union pci_cmd (Offset 04) PCI Command <byte 13944> {field (By field)} <byte 13944> bits:1 io_access I/O Access Control bits:1 mem_access Memory Access Control bits:1 pcim_en PCI Master Enable bits:1 scycle_en Special Cycle Enable (read only, always returns 0) bits:1 memwinv Memory Write & Invalidate bits:1 paltsnp_en Palette Snooping Enable (read only, always returns 0) bits:1 perrrsp Parity Error Response bits:1 waitcycctrl Wait Cycle Control bits:1 serrx_en SERR# Enable bits:1 fbbw_en Fast Back-to-Back Write enable (read only, always returns 0) bits:6 rsvd Reserved {} or pci_cmd (Offset 04) PCI Command <byte 13944> ushort value As word endunion pci_cmd (Offset 04) PCI Command <byte 13946> union pci_status (Offset 06) PCI Status <byte 13946> {field (By field)} <byte 13946> bits:4 rsvd Reserved bits:1 cpl New Capabilities bits:1 cap66mhz 66MHz Capable bits:1 udfsup UDF Supported (read only, always returns 0) bits:1 capfbbw Fast Back-to-Back Capable (read only, always returns 0)

bits:1 dperr Data Parity Error Detected bits:2 devsel_time PCI_DEVSEL# response timing (read only, always returns 1) bits:1 sgnltabrt Signaled Target Abort bits:1 rcvdtabrt Received Target Abort bits:1 rcvdmabrt Received Master Abort bits:1 sgnlsyserr Signaled System Error bits:1 perr Detected Parity Error {} or pci_status (Offset 06) PCI Status <byte 13946> ushort value As word endunion pci_status (Offset 06) PCI Status {} or pcicfg_reg_04 (Offset 04) PCI CMD/STATUS <byte 13944> ulong value As longword endunion pcicfg_reg_04 (Offset 04) PCI CMD/STATUS <byte 13948> union pcicfg_reg_08 (Offset 08) PCI REVID/CLASS <byte 13948> {field (By field)} <byte 13948> union pci_revid (Offset 08) PCI Revision <byte 13948> {field (By field)} <byte 13948> tbits:2 minor Minor tbits:3 major Major tbits:3 res Reserved {} or pci_revid (Offset 08) PCI Revision <byte 13948> utiny value As byte endunion pci_revid (Offset 08) PCI Revision <byte 13949> union pci_class (Offset 09) PCI Class <byte 13949> {field (By field)} <byte 13949> tbits:8 baseclcode Base Class Code <byte 13950> tbits:8 subclcode Subclass Code <byte 13951> tbits:8 reglevpi Register Level Programming Interface {} or pci_class (Offset 09) PCI Class <byte 13949> utiny[3] value As byte array endunion pci_class (Offset 09) PCI Class {} or pcicfg_reg_08 (Offset 08) PCI REVID/CLASS <byte 13948> ulong value As longword endunion pcicfg_reg_08 (Offset 08) PCI REVID/CLASS <byte 13952> union pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST <byte 13952> {field (By field)} <byte 13952> union pci_clsize (Offset 0C) PCI Cache Line Size

<byte 13952> {field (By field)} <byte 13952> tbits:8 size PCI cache line size {} or pci_clsize (Offset 0C) PCI Cache Line Size <byte 13952> utiny value As byte endunion pci_clsize (Offset 0C) PCI Cache Line Size <byte 13953> union pci_lattmr (Offset 0D) PCI Latency Timer <byte 13953> {field (By field)} <byte 13953> tbits:8 tmr PCI latency timer {} or pci_lattmr (Offset 0D) PCI Latency Timer <byte 13953> utiny value As byte endunion pci_lattmr (Offset 0D) PCI Latency Timer <byte 13954> union pci_hdrtype (Offset 0E) PCI Header Type <byte 13954> {field (By field)} <byte 13954> tbits:8 type PCI header type (read only) {} or pci_hdrtype (Offset 0E) PCI Header Type <byte 13954> utiny value As byte endunion pci_hdrtype (Offset 0E) PCI Header Type <byte 13955> {pci_rsvd0f ((Offset 0F) Reserved (BIST))} <byte 13955> utiny value {} {} or pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST <byte 13952> ulong value As longword endunion pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST <byte 13956> {pci_rsvd10_13 ((Offset 10) Reserved (RSVBAR))} <byte 13956> ulong value {} <byte 13960> {pci_rsvd14_17 ((Offset 14) Reserved (RSVBAR))} <byte 13960> ulong value {} <byte 13964> union pci_iobasel (Offset 18) PCI Lower I/O Base Address <byte 13964> {field (By field)} <byte 13964> lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {}

or pci_iobasel (Offset 18) PCI Lower I/O Base Address <byte 13964> ulong value As longword endunion pci_iobasel (Offset 18) PCI Lower I/O Base Address <byte 13968> union pci_iobaseu (Offset 1C) PCI Upper I/O Base Address <byte 13968> {field (By field)} <byte 13968> lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobaseu (Offset 1C) PCI Upper I/O Base Address <byte 13968> ulong value As longword endunion pci_iobaseu (Offset 1C) PCI Upper I/O Base Address <byte 13972> union pci_membasel (Offset 20) PCI Lower Memory Address Base <byte 13972> {field (By field)} <byte 13972> lbits:1 memspace Memory Space Indicator lbits:2 loctype Location Type lbits:1 prefetch Prefetchable lbits:9 alwayszero Always read as zero lbits:19 baseaddr Lower Base Address {} or pci_membasel (Offset 20) PCI Lower Memory Address Base <byte 13972> ulong value As longword (Bits 31:0) endunion pci_membasel (Offset 20) PCI Lower Memory Address Base <byte 13976> union pci_membaseu (Offset 24) PCI Upper Memory Address Base <byte 13976> {field (By field)} <byte 13976> lbits:32 baseaddr Upper Base Address {} or pci_membaseu (Offset 24) PCI Upper Memory Address Base <byte 13976> ulong value As longword (Bits 63:32) endunion pci_membaseu (Offset 24) PCI Upper Memory Address Base <byte 13980> {pci_rsrvd28_2b ((Offset 28) Reserved)} <byte 13980> ulong value {} <byte 13984> union pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID <byte 13984> {field (By field)} <byte 13984> union pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID <byte 13984> {field (By field)} <byte 13984> bits:16 id ID {} or pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID

<byte 13984> ushort value As word endunion pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID <byte 13986> union pci_subsys_id (Offset 2E) PCI Subsystem ID <byte 13986> {field (By field)} <byte 13986> bits:16 id ID {} or pci_subsys_id (Offset 2E) PCI Subsystem ID <byte 13986> ushort value As word endunion pci_subsys_id (Offset 2E) PCI Subsystem ID {} or pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID <byte 13984> ulong value As longword endunion pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID <byte 13988> union pci_rombase (Offset 30) PCI ROM Base Address <byte 13988> {field (By field)} <byte 13988> lbits:1 decode_en Decode enable lbits:16 rsvd Reserved - always zero lbits:15 address Address Decoding {} or pci_rombase (Offset 30) PCI ROM Base Address <byte 13988> ulong value As longword endunion pci_rombase (Offset 30) PCI ROM Base Address <byte 13992> union pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED <byte 13992> {field (By field)} <byte 13992> union pci_cap_ptr (Offset 34) PCI Capabilities Pointer <byte 13992> {field (By field)} <byte 13992> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_ptr (Offset 34) PCI Capabilities Pointer <byte 13992> utiny value As byte endunion pci_cap_ptr (Offset 34) PCI Capabilities Pointer <byte 13993> {pci_rsvd35 ((Offset 35) Reserved)} <byte 13993> utiny value {} <byte 13994> {pci_rsvd36_37 ((Offset 36) Reserved)} <byte 13994> ushort value {} {} or pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED <byte 13992>

ulong value As longword endunion pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED <byte 13996> {pci_rsvd38_3b ((Offset 38) Reserved)} <byte 13996> ulong value {} <byte 14000> union pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED <byte 14000> {field (By field)} <byte 14000> union pci_int_line (Offset 3C) PCI Interrupt Line <byte 14000> {field (By field)} <byte 14000> tbits:8 line PCI Interrupt Line {} or pci_int_line (Offset 3C) PCI Interrupt Line <byte 14000> utiny value As byte endunion pci_int_line (Offset 3C) PCI Interrupt Line <byte 14001> union pci_int_pin (Offset 3D) PCI Interrupt Pin <byte 14001> {field (By field)} <byte 14001> tbits:8 pin PCI Interrupt Pin (read only) {} or pci_int_pin (Offset 3D) PCI Interrupt Pin <byte 14001> utiny value As byte endunion pci_int_pin (Offset 3D) PCI Interrupt Pin <byte 14002> union pci_min_gnt (Offset 3E) PCI Minimum Grant <byte 14002> {field (By field)} <byte 14002> tbits:8 grant PCI Minimum Grant (read only) {} or pci_min_gnt (Offset 3E) PCI Minimum Grant <byte 14002> utiny value As byte endunion pci_min_gnt (Offset 3E) PCI Minimum Grant <byte 14003> {reserved ((Offset 3F) Reserved)} <byte 14003> utiny value {} {} or pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED <byte 14000> ulong value As longword endunion pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED <byte 14004> union pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR <byte 14004> {field (By field)} <byte 14004> {pci_rsvd40 ((Offset 40) Reserved)}

<byte 14004> utiny value {} <byte 14005> {pci_rsvd41 ((Offset 41) Reserved)} <byte 14005> utiny value {} <byte 14006> union pci_romctr (Offset 42) PCI ROM Control <byte 14006> {field (By field)} <byte 14006> tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or pci_romctr (Offset 42) PCI ROM Control <byte 14006> utiny value As byte endunion pci_romctr (Offset 42) PCI ROM Control <byte 14007> union pci_mctr (Offset 43) PCI Master Control <byte 14007> {field (By field)} <byte 14007> tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or pci_mctr (Offset 43) PCI Master Control <byte 14007> utiny value As byte endunion pci_mctr (Offset 43) PCI Master Control {} or pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR <byte 14004> ulong value As longword endunion pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR <byte 14008> union pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT <byte 14008> {field (By field)} <byte 14008> union pci_softrst (Offset 44) PCI Interface Reset Control <byte 14008> {field (By field)} <byte 14008> tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or pci_softrst (Offset 44) PCI Interface Reset Control <byte 14008> utiny value As byte endunion pci_softrst (Offset 44) PCI Interface Reset Control <byte 14009> union pci_intpend (Offset 45) PCI Interrupt <byte 14009>

{field (By field)} <byte 14009> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_intpend (Offset 45) PCI Interrupt <byte 14009> utiny value As byte endunion pci_intpend (Offset 45) PCI Interrupt <byte 14010> union pci_inten (Offset 46) PCI Interrupt Enable Pending <byte 14010> {field (By field)} <byte 14010> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_inten (Offset 46) PCI Interrupt Enable Pending <byte 14010> utiny value As byte endunion pci_inten (Offset 46) PCI Interrupt Enable Pending <byte 14011> union pci_instat (Offset 47) PCI Interrupt Status <byte 14011> {field (By field)} <byte 14011> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_instat (Offset 47) PCI Interrupt Status <byte 14011> utiny value As byte endunion pci_instat (Offset 47) PCI Interrupt Status {} or pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT <byte 14008> ulong value As longword endunion pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT <byte 14012> {pci_rsvd48_4b ((Offset 48) Reserved)} <byte 14012> ulong value {} <byte 14016> {pci_rsvd4c_4f ((Offset 4C) Reserved)} <byte 14016> ulong value {}

<byte 14020> union pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC <byte 14020> {field (By field)} <byte 14020> union pci_cap_id (Offset 50) PCI Capabilities Identifier <byte 14020> {field (By field)} <byte 14020> tbits:8 cap_id Capability structure identifier. {} or pci_cap_id (Offset 50) PCI Capabilities Identifier <byte 14020> utiny value As byte endunion pci_cap_id (Offset 50) PCI Capabilities Identifier <byte 14021> union pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities <byte 14021> {field (By field)} <byte 14021> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities <byte 14021> utiny value As byte endunion pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities <byte 14022> union pci_pmc (Offset 52) PCI Power Management Capabilities <byte 14022> {field (By field)} <byte 14022> bits:3 ver PCI Power Management Specification Version bits:1 clk PME Clock bits:1 aps Auxilliary Power Source bits:1 dsi Device Specific Initialization bits:3 rsvd Reserved bits:1 d1 D1 Support bits:1 d2 D2 Support bits:5 pme PME Support {} or pci_pmc (Offset 52) PCI Power Management Capabilities <byte 14022> ushort value As word endunion pci_pmc (Offset 52) PCI Power Management Capabilities {} or pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC <byte 14020> ulong value As longword endunion pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC <byte 14024> union pci_pmcs (Offset 54) PCI Power Management Control and Status <byte 14024> {field (By field)} <byte 14024> lbits:2 pst Power State lbits:6 reserved1 Reserved lbits:1 pen PME Enable lbits:4 sel Data Select lbits:2 scl Data Scale lbits:1 pme PME Status

lbits:16 reserved Reserved {} or pci_pmcs (Offset 54) PCI Power Management Control and Status <byte 14024> ulong value As word endunion pci_pmcs (Offset 54) PCI Power Management Control and Status <byte 14028> union pci_par (Offset 58) PCI Programmable Address Register <byte 14028> {field (By field)} <byte 14028> lbits:20 ra ROM/RAM Address lbits:11 rsvd Reserved lbits:1 inc Increment For DWord aligned addresses {} or pci_par (Offset 58) PCI Programmable Address Register <byte 14028> ulong value As longword endunion pci_par (Offset 58) PCI Programmable Address Register <byte 14032> union pci_dar (Offset 5C) PCI Programmable Data Register <byte 14032> {field (By field)} <byte 14032> lbits:32 data Read/Write Data {} or pci_dar (Offset 5C) PCI Programmable Data Register <byte 14032> ulong value As longword endunion pci_dar (Offset 5C) PCI Programmable Data Register <byte 14036> {pci_rsvd60_6f ((Offset 60) Reserved)} <byte 14036> ulong value {} <byte 14040> union pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC <byte 14040> {field (By field)} <byte 14040> union pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Id entifier <byte 14040> {field (By field)} <byte 14040> tbits:8 cap_id Capability structure identifier. {} or pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Ident ifier <byte 14040> utiny value As byte endunion pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier <byte 14041> union pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capabili ty <byte 14041> {field (By field)} <byte 14041> tbits:8 offset Offset to the first item in the capabilities linked list

{} or pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability <byte 14041> utiny value As byte endunion pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capab ility <byte 14042> union pci_mc (Offset 66) PCI Message Control Register <byte 14042> {field (By field)} <byte 14042> bits:1 men Message Signaled Interrupts Enable bits:3 mmc Multiple Message Capable bits:3 mme Multiple Message Enable bits:1 c64 64 Bit Address Capable Read bits:8 rsvd Reserved {} or pci_mc (Offset 66) PCI Message Control Register <byte 14042> ushort value As word endunion pci_mc (Offset 66) PCI Message Control Register {} or pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC <byte 14040> ulong value As longword endunion pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC <byte 14044> union pci_ma (Offset 68) PCI Message Address <byte 14044> {field (By field)} <byte 14044> lbits:2 rsvd Reserved lbits:30 address Message Address {} or pci_ma (Offset 68) PCI Message Address <byte 14044> ulong value As longword endunion pci_ma (Offset 68) PCI Message Address <byte 14048> union pci_mua (Offset 6C) PCI Message Upper Address <byte 14048> {field (By field)} <byte 14048> lbits:32 address Message Upper Address {} or pci_mua (Offset 6C) PCI Message Upper Address <byte 14048> ulong value As longword endunion pci_mua (Offset 6C) PCI Message Upper Address <byte 14052> union pci_md (Offset 70) PCI Message Data <byte 14052> {field (By field)} <byte 14052> lbits:16 mid Message ID lbits:16 rsvd Reserved {} or pci_md (Offset 70) PCI Message Data <byte 14052> ulong value As longword

endunion pci_md (Offset 70) PCI Message Data <byte 14056> union pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD <byte 14056> {field (By field)} <byte 14056> union pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier <byte 14056> {field (By field)} <byte 14056> tbits:8 cap_id Capability structure identifier. {} or pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier <byte 14056> utiny value As byte endunion pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier <byte 14057> union pci_x_next_cap (Offset 75) PCI Next Capability Register <byte 14057> {field (By field)} <byte 14057> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_x_next_cap (Offset 75) PCI Next Capability Register <byte 14057> utiny value As byte endunion pci_x_next_cap (Offset 75) PCI Next Capability Register <byte 14058> union pci_x_cmd (Offset 76) PCI-X Command Register <byte 14058> {field (By field)} <byte 14058> bits:1 dper Data Parity Error Recovery bits:1 ero Enable Relaxed Ordering bits:2 mbc Maximum Memory Read Byte Count bits:3 mos Maximum Outstanding Split Transactions bits:9 rsvd Reserved {} or pci_x_cmd (Offset 76) PCI-X Command Register <byte 14058> ushort value As word endunion pci_x_cmd (Offset 76) PCI-X Command Register {} or pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD <byte 14056> ulong value As longword endunion pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD <byte 14060> union pci_x_s (Offset 78) PCI-X Status Register <byte 14060> {field (By field)} <byte 14060> lbits:3 fn Function Number lbits:5 dn Device Number lbits:8 bn Bus Number lbits:1 d64 64-bit Device lbits:1 c133 133 MHz Capable lbits:1 scd Split Completion Discarded lbits:1 usc Unexpected Split Completion lbits:1 dc Device Complexity

lbits:2 dmbc Designed Maximum Memory Read Byte Count lbits:3 dmos Designed Maximum Outstanding Split Transactions lbits:3 dmcr Designed Maximum Cumulative Read Size lbits:1 rcse Received Split Completion Error Message lbits:2 rsvd Reserved {} or pci_x_s (Offset 78) PCI-X Status Register <byte 14060> ulong value As longword endunion pci_x_s (Offset 78) PCI-X Status Register {} endunion pcicfg[9] Tachyon DX2+ PCI Configuration Registers <byte 14064> union pcicfg[10] Tachyon DX2+ PCI Configuration Registers <byte 14064> ulong[31] pcicfga Tachyon DX2+ PCI Configuration Registers As Longwords or pcicfg[10] Tachyon DX2+ PCI Configuration Registers <byte 14064> {pcicfg (Tachyon DX2+ PCI Configuration Registers By Field)} <byte 14064> union pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID <byte 14064> {field (By field)} <byte 14064> union pci_vendor_id (Offset 00) PCI Vendor ID <byte 14064> {field (By field)} <byte 14064> bits:16 id ID {} or pci_vendor_id (Offset 00) PCI Vendor ID <byte 14064> ushort value As word endunion pci_vendor_id (Offset 00) PCI Vendor ID <byte 14066> union pci_device_id (Offset 02) PCI Device ID <byte 14066> {field (By field)} <byte 14066> bits:16 id ID {} or pci_device_id (Offset 02) PCI Device ID <byte 14066> ushort value As word endunion pci_device_id (Offset 02) PCI Device ID {} or pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID <byte 14064> ulong value As longword endunion pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID <byte 14068> union pcicfg_reg_04 (Offset 04) PCI CMD/STATUS <byte 14068> {field (By field)} <byte 14068> union pci_cmd (Offset 04) PCI Command <byte 14068> {field (By field)} <byte 14068> bits:1 io_access I/O Access Control

bits:1 mem_access Memory Access Control bits:1 pcim_en PCI Master Enable bits:1 scycle_en Special Cycle Enable (read only, always returns 0) bits:1 memwinv Memory Write & Invalidate bits:1 paltsnp_en Palette Snooping Enable (read only, always returns 0) bits:1 perrrsp Parity Error Response bits:1 waitcycctrl Wait Cycle Control bits:1 serrx_en SERR# Enable bits:1 fbbw_en Fast Back-to-Back Write enable (read only, always returns 0) bits:6 rsvd Reserved {} or pci_cmd (Offset 04) PCI Command <byte 14068> ushort value As word endunion pci_cmd (Offset 04) PCI Command <byte 14070> union pci_status (Offset 06) PCI Status <byte 14070> {field (By field)} <byte 14070> bits:4 rsvd Reserved bits:1 cpl New Capabilities bits:1 cap66mhz 66MHz Capable bits:1 udfsup UDF Supported (read only, always returns 0) bits:1 capfbbw Fast Back-to-Back Capable (read only, always returns 0) bits:1 dperr Data Parity Error Detected bits:2 devsel_time PCI_DEVSEL# response timing (read only, always returns 1) bits:1 sgnltabrt Signaled Target Abort bits:1 rcvdtabrt Received Target Abort bits:1 rcvdmabrt Received Master Abort bits:1 sgnlsyserr Signaled System Error bits:1 perr Detected Parity Error {} or pci_status (Offset 06) PCI Status <byte 14070> ushort value As word endunion pci_status (Offset 06) PCI Status {} or pcicfg_reg_04 (Offset 04) PCI CMD/STATUS <byte 14068> ulong value As longword endunion pcicfg_reg_04 (Offset 04) PCI CMD/STATUS <byte 14072> union pcicfg_reg_08 (Offset 08) PCI REVID/CLASS <byte 14072> {field (By field)} <byte 14072> union pci_revid (Offset 08) PCI Revision <byte 14072> {field (By field)} <byte 14072> tbits:2 minor Minor tbits:3 major Major tbits:3 res Reserved {} or pci_revid (Offset 08) PCI Revision <byte 14072> utiny value As byte endunion pci_revid (Offset 08) PCI Revision <byte 14073>

union pci_class (Offset 09) PCI Class <byte 14073> {field (By field)} <byte 14073> tbits:8 baseclcode Base Class Code <byte 14074> tbits:8 subclcode Subclass Code <byte 14075> tbits:8 reglevpi Register Level Programming Interface {} or pci_class (Offset 09) PCI Class <byte 14073> utiny[3] value As byte array endunion pci_class (Offset 09) PCI Class {} or pcicfg_reg_08 (Offset 08) PCI REVID/CLASS <byte 14072> ulong value As longword endunion pcicfg_reg_08 (Offset 08) PCI REVID/CLASS <byte 14076> union pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST <byte 14076> {field (By field)} <byte 14076> union pci_clsize (Offset 0C) PCI Cache Line Size <byte 14076> {field (By field)} <byte 14076> tbits:8 size PCI cache line size {} or pci_clsize (Offset 0C) PCI Cache Line Size <byte 14076> utiny value As byte endunion pci_clsize (Offset 0C) PCI Cache Line Size <byte 14077> union pci_lattmr (Offset 0D) PCI Latency Timer <byte 14077> {field (By field)} <byte 14077> tbits:8 tmr PCI latency timer {} or pci_lattmr (Offset 0D) PCI Latency Timer <byte 14077> utiny value As byte endunion pci_lattmr (Offset 0D) PCI Latency Timer <byte 14078> union pci_hdrtype (Offset 0E) PCI Header Type <byte 14078> {field (By field)} <byte 14078> tbits:8 type PCI header type (read only) {} or pci_hdrtype (Offset 0E) PCI Header Type <byte 14078> utiny value As byte endunion pci_hdrtype (Offset 0E) PCI Header Type <byte 14079> {pci_rsvd0f ((Offset 0F) Reserved (BIST))} <byte 14079> utiny value

{} {} or pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST <byte 14076> ulong value As longword endunion pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST <byte 14080> {pci_rsvd10_13 ((Offset 10) Reserved (RSVBAR))} <byte 14080> ulong value {} <byte 14084> {pci_rsvd14_17 ((Offset 14) Reserved (RSVBAR))} <byte 14084> ulong value {} <byte 14088> union pci_iobasel (Offset 18) PCI Lower I/O Base Address <byte 14088> {field (By field)} <byte 14088> lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobasel (Offset 18) PCI Lower I/O Base Address <byte 14088> ulong value As longword endunion pci_iobasel (Offset 18) PCI Lower I/O Base Address <byte 14092> union pci_iobaseu (Offset 1C) PCI Upper I/O Base Address <byte 14092> {field (By field)} <byte 14092> lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobaseu (Offset 1C) PCI Upper I/O Base Address <byte 14092> ulong value As longword endunion pci_iobaseu (Offset 1C) PCI Upper I/O Base Address <byte 14096> union pci_membasel (Offset 20) PCI Lower Memory Address Base <byte 14096> {field (By field)} <byte 14096> lbits:1 memspace Memory Space Indicator lbits:2 loctype Location Type lbits:1 prefetch Prefetchable lbits:9 alwayszero Always read as zero lbits:19 baseaddr Lower Base Address {} or pci_membasel (Offset 20) PCI Lower Memory Address Base <byte 14096> ulong value As longword (Bits 31:0) endunion pci_membasel (Offset 20) PCI Lower Memory Address Base <byte 14100> union pci_membaseu (Offset 24) PCI Upper Memory Address Base <byte 14100>

{field (By field)} <byte 14100> lbits:32 baseaddr Upper Base Address {} or pci_membaseu (Offset 24) PCI Upper Memory Address Base <byte 14100> ulong value As longword (Bits 63:32) endunion pci_membaseu (Offset 24) PCI Upper Memory Address Base <byte 14104> {pci_rsrvd28_2b ((Offset 28) Reserved)} <byte 14104> ulong value {} <byte 14108> union pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID <byte 14108> {field (By field)} <byte 14108> union pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID <byte 14108> {field (By field)} <byte 14108> bits:16 id ID {} or pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID <byte 14108> ushort value As word endunion pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID <byte 14110> union pci_subsys_id (Offset 2E) PCI Subsystem ID <byte 14110> {field (By field)} <byte 14110> bits:16 id ID {} or pci_subsys_id (Offset 2E) PCI Subsystem ID <byte 14110> ushort value As word endunion pci_subsys_id (Offset 2E) PCI Subsystem ID {} or pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID <byte 14108> ulong value As longword endunion pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID <byte 14112> union pci_rombase (Offset 30) PCI ROM Base Address <byte 14112> {field (By field)} <byte 14112> lbits:1 decode_en Decode enable lbits:16 rsvd Reserved - always zero lbits:15 address Address Decoding {} or pci_rombase (Offset 30) PCI ROM Base Address <byte 14112> ulong value As longword endunion pci_rombase (Offset 30) PCI ROM Base Address <byte 14116> union pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED <byte 14116>

{field (By field)} <byte 14116> union pci_cap_ptr (Offset 34) PCI Capabilities Pointer <byte 14116> {field (By field)} <byte 14116> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_ptr (Offset 34) PCI Capabilities Pointer <byte 14116> utiny value As byte endunion pci_cap_ptr (Offset 34) PCI Capabilities Pointer <byte 14117> {pci_rsvd35 ((Offset 35) Reserved)} <byte 14117> utiny value {} <byte 14118> {pci_rsvd36_37 ((Offset 36) Reserved)} <byte 14118> ushort value {} {} or pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED <byte 14116> ulong value As longword endunion pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED <byte 14120> {pci_rsvd38_3b ((Offset 38) Reserved)} <byte 14120> ulong value {} <byte 14124> union pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED <byte 14124> {field (By field)} <byte 14124> union pci_int_line (Offset 3C) PCI Interrupt Line <byte 14124> {field (By field)} <byte 14124> tbits:8 line PCI Interrupt Line {} or pci_int_line (Offset 3C) PCI Interrupt Line <byte 14124> utiny value As byte endunion pci_int_line (Offset 3C) PCI Interrupt Line <byte 14125> union pci_int_pin (Offset 3D) PCI Interrupt Pin <byte 14125> {field (By field)} <byte 14125> tbits:8 pin PCI Interrupt Pin (read only) {} or pci_int_pin (Offset 3D) PCI Interrupt Pin <byte 14125> utiny value As byte endunion pci_int_pin (Offset 3D) PCI Interrupt Pin <byte 14126> union pci_min_gnt (Offset 3E) PCI Minimum Grant

<byte 14126> {field (By field)} <byte 14126> tbits:8 grant PCI Minimum Grant (read only) {} or pci_min_gnt (Offset 3E) PCI Minimum Grant <byte 14126> utiny value As byte endunion pci_min_gnt (Offset 3E) PCI Minimum Grant <byte 14127> {reserved ((Offset 3F) Reserved)} <byte 14127> utiny value {} {} or pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED <byte 14124> ulong value As longword endunion pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED <byte 14128> union pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR <byte 14128> {field (By field)} <byte 14128> {pci_rsvd40 ((Offset 40) Reserved)} <byte 14128> utiny value {} <byte 14129> {pci_rsvd41 ((Offset 41) Reserved)} <byte 14129> utiny value {} <byte 14130> union pci_romctr (Offset 42) PCI ROM Control <byte 14130> {field (By field)} <byte 14130> tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or pci_romctr (Offset 42) PCI ROM Control <byte 14130> utiny value As byte endunion pci_romctr (Offset 42) PCI ROM Control <byte 14131> union pci_mctr (Offset 43) PCI Master Control <byte 14131> {field (By field)} <byte 14131> tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or pci_mctr (Offset 43) PCI Master Control <byte 14131> utiny value As byte

endunion pci_mctr (Offset 43) PCI Master Control {} or pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR <byte 14128> ulong value As longword endunion pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR <byte 14132> union pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT <byte 14132> {field (By field)} <byte 14132> union pci_softrst (Offset 44) PCI Interface Reset Control <byte 14132> {field (By field)} <byte 14132> tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or pci_softrst (Offset 44) PCI Interface Reset Control <byte 14132> utiny value As byte endunion pci_softrst (Offset 44) PCI Interface Reset Control <byte 14133> union pci_intpend (Offset 45) PCI Interrupt <byte 14133> {field (By field)} <byte 14133> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_intpend (Offset 45) PCI Interrupt <byte 14133> utiny value As byte endunion pci_intpend (Offset 45) PCI Interrupt <byte 14134> union pci_inten (Offset 46) PCI Interrupt Enable Pending <byte 14134> {field (By field)} <byte 14134> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_inten (Offset 46) PCI Interrupt Enable Pending <byte 14134> utiny value As byte endunion pci_inten (Offset 46) PCI Interrupt Enable Pending <byte 14135> union pci_instat (Offset 47) PCI Interrupt Status <byte 14135> {field (By field)} <byte 14135> tbits:1 per PCI Error Detected Interrupt

tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_instat (Offset 47) PCI Interrupt Status <byte 14135> utiny value As byte endunion pci_instat (Offset 47) PCI Interrupt Status {} or pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT <byte 14132> ulong value As longword endunion pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT <byte 14136> {pci_rsvd48_4b ((Offset 48) Reserved)} <byte 14136> ulong value {} <byte 14140> {pci_rsvd4c_4f ((Offset 4C) Reserved)} <byte 14140> ulong value {} <byte 14144> union pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC <byte 14144> {field (By field)} <byte 14144> union pci_cap_id (Offset 50) PCI Capabilities Identifier <byte 14144> {field (By field)} <byte 14144> tbits:8 cap_id Capability structure identifier. {} or pci_cap_id (Offset 50) PCI Capabilities Identifier <byte 14144> utiny value As byte endunion pci_cap_id (Offset 50) PCI Capabilities Identifier <byte 14145> union pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities <byte 14145> {field (By field)} <byte 14145> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities <byte 14145> utiny value As byte endunion pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities <byte 14146> union pci_pmc (Offset 52) PCI Power Management Capabilities <byte 14146> {field (By field)} <byte 14146> bits:3 ver PCI Power Management Specification Version bits:1 clk PME Clock bits:1 aps Auxilliary Power Source bits:1 dsi Device Specific Initialization

bits:3 rsvd Reserved bits:1 d1 D1 Support bits:1 d2 D2 Support bits:5 pme PME Support {} or pci_pmc (Offset 52) PCI Power Management Capabilities <byte 14146> ushort value As word endunion pci_pmc (Offset 52) PCI Power Management Capabilities {} or pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC <byte 14144> ulong value As longword endunion pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC <byte 14148> union pci_pmcs (Offset 54) PCI Power Management Control and Status <byte 14148> {field (By field)} <byte 14148> lbits:2 pst Power State lbits:6 reserved1 Reserved lbits:1 pen PME Enable lbits:4 sel Data Select lbits:2 scl Data Scale lbits:1 pme PME Status lbits:16 reserved Reserved {} or pci_pmcs (Offset 54) PCI Power Management Control and Status <byte 14148> ulong value As word endunion pci_pmcs (Offset 54) PCI Power Management Control and Status <byte 14152> union pci_par (Offset 58) PCI Programmable Address Register <byte 14152> {field (By field)} <byte 14152> lbits:20 ra ROM/RAM Address lbits:11 rsvd Reserved lbits:1 inc Increment For DWord aligned addresses {} or pci_par (Offset 58) PCI Programmable Address Register <byte 14152> ulong value As longword endunion pci_par (Offset 58) PCI Programmable Address Register <byte 14156> union pci_dar (Offset 5C) PCI Programmable Data Register <byte 14156> {field (By field)} <byte 14156> lbits:32 data Read/Write Data {} or pci_dar (Offset 5C) PCI Programmable Data Register <byte 14156> ulong value As longword endunion pci_dar (Offset 5C) PCI Programmable Data Register <byte 14160> {pci_rsvd60_6f ((Offset 60) Reserved)} <byte 14160> ulong value {}

<byte 14164> union pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC <byte 14164> {field (By field)} <byte 14164> union pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Id entifier <byte 14164> {field (By field)} <byte 14164> tbits:8 cap_id Capability structure identifier. {} or pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Ident ifier <byte 14164> utiny value As byte endunion pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier <byte 14165> union pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capabili ty <byte 14165> {field (By field)} <byte 14165> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability <byte 14165> utiny value As byte endunion pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capab ility <byte 14166> union pci_mc (Offset 66) PCI Message Control Register <byte 14166> {field (By field)} <byte 14166> bits:1 men Message Signaled Interrupts Enable bits:3 mmc Multiple Message Capable bits:3 mme Multiple Message Enable bits:1 c64 64 Bit Address Capable Read bits:8 rsvd Reserved {} or pci_mc (Offset 66) PCI Message Control Register <byte 14166> ushort value As word endunion pci_mc (Offset 66) PCI Message Control Register {} or pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC <byte 14164> ulong value As longword endunion pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC <byte 14168> union pci_ma (Offset 68) PCI Message Address <byte 14168> {field (By field)} <byte 14168> lbits:2 rsvd Reserved lbits:30 address Message Address {} or pci_ma (Offset 68) PCI Message Address

<byte 14168> ulong value As longword endunion pci_ma (Offset 68) PCI Message Address <byte 14172> union pci_mua (Offset 6C) PCI Message Upper Address <byte 14172> {field (By field)} <byte 14172> lbits:32 address Message Upper Address {} or pci_mua (Offset 6C) PCI Message Upper Address <byte 14172> ulong value As longword endunion pci_mua (Offset 6C) PCI Message Upper Address <byte 14176> union pci_md (Offset 70) PCI Message Data <byte 14176> {field (By field)} <byte 14176> lbits:16 mid Message ID lbits:16 rsvd Reserved {} or pci_md (Offset 70) PCI Message Data <byte 14176> ulong value As longword endunion pci_md (Offset 70) PCI Message Data <byte 14180> union pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD <byte 14180> {field (By field)} <byte 14180> union pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier <byte 14180> {field (By field)} <byte 14180> tbits:8 cap_id Capability structure identifier. {} or pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier <byte 14180> utiny value As byte endunion pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier <byte 14181> union pci_x_next_cap (Offset 75) PCI Next Capability Register <byte 14181> {field (By field)} <byte 14181> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_x_next_cap (Offset 75) PCI Next Capability Register <byte 14181> utiny value As byte endunion pci_x_next_cap (Offset 75) PCI Next Capability Register <byte 14182> union pci_x_cmd (Offset 76) PCI-X Command Register <byte 14182> {field (By field)} <byte 14182> bits:1 dper Data Parity Error Recovery bits:1 ero Enable Relaxed Ordering bits:2 mbc Maximum Memory Read Byte Count

bits:3 mos Maximum Outstanding Split Transactions bits:9 rsvd Reserved {} or pci_x_cmd (Offset 76) PCI-X Command Register <byte 14182> ushort value As word endunion pci_x_cmd (Offset 76) PCI-X Command Register {} or pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD <byte 14180> ulong value As longword endunion pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD <byte 14184> union pci_x_s (Offset 78) PCI-X Status Register <byte 14184> {field (By field)} <byte 14184> lbits:3 fn Function Number lbits:5 dn Device Number lbits:8 bn Bus Number lbits:1 d64 64-bit Device lbits:1 c133 133 MHz Capable lbits:1 scd Split Completion Discarded lbits:1 usc Unexpected Split Completion lbits:1 dc Device Complexity lbits:2 dmbc Designed Maximum Memory Read Byte Count lbits:3 dmos Designed Maximum Outstanding Split Transactions lbits:3 dmcr Designed Maximum Cumulative Read Size lbits:1 rcse Received Split Completion Error Message lbits:2 rsvd Reserved {} or pci_x_s (Offset 78) PCI-X Status Register <byte 14184> ulong value As longword endunion pci_x_s (Offset 78) PCI-X Status Register {} endunion pcicfg[10] Tachyon DX2+ PCI Configuration Registers <byte 14188> union pcicfg[11] Tachyon DX2+ PCI Configuration Registers <byte 14188> ulong[31] pcicfga Tachyon DX2+ PCI Configuration Registers As Longwords or pcicfg[11] Tachyon DX2+ PCI Configuration Registers <byte 14188> {pcicfg (Tachyon DX2+ PCI Configuration Registers By Field)} <byte 14188> union pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID <byte 14188> {field (By field)} <byte 14188> union pci_vendor_id (Offset 00) PCI Vendor ID <byte 14188> {field (By field)} <byte 14188> bits:16 id ID {} or pci_vendor_id (Offset 00) PCI Vendor ID <byte 14188> ushort value As word endunion pci_vendor_id (Offset 00) PCI Vendor ID <byte 14190>

union pci_device_id (Offset 02) PCI Device ID <byte 14190> {field (By field)} <byte 14190> bits:16 id ID {} or pci_device_id (Offset 02) PCI Device ID <byte 14190> ushort value As word endunion pci_device_id (Offset 02) PCI Device ID {} or pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID <byte 14188> ulong value As longword endunion pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID <byte 14192> union pcicfg_reg_04 (Offset 04) PCI CMD/STATUS <byte 14192> {field (By field)} <byte 14192> union pci_cmd (Offset 04) PCI Command <byte 14192> {field (By field)} <byte 14192> bits:1 io_access I/O Access Control bits:1 mem_access Memory Access Control bits:1 pcim_en PCI Master Enable bits:1 scycle_en Special Cycle Enable (read only, always returns 0) bits:1 memwinv Memory Write & Invalidate bits:1 paltsnp_en Palette Snooping Enable (read only, always returns 0) bits:1 perrrsp Parity Error Response bits:1 waitcycctrl Wait Cycle Control bits:1 serrx_en SERR# Enable bits:1 fbbw_en Fast Back-to-Back Write enable (read only, always returns 0) bits:6 rsvd Reserved {} or pci_cmd (Offset 04) PCI Command <byte 14192> ushort value As word endunion pci_cmd (Offset 04) PCI Command <byte 14194> union pci_status (Offset 06) PCI Status <byte 14194> {field (By field)} <byte 14194> bits:4 rsvd Reserved bits:1 cpl New Capabilities bits:1 cap66mhz 66MHz Capable bits:1 udfsup UDF Supported (read only, always returns 0) bits:1 capfbbw Fast Back-to-Back Capable (read only, always returns 0) bits:1 dperr Data Parity Error Detected bits:2 devsel_time PCI_DEVSEL# response timing (read only, always returns 1) bits:1 sgnltabrt Signaled Target Abort bits:1 rcvdtabrt Received Target Abort bits:1 rcvdmabrt Received Master Abort bits:1 sgnlsyserr Signaled System Error bits:1 perr Detected Parity Error {} or pci_status (Offset 06) PCI Status <byte 14194>

ushort value As word endunion pci_status (Offset 06) PCI Status {} or pcicfg_reg_04 (Offset 04) PCI CMD/STATUS <byte 14192> ulong value As longword endunion pcicfg_reg_04 (Offset 04) PCI CMD/STATUS <byte 14196> union pcicfg_reg_08 (Offset 08) PCI REVID/CLASS <byte 14196> {field (By field)} <byte 14196> union pci_revid (Offset 08) PCI Revision <byte 14196> {field (By field)} <byte 14196> tbits:2 minor Minor tbits:3 major Major tbits:3 res Reserved {} or pci_revid (Offset 08) PCI Revision <byte 14196> utiny value As byte endunion pci_revid (Offset 08) PCI Revision <byte 14197> union pci_class (Offset 09) PCI Class <byte 14197> {field (By field)} <byte 14197> tbits:8 baseclcode Base Class Code <byte 14198> tbits:8 subclcode Subclass Code <byte 14199> tbits:8 reglevpi Register Level Programming Interface {} or pci_class (Offset 09) PCI Class <byte 14197> utiny[3] value As byte array endunion pci_class (Offset 09) PCI Class {} or pcicfg_reg_08 (Offset 08) PCI REVID/CLASS <byte 14196> ulong value As longword endunion pcicfg_reg_08 (Offset 08) PCI REVID/CLASS <byte 14200> union pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST <byte 14200> {field (By field)} <byte 14200> union pci_clsize (Offset 0C) PCI Cache Line Size <byte 14200> {field (By field)} <byte 14200> tbits:8 size PCI cache line size {} or pci_clsize (Offset 0C) PCI Cache Line Size <byte 14200> utiny value As byte endunion pci_clsize (Offset 0C) PCI Cache Line Size <byte 14201>

union pci_lattmr (Offset 0D) PCI Latency Timer <byte 14201> {field (By field)} <byte 14201> tbits:8 tmr PCI latency timer {} or pci_lattmr (Offset 0D) PCI Latency Timer <byte 14201> utiny value As byte endunion pci_lattmr (Offset 0D) PCI Latency Timer <byte 14202> union pci_hdrtype (Offset 0E) PCI Header Type <byte 14202> {field (By field)} <byte 14202> tbits:8 type PCI header type (read only) {} or pci_hdrtype (Offset 0E) PCI Header Type <byte 14202> utiny value As byte endunion pci_hdrtype (Offset 0E) PCI Header Type <byte 14203> {pci_rsvd0f ((Offset 0F) Reserved (BIST))} <byte 14203> utiny value {} {} or pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST <byte 14200> ulong value As longword endunion pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST <byte 14204> {pci_rsvd10_13 ((Offset 10) Reserved (RSVBAR))} <byte 14204> ulong value {} <byte 14208> {pci_rsvd14_17 ((Offset 14) Reserved (RSVBAR))} <byte 14208> ulong value {} <byte 14212> union pci_iobasel (Offset 18) PCI Lower I/O Base Address <byte 14212> {field (By field)} <byte 14212> lbits:1 memspace I/O Space Indicator lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobasel (Offset 18) PCI Lower I/O Base Address <byte 14212> ulong value As longword endunion pci_iobasel (Offset 18) PCI Lower I/O Base Address <byte 14216> union pci_iobaseu (Offset 1C) PCI Upper I/O Base Address <byte 14216> {field (By field)} <byte 14216> lbits:1 memspace I/O Space Indicator

lbits:7 alwayszero Always read as zero lbits:24 baseaddr Base Address {} or pci_iobaseu (Offset 1C) PCI Upper I/O Base Address <byte 14216> ulong value As longword endunion pci_iobaseu (Offset 1C) PCI Upper I/O Base Address <byte 14220> union pci_membasel (Offset 20) PCI Lower Memory Address Base <byte 14220> {field (By field)} <byte 14220> lbits:1 memspace Memory Space Indicator lbits:2 loctype Location Type lbits:1 prefetch Prefetchable lbits:9 alwayszero Always read as zero lbits:19 baseaddr Lower Base Address {} or pci_membasel (Offset 20) PCI Lower Memory Address Base <byte 14220> ulong value As longword (Bits 31:0) endunion pci_membasel (Offset 20) PCI Lower Memory Address Base <byte 14224> union pci_membaseu (Offset 24) PCI Upper Memory Address Base <byte 14224> {field (By field)} <byte 14224> lbits:32 baseaddr Upper Base Address {} or pci_membaseu (Offset 24) PCI Upper Memory Address Base <byte 14224> ulong value As longword (Bits 63:32) endunion pci_membaseu (Offset 24) PCI Upper Memory Address Base <byte 14228> {pci_rsrvd28_2b ((Offset 28) Reserved)} <byte 14228> ulong value {} <byte 14232> union pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID <byte 14232> {field (By field)} <byte 14232> union pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID <byte 14232> {field (By field)} <byte 14232> bits:16 id ID {} or pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID <byte 14232> ushort value As word endunion pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID <byte 14234> union pci_subsys_id (Offset 2E) PCI Subsystem ID <byte 14234> {field (By field)} <byte 14234> bits:16 id ID {}

or pci_subsys_id (Offset 2E) PCI Subsystem ID <byte 14234> ushort value As word endunion pci_subsys_id (Offset 2E) PCI Subsystem ID {} or pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID <byte 14232> ulong value As longword endunion pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID <byte 14236> union pci_rombase (Offset 30) PCI ROM Base Address <byte 14236> {field (By field)} <byte 14236> lbits:1 decode_en Decode enable lbits:16 rsvd Reserved - always zero lbits:15 address Address Decoding {} or pci_rombase (Offset 30) PCI ROM Base Address <byte 14236> ulong value As longword endunion pci_rombase (Offset 30) PCI ROM Base Address <byte 14240> union pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED <byte 14240> {field (By field)} <byte 14240> union pci_cap_ptr (Offset 34) PCI Capabilities Pointer <byte 14240> {field (By field)} <byte 14240> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_ptr (Offset 34) PCI Capabilities Pointer <byte 14240> utiny value As byte endunion pci_cap_ptr (Offset 34) PCI Capabilities Pointer <byte 14241> {pci_rsvd35 ((Offset 35) Reserved)} <byte 14241> utiny value {} <byte 14242> {pci_rsvd36_37 ((Offset 36) Reserved)} <byte 14242> ushort value {} {} or pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED <byte 14240> ulong value As longword endunion pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED <byte 14244> {pci_rsvd38_3b ((Offset 38) Reserved)} <byte 14244> ulong value {} <byte 14248> union pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED <byte 14248>

{field (By field)} <byte 14248> union pci_int_line (Offset 3C) PCI Interrupt Line <byte 14248> {field (By field)} <byte 14248> tbits:8 line PCI Interrupt Line {} or pci_int_line (Offset 3C) PCI Interrupt Line <byte 14248> utiny value As byte endunion pci_int_line (Offset 3C) PCI Interrupt Line <byte 14249> union pci_int_pin (Offset 3D) PCI Interrupt Pin <byte 14249> {field (By field)} <byte 14249> tbits:8 pin PCI Interrupt Pin (read only) {} or pci_int_pin (Offset 3D) PCI Interrupt Pin <byte 14249> utiny value As byte endunion pci_int_pin (Offset 3D) PCI Interrupt Pin <byte 14250> union pci_min_gnt (Offset 3E) PCI Minimum Grant <byte 14250> {field (By field)} <byte 14250> tbits:8 grant PCI Minimum Grant (read only) {} or pci_min_gnt (Offset 3E) PCI Minimum Grant <byte 14250> utiny value As byte endunion pci_min_gnt (Offset 3E) PCI Minimum Grant <byte 14251> {reserved ((Offset 3F) Reserved)} <byte 14251> utiny value {} {} or pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED <byte 14248> ulong value As longword endunion pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED <byte 14252> union pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR <byte 14252> {field (By field)} <byte 14252> {pci_rsvd40 ((Offset 40) Reserved)} <byte 14252> utiny value {} <byte 14253> {pci_rsvd41 ((Offset 41) Reserved)} <byte 14253> utiny value {} <byte 14254> union pci_romctr (Offset 42) PCI ROM Control

<byte 14254> {field (By field)} <byte 14254> tbits:1 vpp_en ROM VPP Enable tbits:1 fla Flash Installed (read only) tbits:1 rom ROM Installed (read only) tbits:5 reserved Reserved {} or pci_romctr (Offset 42) PCI ROM Control <byte 14254> utiny value As byte endunion pci_romctr (Offset 42) PCI ROM Control <byte 14255> union pci_mctr (Offset 43) PCI Master Control <byte 14255> {field (By field)} <byte 14255> tbits:2 reserved1 Reserved tbits:1 p64 PCI Present and Active tbits:4 reserved Reserved tbits:1 dlt Disable Latency Timer {} or pci_mctr (Offset 43) PCI Master Control <byte 14255> utiny value As byte endunion pci_mctr (Offset 43) PCI Master Control {} or pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR <byte 14252> ulong value As longword endunion pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR <byte 14256> union pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT <byte 14256> {field (By field)} <byte 14256> union pci_softrst (Offset 44) PCI Interface Reset Control <byte 14256> {field (By field)} <byte 14256> tbits:1 rst PCI Interface Soft Reset tbits:7 reserved Reserved {} or pci_softrst (Offset 44) PCI Interface Reset Control <byte 14256> utiny value As byte endunion pci_softrst (Offset 44) PCI Interface Reset Control <byte 14257> union pci_intpend (Offset 45) PCI Interrupt <byte 14257> {field (By field)} <byte 14257> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_intpend (Offset 45) PCI Interrupt

<byte 14257> utiny value As byte endunion pci_intpend (Offset 45) PCI Interrupt <byte 14258> union pci_inten (Offset 46) PCI Interrupt Enable Pending <byte 14258> {field (By field)} <byte 14258> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_inten (Offset 46) PCI Interrupt Enable Pending <byte 14258> utiny value As byte endunion pci_inten (Offset 46) PCI Interrupt Enable Pending <byte 14259> union pci_instat (Offset 47) PCI Interrupt Status <byte 14259> {field (By field)} <byte 14259> tbits:1 per PCI Error Detected Interrupt tbits:1 der Device Error Detected Interrupt tbits:1 fint Function Interrupt tbits:2 reserved1 Reserved tbits:1 ube Unsupported Byte Enables tbits:2 reserved Reserved {} or pci_instat (Offset 47) PCI Interrupt Status <byte 14259> utiny value As byte endunion pci_instat (Offset 47) PCI Interrupt Status {} or pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT <byte 14256> ulong value As longword endunion pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT <byte 14260> {pci_rsvd48_4b ((Offset 48) Reserved)} <byte 14260> ulong value {} <byte 14264> {pci_rsvd4c_4f ((Offset 4C) Reserved)} <byte 14264> ulong value {} <byte 14268> union pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC <byte 14268> {field (By field)} <byte 14268> union pci_cap_id (Offset 50) PCI Capabilities Identifier <byte 14268> {field (By field)} <byte 14268> tbits:8 cap_id Capability structure identifier.

{} or pci_cap_id (Offset 50) PCI Capabilities Identifier <byte 14268> utiny value As byte endunion pci_cap_id (Offset 50) PCI Capabilities Identifier <byte 14269> union pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities <byte 14269> {field (By field)} <byte 14269> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities <byte 14269> utiny value As byte endunion pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities <byte 14270> union pci_pmc (Offset 52) PCI Power Management Capabilities <byte 14270> {field (By field)} <byte 14270> bits:3 ver PCI Power Management Specification Version bits:1 clk PME Clock bits:1 aps Auxilliary Power Source bits:1 dsi Device Specific Initialization bits:3 rsvd Reserved bits:1 d1 D1 Support bits:1 d2 D2 Support bits:5 pme PME Support {} or pci_pmc (Offset 52) PCI Power Management Capabilities <byte 14270> ushort value As word endunion pci_pmc (Offset 52) PCI Power Management Capabilities {} or pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC <byte 14268> ulong value As longword endunion pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC <byte 14272> union pci_pmcs (Offset 54) PCI Power Management Control and Status <byte 14272> {field (By field)} <byte 14272> lbits:2 pst Power State lbits:6 reserved1 Reserved lbits:1 pen PME Enable lbits:4 sel Data Select lbits:2 scl Data Scale lbits:1 pme PME Status lbits:16 reserved Reserved {} or pci_pmcs (Offset 54) PCI Power Management Control and Status <byte 14272> ulong value As word endunion pci_pmcs (Offset 54) PCI Power Management Control and Status <byte 14276> union pci_par (Offset 58) PCI Programmable Address Register <byte 14276> {field (By field)}

<byte 14276> lbits:20 ra ROM/RAM Address lbits:11 rsvd Reserved lbits:1 inc Increment For DWord aligned addresses {} or pci_par (Offset 58) PCI Programmable Address Register <byte 14276> ulong value As longword endunion pci_par (Offset 58) PCI Programmable Address Register <byte 14280> union pci_dar (Offset 5C) PCI Programmable Data Register <byte 14280> {field (By field)} <byte 14280> lbits:32 data Read/Write Data {} or pci_dar (Offset 5C) PCI Programmable Data Register <byte 14280> ulong value As longword endunion pci_dar (Offset 5C) PCI Programmable Data Register <byte 14284> {pci_rsvd60_6f ((Offset 60) Reserved)} <byte 14284> ulong value {} <byte 14288> union pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC <byte 14288> {field (By field)} <byte 14288> union pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Id entifier <byte 14288> {field (By field)} <byte 14288> tbits:8 cap_id Capability structure identifier. {} or pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Ident ifier <byte 14288> utiny value As byte endunion pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier <byte 14289> union pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capabili ty <byte 14289> {field (By field)} <byte 14289> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability <byte 14289> utiny value As byte endunion pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capab ility <byte 14290> union pci_mc (Offset 66) PCI Message Control Register <byte 14290> {field (By field)}

<byte 14290> bits:1 men Message Signaled Interrupts Enable bits:3 mmc Multiple Message Capable bits:3 mme Multiple Message Enable bits:1 c64 64 Bit Address Capable Read bits:8 rsvd Reserved {} or pci_mc (Offset 66) PCI Message Control Register <byte 14290> ushort value As word endunion pci_mc (Offset 66) PCI Message Control Register {} or pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC <byte 14288> ulong value As longword endunion pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC <byte 14292> union pci_ma (Offset 68) PCI Message Address <byte 14292> {field (By field)} <byte 14292> lbits:2 rsvd Reserved lbits:30 address Message Address {} or pci_ma (Offset 68) PCI Message Address <byte 14292> ulong value As longword endunion pci_ma (Offset 68) PCI Message Address <byte 14296> union pci_mua (Offset 6C) PCI Message Upper Address <byte 14296> {field (By field)} <byte 14296> lbits:32 address Message Upper Address {} or pci_mua (Offset 6C) PCI Message Upper Address <byte 14296> ulong value As longword endunion pci_mua (Offset 6C) PCI Message Upper Address <byte 14300> union pci_md (Offset 70) PCI Message Data <byte 14300> {field (By field)} <byte 14300> lbits:16 mid Message ID lbits:16 rsvd Reserved {} or pci_md (Offset 70) PCI Message Data <byte 14300> ulong value As longword endunion pci_md (Offset 70) PCI Message Data <byte 14304> union pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD <byte 14304> {field (By field)} <byte 14304> union pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier <byte 14304> {field (By field)} <byte 14304>

tbits:8 cap_id Capability structure identifier. {} or pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier <byte 14304> utiny value As byte endunion pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier <byte 14305> union pci_x_next_cap (Offset 75) PCI Next Capability Register <byte 14305> {field (By field)} <byte 14305> tbits:8 offset Offset to the first item in the capabilities linked list {} or pci_x_next_cap (Offset 75) PCI Next Capability Register <byte 14305> utiny value As byte endunion pci_x_next_cap (Offset 75) PCI Next Capability Register <byte 14306> union pci_x_cmd (Offset 76) PCI-X Command Register <byte 14306> {field (By field)} <byte 14306> bits:1 dper Data Parity Error Recovery bits:1 ero Enable Relaxed Ordering bits:2 mbc Maximum Memory Read Byte Count bits:3 mos Maximum Outstanding Split Transactions bits:9 rsvd Reserved {} or pci_x_cmd (Offset 76) PCI-X Command Register <byte 14306> ushort value As word endunion pci_x_cmd (Offset 76) PCI-X Command Register {} or pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD <byte 14304> ulong value As longword endunion pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD <byte 14308> union pci_x_s (Offset 78) PCI-X Status Register <byte 14308> {field (By field)} <byte 14308> lbits:3 fn Function Number lbits:5 dn Device Number lbits:8 bn Bus Number lbits:1 d64 64-bit Device lbits:1 c133 133 MHz Capable lbits:1 scd Split Completion Discarded lbits:1 usc Unexpected Split Completion lbits:1 dc Device Complexity lbits:2 dmbc Designed Maximum Memory Read Byte Count lbits:3 dmos Designed Maximum Outstanding Split Transactions lbits:3 dmcr Designed Maximum Cumulative Read Size lbits:1 rcse Received Split Completion Error Message lbits:2 rsvd Reserved {} or pci_x_s (Offset 78) PCI-X Status Register <byte 14308> ulong value As longword endunion pci_x_s (Offset 78) PCI-X Status Register

{} endunion pcicfg[11] Tachyon DX2+ PCI Configuration Registers <byte 14312> union ncfghi[0] Tachyon DX2+ PCI Non-Configuration Registers High <byte 14312> ulong[12] ncfghia Tachyon DX2+ PCI Non-Configuration Registers -- High As Longwo rds or ncfghi[0] Tachyon DX2+ PCI Non-Configuration Registers High <byte 14312> {ncfghi (Tachyon DX2+ PCI Non-Configuration Registers -- High By Field)} <byte 14312> union ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register <byte 14312> {field (By field)} <byte 14312> lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register <byte 14312> ulong value As longword endunion ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register <byte 14316> union ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register <byte 14316> {field (By field)} <byte 14316> lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register <byte 14316> ulong value As longword endunion ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register <byte 14320> union ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Regi ster <byte 14320> {field (By field)} <byte 14320>

lbits:12 qf1 Quiesce Function 1 lbits:12 qf0 Quiesce Function 0 lbits:8 reserved Reserved {} or ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Registe r <byte 14320> ulong value As longword endunion ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration R egister <byte 14324> union ncfghi_gcr (Offset 0x40C) Global Control Register <byte 14324> {field (By field)} <byte 14324> lbits:1 ror Reissue on Retry lbits:8 reserved3 Reserved lbits:1 rod Reissue on Disconnect lbits:1 gsr Global Soft Reset lbits:2 reserved2 Reserved lbits:1 omw Optimize Memory Write lbits:10 reserved1 Reserved lbits:1 isr iTR Soft Reset lbits:1 nse No Snoop Enable lbits:6 reserved Reserved {} or ncfghi_gcr (Offset 0x40C) Global Control Register <byte 14324> ulong value As longword endunion ncfghi_gcr (Offset 0x40C) Global Control Register <byte 14328> union ncfghi_gsr (Offset 0x410) Global Status Register <byte 14328> {field (By field)} <byte 14328> lbits:3 pfom PCI/PCI-X Frequency and Operating Mode lbits:8 reserved2 Reserved lbits:1 pebr Parity Error from Boot RAM lbits:1 rra Reserved Region Access lbits:1 dmcs Driver Mode Control Status lbits:1 reserved1 Reserved lbits:1 madr3 Memory Address 3 lbits:1 rcs Reference Clock Stable lbits:15 reserved Reserved {} or ncfghi_gsr (Offset 0x410) Global Status Register <byte 14328> ulong value As longword endunion ncfghi_gsr (Offset 0x410) Global Status Register <byte 14332> union ncfghi_reg_414 (Offset 0x414) BWR/RESERVED <byte 14332> {field (By field)} <byte 14332> union ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register <byte 14332> {field (By field)} <byte 14332> bits:1 dusc Disable USC Check bits:1 reserved1 Reserved

bits:1 en698 Enable DX698 bits:1 en711 Enable DX711 bits:1 en762 Enable DX762 bits:1 en820 Enable DX820 bits:1 reserved Reserved bits:1 dofc Disable Outbound FIFO CRC Checking bits:1 difc Disable Inbound FIFO CRC Checking bits:7 nd Not Defined {} or ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register <byte 14332> ushort value As word endunion ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register <byte 14334> {ncfghi_rsvd416_417 ((Offset 0x416) Reserved)} <byte 14334> ushort value {} {} or ncfghi_reg_414 (Offset 0x414) BWR/RESERVED <byte 14332> ulong value As longword endunion ncfghi_reg_414 (Offset 0x414) BWR/RESERVED <byte 14336> {ncfghi_rsvd418_41B ((Offset 0x418) Reserved)} <byte 14336> ulong value {} <byte 14340> {ncfghi_rsvd41C_41F ((Offset 0x41C) Reserved)} <byte 14340> ulong value {} <byte 14344> union ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low <byte 14344> {field (By field)} <byte 14344> lbits:32 address Address {} or ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low <byte 14344> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low <byte 14348> union ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High <byte 14348> {field (By field)} <byte 14348> lbits:32 address Address {} or ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High <byte 14348> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High <byte 14352> union ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low <byte 14352> {field (By field)} <byte 14352>

lbits:32 address Address {} or ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low <byte 14352> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low <byte 14356> union ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High <byte 14356> {field (By field)} <byte 14356> lbits:32 address Address {} or ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High <byte 14356> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High {} endunion ncfghi[0] Tachyon DX2+ PCI Non-Configuration Registers High <byte 14360> union ncfghi[1] Tachyon DX2+ PCI Non-Configuration Registers High <byte 14360> ulong[12] ncfghia Tachyon DX2+ PCI Non-Configuration Registers -- High As Longwo rds or ncfghi[1] Tachyon DX2+ PCI Non-Configuration Registers High <byte 14360> {ncfghi (Tachyon DX2+ PCI Non-Configuration Registers -- High By Field)} <byte 14360> union ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register <byte 14360> {field (By field)} <byte 14360> lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register <byte 14360> ulong value As longword endunion ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register <byte 14364> union ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register <byte 14364> {field (By field)} <byte 14364> lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved

lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register <byte 14364> ulong value As longword endunion ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register <byte 14368> union ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Regi ster <byte 14368> {field (By field)} <byte 14368> lbits:12 qf1 Quiesce Function 1 lbits:12 qf0 Quiesce Function 0 lbits:8 reserved Reserved {} or ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Registe r <byte 14368> ulong value As longword endunion ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration R egister <byte 14372> union ncfghi_gcr (Offset 0x40C) Global Control Register <byte 14372> {field (By field)} <byte 14372> lbits:1 ror Reissue on Retry lbits:8 reserved3 Reserved lbits:1 rod Reissue on Disconnect lbits:1 gsr Global Soft Reset lbits:2 reserved2 Reserved lbits:1 omw Optimize Memory Write lbits:10 reserved1 Reserved lbits:1 isr iTR Soft Reset lbits:1 nse No Snoop Enable lbits:6 reserved Reserved {} or ncfghi_gcr (Offset 0x40C) Global Control Register <byte 14372> ulong value As longword endunion ncfghi_gcr (Offset 0x40C) Global Control Register <byte 14376> union ncfghi_gsr (Offset 0x410) Global Status Register <byte 14376> {field (By field)} <byte 14376> lbits:3 pfom PCI/PCI-X Frequency and Operating Mode lbits:8 reserved2 Reserved lbits:1 pebr Parity Error from Boot RAM lbits:1 rra Reserved Region Access lbits:1 dmcs Driver Mode Control Status lbits:1 reserved1 Reserved lbits:1 madr3 Memory Address 3 lbits:1 rcs Reference Clock Stable

lbits:15 reserved Reserved {} or ncfghi_gsr (Offset 0x410) Global Status Register <byte 14376> ulong value As longword endunion ncfghi_gsr (Offset 0x410) Global Status Register <byte 14380> union ncfghi_reg_414 (Offset 0x414) BWR/RESERVED <byte 14380> {field (By field)} <byte 14380> union ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register <byte 14380> {field (By field)} <byte 14380> bits:1 dusc Disable USC Check bits:1 reserved1 Reserved bits:1 en698 Enable DX698 bits:1 en711 Enable DX711 bits:1 en762 Enable DX762 bits:1 en820 Enable DX820 bits:1 reserved Reserved bits:1 dofc Disable Outbound FIFO CRC Checking bits:1 difc Disable Inbound FIFO CRC Checking bits:7 nd Not Defined {} or ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register <byte 14380> ushort value As word endunion ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register <byte 14382> {ncfghi_rsvd416_417 ((Offset 0x416) Reserved)} <byte 14382> ushort value {} {} or ncfghi_reg_414 (Offset 0x414) BWR/RESERVED <byte 14380> ulong value As longword endunion ncfghi_reg_414 (Offset 0x414) BWR/RESERVED <byte 14384> {ncfghi_rsvd418_41B ((Offset 0x418) Reserved)} <byte 14384> ulong value {} <byte 14388> {ncfghi_rsvd41C_41F ((Offset 0x41C) Reserved)} <byte 14388> ulong value {} <byte 14392> union ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low <byte 14392> {field (By field)} <byte 14392> lbits:32 address Address {} or ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low <byte 14392> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}

endunion ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low <byte 14396> union ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High <byte 14396> {field (By field)} <byte 14396> lbits:32 address Address {} or ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High <byte 14396> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High <byte 14400> union ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low <byte 14400> {field (By field)} <byte 14400> lbits:32 address Address {} or ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low <byte 14400> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low <byte 14404> union ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High <byte 14404> {field (By field)} <byte 14404> lbits:32 address Address {} or ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High <byte 14404> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High {} endunion ncfghi[1] Tachyon DX2+ PCI Non-Configuration Registers High <byte 14408> union ncfghi[2] Tachyon DX2+ PCI Non-Configuration Registers High <byte 14408> ulong[12] ncfghia Tachyon DX2+ PCI Non-Configuration Registers -- High As Longwo rds or ncfghi[2] Tachyon DX2+ PCI Non-Configuration Registers High <byte 14408> {ncfghi (Tachyon DX2+ PCI Non-Configuration Registers -- High By Field)} <byte 14408> union ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register <byte 14408> {field (By field)} <byte 14408> lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1

lbits:18 reserved Reserved {} or ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register <byte 14408> ulong value As longword endunion ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register <byte 14412> union ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register <byte 14412> {field (By field)} <byte 14412> lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register <byte 14412> ulong value As longword endunion ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register <byte 14416> union ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Regi ster <byte 14416> {field (By field)} <byte 14416> lbits:12 qf1 Quiesce Function 1 lbits:12 qf0 Quiesce Function 0 lbits:8 reserved Reserved {} or ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Registe r <byte 14416> ulong value As longword endunion ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration R egister <byte 14420> union ncfghi_gcr (Offset 0x40C) Global Control Register <byte 14420> {field (By field)} <byte 14420> lbits:1 ror Reissue on Retry lbits:8 reserved3 Reserved lbits:1 rod Reissue on Disconnect lbits:1 gsr Global Soft Reset lbits:2 reserved2 Reserved lbits:1 omw Optimize Memory Write lbits:10 reserved1 Reserved lbits:1 isr iTR Soft Reset lbits:1 nse No Snoop Enable lbits:6 reserved Reserved {}

or ncfghi_gcr (Offset 0x40C) Global Control Register <byte 14420> ulong value As longword endunion ncfghi_gcr (Offset 0x40C) Global Control Register <byte 14424> union ncfghi_gsr (Offset 0x410) Global Status Register <byte 14424> {field (By field)} <byte 14424> lbits:3 pfom PCI/PCI-X Frequency and Operating Mode lbits:8 reserved2 Reserved lbits:1 pebr Parity Error from Boot RAM lbits:1 rra Reserved Region Access lbits:1 dmcs Driver Mode Control Status lbits:1 reserved1 Reserved lbits:1 madr3 Memory Address 3 lbits:1 rcs Reference Clock Stable lbits:15 reserved Reserved {} or ncfghi_gsr (Offset 0x410) Global Status Register <byte 14424> ulong value As longword endunion ncfghi_gsr (Offset 0x410) Global Status Register <byte 14428> union ncfghi_reg_414 (Offset 0x414) BWR/RESERVED <byte 14428> {field (By field)} <byte 14428> union ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register <byte 14428> {field (By field)} <byte 14428> bits:1 dusc Disable USC Check bits:1 reserved1 Reserved bits:1 en698 Enable DX698 bits:1 en711 Enable DX711 bits:1 en762 Enable DX762 bits:1 en820 Enable DX820 bits:1 reserved Reserved bits:1 dofc Disable Outbound FIFO CRC Checking bits:1 difc Disable Inbound FIFO CRC Checking bits:7 nd Not Defined {} or ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register <byte 14428> ushort value As word endunion ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register <byte 14430> {ncfghi_rsvd416_417 ((Offset 0x416) Reserved)} <byte 14430> ushort value {} {} or ncfghi_reg_414 (Offset 0x414) BWR/RESERVED <byte 14428> ulong value As longword endunion ncfghi_reg_414 (Offset 0x414) BWR/RESERVED <byte 14432> {ncfghi_rsvd418_41B ((Offset 0x418) Reserved)} <byte 14432>

ulong value {} <byte 14436> {ncfghi_rsvd41C_41F ((Offset 0x41C) Reserved)} <byte 14436> ulong value {} <byte 14440> union ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low <byte 14440> {field (By field)} <byte 14440> lbits:32 address Address {} or ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low <byte 14440> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low <byte 14444> union ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High <byte 14444> {field (By field)} <byte 14444> lbits:32 address Address {} or ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High <byte 14444> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High <byte 14448> union ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low <byte 14448> {field (By field)} <byte 14448> lbits:32 address Address {} or ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low <byte 14448> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low <byte 14452> union ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High <byte 14452> {field (By field)} <byte 14452> lbits:32 address Address {} or ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High <byte 14452> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High {} endunion ncfghi[2] Tachyon DX2+ PCI Non-Configuration Registers High <byte 14456> union ncfghi[3] Tachyon DX2+ PCI Non-Configuration Registers High <byte 14456> ulong[12] ncfghia Tachyon DX2+ PCI Non-Configuration Registers -- High As Longwo rds or ncfghi[3] Tachyon DX2+ PCI Non-Configuration Registers High <byte 14456>

{ncfghi (Tachyon DX2+ PCI Non-Configuration Registers -- High By Field)} <byte 14456> union ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register <byte 14456> {field (By field)} <byte 14456> lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register <byte 14456> ulong value As longword endunion ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register <byte 14460> union ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register <byte 14460> {field (By field)} <byte 14460> lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register <byte 14460> ulong value As longword endunion ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register <byte 14464> union ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Regi ster <byte 14464> {field (By field)} <byte 14464> lbits:12 qf1 Quiesce Function 1 lbits:12 qf0 Quiesce Function 0 lbits:8 reserved Reserved {} or ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Registe r <byte 14464> ulong value As longword endunion ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration R

egister <byte 14468> union ncfghi_gcr (Offset 0x40C) Global Control Register <byte 14468> {field (By field)} <byte 14468> lbits:1 ror Reissue on Retry lbits:8 reserved3 Reserved lbits:1 rod Reissue on Disconnect lbits:1 gsr Global Soft Reset lbits:2 reserved2 Reserved lbits:1 omw Optimize Memory Write lbits:10 reserved1 Reserved lbits:1 isr iTR Soft Reset lbits:1 nse No Snoop Enable lbits:6 reserved Reserved {} or ncfghi_gcr (Offset 0x40C) Global Control Register <byte 14468> ulong value As longword endunion ncfghi_gcr (Offset 0x40C) Global Control Register <byte 14472> union ncfghi_gsr (Offset 0x410) Global Status Register <byte 14472> {field (By field)} <byte 14472> lbits:3 pfom PCI/PCI-X Frequency and Operating Mode lbits:8 reserved2 Reserved lbits:1 pebr Parity Error from Boot RAM lbits:1 rra Reserved Region Access lbits:1 dmcs Driver Mode Control Status lbits:1 reserved1 Reserved lbits:1 madr3 Memory Address 3 lbits:1 rcs Reference Clock Stable lbits:15 reserved Reserved {} or ncfghi_gsr (Offset 0x410) Global Status Register <byte 14472> ulong value As longword endunion ncfghi_gsr (Offset 0x410) Global Status Register <byte 14476> union ncfghi_reg_414 (Offset 0x414) BWR/RESERVED <byte 14476> {field (By field)} <byte 14476> union ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register <byte 14476> {field (By field)} <byte 14476> bits:1 dusc Disable USC Check bits:1 reserved1 Reserved bits:1 en698 Enable DX698 bits:1 en711 Enable DX711 bits:1 en762 Enable DX762 bits:1 en820 Enable DX820 bits:1 reserved Reserved bits:1 dofc Disable Outbound FIFO CRC Checking bits:1 difc Disable Inbound FIFO CRC Checking bits:7 nd Not Defined {}

or ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register <byte 14476> ushort value As word endunion ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register <byte 14478> {ncfghi_rsvd416_417 ((Offset 0x416) Reserved)} <byte 14478> ushort value {} {} or ncfghi_reg_414 (Offset 0x414) BWR/RESERVED <byte 14476> ulong value As longword endunion ncfghi_reg_414 (Offset 0x414) BWR/RESERVED <byte 14480> {ncfghi_rsvd418_41B ((Offset 0x418) Reserved)} <byte 14480> ulong value {} <byte 14484> {ncfghi_rsvd41C_41F ((Offset 0x41C) Reserved)} <byte 14484> ulong value {} <byte 14488> union ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low <byte 14488> {field (By field)} <byte 14488> lbits:32 address Address {} or ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low <byte 14488> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low <byte 14492> union ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High <byte 14492> {field (By field)} <byte 14492> lbits:32 address Address {} or ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High <byte 14492> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High <byte 14496> union ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low <byte 14496> {field (By field)} <byte 14496> lbits:32 address Address {} or ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low <byte 14496> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low <byte 14500> union ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High <byte 14500>

{field (By field)} <byte 14500> lbits:32 address Address {} or ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High <byte 14500> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High {} endunion ncfghi[3] Tachyon DX2+ PCI Non-Configuration Registers High <byte 14504> union ncfghi[4] Tachyon DX2+ PCI Non-Configuration Registers High <byte 14504> ulong[12] ncfghia Tachyon DX2+ PCI Non-Configuration Registers -- High As Longwo rds or ncfghi[4] Tachyon DX2+ PCI Non-Configuration Registers High <byte 14504> {ncfghi (Tachyon DX2+ PCI Non-Configuration Registers -- High By Field)} <byte 14504> union ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register <byte 14504> {field (By field)} <byte 14504> lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register <byte 14504> ulong value As longword endunion ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register <byte 14508> union ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register <byte 14508> {field (By field)} <byte 14508> lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register <byte 14508>

ulong value As longword endunion ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register <byte 14512> union ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Regi ster <byte 14512> {field (By field)} <byte 14512> lbits:12 qf1 Quiesce Function 1 lbits:12 qf0 Quiesce Function 0 lbits:8 reserved Reserved {} or ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Registe r <byte 14512> ulong value As longword endunion ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration R egister <byte 14516> union ncfghi_gcr (Offset 0x40C) Global Control Register <byte 14516> {field (By field)} <byte 14516> lbits:1 ror Reissue on Retry lbits:8 reserved3 Reserved lbits:1 rod Reissue on Disconnect lbits:1 gsr Global Soft Reset lbits:2 reserved2 Reserved lbits:1 omw Optimize Memory Write lbits:10 reserved1 Reserved lbits:1 isr iTR Soft Reset lbits:1 nse No Snoop Enable lbits:6 reserved Reserved {} or ncfghi_gcr (Offset 0x40C) Global Control Register <byte 14516> ulong value As longword endunion ncfghi_gcr (Offset 0x40C) Global Control Register <byte 14520> union ncfghi_gsr (Offset 0x410) Global Status Register <byte 14520> {field (By field)} <byte 14520> lbits:3 pfom PCI/PCI-X Frequency and Operating Mode lbits:8 reserved2 Reserved lbits:1 pebr Parity Error from Boot RAM lbits:1 rra Reserved Region Access lbits:1 dmcs Driver Mode Control Status lbits:1 reserved1 Reserved lbits:1 madr3 Memory Address 3 lbits:1 rcs Reference Clock Stable lbits:15 reserved Reserved {} or ncfghi_gsr (Offset 0x410) Global Status Register <byte 14520> ulong value As longword endunion ncfghi_gsr (Offset 0x410) Global Status Register <byte 14524> union ncfghi_reg_414 (Offset 0x414) BWR/RESERVED <byte 14524>

{field (By field)} <byte 14524> union ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register <byte 14524> {field (By field)} <byte 14524> bits:1 dusc Disable USC Check bits:1 reserved1 Reserved bits:1 en698 Enable DX698 bits:1 en711 Enable DX711 bits:1 en762 Enable DX762 bits:1 en820 Enable DX820 bits:1 reserved Reserved bits:1 dofc Disable Outbound FIFO CRC Checking bits:1 difc Disable Inbound FIFO CRC Checking bits:7 nd Not Defined {} or ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register <byte 14524> ushort value As word endunion ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register <byte 14526> {ncfghi_rsvd416_417 ((Offset 0x416) Reserved)} <byte 14526> ushort value {} {} or ncfghi_reg_414 (Offset 0x414) BWR/RESERVED <byte 14524> ulong value As longword endunion ncfghi_reg_414 (Offset 0x414) BWR/RESERVED <byte 14528> {ncfghi_rsvd418_41B ((Offset 0x418) Reserved)} <byte 14528> ulong value {} <byte 14532> {ncfghi_rsvd41C_41F ((Offset 0x41C) Reserved)} <byte 14532> ulong value {} <byte 14536> union ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low <byte 14536> {field (By field)} <byte 14536> lbits:32 address Address {} or ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low <byte 14536> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low <byte 14540> union ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High <byte 14540> {field (By field)} <byte 14540> lbits:32 address Address {} or ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High

<byte 14540> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High <byte 14544> union ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low <byte 14544> {field (By field)} <byte 14544> lbits:32 address Address {} or ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low <byte 14544> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low <byte 14548> union ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High <byte 14548> {field (By field)} <byte 14548> lbits:32 address Address {} or ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High <byte 14548> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High {} endunion ncfghi[4] Tachyon DX2+ PCI Non-Configuration Registers High <byte 14552> union ncfghi[5] Tachyon DX2+ PCI Non-Configuration Registers High <byte 14552> ulong[12] ncfghia Tachyon DX2+ PCI Non-Configuration Registers -- High As Longwo rds or ncfghi[5] Tachyon DX2+ PCI Non-Configuration Registers High <byte 14552> {ncfghi (Tachyon DX2+ PCI Non-Configuration Registers -- High By Field)} <byte 14552> union ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register <byte 14552> {field (By field)} <byte 14552> lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register <byte 14552> ulong value As longword endunion ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register <byte 14556> union ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register <byte 14556>

{field (By field)} <byte 14556> lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register <byte 14556> ulong value As longword endunion ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register <byte 14560> union ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Regi ster <byte 14560> {field (By field)} <byte 14560> lbits:12 qf1 Quiesce Function 1 lbits:12 qf0 Quiesce Function 0 lbits:8 reserved Reserved {} or ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Registe r <byte 14560> ulong value As longword endunion ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration R egister <byte 14564> union ncfghi_gcr (Offset 0x40C) Global Control Register <byte 14564> {field (By field)} <byte 14564> lbits:1 ror Reissue on Retry lbits:8 reserved3 Reserved lbits:1 rod Reissue on Disconnect lbits:1 gsr Global Soft Reset lbits:2 reserved2 Reserved lbits:1 omw Optimize Memory Write lbits:10 reserved1 Reserved lbits:1 isr iTR Soft Reset lbits:1 nse No Snoop Enable lbits:6 reserved Reserved {} or ncfghi_gcr (Offset 0x40C) Global Control Register <byte 14564> ulong value As longword endunion ncfghi_gcr (Offset 0x40C) Global Control Register <byte 14568> union ncfghi_gsr (Offset 0x410) Global Status Register <byte 14568> {field (By field)} <byte 14568>

lbits:3 pfom PCI/PCI-X Frequency and Operating Mode lbits:8 reserved2 Reserved lbits:1 pebr Parity Error from Boot RAM lbits:1 rra Reserved Region Access lbits:1 dmcs Driver Mode Control Status lbits:1 reserved1 Reserved lbits:1 madr3 Memory Address 3 lbits:1 rcs Reference Clock Stable lbits:15 reserved Reserved {} or ncfghi_gsr (Offset 0x410) Global Status Register <byte 14568> ulong value As longword endunion ncfghi_gsr (Offset 0x410) Global Status Register <byte 14572> union ncfghi_reg_414 (Offset 0x414) BWR/RESERVED <byte 14572> {field (By field)} <byte 14572> union ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register <byte 14572> {field (By field)} <byte 14572> bits:1 dusc Disable USC Check bits:1 reserved1 Reserved bits:1 en698 Enable DX698 bits:1 en711 Enable DX711 bits:1 en762 Enable DX762 bits:1 en820 Enable DX820 bits:1 reserved Reserved bits:1 dofc Disable Outbound FIFO CRC Checking bits:1 difc Disable Inbound FIFO CRC Checking bits:7 nd Not Defined {} or ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register <byte 14572> ushort value As word endunion ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register <byte 14574> {ncfghi_rsvd416_417 ((Offset 0x416) Reserved)} <byte 14574> ushort value {} {} or ncfghi_reg_414 (Offset 0x414) BWR/RESERVED <byte 14572> ulong value As longword endunion ncfghi_reg_414 (Offset 0x414) BWR/RESERVED <byte 14576> {ncfghi_rsvd418_41B ((Offset 0x418) Reserved)} <byte 14576> ulong value {} <byte 14580> {ncfghi_rsvd41C_41F ((Offset 0x41C) Reserved)} <byte 14580> ulong value {} <byte 14584> union ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low

<byte 14584> {field (By field)} <byte 14584> lbits:32 address Address {} or ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low <byte 14584> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low <byte 14588> union ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High <byte 14588> {field (By field)} <byte 14588> lbits:32 address Address {} or ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High <byte 14588> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High <byte 14592> union ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low <byte 14592> {field (By field)} <byte 14592> lbits:32 address Address {} or ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low <byte 14592> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low <byte 14596> union ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High <byte 14596> {field (By field)} <byte 14596> lbits:32 address Address {} or ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High <byte 14596> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High {} endunion ncfghi[5] Tachyon DX2+ PCI Non-Configuration Registers High <byte 14600> union ncfghi[6] Tachyon DX2+ PCI Non-Configuration Registers High <byte 14600> ulong[12] ncfghia Tachyon DX2+ PCI Non-Configuration Registers -- High As Longwo rds or ncfghi[6] Tachyon DX2+ PCI Non-Configuration Registers High <byte 14600> {ncfghi (Tachyon DX2+ PCI Non-Configuration Registers -- High By Field)} <byte 14600> union ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register <byte 14600> {field (By field)} <byte 14600> lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt

lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register <byte 14600> ulong value As longword endunion ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register <byte 14604> union ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register <byte 14604> {field (By field)} <byte 14604> lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register <byte 14604> ulong value As longword endunion ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register <byte 14608> union ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Regi ster <byte 14608> {field (By field)} <byte 14608> lbits:12 qf1 Quiesce Function 1 lbits:12 qf0 Quiesce Function 0 lbits:8 reserved Reserved {} or ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Registe r <byte 14608> ulong value As longword endunion ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration R egister <byte 14612> union ncfghi_gcr (Offset 0x40C) Global Control Register <byte 14612> {field (By field)} <byte 14612> lbits:1 ror Reissue on Retry lbits:8 reserved3 Reserved lbits:1 rod Reissue on Disconnect

lbits:1 gsr Global Soft Reset lbits:2 reserved2 Reserved lbits:1 omw Optimize Memory Write lbits:10 reserved1 Reserved lbits:1 isr iTR Soft Reset lbits:1 nse No Snoop Enable lbits:6 reserved Reserved {} or ncfghi_gcr (Offset 0x40C) Global Control Register <byte 14612> ulong value As longword endunion ncfghi_gcr (Offset 0x40C) Global Control Register <byte 14616> union ncfghi_gsr (Offset 0x410) Global Status Register <byte 14616> {field (By field)} <byte 14616> lbits:3 pfom PCI/PCI-X Frequency and Operating Mode lbits:8 reserved2 Reserved lbits:1 pebr Parity Error from Boot RAM lbits:1 rra Reserved Region Access lbits:1 dmcs Driver Mode Control Status lbits:1 reserved1 Reserved lbits:1 madr3 Memory Address 3 lbits:1 rcs Reference Clock Stable lbits:15 reserved Reserved {} or ncfghi_gsr (Offset 0x410) Global Status Register <byte 14616> ulong value As longword endunion ncfghi_gsr (Offset 0x410) Global Status Register <byte 14620> union ncfghi_reg_414 (Offset 0x414) BWR/RESERVED <byte 14620> {field (By field)} <byte 14620> union ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register <byte 14620> {field (By field)} <byte 14620> bits:1 dusc Disable USC Check bits:1 reserved1 Reserved bits:1 en698 Enable DX698 bits:1 en711 Enable DX711 bits:1 en762 Enable DX762 bits:1 en820 Enable DX820 bits:1 reserved Reserved bits:1 dofc Disable Outbound FIFO CRC Checking bits:1 difc Disable Inbound FIFO CRC Checking bits:7 nd Not Defined {} or ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register <byte 14620> ushort value As word endunion ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register <byte 14622> {ncfghi_rsvd416_417 ((Offset 0x416) Reserved)} <byte 14622> ushort value {}

{} or ncfghi_reg_414 (Offset 0x414) BWR/RESERVED <byte 14620> ulong value As longword endunion ncfghi_reg_414 (Offset 0x414) BWR/RESERVED <byte 14624> {ncfghi_rsvd418_41B ((Offset 0x418) Reserved)} <byte 14624> ulong value {} <byte 14628> {ncfghi_rsvd41C_41F ((Offset 0x41C) Reserved)} <byte 14628> ulong value {} <byte 14632> union ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low <byte 14632> {field (By field)} <byte 14632> lbits:32 address Address {} or ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low <byte 14632> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low <byte 14636> union ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High <byte 14636> {field (By field)} <byte 14636> lbits:32 address Address {} or ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High <byte 14636> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High <byte 14640> union ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low <byte 14640> {field (By field)} <byte 14640> lbits:32 address Address {} or ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low <byte 14640> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low <byte 14644> union ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High <byte 14644> {field (By field)} <byte 14644> lbits:32 address Address {} or ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High <byte 14644> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High {}

endunion ncfghi[6] Tachyon DX2+ PCI Non-Configuration Registers High <byte 14648> union ncfghi[7] Tachyon DX2+ PCI Non-Configuration Registers High <byte 14648> ulong[12] ncfghia Tachyon DX2+ PCI Non-Configuration Registers -- High As Longwo rds or ncfghi[7] Tachyon DX2+ PCI Non-Configuration Registers High <byte 14648> {ncfghi (Tachyon DX2+ PCI Non-Configuration Registers -- High By Field)} <byte 14648> union ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register <byte 14648> {field (By field)} <byte 14648> lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register <byte 14648> ulong value As longword endunion ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register <byte 14652> union ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register <byte 14652> {field (By field)} <byte 14652> lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register <byte 14652> ulong value As longword endunion ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register <byte 14656> union ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Regi ster <byte 14656> {field (By field)} <byte 14656> lbits:12 qf1 Quiesce Function 1

lbits:12 qf0 Quiesce Function 0 lbits:8 reserved Reserved {} or ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Registe r <byte 14656> ulong value As longword endunion ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration R egister <byte 14660> union ncfghi_gcr (Offset 0x40C) Global Control Register <byte 14660> {field (By field)} <byte 14660> lbits:1 ror Reissue on Retry lbits:8 reserved3 Reserved lbits:1 rod Reissue on Disconnect lbits:1 gsr Global Soft Reset lbits:2 reserved2 Reserved lbits:1 omw Optimize Memory Write lbits:10 reserved1 Reserved lbits:1 isr iTR Soft Reset lbits:1 nse No Snoop Enable lbits:6 reserved Reserved {} or ncfghi_gcr (Offset 0x40C) Global Control Register <byte 14660> ulong value As longword endunion ncfghi_gcr (Offset 0x40C) Global Control Register <byte 14664> union ncfghi_gsr (Offset 0x410) Global Status Register <byte 14664> {field (By field)} <byte 14664> lbits:3 pfom PCI/PCI-X Frequency and Operating Mode lbits:8 reserved2 Reserved lbits:1 pebr Parity Error from Boot RAM lbits:1 rra Reserved Region Access lbits:1 dmcs Driver Mode Control Status lbits:1 reserved1 Reserved lbits:1 madr3 Memory Address 3 lbits:1 rcs Reference Clock Stable lbits:15 reserved Reserved {} or ncfghi_gsr (Offset 0x410) Global Status Register <byte 14664> ulong value As longword endunion ncfghi_gsr (Offset 0x410) Global Status Register <byte 14668> union ncfghi_reg_414 (Offset 0x414) BWR/RESERVED <byte 14668> {field (By field)} <byte 14668> union ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register <byte 14668> {field (By field)} <byte 14668> bits:1 dusc Disable USC Check bits:1 reserved1 Reserved bits:1 en698 Enable DX698

bits:1 en711 Enable DX711 bits:1 en762 Enable DX762 bits:1 en820 Enable DX820 bits:1 reserved Reserved bits:1 dofc Disable Outbound FIFO CRC Checking bits:1 difc Disable Inbound FIFO CRC Checking bits:7 nd Not Defined {} or ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register <byte 14668> ushort value As word endunion ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register <byte 14670> {ncfghi_rsvd416_417 ((Offset 0x416) Reserved)} <byte 14670> ushort value {} {} or ncfghi_reg_414 (Offset 0x414) BWR/RESERVED <byte 14668> ulong value As longword endunion ncfghi_reg_414 (Offset 0x414) BWR/RESERVED <byte 14672> {ncfghi_rsvd418_41B ((Offset 0x418) Reserved)} <byte 14672> ulong value {} <byte 14676> {ncfghi_rsvd41C_41F ((Offset 0x41C) Reserved)} <byte 14676> ulong value {} <byte 14680> union ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low <byte 14680> {field (By field)} <byte 14680> lbits:32 address Address {} or ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low <byte 14680> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low <byte 14684> union ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High <byte 14684> {field (By field)} <byte 14684> lbits:32 address Address {} or ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High <byte 14684> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High <byte 14688> union ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low <byte 14688> {field (By field)} <byte 14688> lbits:32 address Address

{} or ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low <byte 14688> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low <byte 14692> union ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High <byte 14692> {field (By field)} <byte 14692> lbits:32 address Address {} or ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High <byte 14692> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High {} endunion ncfghi[7] Tachyon DX2+ PCI Non-Configuration Registers High <byte 14696> union ncfghi[8] Tachyon DX2+ PCI Non-Configuration Registers High <byte 14696> ulong[12] ncfghia Tachyon DX2+ PCI Non-Configuration Registers -- High As Longwo rds or ncfghi[8] Tachyon DX2+ PCI Non-Configuration Registers High <byte 14696> {ncfghi (Tachyon DX2+ PCI Non-Configuration Registers -- High By Field)} <byte 14696> union ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register <byte 14696> {field (By field)} <byte 14696> lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register <byte 14696> ulong value As longword endunion ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register <byte 14700> union ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register <byte 14700> {field (By field)} <byte 14700> lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1

lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register <byte 14700> ulong value As longword endunion ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register <byte 14704> union ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Regi ster <byte 14704> {field (By field)} <byte 14704> lbits:12 qf1 Quiesce Function 1 lbits:12 qf0 Quiesce Function 0 lbits:8 reserved Reserved {} or ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Registe r <byte 14704> ulong value As longword endunion ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration R egister <byte 14708> union ncfghi_gcr (Offset 0x40C) Global Control Register <byte 14708> {field (By field)} <byte 14708> lbits:1 ror Reissue on Retry lbits:8 reserved3 Reserved lbits:1 rod Reissue on Disconnect lbits:1 gsr Global Soft Reset lbits:2 reserved2 Reserved lbits:1 omw Optimize Memory Write lbits:10 reserved1 Reserved lbits:1 isr iTR Soft Reset lbits:1 nse No Snoop Enable lbits:6 reserved Reserved {} or ncfghi_gcr (Offset 0x40C) Global Control Register <byte 14708> ulong value As longword endunion ncfghi_gcr (Offset 0x40C) Global Control Register <byte 14712> union ncfghi_gsr (Offset 0x410) Global Status Register <byte 14712> {field (By field)} <byte 14712> lbits:3 pfom PCI/PCI-X Frequency and Operating Mode lbits:8 reserved2 Reserved lbits:1 pebr Parity Error from Boot RAM lbits:1 rra Reserved Region Access lbits:1 dmcs Driver Mode Control Status lbits:1 reserved1 Reserved lbits:1 madr3 Memory Address 3 lbits:1 rcs Reference Clock Stable lbits:15 reserved Reserved

{} or ncfghi_gsr (Offset 0x410) Global Status Register <byte 14712> ulong value As longword endunion ncfghi_gsr (Offset 0x410) Global Status Register <byte 14716> union ncfghi_reg_414 (Offset 0x414) BWR/RESERVED <byte 14716> {field (By field)} <byte 14716> union ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register <byte 14716> {field (By field)} <byte 14716> bits:1 dusc Disable USC Check bits:1 reserved1 Reserved bits:1 en698 Enable DX698 bits:1 en711 Enable DX711 bits:1 en762 Enable DX762 bits:1 en820 Enable DX820 bits:1 reserved Reserved bits:1 dofc Disable Outbound FIFO CRC Checking bits:1 difc Disable Inbound FIFO CRC Checking bits:7 nd Not Defined {} or ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register <byte 14716> ushort value As word endunion ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register <byte 14718> {ncfghi_rsvd416_417 ((Offset 0x416) Reserved)} <byte 14718> ushort value {} {} or ncfghi_reg_414 (Offset 0x414) BWR/RESERVED <byte 14716> ulong value As longword endunion ncfghi_reg_414 (Offset 0x414) BWR/RESERVED <byte 14720> {ncfghi_rsvd418_41B ((Offset 0x418) Reserved)} <byte 14720> ulong value {} <byte 14724> {ncfghi_rsvd41C_41F ((Offset 0x41C) Reserved)} <byte 14724> ulong value {} <byte 14728> union ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low <byte 14728> {field (By field)} <byte 14728> lbits:32 address Address {} or ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low <byte 14728> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low

<byte 14732> union ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High <byte 14732> {field (By field)} <byte 14732> lbits:32 address Address {} or ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High <byte 14732> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High <byte 14736> union ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low <byte 14736> {field (By field)} <byte 14736> lbits:32 address Address {} or ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low <byte 14736> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low <byte 14740> union ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High <byte 14740> {field (By field)} <byte 14740> lbits:32 address Address {} or ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High <byte 14740> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High {} endunion ncfghi[8] Tachyon DX2+ PCI Non-Configuration Registers High <byte 14744> union ncfghi[9] Tachyon DX2+ PCI Non-Configuration Registers High <byte 14744> ulong[12] ncfghia Tachyon DX2+ PCI Non-Configuration Registers -- High As Longwo rds or ncfghi[9] Tachyon DX2+ PCI Non-Configuration Registers High <byte 14744> {ncfghi (Tachyon DX2+ PCI Non-Configuration Registers -- High By Field)} <byte 14744> union ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register <byte 14744> {field (By field)} <byte 14744> lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved

{} or ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register <byte 14744> ulong value As longword endunion ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register <byte 14748> union ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register <byte 14748> {field (By field)} <byte 14748> lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register <byte 14748> ulong value As longword endunion ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register <byte 14752> union ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Regi ster <byte 14752> {field (By field)} <byte 14752> lbits:12 qf1 Quiesce Function 1 lbits:12 qf0 Quiesce Function 0 lbits:8 reserved Reserved {} or ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Registe r <byte 14752> ulong value As longword endunion ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration R egister <byte 14756> union ncfghi_gcr (Offset 0x40C) Global Control Register <byte 14756> {field (By field)} <byte 14756> lbits:1 ror Reissue on Retry lbits:8 reserved3 Reserved lbits:1 rod Reissue on Disconnect lbits:1 gsr Global Soft Reset lbits:2 reserved2 Reserved lbits:1 omw Optimize Memory Write lbits:10 reserved1 Reserved lbits:1 isr iTR Soft Reset lbits:1 nse No Snoop Enable lbits:6 reserved Reserved {} or ncfghi_gcr (Offset 0x40C) Global Control Register

<byte 14756> ulong value As longword endunion ncfghi_gcr (Offset 0x40C) Global Control Register <byte 14760> union ncfghi_gsr (Offset 0x410) Global Status Register <byte 14760> {field (By field)} <byte 14760> lbits:3 pfom PCI/PCI-X Frequency and Operating Mode lbits:8 reserved2 Reserved lbits:1 pebr Parity Error from Boot RAM lbits:1 rra Reserved Region Access lbits:1 dmcs Driver Mode Control Status lbits:1 reserved1 Reserved lbits:1 madr3 Memory Address 3 lbits:1 rcs Reference Clock Stable lbits:15 reserved Reserved {} or ncfghi_gsr (Offset 0x410) Global Status Register <byte 14760> ulong value As longword endunion ncfghi_gsr (Offset 0x410) Global Status Register <byte 14764> union ncfghi_reg_414 (Offset 0x414) BWR/RESERVED <byte 14764> {field (By field)} <byte 14764> union ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register <byte 14764> {field (By field)} <byte 14764> bits:1 dusc Disable USC Check bits:1 reserved1 Reserved bits:1 en698 Enable DX698 bits:1 en711 Enable DX711 bits:1 en762 Enable DX762 bits:1 en820 Enable DX820 bits:1 reserved Reserved bits:1 dofc Disable Outbound FIFO CRC Checking bits:1 difc Disable Inbound FIFO CRC Checking bits:7 nd Not Defined {} or ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register <byte 14764> ushort value As word endunion ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register <byte 14766> {ncfghi_rsvd416_417 ((Offset 0x416) Reserved)} <byte 14766> ushort value {} {} or ncfghi_reg_414 (Offset 0x414) BWR/RESERVED <byte 14764> ulong value As longword endunion ncfghi_reg_414 (Offset 0x414) BWR/RESERVED <byte 14768> {ncfghi_rsvd418_41B ((Offset 0x418) Reserved)} <byte 14768> ulong value

{} <byte 14772> {ncfghi_rsvd41C_41F ((Offset 0x41C) Reserved)} <byte 14772> ulong value {} <byte 14776> union ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low <byte 14776> {field (By field)} <byte 14776> lbits:32 address Address {} or ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low <byte 14776> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low <byte 14780> union ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High <byte 14780> {field (By field)} <byte 14780> lbits:32 address Address {} or ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High <byte 14780> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High <byte 14784> union ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low <byte 14784> {field (By field)} <byte 14784> lbits:32 address Address {} or ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low <byte 14784> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low <byte 14788> union ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High <byte 14788> {field (By field)} <byte 14788> lbits:32 address Address {} or ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High <byte 14788> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High {} endunion ncfghi[9] Tachyon DX2+ PCI Non-Configuration Registers High <byte 14792> union ncfghi[10] Tachyon DX2+ PCI Non-Configuration Registers High <byte 14792> ulong[12] ncfghia Tachyon DX2+ PCI Non-Configuration Registers -- High As Longwo rds or ncfghi[10] Tachyon DX2+ PCI Non-Configuration Registers High <byte 14792> {ncfghi (Tachyon DX2+ PCI Non-Configuration Registers -- High By Field)}

<byte 14792> union ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register <byte 14792> {field (By field)} <byte 14792> lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register <byte 14792> ulong value As longword endunion ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register <byte 14796> union ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register <byte 14796> {field (By field)} <byte 14796> lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register <byte 14796> ulong value As longword endunion ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register <byte 14800> union ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Regi ster <byte 14800> {field (By field)} <byte 14800> lbits:12 qf1 Quiesce Function 1 lbits:12 qf0 Quiesce Function 0 lbits:8 reserved Reserved {} or ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Registe r <byte 14800> ulong value As longword endunion ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration R egister

<byte 14804> union ncfghi_gcr (Offset 0x40C) Global Control Register <byte 14804> {field (By field)} <byte 14804> lbits:1 ror Reissue on Retry lbits:8 reserved3 Reserved lbits:1 rod Reissue on Disconnect lbits:1 gsr Global Soft Reset lbits:2 reserved2 Reserved lbits:1 omw Optimize Memory Write lbits:10 reserved1 Reserved lbits:1 isr iTR Soft Reset lbits:1 nse No Snoop Enable lbits:6 reserved Reserved {} or ncfghi_gcr (Offset 0x40C) Global Control Register <byte 14804> ulong value As longword endunion ncfghi_gcr (Offset 0x40C) Global Control Register <byte 14808> union ncfghi_gsr (Offset 0x410) Global Status Register <byte 14808> {field (By field)} <byte 14808> lbits:3 pfom PCI/PCI-X Frequency and Operating Mode lbits:8 reserved2 Reserved lbits:1 pebr Parity Error from Boot RAM lbits:1 rra Reserved Region Access lbits:1 dmcs Driver Mode Control Status lbits:1 reserved1 Reserved lbits:1 madr3 Memory Address 3 lbits:1 rcs Reference Clock Stable lbits:15 reserved Reserved {} or ncfghi_gsr (Offset 0x410) Global Status Register <byte 14808> ulong value As longword endunion ncfghi_gsr (Offset 0x410) Global Status Register <byte 14812> union ncfghi_reg_414 (Offset 0x414) BWR/RESERVED <byte 14812> {field (By field)} <byte 14812> union ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register <byte 14812> {field (By field)} <byte 14812> bits:1 dusc Disable USC Check bits:1 reserved1 Reserved bits:1 en698 Enable DX698 bits:1 en711 Enable DX711 bits:1 en762 Enable DX762 bits:1 en820 Enable DX820 bits:1 reserved Reserved bits:1 dofc Disable Outbound FIFO CRC Checking bits:1 difc Disable Inbound FIFO CRC Checking bits:7 nd Not Defined {} or ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register

<byte 14812> ushort value As word endunion ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register <byte 14814> {ncfghi_rsvd416_417 ((Offset 0x416) Reserved)} <byte 14814> ushort value {} {} or ncfghi_reg_414 (Offset 0x414) BWR/RESERVED <byte 14812> ulong value As longword endunion ncfghi_reg_414 (Offset 0x414) BWR/RESERVED <byte 14816> {ncfghi_rsvd418_41B ((Offset 0x418) Reserved)} <byte 14816> ulong value {} <byte 14820> {ncfghi_rsvd41C_41F ((Offset 0x41C) Reserved)} <byte 14820> ulong value {} <byte 14824> union ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low <byte 14824> {field (By field)} <byte 14824> lbits:32 address Address {} or ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low <byte 14824> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low <byte 14828> union ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High <byte 14828> {field (By field)} <byte 14828> lbits:32 address Address {} or ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High <byte 14828> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High <byte 14832> union ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low <byte 14832> {field (By field)} <byte 14832> lbits:32 address Address {} or ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low <byte 14832> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low <byte 14836> union ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High <byte 14836> {field (By field)}

<byte 14836> lbits:32 address Address {} or ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High <byte 14836> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High {} endunion ncfghi[10] Tachyon DX2+ PCI Non-Configuration Registers High <byte 14840> union ncfghi[11] Tachyon DX2+ PCI Non-Configuration Registers High <byte 14840> ulong[12] ncfghia Tachyon DX2+ PCI Non-Configuration Registers -- High As Longwo rds or ncfghi[11] Tachyon DX2+ PCI Non-Configuration Registers High <byte 14840> {ncfghi (Tachyon DX2+ PCI Non-Configuration Registers -- High By Field)} <byte 14840> union ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register <byte 14840> {field (By field)} <byte 14840> lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register <byte 14840> ulong value As longword endunion ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register <byte 14844> union ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register <byte 14844> {field (By field)} <byte 14844> lbits:1 per0 PCI Error Detected Interrupt Function 0 lbits:1 der0 Device Error Detected Interrupt Function 0 lbits:1 int0 Function 0 Interrupt lbits:2 reserved3 Reserved lbits:1 ube0 Unsupported Byte Enable Function 0 lbits:2 reserved2 Reserved lbits:1 per1 PCI Error Detected Interrupt Function 1 lbits:1 der1 Device Error Detected Interrupt Function 1 lbits:1 int1 Function 1 Interrupt lbits:2 reserved1 Reserved lbits:1 ube1 Unsupported Byte Enable Function 1 lbits:18 reserved Reserved {} or ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register <byte 14844> ulong value As longword

endunion ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register <byte 14848> union ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Regi ster <byte 14848> {field (By field)} <byte 14848> lbits:12 qf1 Quiesce Function 1 lbits:12 qf0 Quiesce Function 0 lbits:8 reserved Reserved {} or ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Registe r <byte 14848> ulong value As longword endunion ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration R egister <byte 14852> union ncfghi_gcr (Offset 0x40C) Global Control Register <byte 14852> {field (By field)} <byte 14852> lbits:1 ror Reissue on Retry lbits:8 reserved3 Reserved lbits:1 rod Reissue on Disconnect lbits:1 gsr Global Soft Reset lbits:2 reserved2 Reserved lbits:1 omw Optimize Memory Write lbits:10 reserved1 Reserved lbits:1 isr iTR Soft Reset lbits:1 nse No Snoop Enable lbits:6 reserved Reserved {} or ncfghi_gcr (Offset 0x40C) Global Control Register <byte 14852> ulong value As longword endunion ncfghi_gcr (Offset 0x40C) Global Control Register <byte 14856> union ncfghi_gsr (Offset 0x410) Global Status Register <byte 14856> {field (By field)} <byte 14856> lbits:3 pfom PCI/PCI-X Frequency and Operating Mode lbits:8 reserved2 Reserved lbits:1 pebr Parity Error from Boot RAM lbits:1 rra Reserved Region Access lbits:1 dmcs Driver Mode Control Status lbits:1 reserved1 Reserved lbits:1 madr3 Memory Address 3 lbits:1 rcs Reference Clock Stable lbits:15 reserved Reserved {} or ncfghi_gsr (Offset 0x410) Global Status Register <byte 14856> ulong value As longword endunion ncfghi_gsr (Offset 0x410) Global Status Register <byte 14860> union ncfghi_reg_414 (Offset 0x414) BWR/RESERVED <byte 14860> {field (By field)}

<byte 14860> union ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register <byte 14860> {field (By field)} <byte 14860> bits:1 dusc Disable USC Check bits:1 reserved1 Reserved bits:1 en698 Enable DX698 bits:1 en711 Enable DX711 bits:1 en762 Enable DX762 bits:1 en820 Enable DX820 bits:1 reserved Reserved bits:1 dofc Disable Outbound FIFO CRC Checking bits:1 difc Disable Inbound FIFO CRC Checking bits:7 nd Not Defined {} or ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register <byte 14860> ushort value As word endunion ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register <byte 14862> {ncfghi_rsvd416_417 ((Offset 0x416) Reserved)} <byte 14862> ushort value {} {} or ncfghi_reg_414 (Offset 0x414) BWR/RESERVED <byte 14860> ulong value As longword endunion ncfghi_reg_414 (Offset 0x414) BWR/RESERVED <byte 14864> {ncfghi_rsvd418_41B ((Offset 0x418) Reserved)} <byte 14864> ulong value {} <byte 14868> {ncfghi_rsvd41C_41F ((Offset 0x41C) Reserved)} <byte 14868> ulong value {} <byte 14872> union ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low <byte 14872> {field (By field)} <byte 14872> lbits:32 address Address {} or ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low <byte 14872> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low <byte 14876> union ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High <byte 14876> {field (By field)} <byte 14876> lbits:32 address Address {} or ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High <byte 14876>

ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High <byte 14880> union ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low <byte 14880> {field (By field)} <byte 14880> lbits:32 address Address {} or ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low <byte 14880> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low <byte 14884> union ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High <byte 14884> {field (By field)} <byte 14884> lbits:32 address Address {} or ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High <byte 14884> ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High} endunion ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High {} endunion ncfghi[11] Tachyon DX2+ PCI Non-Configuration Registers High <byte 14888> union gbic_sid[0] GBIC Small Form Factor Serial ID data <byte 14888> ulong[33] gbic_sida GBIC Small Form Factor Serial ID Data As Longwords or gbic_sid[0] GBIC Small Form Factor Serial ID data <byte 14888> {gbic_sid (GBIC Small Form Factor Serial ID Data By Field)} <byte 14888> {base_id (Base ID Fields (Addresses 0-63))} <byte 14888> utiny transceiver0 Transceiver code 0 <byte 14889> utiny connector Connector type <byte 14890> utiny ext_identifier Extended identifier <byte 14891> utiny identifier Identifier, transceiver type <byte 14892> utiny transceiver4 Transceiver code 4 <byte 14893> utiny transceiver3 Transceiver code 3 <byte 14894> utiny transceiver2 Transceiver code 2 <byte 14895> utiny transceiver1 Transceiver code 1 <byte 14896> utiny encoding Encoding <byte 14897> utiny transceiver7 Transceiver code 7 <byte 14898> utiny transceiver6 Transceiver code 6 <byte 14899> utiny transceiver5 Transceiver code 5 <byte 14900>

utiny distance_9u_100m 9u, Distance (100m units) <byte 14901> utiny distance_9u_km 9u, Distance (1000m units) <byte 14902> utiny reserved Reserved <byte 14903> utiny br_nom Baud rate, nominal <byte 14904> utiny reserved1 Reserved <byte 14905> utiny distance_cu CU, Distance (1m units) <byte 14906> utiny distance_60u_10m 60u, Distance (10m units) <byte 14907> utiny distance_50u_10m 50u, Distance (10m units) <byte 14908> utiny[16] vendor_name Vendor name <byte 14924> utiny[3] vendor_oui Vendor OUI <byte 14927> utiny reserved2 Reserved <byte 14928> utiny[16] vendor_pn Vendor part number <byte 14944> utiny[4] vendor_rev Vendor revision <byte 14948> utiny ccid CCID check code (Addresses 0-62) <byte 14949> utiny[3] reserved3 Reserved {} <byte 14952> {extn_id (Extended ID Fields (Addresses 64-95))} <byte 14952> utiny br_min Baud rate, mmin (% lower margin) <byte 14953> utiny br_max Baud rate, max (% upper margin) <byte 14954> utiny[2] options Options <byte 14956> utiny[16] vendor_sn Vendor serial number <byte 14972> utiny[8] date_code Date code <byte 14980> utiny ccex CCEX check code (Addresses 64-94) <byte 14981> utiny[3] reserved Reserved {} <byte 14984> {vend_id (Vendor Specific ID Fields (Addresses 96-127))} <byte 14984> utiny[32] vendor_specific_data {} <byte 15016> {saved (Saved information (not part of SFF Serial Data EEPROM information)} <byte 15016> utiny status Tachyon port diagnostic Check Code test results: 0 = Both check cod es passed, 1 = CCID check code failed (addresses 0-62), 2 = CCEX check code fail ed (addresses 64-94), 3 = Both check codes failed, -1 = Serial ID has not been r ead yet. NOTE: There is no check code for addresses 96-127. <byte 15017>

utiny spare available to use <byte 15018> utiny calc_ccex Saved software calculated CCEX <byte 15019> utiny calc_ccid Saved software calculated CCID {} {} endunion gbic_sid[0] GBIC Small Form Factor Serial ID data <byte 15020> union gbic_sid[1] GBIC Small Form Factor Serial ID data <byte 15020> ulong[33] gbic_sida GBIC Small Form Factor Serial ID Data As Longwords or gbic_sid[1] GBIC Small Form Factor Serial ID data <byte 15020> {gbic_sid (GBIC Small Form Factor Serial ID Data By Field)} <byte 15020> {base_id (Base ID Fields (Addresses 0-63))} <byte 15020> utiny transceiver0 Transceiver code 0 <byte 15021> utiny connector Connector type <byte 15022> utiny ext_identifier Extended identifier <byte 15023> utiny identifier Identifier, transceiver type <byte 15024> utiny transceiver4 Transceiver code 4 <byte 15025> utiny transceiver3 Transceiver code 3 <byte 15026> utiny transceiver2 Transceiver code 2 <byte 15027> utiny transceiver1 Transceiver code 1 <byte 15028> utiny encoding Encoding <byte 15029> utiny transceiver7 Transceiver code 7 <byte 15030> utiny transceiver6 Transceiver code 6 <byte 15031> utiny transceiver5 Transceiver code 5 <byte 15032> utiny distance_9u_100m 9u, Distance (100m units) <byte 15033> utiny distance_9u_km 9u, Distance (1000m units) <byte 15034> utiny reserved Reserved <byte 15035> utiny br_nom Baud rate, nominal <byte 15036> utiny reserved1 Reserved <byte 15037> utiny distance_cu CU, Distance (1m units) <byte 15038> utiny distance_60u_10m 60u, Distance (10m units) <byte 15039> utiny distance_50u_10m 50u, Distance (10m units) <byte 15040> utiny[16] vendor_name Vendor name <byte 15056>

utiny[3] vendor_oui Vendor OUI <byte 15059> utiny reserved2 Reserved <byte 15060> utiny[16] vendor_pn Vendor part number <byte 15076> utiny[4] vendor_rev Vendor revision <byte 15080> utiny ccid CCID check code (Addresses 0-62) <byte 15081> utiny[3] reserved3 Reserved {} <byte 15084> {extn_id (Extended ID Fields (Addresses 64-95))} <byte 15084> utiny br_min Baud rate, mmin (% lower margin) <byte 15085> utiny br_max Baud rate, max (% upper margin) <byte 15086> utiny[2] options Options <byte 15088> utiny[16] vendor_sn Vendor serial number <byte 15104> utiny[8] date_code Date code <byte 15112> utiny ccex CCEX check code (Addresses 64-94) <byte 15113> utiny[3] reserved Reserved {} <byte 15116> {vend_id (Vendor Specific ID Fields (Addresses 96-127))} <byte 15116> utiny[32] vendor_specific_data {} <byte 15148> {saved (Saved information (not part of SFF Serial Data EEPROM information)} <byte 15148> utiny status Tachyon port diagnostic Check Code test results: 0 = Both check cod es passed, 1 = CCID check code failed (addresses 0-62), 2 = CCEX check code fail ed (addresses 64-94), 3 = Both check codes failed, -1 = Serial ID has not been r ead yet. NOTE: There is no check code for addresses 96-127. <byte 15149> utiny spare available to use <byte 15150> utiny calc_ccex Saved software calculated CCEX <byte 15151> utiny calc_ccid Saved software calculated CCID {} {} endunion gbic_sid[1] GBIC Small Form Factor Serial ID data <byte 15152> union gbic_sid[2] GBIC Small Form Factor Serial ID data <byte 15152> ulong[33] gbic_sida GBIC Small Form Factor Serial ID Data As Longwords or gbic_sid[2] GBIC Small Form Factor Serial ID data <byte 15152> {gbic_sid (GBIC Small Form Factor Serial ID Data By Field)} <byte 15152> {base_id (Base ID Fields (Addresses 0-63))} <byte 15152>

utiny transceiver0 Transceiver code 0 <byte 15153> utiny connector Connector type <byte 15154> utiny ext_identifier Extended identifier <byte 15155> utiny identifier Identifier, transceiver type <byte 15156> utiny transceiver4 Transceiver code 4 <byte 15157> utiny transceiver3 Transceiver code 3 <byte 15158> utiny transceiver2 Transceiver code 2 <byte 15159> utiny transceiver1 Transceiver code 1 <byte 15160> utiny encoding Encoding <byte 15161> utiny transceiver7 Transceiver code 7 <byte 15162> utiny transceiver6 Transceiver code 6 <byte 15163> utiny transceiver5 Transceiver code 5 <byte 15164> utiny distance_9u_100m 9u, Distance (100m units) <byte 15165> utiny distance_9u_km 9u, Distance (1000m units) <byte 15166> utiny reserved Reserved <byte 15167> utiny br_nom Baud rate, nominal <byte 15168> utiny reserved1 Reserved <byte 15169> utiny distance_cu CU, Distance (1m units) <byte 15170> utiny distance_60u_10m 60u, Distance (10m units) <byte 15171> utiny distance_50u_10m 50u, Distance (10m units) <byte 15172> utiny[16] vendor_name Vendor name <byte 15188> utiny[3] vendor_oui Vendor OUI <byte 15191> utiny reserved2 Reserved <byte 15192> utiny[16] vendor_pn Vendor part number <byte 15208> utiny[4] vendor_rev Vendor revision <byte 15212> utiny ccid CCID check code (Addresses 0-62) <byte 15213> utiny[3] reserved3 Reserved {} <byte 15216> {extn_id (Extended ID Fields (Addresses 64-95))} <byte 15216> utiny br_min Baud rate, mmin (% lower margin) <byte 15217> utiny br_max Baud rate, max (% upper margin)

<byte 15218> utiny[2] options Options <byte 15220> utiny[16] vendor_sn Vendor serial number <byte 15236> utiny[8] date_code Date code <byte 15244> utiny ccex CCEX check code (Addresses 64-94) <byte 15245> utiny[3] reserved Reserved {} <byte 15248> {vend_id (Vendor Specific ID Fields (Addresses 96-127))} <byte 15248> utiny[32] vendor_specific_data {} <byte 15280> {saved (Saved information (not part of SFF Serial Data EEPROM information)} <byte 15280> utiny status Tachyon port diagnostic Check Code test results: 0 = Both check cod es passed, 1 = CCID check code failed (addresses 0-62), 2 = CCEX check code fail ed (addresses 64-94), 3 = Both check codes failed, -1 = Serial ID has not been r ead yet. NOTE: There is no check code for addresses 96-127. <byte 15281> utiny spare available to use <byte 15282> utiny calc_ccex Saved software calculated CCEX <byte 15283> utiny calc_ccid Saved software calculated CCID {} {} endunion gbic_sid[2] GBIC Small Form Factor Serial ID data <byte 15284> union gbic_sid[3] GBIC Small Form Factor Serial ID data <byte 15284> ulong[33] gbic_sida GBIC Small Form Factor Serial ID Data As Longwords or gbic_sid[3] GBIC Small Form Factor Serial ID data <byte 15284> {gbic_sid (GBIC Small Form Factor Serial ID Data By Field)} <byte 15284> {base_id (Base ID Fields (Addresses 0-63))} <byte 15284> utiny transceiver0 Transceiver code 0 <byte 15285> utiny connector Connector type <byte 15286> utiny ext_identifier Extended identifier <byte 15287> utiny identifier Identifier, transceiver type <byte 15288> utiny transceiver4 Transceiver code 4 <byte 15289> utiny transceiver3 Transceiver code 3 <byte 15290> utiny transceiver2 Transceiver code 2 <byte 15291> utiny transceiver1 Transceiver code 1 <byte 15292> utiny encoding Encoding <byte 15293>

utiny transceiver7 Transceiver code 7 <byte 15294> utiny transceiver6 Transceiver code 6 <byte 15295> utiny transceiver5 Transceiver code 5 <byte 15296> utiny distance_9u_100m 9u, Distance (100m units) <byte 15297> utiny distance_9u_km 9u, Distance (1000m units) <byte 15298> utiny reserved Reserved <byte 15299> utiny br_nom Baud rate, nominal <byte 15300> utiny reserved1 Reserved <byte 15301> utiny distance_cu CU, Distance (1m units) <byte 15302> utiny distance_60u_10m 60u, Distance (10m units) <byte 15303> utiny distance_50u_10m 50u, Distance (10m units) <byte 15304> utiny[16] vendor_name Vendor name <byte 15320> utiny[3] vendor_oui Vendor OUI <byte 15323> utiny reserved2 Reserved <byte 15324> utiny[16] vendor_pn Vendor part number <byte 15340> utiny[4] vendor_rev Vendor revision <byte 15344> utiny ccid CCID check code (Addresses 0-62) <byte 15345> utiny[3] reserved3 Reserved {} <byte 15348> {extn_id (Extended ID Fields (Addresses 64-95))} <byte 15348> utiny br_min Baud rate, mmin (% lower margin) <byte 15349> utiny br_max Baud rate, max (% upper margin) <byte 15350> utiny[2] options Options <byte 15352> utiny[16] vendor_sn Vendor serial number <byte 15368> utiny[8] date_code Date code <byte 15376> utiny ccex CCEX check code (Addresses 64-94) <byte 15377> utiny[3] reserved Reserved {} <byte 15380> {vend_id (Vendor Specific ID Fields (Addresses 96-127))} <byte 15380> utiny[32] vendor_specific_data {} <byte 15412> {saved (Saved information (not part of SFF Serial Data EEPROM information)}

<byte 15412> utiny status Tachyon port diagnostic Check Code test results: 0 = Both check cod es passed, 1 = CCID check code failed (addresses 0-62), 2 = CCEX check code fail ed (addresses 64-94), 3 = Both check codes failed, -1 = Serial ID has not been r ead yet. NOTE: There is no check code for addresses 96-127. <byte 15413> utiny spare available to use <byte 15414> utiny calc_ccex Saved software calculated CCEX <byte 15415> utiny calc_ccid Saved software calculated CCID {} {} endunion gbic_sid[3] GBIC Small Form Factor Serial ID data <byte 15416> union gbic_sid[4] GBIC Small Form Factor Serial ID data <byte 15416> ulong[33] gbic_sida GBIC Small Form Factor Serial ID Data As Longwords or gbic_sid[4] GBIC Small Form Factor Serial ID data <byte 15416> {gbic_sid (GBIC Small Form Factor Serial ID Data By Field)} <byte 15416> {base_id (Base ID Fields (Addresses 0-63))} <byte 15416> utiny transceiver0 Transceiver code 0 <byte 15417> utiny connector Connector type <byte 15418> utiny ext_identifier Extended identifier <byte 15419> utiny identifier Identifier, transceiver type <byte 15420> utiny transceiver4 Transceiver code 4 <byte 15421> utiny transceiver3 Transceiver code 3 <byte 15422> utiny transceiver2 Transceiver code 2 <byte 15423> utiny transceiver1 Transceiver code 1 <byte 15424> utiny encoding Encoding <byte 15425> utiny transceiver7 Transceiver code 7 <byte 15426> utiny transceiver6 Transceiver code 6 <byte 15427> utiny transceiver5 Transceiver code 5 <byte 15428> utiny distance_9u_100m 9u, Distance (100m units) <byte 15429> utiny distance_9u_km 9u, Distance (1000m units) <byte 15430> utiny reserved Reserved <byte 15431> utiny br_nom Baud rate, nominal <byte 15432> utiny reserved1 Reserved <byte 15433> utiny distance_cu CU, Distance (1m units) <byte 15434>

utiny distance_60u_10m 60u, Distance (10m units) <byte 15435> utiny distance_50u_10m 50u, Distance (10m units) <byte 15436> utiny[16] vendor_name Vendor name <byte 15452> utiny[3] vendor_oui Vendor OUI <byte 15455> utiny reserved2 Reserved <byte 15456> utiny[16] vendor_pn Vendor part number <byte 15472> utiny[4] vendor_rev Vendor revision <byte 15476> utiny ccid CCID check code (Addresses 0-62) <byte 15477> utiny[3] reserved3 Reserved {} <byte 15480> {extn_id (Extended ID Fields (Addresses 64-95))} <byte 15480> utiny br_min Baud rate, mmin (% lower margin) <byte 15481> utiny br_max Baud rate, max (% upper margin) <byte 15482> utiny[2] options Options <byte 15484> utiny[16] vendor_sn Vendor serial number <byte 15500> utiny[8] date_code Date code <byte 15508> utiny ccex CCEX check code (Addresses 64-94) <byte 15509> utiny[3] reserved Reserved {} <byte 15512> {vend_id (Vendor Specific ID Fields (Addresses 96-127))} <byte 15512> utiny[32] vendor_specific_data {} <byte 15544> {saved (Saved information (not part of SFF Serial Data EEPROM information)} <byte 15544> utiny status Tachyon port diagnostic Check Code test results: 0 = Both check cod es passed, 1 = CCID check code failed (addresses 0-62), 2 = CCEX check code fail ed (addresses 64-94), 3 = Both check codes failed, -1 = Serial ID has not been r ead yet. NOTE: There is no check code for addresses 96-127. <byte 15545> utiny spare available to use <byte 15546> utiny calc_ccex Saved software calculated CCEX <byte 15547> utiny calc_ccid Saved software calculated CCID {} {} endunion gbic_sid[4] GBIC Small Form Factor Serial ID data <byte 15548> union gbic_sid[5] GBIC Small Form Factor Serial ID data <byte 15548> ulong[33] gbic_sida GBIC Small Form Factor Serial ID Data As Longwords

or gbic_sid[5] GBIC Small Form Factor Serial ID data <byte 15548> {gbic_sid (GBIC Small Form Factor Serial ID Data By Field)} <byte 15548> {base_id (Base ID Fields (Addresses 0-63))} <byte 15548> utiny transceiver0 Transceiver code 0 <byte 15549> utiny connector Connector type <byte 15550> utiny ext_identifier Extended identifier <byte 15551> utiny identifier Identifier, transceiver type <byte 15552> utiny transceiver4 Transceiver code 4 <byte 15553> utiny transceiver3 Transceiver code 3 <byte 15554> utiny transceiver2 Transceiver code 2 <byte 15555> utiny transceiver1 Transceiver code 1 <byte 15556> utiny encoding Encoding <byte 15557> utiny transceiver7 Transceiver code 7 <byte 15558> utiny transceiver6 Transceiver code 6 <byte 15559> utiny transceiver5 Transceiver code 5 <byte 15560> utiny distance_9u_100m 9u, Distance (100m units) <byte 15561> utiny distance_9u_km 9u, Distance (1000m units) <byte 15562> utiny reserved Reserved <byte 15563> utiny br_nom Baud rate, nominal <byte 15564> utiny reserved1 Reserved <byte 15565> utiny distance_cu CU, Distance (1m units) <byte 15566> utiny distance_60u_10m 60u, Distance (10m units) <byte 15567> utiny distance_50u_10m 50u, Distance (10m units) <byte 15568> utiny[16] vendor_name Vendor name <byte 15584> utiny[3] vendor_oui Vendor OUI <byte 15587> utiny reserved2 Reserved <byte 15588> utiny[16] vendor_pn Vendor part number <byte 15604> utiny[4] vendor_rev Vendor revision <byte 15608> utiny ccid CCID check code (Addresses 0-62) <byte 15609> utiny[3] reserved3 Reserved {}

<byte 15612> {extn_id (Extended ID Fields (Addresses 64-95))} <byte 15612> utiny br_min Baud rate, mmin (% lower margin) <byte 15613> utiny br_max Baud rate, max (% upper margin) <byte 15614> utiny[2] options Options <byte 15616> utiny[16] vendor_sn Vendor serial number <byte 15632> utiny[8] date_code Date code <byte 15640> utiny ccex CCEX check code (Addresses 64-94) <byte 15641> utiny[3] reserved Reserved {} <byte 15644> {vend_id (Vendor Specific ID Fields (Addresses 96-127))} <byte 15644> utiny[32] vendor_specific_data {} <byte 15676> {saved (Saved information (not part of SFF Serial Data EEPROM information)} <byte 15676> utiny status Tachyon port diagnostic Check Code test results: 0 = Both check cod es passed, 1 = CCID check code failed (addresses 0-62), 2 = CCEX check code fail ed (addresses 64-94), 3 = Both check codes failed, -1 = Serial ID has not been r ead yet. NOTE: There is no check code for addresses 96-127. <byte 15677> utiny spare available to use <byte 15678> utiny calc_ccex Saved software calculated CCEX <byte 15679> utiny calc_ccid Saved software calculated CCID {} {} endunion gbic_sid[5] GBIC Small Form Factor Serial ID data <byte 15680> union gbic_sid[6] GBIC Small Form Factor Serial ID data <byte 15680> ulong[33] gbic_sida GBIC Small Form Factor Serial ID Data As Longwords or gbic_sid[6] GBIC Small Form Factor Serial ID data <byte 15680> {gbic_sid (GBIC Small Form Factor Serial ID Data By Field)} <byte 15680> {base_id (Base ID Fields (Addresses 0-63))} <byte 15680> utiny transceiver0 Transceiver code 0 <byte 15681> utiny connector Connector type <byte 15682> utiny ext_identifier Extended identifier <byte 15683> utiny identifier Identifier, transceiver type <byte 15684> utiny transceiver4 Transceiver code 4 <byte 15685> utiny transceiver3 Transceiver code 3 <byte 15686>

utiny transceiver2 Transceiver code 2 <byte 15687> utiny transceiver1 Transceiver code 1 <byte 15688> utiny encoding Encoding <byte 15689> utiny transceiver7 Transceiver code 7 <byte 15690> utiny transceiver6 Transceiver code 6 <byte 15691> utiny transceiver5 Transceiver code 5 <byte 15692> utiny distance_9u_100m 9u, Distance (100m units) <byte 15693> utiny distance_9u_km 9u, Distance (1000m units) <byte 15694> utiny reserved Reserved <byte 15695> utiny br_nom Baud rate, nominal <byte 15696> utiny reserved1 Reserved <byte 15697> utiny distance_cu CU, Distance (1m units) <byte 15698> utiny distance_60u_10m 60u, Distance (10m units) <byte 15699> utiny distance_50u_10m 50u, Distance (10m units) <byte 15700> utiny[16] vendor_name Vendor name <byte 15716> utiny[3] vendor_oui Vendor OUI <byte 15719> utiny reserved2 Reserved <byte 15720> utiny[16] vendor_pn Vendor part number <byte 15736> utiny[4] vendor_rev Vendor revision <byte 15740> utiny ccid CCID check code (Addresses 0-62) <byte 15741> utiny[3] reserved3 Reserved {} <byte 15744> {extn_id (Extended ID Fields (Addresses 64-95))} <byte 15744> utiny br_min Baud rate, mmin (% lower margin) <byte 15745> utiny br_max Baud rate, max (% upper margin) <byte 15746> utiny[2] options Options <byte 15748> utiny[16] vendor_sn Vendor serial number <byte 15764> utiny[8] date_code Date code <byte 15772> utiny ccex CCEX check code (Addresses 64-94) <byte 15773> utiny[3] reserved Reserved {} <byte 15776>

{vend_id (Vendor Specific ID Fields (Addresses 96-127))} <byte 15776> utiny[32] vendor_specific_data {} <byte 15808> {saved (Saved information (not part of SFF Serial Data EEPROM information)} <byte 15808> utiny status Tachyon port diagnostic Check Code test results: 0 = Both check cod es passed, 1 = CCID check code failed (addresses 0-62), 2 = CCEX check code fail ed (addresses 64-94), 3 = Both check codes failed, -1 = Serial ID has not been r ead yet. NOTE: There is no check code for addresses 96-127. <byte 15809> utiny spare available to use <byte 15810> utiny calc_ccex Saved software calculated CCEX <byte 15811> utiny calc_ccid Saved software calculated CCID {} {} endunion gbic_sid[6] GBIC Small Form Factor Serial ID data <byte 15812> union gbic_sid[7] GBIC Small Form Factor Serial ID data <byte 15812> ulong[33] gbic_sida GBIC Small Form Factor Serial ID Data As Longwords or gbic_sid[7] GBIC Small Form Factor Serial ID data <byte 15812> {gbic_sid (GBIC Small Form Factor Serial ID Data By Field)} <byte 15812> {base_id (Base ID Fields (Addresses 0-63))} <byte 15812> utiny transceiver0 Transceiver code 0 <byte 15813> utiny connector Connector type <byte 15814> utiny ext_identifier Extended identifier <byte 15815> utiny identifier Identifier, transceiver type <byte 15816> utiny transceiver4 Transceiver code 4 <byte 15817> utiny transceiver3 Transceiver code 3 <byte 15818> utiny transceiver2 Transceiver code 2 <byte 15819> utiny transceiver1 Transceiver code 1 <byte 15820> utiny encoding Encoding <byte 15821> utiny transceiver7 Transceiver code 7 <byte 15822> utiny transceiver6 Transceiver code 6 <byte 15823> utiny transceiver5 Transceiver code 5 <byte 15824> utiny distance_9u_100m 9u, Distance (100m units) <byte 15825> utiny distance_9u_km 9u, Distance (1000m units) <byte 15826> utiny reserved Reserved <byte 15827>

utiny br_nom Baud rate, nominal <byte 15828> utiny reserved1 Reserved <byte 15829> utiny distance_cu CU, Distance (1m units) <byte 15830> utiny distance_60u_10m 60u, Distance (10m units) <byte 15831> utiny distance_50u_10m 50u, Distance (10m units) <byte 15832> utiny[16] vendor_name Vendor name <byte 15848> utiny[3] vendor_oui Vendor OUI <byte 15851> utiny reserved2 Reserved <byte 15852> utiny[16] vendor_pn Vendor part number <byte 15868> utiny[4] vendor_rev Vendor revision <byte 15872> utiny ccid CCID check code (Addresses 0-62) <byte 15873> utiny[3] reserved3 Reserved {} <byte 15876> {extn_id (Extended ID Fields (Addresses 64-95))} <byte 15876> utiny br_min Baud rate, mmin (% lower margin) <byte 15877> utiny br_max Baud rate, max (% upper margin) <byte 15878> utiny[2] options Options <byte 15880> utiny[16] vendor_sn Vendor serial number <byte 15896> utiny[8] date_code Date code <byte 15904> utiny ccex CCEX check code (Addresses 64-94) <byte 15905> utiny[3] reserved Reserved {} <byte 15908> {vend_id (Vendor Specific ID Fields (Addresses 96-127))} <byte 15908> utiny[32] vendor_specific_data {} <byte 15940> {saved (Saved information (not part of SFF Serial Data EEPROM information)} <byte 15940> utiny status Tachyon port diagnostic Check Code test results: 0 = Both check cod es passed, 1 = CCID check code failed (addresses 0-62), 2 = CCEX check code fail ed (addresses 64-94), 3 = Both check codes failed, -1 = Serial ID has not been r ead yet. NOTE: There is no check code for addresses 96-127. <byte 15941> utiny spare available to use <byte 15942> utiny calc_ccex Saved software calculated CCEX <byte 15943> utiny calc_ccid Saved software calculated CCID {}

{} endunion gbic_sid[7] GBIC Small Form Factor Serial ID data <byte 15944> union gbic_sid[8] GBIC Small Form Factor Serial ID data <byte 15944> ulong[33] gbic_sida GBIC Small Form Factor Serial ID Data As Longwords or gbic_sid[8] GBIC Small Form Factor Serial ID data <byte 15944> {gbic_sid (GBIC Small Form Factor Serial ID Data By Field)} <byte 15944> {base_id (Base ID Fields (Addresses 0-63))} <byte 15944> utiny transceiver0 Transceiver code 0 <byte 15945> utiny connector Connector type <byte 15946> utiny ext_identifier Extended identifier <byte 15947> utiny identifier Identifier, transceiver type <byte 15948> utiny transceiver4 Transceiver code 4 <byte 15949> utiny transceiver3 Transceiver code 3 <byte 15950> utiny transceiver2 Transceiver code 2 <byte 15951> utiny transceiver1 Transceiver code 1 <byte 15952> utiny encoding Encoding <byte 15953> utiny transceiver7 Transceiver code 7 <byte 15954> utiny transceiver6 Transceiver code 6 <byte 15955> utiny transceiver5 Transceiver code 5 <byte 15956> utiny distance_9u_100m 9u, Distance (100m units) <byte 15957> utiny distance_9u_km 9u, Distance (1000m units) <byte 15958> utiny reserved Reserved <byte 15959> utiny br_nom Baud rate, nominal <byte 15960> utiny reserved1 Reserved <byte 15961> utiny distance_cu CU, Distance (1m units) <byte 15962> utiny distance_60u_10m 60u, Distance (10m units) <byte 15963> utiny distance_50u_10m 50u, Distance (10m units) <byte 15964> utiny[16] vendor_name Vendor name <byte 15980> utiny[3] vendor_oui Vendor OUI <byte 15983> utiny reserved2 Reserved <byte 15984> utiny[16] vendor_pn Vendor part number <byte 16000>

utiny[4] vendor_rev Vendor revision <byte 16004> utiny ccid CCID check code (Addresses 0-62) <byte 16005> utiny[3] reserved3 Reserved {} <byte 16008> {extn_id (Extended ID Fields (Addresses 64-95))} <byte 16008> utiny br_min Baud rate, mmin (% lower margin) <byte 16009> utiny br_max Baud rate, max (% upper margin) <byte 16010> utiny[2] options Options <byte 16012> utiny[16] vendor_sn Vendor serial number <byte 16028> utiny[8] date_code Date code <byte 16036> utiny ccex CCEX check code (Addresses 64-94) <byte 16037> utiny[3] reserved Reserved {} <byte 16040> {vend_id (Vendor Specific ID Fields (Addresses 96-127))} <byte 16040> utiny[32] vendor_specific_data {} <byte 16072> {saved (Saved information (not part of SFF Serial Data EEPROM information)} <byte 16072> utiny status Tachyon port diagnostic Check Code test results: 0 = Both check cod es passed, 1 = CCID check code failed (addresses 0-62), 2 = CCEX check code fail ed (addresses 64-94), 3 = Both check codes failed, -1 = Serial ID has not been r ead yet. NOTE: There is no check code for addresses 96-127. <byte 16073> utiny spare available to use <byte 16074> utiny calc_ccex Saved software calculated CCEX <byte 16075> utiny calc_ccid Saved software calculated CCID {} {} endunion gbic_sid[8] GBIC Small Form Factor Serial ID data <byte 16076> union gbic_sid[9] GBIC Small Form Factor Serial ID data <byte 16076> ulong[33] gbic_sida GBIC Small Form Factor Serial ID Data As Longwords or gbic_sid[9] GBIC Small Form Factor Serial ID data <byte 16076> {gbic_sid (GBIC Small Form Factor Serial ID Data By Field)} <byte 16076> {base_id (Base ID Fields (Addresses 0-63))} <byte 16076> utiny transceiver0 Transceiver code 0 <byte 16077> utiny connector Connector type <byte 16078> utiny ext_identifier Extended identifier <byte 16079>

utiny identifier Identifier, transceiver type <byte 16080> utiny transceiver4 Transceiver code 4 <byte 16081> utiny transceiver3 Transceiver code 3 <byte 16082> utiny transceiver2 Transceiver code 2 <byte 16083> utiny transceiver1 Transceiver code 1 <byte 16084> utiny encoding Encoding <byte 16085> utiny transceiver7 Transceiver code 7 <byte 16086> utiny transceiver6 Transceiver code 6 <byte 16087> utiny transceiver5 Transceiver code 5 <byte 16088> utiny distance_9u_100m 9u, Distance (100m units) <byte 16089> utiny distance_9u_km 9u, Distance (1000m units) <byte 16090> utiny reserved Reserved <byte 16091> utiny br_nom Baud rate, nominal <byte 16092> utiny reserved1 Reserved <byte 16093> utiny distance_cu CU, Distance (1m units) <byte 16094> utiny distance_60u_10m 60u, Distance (10m units) <byte 16095> utiny distance_50u_10m 50u, Distance (10m units) <byte 16096> utiny[16] vendor_name Vendor name <byte 16112> utiny[3] vendor_oui Vendor OUI <byte 16115> utiny reserved2 Reserved <byte 16116> utiny[16] vendor_pn Vendor part number <byte 16132> utiny[4] vendor_rev Vendor revision <byte 16136> utiny ccid CCID check code (Addresses 0-62) <byte 16137> utiny[3] reserved3 Reserved {} <byte 16140> {extn_id (Extended ID Fields (Addresses 64-95))} <byte 16140> utiny br_min Baud rate, mmin (% lower margin) <byte 16141> utiny br_max Baud rate, max (% upper margin) <byte 16142> utiny[2] options Options <byte 16144> utiny[16] vendor_sn Vendor serial number <byte 16160> utiny[8] date_code Date code

<byte 16168> utiny ccex CCEX check code (Addresses 64-94) <byte 16169> utiny[3] reserved Reserved {} <byte 16172> {vend_id (Vendor Specific ID Fields (Addresses 96-127))} <byte 16172> utiny[32] vendor_specific_data {} <byte 16204> {saved (Saved information (not part of SFF Serial Data EEPROM information)} <byte 16204> utiny status Tachyon port diagnostic Check Code test results: 0 = Both check cod es passed, 1 = CCID check code failed (addresses 0-62), 2 = CCEX check code fail ed (addresses 64-94), 3 = Both check codes failed, -1 = Serial ID has not been r ead yet. NOTE: There is no check code for addresses 96-127. <byte 16205> utiny spare available to use <byte 16206> utiny calc_ccex Saved software calculated CCEX <byte 16207> utiny calc_ccid Saved software calculated CCID {} {} endunion gbic_sid[9] GBIC Small Form Factor Serial ID data <byte 16208> union gbic_sid[10] GBIC Small Form Factor Serial ID data <byte 16208> ulong[33] gbic_sida GBIC Small Form Factor Serial ID Data As Longwords or gbic_sid[10] GBIC Small Form Factor Serial ID data <byte 16208> {gbic_sid (GBIC Small Form Factor Serial ID Data By Field)} <byte 16208> {base_id (Base ID Fields (Addresses 0-63))} <byte 16208> utiny transceiver0 Transceiver code 0 <byte 16209> utiny connector Connector type <byte 16210> utiny ext_identifier Extended identifier <byte 16211> utiny identifier Identifier, transceiver type <byte 16212> utiny transceiver4 Transceiver code 4 <byte 16213> utiny transceiver3 Transceiver code 3 <byte 16214> utiny transceiver2 Transceiver code 2 <byte 16215> utiny transceiver1 Transceiver code 1 <byte 16216> utiny encoding Encoding <byte 16217> utiny transceiver7 Transceiver code 7 <byte 16218> utiny transceiver6 Transceiver code 6 <byte 16219> utiny transceiver5 Transceiver code 5 <byte 16220>

utiny distance_9u_100m 9u, Distance (100m units) <byte 16221> utiny distance_9u_km 9u, Distance (1000m units) <byte 16222> utiny reserved Reserved <byte 16223> utiny br_nom Baud rate, nominal <byte 16224> utiny reserved1 Reserved <byte 16225> utiny distance_cu CU, Distance (1m units) <byte 16226> utiny distance_60u_10m 60u, Distance (10m units) <byte 16227> utiny distance_50u_10m 50u, Distance (10m units) <byte 16228> utiny[16] vendor_name Vendor name <byte 16244> utiny[3] vendor_oui Vendor OUI <byte 16247> utiny reserved2 Reserved <byte 16248> utiny[16] vendor_pn Vendor part number <byte 16264> utiny[4] vendor_rev Vendor revision <byte 16268> utiny ccid CCID check code (Addresses 0-62) <byte 16269> utiny[3] reserved3 Reserved {} <byte 16272> {extn_id (Extended ID Fields (Addresses 64-95))} <byte 16272> utiny br_min Baud rate, mmin (% lower margin) <byte 16273> utiny br_max Baud rate, max (% upper margin) <byte 16274> utiny[2] options Options <byte 16276> utiny[16] vendor_sn Vendor serial number <byte 16292> utiny[8] date_code Date code <byte 16300> utiny ccex CCEX check code (Addresses 64-94) <byte 16301> utiny[3] reserved Reserved {} <byte 16304> {vend_id (Vendor Specific ID Fields (Addresses 96-127))} <byte 16304> utiny[32] vendor_specific_data {} <byte 16336> {saved (Saved information (not part of SFF Serial Data EEPROM information)} <byte 16336> utiny status Tachyon port diagnostic Check Code test results: 0 = Both check cod es passed, 1 = CCID check code failed (addresses 0-62), 2 = CCEX check code fail ed (addresses 64-94), 3 = Both check codes failed, -1 = Serial ID has not been r ead yet. NOTE: There is no check code for addresses 96-127. <byte 16337>

utiny spare available to use <byte 16338> utiny calc_ccex Saved software calculated CCEX <byte 16339> utiny calc_ccid Saved software calculated CCID {} {} endunion gbic_sid[10] GBIC Small Form Factor Serial ID data <byte 16340> union gbic_sid[11] GBIC Small Form Factor Serial ID data <byte 16340> ulong[33] gbic_sida GBIC Small Form Factor Serial ID Data As Longwords or gbic_sid[11] GBIC Small Form Factor Serial ID data <byte 16340> {gbic_sid (GBIC Small Form Factor Serial ID Data By Field)} <byte 16340> {base_id (Base ID Fields (Addresses 0-63))} <byte 16340> utiny transceiver0 Transceiver code 0 <byte 16341> utiny connector Connector type <byte 16342> utiny ext_identifier Extended identifier <byte 16343> utiny identifier Identifier, transceiver type <byte 16344> utiny transceiver4 Transceiver code 4 <byte 16345> utiny transceiver3 Transceiver code 3 <byte 16346> utiny transceiver2 Transceiver code 2 <byte 16347> utiny transceiver1 Transceiver code 1 <byte 16348> utiny encoding Encoding <byte 16349> utiny transceiver7 Transceiver code 7 <byte 16350> utiny transceiver6 Transceiver code 6 <byte 16351> utiny transceiver5 Transceiver code 5 <byte 16352> utiny distance_9u_100m 9u, Distance (100m units) <byte 16353> utiny distance_9u_km 9u, Distance (1000m units) <byte 16354> utiny reserved Reserved <byte 16355> utiny br_nom Baud rate, nominal <byte 16356> utiny reserved1 Reserved <byte 16357> utiny distance_cu CU, Distance (1m units) <byte 16358> utiny distance_60u_10m 60u, Distance (10m units) <byte 16359> utiny distance_50u_10m 50u, Distance (10m units) <byte 16360> utiny[16] vendor_name Vendor name <byte 16376>

utiny[3] vendor_oui Vendor OUI <byte 16379> utiny reserved2 Reserved <byte 16380> utiny[16] vendor_pn Vendor part number <byte 16396> utiny[4] vendor_rev Vendor revision <byte 16400> utiny ccid CCID check code (Addresses 0-62) <byte 16401> utiny[3] reserved3 Reserved {} <byte 16404> {extn_id (Extended ID Fields (Addresses 64-95))} <byte 16404> utiny br_min Baud rate, mmin (% lower margin) <byte 16405> utiny br_max Baud rate, max (% upper margin) <byte 16406> utiny[2] options Options <byte 16408> utiny[16] vendor_sn Vendor serial number <byte 16424> utiny[8] date_code Date code <byte 16432> utiny ccex CCEX check code (Addresses 64-94) <byte 16433> utiny[3] reserved Reserved {} <byte 16436> {vend_id (Vendor Specific ID Fields (Addresses 96-127))} <byte 16436> utiny[32] vendor_specific_data {} <byte 16468> {saved (Saved information (not part of SFF Serial Data EEPROM information)} <byte 16468> utiny status Tachyon port diagnostic Check Code test results: 0 = Both check cod es passed, 1 = CCID check code failed (addresses 0-62), 2 = CCEX check code fail ed (addresses 64-94), 3 = Both check codes failed, -1 = Serial ID has not been r ead yet. NOTE: There is no check code for addresses 96-127. <byte 16469> utiny spare available to use <byte 16470> utiny calc_ccex Saved software calculated CCEX <byte 16471> utiny calc_ccid Saved software calculated CCID {} {} endunion gbic_sid[11] GBIC Small Form Factor Serial ID data {} {} <byte 16472> {recursive_event[0] (Recursive entry array)} <byte 16472> ulong tt Trap type <byte 16476> ulong tc Termination code <byte 16480> ulong srr0 SRR0 register

<byte 16484> ulong srr1 SRR1 register <byte 16488> ulong cr CR register <byte 16492> ulong xer XER register <byte 16496> ulong esr ESR register <byte 16500> ulong ctr CTR register <byte 16504> ulong lr LR register <byte 16508> ulong exception Exception code <byte 16512> ulong count Exception count {} <byte 16516> {recursive_event[1] (Recursive entry array)} <byte 16516> ulong tt Trap type <byte 16520> ulong tc Termination code <byte 16524> ulong srr0 SRR0 register <byte 16528> ulong srr1 SRR1 register <byte 16532> ulong cr CR register <byte 16536> ulong xer XER register <byte 16540> ulong esr ESR register <byte 16544> ulong ctr CTR register <byte 16548> ulong lr LR register <byte 16552> ulong exception Exception code <byte 16556> ulong count Exception count {} <byte 16560> {recursive_event[2] (Recursive entry array)} <byte 16560> ulong tt Trap type <byte 16564> ulong tc Termination code <byte 16568> ulong srr0 SRR0 register <byte 16572> ulong srr1 SRR1 register <byte 16576> ulong cr CR register <byte 16580> ulong xer XER register <byte 16584> ulong esr ESR register <byte 16588> ulong ctr CTR register

<byte 16592> ulong lr LR register <byte 16596> ulong exception Exception code <byte 16600> ulong count Exception count {} <byte 16604> {recursive_event[3] (Recursive entry array)} <byte 16604> ulong tt Trap type <byte 16608> ulong tc Termination code <byte 16612> ulong srr0 SRR0 register <byte 16616> ulong srr1 SRR1 register <byte 16620> ulong cr CR register <byte 16624> ulong xer XER register <byte 16628> ulong esr ESR register <byte 16632> ulong ctr CTR register <byte 16636> ulong lr LR register <byte 16640> ulong exception Exception code <byte 16644> ulong count Exception count {} <byte 16648> {recursive_event[4] (Recursive entry array)} <byte 16648> ulong tt Trap type <byte 16652> ulong tc Termination code <byte 16656> ulong srr0 SRR0 register <byte 16660> ulong srr1 SRR1 register <byte 16664> ulong cr CR register <byte 16668> ulong xer XER register <byte 16672> ulong esr ESR register <byte 16676> ulong ctr CTR register <byte 16680> ulong lr LR register <byte 16684> ulong exception Exception code <byte 16688> ulong count Exception count {} <byte 16692> {recursive_event[5] (Recursive entry array)} <byte 16692>

ulong tt Trap type <byte 16696> ulong tc Termination code <byte 16700> ulong srr0 SRR0 register <byte 16704> ulong srr1 SRR1 register <byte 16708> ulong cr CR register <byte 16712> ulong xer XER register <byte 16716> ulong esr ESR register <byte 16720> ulong ctr CTR register <byte 16724> ulong lr LR register <byte 16728> ulong exception Exception code <byte 16732> ulong count Exception count {} <byte 16736> {recursive_event[6] (Recursive entry array)} <byte 16736> ulong tt Trap type <byte 16740> ulong tc Termination code <byte 16744> ulong srr0 SRR0 register <byte 16748> ulong srr1 SRR1 register <byte 16752> ulong cr CR register <byte 16756> ulong xer XER register <byte 16760> ulong esr ESR register <byte 16764> ulong ctr CTR register <byte 16768> ulong lr LR register <byte 16772> ulong exception Exception code <byte 16776> ulong count Exception count {} <byte 16780> {recursive_event[7] (Recursive entry array)} <byte 16780> ulong tt Trap type <byte 16784> ulong tc Termination code <byte 16788> ulong srr0 SRR0 register <byte 16792> ulong srr1 SRR1 register <byte 16796> ulong cr CR register <byte 16800>

ulong xer XER register <byte 16804> ulong esr ESR register <byte 16808> ulong ctr CTR register <byte 16812> ulong lr LR register <byte 16816> ulong exception Exception code <byte 16820> ulong count Exception count {} <byte 16824> {recursive_event[8] (Recursive entry array)} <byte 16824> ulong tt Trap type <byte 16828> ulong tc Termination code <byte 16832> ulong srr0 SRR0 register <byte 16836> ulong srr1 SRR1 register <byte 16840> ulong cr CR register <byte 16844> ulong xer XER register <byte 16848> ulong esr ESR register <byte 16852> ulong ctr CTR register <byte 16856> ulong lr LR register <byte 16860> ulong exception Exception code <byte 16864> ulong count Exception count {} <byte 16868> {recursive_event[9] (Recursive entry array)} <byte 16868> ulong tt Trap type <byte 16872> ulong tc Termination code <byte 16876> ulong srr0 SRR0 register <byte 16880> ulong srr1 SRR1 register <byte 16884> ulong cr CR register <byte 16888> ulong xer XER register <byte 16892> ulong esr ESR register <byte 16896> ulong ctr CTR register <byte 16900> ulong lr LR register <byte 16904> ulong exception Exception code <byte 16908>

ulong count Exception count {} <byte 16912> {recursive_event[10] (Recursive entry array)} <byte 16912> ulong tt Trap type <byte 16916> ulong tc Termination code <byte 16920> ulong srr0 SRR0 register <byte 16924> ulong srr1 SRR1 register <byte 16928> ulong cr CR register <byte 16932> ulong xer XER register <byte 16936> ulong esr ESR register <byte 16940> ulong ctr CTR register <byte 16944> ulong lr LR register <byte 16948> ulong exception Exception code <byte 16952> ulong count Exception count {} <byte 16956> {recursive_event[11] (Recursive entry array)} <byte 16956> ulong tt Trap type <byte 16960> ulong tc Termination code <byte 16964> ulong srr0 SRR0 register <byte 16968> ulong srr1 SRR1 register <byte 16972> ulong cr CR register <byte 16976> ulong xer XER register <byte 16980> ulong esr ESR register <byte 16984> ulong ctr CTR register <byte 16988> ulong lr LR register <byte 16992> ulong exception Exception code <byte 16996> ulong count Exception count {} <byte 17000> {recursive_event[12] (Recursive entry array)} <byte 17000> ulong tt Trap type <byte 17004> ulong tc Termination code <byte 17008> ulong srr0 SRR0 register

<byte 17012> ulong srr1 SRR1 register <byte 17016> ulong cr CR register <byte 17020> ulong xer XER register <byte 17024> ulong esr ESR register <byte 17028> ulong ctr CTR register <byte 17032> ulong lr LR register <byte 17036> ulong exception Exception code <byte 17040> ulong count Exception count {} <byte 17044> {recursive_event[13] (Recursive entry array)} <byte 17044> ulong tt Trap type <byte 17048> ulong tc Termination code <byte 17052> ulong srr0 SRR0 register <byte 17056> ulong srr1 SRR1 register <byte 17060> ulong cr CR register <byte 17064> ulong xer XER register <byte 17068> ulong esr ESR register <byte 17072> ulong ctr CTR register <byte 17076> ulong lr LR register <byte 17080> ulong exception Exception code <byte 17084> ulong count Exception count {} <byte 17088> {recursive_event[14] (Recursive entry array)} <byte 17088> ulong tt Trap type <byte 17092> ulong tc Termination code <byte 17096> ulong srr0 SRR0 register <byte 17100> ulong srr1 SRR1 register <byte 17104> ulong cr CR register <byte 17108> ulong xer XER register <byte 17112> ulong esr ESR register <byte 17116> ulong ctr CTR register

<byte 17120> ulong lr LR register <byte 17124> ulong exception Exception code <byte 17128> ulong count Exception count {} <byte 17132> {recursive_event[15] (Recursive entry array)} <byte 17132> ulong tt Trap type <byte 17136> ulong tc Termination code <byte 17140> ulong srr0 SRR0 register <byte 17144> ulong srr1 SRR1 register <byte 17148> ulong cr CR register <byte 17152> ulong xer XER register <byte 17156> ulong esr ESR register <byte 17160> ulong ctr CTR register <byte 17164> ulong lr LR register <byte 17168> ulong exception Exception code <byte 17172> ulong count Exception count {} <byte 17176> {recursive_event[16] (Recursive entry array)} <byte 17176> ulong tt Trap type <byte 17180> ulong tc Termination code <byte 17184> ulong srr0 SRR0 register <byte 17188> ulong srr1 SRR1 register <byte 17192> ulong cr CR register <byte 17196> ulong xer XER register <byte 17200> ulong esr ESR register <byte 17204> ulong ctr CTR register <byte 17208> ulong lr LR register <byte 17212> ulong exception Exception code <byte 17216> ulong count Exception count {} <byte 17220> {recursive_event[17] (Recursive entry array)} <byte 17220>

ulong tt Trap type <byte 17224> ulong tc Termination code <byte 17228> ulong srr0 SRR0 register <byte 17232> ulong srr1 SRR1 register <byte 17236> ulong cr CR register <byte 17240> ulong xer XER register <byte 17244> ulong esr ESR register <byte 17248> ulong ctr CTR register <byte 17252> ulong lr LR register <byte 17256> ulong exception Exception code <byte 17260> ulong count Exception count {} <byte 17264> {recursive_event[18] (Recursive entry array)} <byte 17264> ulong tt Trap type <byte 17268> ulong tc Termination code <byte 17272> ulong srr0 SRR0 register <byte 17276> ulong srr1 SRR1 register <byte 17280> ulong cr CR register <byte 17284> ulong xer XER register <byte 17288> ulong esr ESR register <byte 17292> ulong ctr CTR register <byte 17296> ulong lr LR register <byte 17300> ulong exception Exception code <byte 17304> ulong count Exception count {} <byte 17308> {recursive_event[19] (Recursive entry array)} <byte 17308> ulong tt Trap type <byte 17312> ulong tc Termination code <byte 17316> ulong srr0 SRR0 register <byte 17320> ulong srr1 SRR1 register <byte 17324> ulong cr CR register <byte 17328>

ulong xer XER register <byte 17332> ulong esr ESR register <byte 17336> ulong ctr CTR register <byte 17340> ulong lr LR register <byte 17344> ulong exception Exception code <byte 17348> ulong count Exception count {} <byte 17352> {recursive_event[20] (Recursive entry array)} <byte 17352> ulong tt Trap type <byte 17356> ulong tc Termination code <byte 17360> ulong srr0 SRR0 register <byte 17364> ulong srr1 SRR1 register <byte 17368> ulong cr CR register <byte 17372> ulong xer XER register <byte 17376> ulong esr ESR register <byte 17380> ulong ctr CTR register <byte 17384> ulong lr LR register <byte 17388> ulong exception Exception code <byte 17392> ulong count Exception count {} <byte 17396> {recursive_event[21] (Recursive entry array)} <byte 17396> ulong tt Trap type <byte 17400> ulong tc Termination code <byte 17404> ulong srr0 SRR0 register <byte 17408> ulong srr1 SRR1 register <byte 17412> ulong cr CR register <byte 17416> ulong xer XER register <byte 17420> ulong esr ESR register <byte 17424> ulong ctr CTR register <byte 17428> ulong lr LR register <byte 17432> ulong exception Exception code <byte 17436>

ulong count Exception count {} <byte 17440> {recursive_event[22] (Recursive entry array)} <byte 17440> ulong tt Trap type <byte 17444> ulong tc Termination code <byte 17448> ulong srr0 SRR0 register <byte 17452> ulong srr1 SRR1 register <byte 17456> ulong cr CR register <byte 17460> ulong xer XER register <byte 17464> ulong esr ESR register <byte 17468> ulong ctr CTR register <byte 17472> ulong lr LR register <byte 17476> ulong exception Exception code <byte 17480> ulong count Exception count {} <byte 17484> {recursive_event[23] (Recursive entry array)} <byte 17484> ulong tt Trap type <byte 17488> ulong tc Termination code <byte 17492> ulong srr0 SRR0 register <byte 17496> ulong srr1 SRR1 register <byte 17500> ulong cr CR register <byte 17504> ulong xer XER register <byte 17508> ulong esr ESR register <byte 17512> ulong ctr CTR register <byte 17516> ulong lr LR register <byte 17520> ulong exception Exception code <byte 17524> ulong count Exception count {} <byte 17528> {recursive_event[24] (Recursive entry array)} <byte 17528> ulong tt Trap type <byte 17532> ulong tc Termination code <byte 17536> ulong srr0 SRR0 register

<byte 17540> ulong srr1 SRR1 register <byte 17544> ulong cr CR register <byte 17548> ulong xer XER register <byte 17552> ulong esr ESR register <byte 17556> ulong ctr CTR register <byte 17560> ulong lr LR register <byte 17564> ulong exception Exception code <byte 17568> ulong count Exception count {} <byte 17572> {recursive_event[25] (Recursive entry array)} <byte 17572> ulong tt Trap type <byte 17576> ulong tc Termination code <byte 17580> ulong srr0 SRR0 register <byte 17584> ulong srr1 SRR1 register <byte 17588> ulong cr CR register <byte 17592> ulong xer XER register <byte 17596> ulong esr ESR register <byte 17600> ulong ctr CTR register <byte 17604> ulong lr LR register <byte 17608> ulong exception Exception code <byte 17612> ulong count Exception count {} <byte 17616> {recursive_event[26] (Recursive entry array)} <byte 17616> ulong tt Trap type <byte 17620> ulong tc Termination code <byte 17624> ulong srr0 SRR0 register <byte 17628> ulong srr1 SRR1 register <byte 17632> ulong cr CR register <byte 17636> ulong xer XER register <byte 17640> ulong esr ESR register <byte 17644> ulong ctr CTR register

<byte 17648> ulong lr LR register <byte 17652> ulong exception Exception code <byte 17656> ulong count Exception count {} <byte 17660> {recursive_event[27] (Recursive entry array)} <byte 17660> ulong tt Trap type <byte 17664> ulong tc Termination code <byte 17668> ulong srr0 SRR0 register <byte 17672> ulong srr1 SRR1 register <byte 17676> ulong cr CR register <byte 17680> ulong xer XER register <byte 17684> ulong esr ESR register <byte 17688> ulong ctr CTR register <byte 17692> ulong lr LR register <byte 17696> ulong exception Exception code <byte 17700> ulong count Exception count {} <byte 17704> {recursive_event[28] (Recursive entry array)} <byte 17704> ulong tt Trap type <byte 17708> ulong tc Termination code <byte 17712> ulong srr0 SRR0 register <byte 17716> ulong srr1 SRR1 register <byte 17720> ulong cr CR register <byte 17724> ulong xer XER register <byte 17728> ulong esr ESR register <byte 17732> ulong ctr CTR register <byte 17736> ulong lr LR register <byte 17740> ulong exception Exception code <byte 17744> ulong count Exception count {} <byte 17748> {recursive_event[29] (Recursive entry array)} <byte 17748>

ulong tt Trap type <byte 17752> ulong tc Termination code <byte 17756> ulong srr0 SRR0 register <byte 17760> ulong srr1 SRR1 register <byte 17764> ulong cr CR register <byte 17768> ulong xer XER register <byte 17772> ulong esr ESR register <byte 17776> ulong ctr CTR register <byte 17780> ulong lr LR register <byte 17784> ulong exception Exception code <byte 17788> ulong count Exception count {} <byte 17792> {recursive_event[30] (Recursive entry array)} <byte 17792> ulong tt Trap type <byte 17796> ulong tc Termination code <byte 17800> ulong srr0 SRR0 register <byte 17804> ulong srr1 SRR1 register <byte 17808> ulong cr CR register <byte 17812> ulong xer XER register <byte 17816> ulong esr ESR register <byte 17820> ulong ctr CTR register <byte 17824> ulong lr LR register <byte 17828> ulong exception Exception code <byte 17832> ulong count Exception count {} <byte 17836> {recursive_event[31] (Recursive entry array)} <byte 17836> ulong tt Trap type <byte 17840> ulong tc Termination code <byte 17844> ulong srr0 SRR0 register <byte 17848> ulong srr1 SRR1 register <byte 17852> ulong cr CR register <byte 17856>

ulong xer XER register <byte 17860> ulong esr ESR register <byte 17864> ulong ctr CTR register <byte 17868> ulong lr LR register <byte 17872> ulong exception Exception code <byte 17876> ulong count Exception count {} <byte 17880> {recursive_event[32] (Recursive entry array)} <byte 17880> ulong tt Trap type <byte 17884> ulong tc Termination code <byte 17888> ulong srr0 SRR0 register <byte 17892> ulong srr1 SRR1 register <byte 17896> ulong cr CR register <byte 17900> ulong xer XER register <byte 17904> ulong esr ESR register <byte 17908> ulong ctr CTR register <byte 17912> ulong lr LR register <byte 17916> ulong exception Exception code <byte 17920> ulong count Exception count {} <byte 17924> {unexpected_event[0] (Unexpected event array)} <byte 17924> ulong type Unexpected event type <byte 17928> ulong pto Post-Termination Operation Indicator <byte 17932> ulong[11] param Unexpected event parameters {} <byte 17976> {unexpected_event[1] (Unexpected event array)} <byte 17976> ulong type Unexpected event type <byte 17980> ulong pto Post-Termination Operation Indicator <byte 17984> ulong[11] param Unexpected event parameters {} <byte 18028> {unexpected_event[2] (Unexpected event array)} <byte 18028> ulong type Unexpected event type <byte 18032>

ulong pto Post-Termination Operation Indicator <byte 18036> ulong[11] param Unexpected event parameters {} <byte 18080> {unexpected_event[3] (Unexpected event array)} <byte 18080> ulong type Unexpected event type <byte 18084> ulong pto Post-Termination Operation Indicator <byte 18088> ulong[11] param Unexpected event parameters {} <byte 18132> {first_event (First event information)} <byte 18132> ulong tt Trap type <byte 18136> ulong tc Termination code <byte 18140> ulong srr0 SRR0 register <byte 18144> ulong srr1 SRR1 register <byte 18148> ulong cr CR register <byte 18152> ulong xer XER register <byte 18156> ulong esr ESR register <byte 18160> ulong ctr CTR register <byte 18164> ulong lr LR register <byte 18168> ulong exception Exception code <byte 18172> ulong count Exception count {} <byte 18176> ulonglong brcookie Back revision cookie {} <byte 18184> {ltecb (Last Termination Event Control Block)} <byte 18184> utiny recursive_notlogged Recursive entry not yet logged count <byte 18185> utiny info_notlogged Last Termination Event Information not yet logged <byte 18186> utiny reserved Reserved <byte 18187> utiny ltecb_revision Last Termination Event Control Block Revision number <byte 18188> utiny unexpected_logged Unexpected event already logged count <byte 18189> utiny unexpected_notlogged Unexpected event not yet logged count <byte 18190> utiny unexpected_event_index Unexpected event array index <byte 18191> utiny recursive_logged Recursive entry already logged count <byte 18192>

ulong info_edc Last Termination Event Information EDC {} {} <byte 18196> do_not_display[236] union_pad Union Element Padding (DO NOT DISPLAY!) or u Last Termination Event Block Union <byte 0> utiny[18432] union_pad Union Element Padding (DO NOT DISPLAY!) endunion u Last Termination Event Block Union {} FSWGAS EVENT CODE TRANSLATION BLOCKS: EC BLOCK: 0102000d SCID_EXEC_TOD_CHANGE TRANSLATIONBLOCK TRANSLATE('Action: %[exec_tod]', eip0D.action); TRANSLATE('Current date/time: %[scmitim]', eip0D.ctime); TRANSLATE('Previous date/time: %[scmitim]', eip0D.ptime); ENDTRANSLATIONBLOCK EC BLOCK: 0301400b SCID_SCS_DDRIVE_INOP TRANSLATIONBLOCK TRANSLATE('Device: %[uuid]', eip0B.device); TRANSLATE('Port ID: %s', eip0B.cerp_id); CONDITIONAL(eip0B.dencl_num != 99, TRANSLATE('Rack: %d.', eip0B.rack_num), TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip0B.dencl_num != 99, TRANSLATE('Enclosure: %d.', eip0B.dencl_num) ); CONDITIONAL(eip0B.dencl_num != 99, TRANSLATE('Bay: %d.', eip0B.bay) ); TRANSLATE( 'Reason code: 0x%04X (%[drv_inop])', eip0B.reason_code, eip0B.reason_code ); CONDITIONAL(eip0B.flags.quorum_disk != 0, TRANSLATE( 'Quorum space write sequence: %d.', eip0B.quorum_sequence ) ); CONDITIONAL(eip0B.flags.inq_state != 0, TRANSLATE( 'Inquiry data is valid (get more details)' ); TRANSLATE( 'Device capacity (blocks): %d.', eip0B.capacity ) ); CONDITIONAL(eip0B.rss_flags.member_migrating != 0, TRANSLATE( 'Redundant Storage Set member is migrating' )

); CONDITIONAL(eip0B.rss_flags.member_missing != 0, TRANSLATE( 'Redundant Storage Set member is missing' ) ); CONDITIONAL(eip0B.rss_flags.member_abnormal != 0, TRANSLATE( 'Redundant Storage Set member state: %d.', eip0B.member_state ) ); ENDTRANSLATIONBLOCK EC BLOCK: 03024f0b SCID_SCS_TOO_MANY_DISKS TRANSLATIONBLOCK TRANSLATE('Device: %[uuid]', eip0B.device); TRANSLATE('Port ID: %s', eip0B.cerp_id); CONDITIONAL(eip0B.dencl_num != 99, TRANSLATE('Rack: %d.', eip0B.rack_num), TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip0B.dencl_num != 99, TRANSLATE('Enclosure: %d.', eip0B.dencl_num) ); CONDITIONAL(eip0B.dencl_num != 99, TRANSLATE('Bay: %d.', eip0B.bay) ); ENDTRANSLATIONBLOCK EC BLOCK: 0303000a SCID_SCS_START_OF_BOOT TRANSLATIONBLOCK TRANSLATE('Controller: %[wwn]', eip0A.node_name); TRANSLATE('DebugFlags: %08X PrintFlags: %08X', eip0A.debug_flags, eip0A.print_flags); ENDTRANSLATIONBLOCK EC BLOCK: 0304000a SCID_SCS_REALIZE_CELL_TRANSITION TRANSLATIONBLOCK TRANSLATE('Controller: %[wwn]', eip0A.node_name); TRANSLATE('Storage System: %[tag]', eip0A.scell_tag); TRANSLATE('DebugFlags: %08X PrintFlags: %08X', eip0A.debug_flags, eip0A.print_flags); ENDTRANSLATIONBLOCK EC BLOCK: 0305000a SCID_SCS_FINISHED_JOINING_SLAVE TRANSLATIONBLOCK TRANSLATE('Controller: %[wwn]', eip0A.node_name); TRANSLATE('Storage System: %[tag]', eip0A.scell_tag); TRANSLATE('DebugFlags: %08X PrintFlags: %08X', eip0A.debug_flags, eip0A.print_flags); ENDTRANSLATIONBLOCK EC BLOCK: 0306000a SCID_SCS_FINISHED_SLAVE_LEAVE TRANSLATIONBLOCK CONDITIONAL(eip0A.node_name.lo != 0, TRANSLATE('Controller: %[wwn]', eip0A.node_name), TRANSLATE('Controller node name not known') ); TRANSLATE('Storage System: %[tag]', eip0A.scell_tag);

TRANSLATE('DebugFlags: %08X PrintFlags: %08X', eip0A.debug_flags, eip0A.print_flags); ENDTRANSLATIONBLOCK EC BLOCK: 0307000a SCID_SCS_MASTER_FAILOVER TRANSLATIONBLOCK TRANSLATE('Controller: %[wwn]', eip0A.node_name); TRANSLATE('Storage System: %[tag]', eip0A.scell_tag); TRANSLATE('DebugFlags: %08X PrintFlags: %08X', eip0A.debug_flags, eip0A.print_flags); ENDTRANSLATIONBLOCK EC BLOCK: 0308000a SCID_SCS_NSC_BROUGHT_IN TRANSLATIONBLOCK TRANSLATE('Controller: %[wwn]', eip0A.node_name); TRANSLATE('Storage System: %[tag]', eip0A.scell_tag); TRANSLATE('DebugFlags: %08X PrintFlags: %08X', eip0A.debug_flags, eip0A.print_flags); ENDTRANSLATIONBLOCK EC BLOCK: 03090018 SCID_SCS_MIGRATION_START TRANSLATIONBLOCK CONDITIONAL(eip18.source_migr == 0x06, TRANSLATE('Merge started') ); CONDITIONAL(eip18.source_migr == 0x0A, TRANSLATE('Split started') ); TRANSLATE('Disk Group tag: %[tag]', eip18.ldad_tag); TRANSLATE('Source Redundant Storage Set: %04X', eip18.source_rss); TRANSLATE('Target Redundant Storage Set: %04X', eip18.target_rss); TRANSLATE('Source migration flags: %04x', eip18.source_migr); TRANSLATE('Target migration flags: %04x', eip18.target_migr); TRANSLATE('Source volumes: %02X %02X %02X %02X %02X %02X %02X %02X', eip18.smembers[0], eip18.smembers[1], eip18.smembers[2], eip18.smembers[3], eip18.smembers[4], eip18.smembers[5], eip18.smembers[6], eip18.smembers[7]); TRANSLATE(' %02X %02X %02X %02X %02X %02X %02X %02X', eip18.smembers[8], eip18.smembers[9], eip18.smembers[10], eip18.smembers[11], eip18.smembers[12], eip18.smembers[13], eip18.smembers[14], eip18.smembers[15]); TRANSLATE('Target volumes: %02X %02X %02X %02X %02X %02X %02X %02X', eip18.tmembers[0], eip18.tmembers[1], eip18.tmembers[2], eip18.tmembers[3], eip18.tmembers[4], eip18.tmembers[5], eip18.tmembers[6], eip18.tmembers[7]); TRANSLATE(' %02X %02X %02X %02X %02X %02X %02X %02X', eip18.tmembers[8], eip18.tmembers[9], eip18.tmembers[10], eip18.tmembers[11], eip18.tmembers[12], eip18.tmembers[13], eip18.tmembers[14], eip18.tmembers[15]); ENDTRANSLATIONBLOCK EC BLOCK: 030a0018 SCID_SCS_MIGRATION_END TRANSLATIONBLOCK CONDITIONAL(eip18.source_migr == 0x06, TRANSLATE('Merge finished') ); CONDITIONAL(eip18.source_migr == 0x0A, TRANSLATE('Split finished')

); TRANSLATE('Disk Group tag: %[tag]', eip18.ldad_tag); TRANSLATE('Source Redundant Storage Set: %04X', eip18.source_rss); TRANSLATE('Target Redundant Storage Set: %04X', eip18.target_rss); TRANSLATE('Source migration flags: %04x', eip18.source_migr); TRANSLATE('Target migration flags: %04x', eip18.target_migr); TRANSLATE('Source volumes: %02X %02X %02X %02X %02X %02X %02X %02X', eip18.smembers[0], eip18.smembers[1], eip18.smembers[2], eip18.smembers[3], eip18.smembers[4], eip18.smembers[5], eip18.smembers[6], eip18.smembers[7]); TRANSLATE(' %02X %02X %02X %02X %02X %02X %02X %02X', eip18.smembers[8], eip18.smembers[9], eip18.smembers[10], eip18.smembers[11], eip18.smembers[12], eip18.smembers[13], eip18.smembers[14], eip18.smembers[15]); TRANSLATE('Target volumes: %02X %02X %02X %02X %02X %02X %02X %02X', eip18.tmembers[0], eip18.tmembers[1], eip18.tmembers[2], eip18.tmembers[3], eip18.tmembers[4], eip18.tmembers[5], eip18.tmembers[6], eip18.tmembers[7]); TRANSLATE(' %02X %02X %02X %02X %02X %02X %02X %02X', eip18.tmembers[8], eip18.tmembers[9], eip18.tmembers[10], eip18.tmembers[11], eip18.tmembers[12], eip18.tmembers[13], eip18.tmembers[14], eip18.tmembers[15]); ENDTRANSLATIONBLOCK EC BLOCK: 030b4f0b SCID_SCS_DRIVE_FAIL_DURING_REALIZE TRANSLATIONBLOCK TRANSLATE('Device: %[uuid]', eip0B.device); TRANSLATE('Port ID: %s', eip0B.cerp_id); CONDITIONAL(eip0B.dencl_num != 99, TRANSLATE('Rack: %d.', eip0B.rack_num), TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip0B.dencl_num != 99, TRANSLATE('Enclosure: %d.', eip0B.dencl_num) ); CONDITIONAL(eip0B.dencl_num != 99, TRANSLATE('Bay: %d.', eip0B.bay) ); ENDTRANSLATIONBLOCK EC BLOCK: 030c001e SCID_SCS_FLAGS_CHANGED TRANSLATIONBLOCK TRANSLATE('DebugFlags: %08X PrintFlags: %08X Caller PC : %08X', eip1E.data[0], eip1E.data[1], eip1E.data[2]); ENDTRANSLATIONBLOCK EC BLOCK: 030d001e SCID_SCS_CSM_HANG_PROCESS TRANSLATIONBLOCK CONDITIONAL(eip1E.data[0] != 0, TRANSLATE('Process: %s %02d', eip1E.info, eip1E.data[0]) ); CONDITIONAL(eip1E.data[0] == 0, TRANSLATE('Process: %s', eip1E.info) ); CONDITIONAL(eip1E.data[1] != 0, TRANSLATE('Stack[0]: %08x (%s)', eip1E.data[1], XLATE_PC_CURRENT(eip1E.data[1])) );

CONDITIONAL(eip1E.data[2] != 0, TRANSLATE('Stack[1]: %08x (%s)', eip1E.data[2], XLATE_PC_CURRENT(eip1E.data[2])) ); CONDITIONAL(eip1E.data[3] != 0, TRANSLATE('Stack[2]: %08x (%s)', eip1E.data[3], XLATE_PC_CURRENT(eip1E.data[3])) ); CONDITIONAL(eip1E.data[4] != 0, TRANSLATE('Stack[3]: %08x (%s)', eip1E.data[4], XLATE_PC_CURRENT(eip1E.data[4])) ); CONDITIONAL(eip1E.data[5] != 0, TRANSLATE('Stack[4]: %08x (%s)', eip1E.data[5], XLATE_PC_CURRENT(eip1E.data[5])) ); CONDITIONAL(eip1E.data[6] != 0, TRANSLATE('Stack[5]: %08x (%s)', eip1E.data[6], XLATE_PC_CURRENT(eip1E.data[6])) ); CONDITIONAL(eip1E.data[7] != 0, TRANSLATE('Stack[6]: %08x (%s)', eip1E.data[7], XLATE_PC_CURRENT(eip1E.data[7])) ); CONDITIONAL(eip1E.data[8] != 0, TRANSLATE('Stack[7]: %08x (%s)', eip1E.data[8], XLATE_PC_CURRENT(eip1E.data[8])) ); CONDITIONAL(eip1E.data[9] != 0, TRANSLATE('Stack[8]: %08x (%s)', eip1E.data[9], XLATE_PC_CURRENT(eip1E.data[9])) ); CONDITIONAL(eip1E.data[10] != 0, TRANSLATE('Stack[9]: %08x (%s)', eip1E.data[10], XLATE_PC_CURRENT(eip1E.data[10])) ); CONDITIONAL(eip1E.data[11] != 0, TRANSLATE('Stack[10]: %08x (%s)', eip1E.data[11], XLATE_PC_CURRENT(eip1E.data[11])) ); CONDITIONAL(eip1E.data[12] != 0, TRANSLATE('Stack[11]: %08x (%s)', eip1E.data[12], XLATE_PC_CURRENT(eip1E.data[12])) ); CONDITIONAL(eip1E.data[13] != 0, TRANSLATE('Stack[12]: %08x (%s)', eip1E.data[13], XLATE_PC_CURRENT(eip1E.data[13])) ); CONDITIONAL(eip1E.data[14] != 0, TRANSLATE('Stack[13]: %08x (%s)', eip1E.data[14], XLATE_PC_CURRENT(eip1E.data[14])) ); CONDITIONAL(eip1E.data[15] != 0, TRANSLATE('Stack[14]: %08x (%s)', eip1E.data[15], XLATE_PC_CURRENT(eip1E.data[15])) ); CONDITIONAL(eip1E.data[16] != 0, TRANSLATE('Stack[15]: %08x (%s)', eip1E.data[16], XLATE_PC_CURRENT(eip1E.data[16])) );

CONDITIONAL(eip1E.data[17] != 0, TRANSLATE('Stack[16]: %08x (%s)', XLATE_PC_CURRENT(eip1E.data[17])) ); CONDITIONAL(eip1E.data[18] != 0, TRANSLATE('Stack[17]: %08x (%s)', XLATE_PC_CURRENT(eip1E.data[18])) ); CONDITIONAL(eip1E.data[19] != 0, TRANSLATE('Stack[18]: %08x (%s)', XLATE_PC_CURRENT(eip1E.data[19])) ); CONDITIONAL(eip1E.data[20] != 0, TRANSLATE('Stack[19]: %08x (%s)', XLATE_PC_CURRENT(eip1E.data[20])) ); CONDITIONAL(eip1E.data[21] != 0, TRANSLATE('Stack[20]: %08x (%s)', XLATE_PC_CURRENT(eip1E.data[21])) ); CONDITIONAL(eip1E.data[22] != 0, TRANSLATE('Stack[21]: %08x (%s)', XLATE_PC_CURRENT(eip1E.data[22])) ); CONDITIONAL(eip1E.data[23] != 0, TRANSLATE('Stack[22]: %08x (%s)', XLATE_PC_CURRENT(eip1E.data[23])) ); ENDTRANSLATIONBLOCK

eip1E.data[17],

eip1E.data[18],

eip1E.data[19],

eip1E.data[20],

eip1E.data[21],

eip1E.data[22],

eip1E.data[23],

EC BLOCK: 030e070b SCID_SCS_ID_WRITE_DRIVE_CHANGED TRANSLATIONBLOCK TRANSLATE('Device about to write: %[uuid]', eip0B.device); TRANSLATE('Port ID: %s', eip0B.cerp_id); CONDITIONAL(eip0B.dencl_num != 99, TRANSLATE('Rack: %d.', eip0B.rack_num), TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip0B.dencl_num != 99, TRANSLATE('Enclosure: %d.', eip0B.dencl_num) ); CONDITIONAL(eip0B.dencl_num != 99, TRANSLATE('Bay: %d.', eip0B.bay) ); TRANSLATE( 'Reason code: 0x%04X (%[drv_inop])', eip0B.reason_code, eip0B.reason_code ); CONDITIONAL(eip0B.flags.quorum_disk != 0, TRANSLATE( 'Quorum space write sequence: %d.', eip0B.quorum_sequence ) ); CONDITIONAL(eip0B.flags.inq_state != 0, TRANSLATE( 'Inquiry data is valid (get more details)' ); TRANSLATE(

'Device capacity (blocks): %d.', eip0B.capacity ) ); CONDITIONAL(eip0B.rss_flags.member_migrating != 0, TRANSLATE( 'Redundant Storage Set member is migrating' ) ); CONDITIONAL(eip0B.rss_flags.member_missing != 0, TRANSLATE( 'Redundant Storage Set member is missing' ) ); CONDITIONAL(eip0B.rss_flags.member_abnormal != 0, TRANSLATE( 'Redundant Storage Set member state: %d.', eip0B.member_state ) ); TRANSLATE('Device we should have written: %[uuid]', eip0B.second_device); TRANSLATE('Device fnb: 0x%08X', eip0B.second_fnb_ptr); TRANSLATE('Device poid, vol: 0x%04X, 0x%04X', eip0B.poid, eip0B.volnoid); ENDTRANSLATIONBLOCK EC BLOCK: 030f001e SCID_SCS_ROHS_COMPLIANCE TRANSLATIONBLOCK CONDITIONAL(eip1E.data[0] != 0, TRANSLATE( 'The HSV450 controller is RoHS compliant.' ) ); CONDITIONAL(eip1E.data[0] == 0, TRANSLATE( 'The HSV450 controller is not RoHS compliant.' ) ); CONDITIONAL(eip1E.data[1] == 1, TRANSLATE( 'This controller is a HSV450-A REV2 hardware build.' ) ); ENDTRANSLATIONBLOCK EC BLOCK: 0310001f SCID_SCS_UNIT_FAILOVER TRANSLATIONBLOCK TRANSLATE('Storage System Virtual Disk: %[tag]', eip1F.scvd_tag); TRANSLATE('Prev Controller: %[wwn]', eip1F.prev_wwn); TRANSLATE('Current Controller: %[wwn]', eip1F.current_wwn); ENDTRANSLATIONBLOCK EC BLOCK: 03114420 SCID_SCS_FABRIC_ON_LOOP TRANSLATIONBLOCK TRANSLATE('Controller: %[wwn]', eip20.node_name); TRANSLATE('FC port: %d', eip20.port); TRANSLATE('Port state: %d', eip20.data);

ENDTRANSLATIONBLOCK EC BLOCK: 03120021 SCID_SCS_SCVD_ATTACH_DONE TRANSLATIONBLOCK TRANSLATE('Storage System Virtual Disk: %[tag]', eip21.target_tag); TRANSLATE('Parent Storage System Virtual Disk: %[tag]', eip21.parent_tag); TRANSLATE('Type: %[scmi_scvd_snap_attach_type]', eip21.operation); TRANSLATE('Status: %d', eip21.status); CONDITIONAL(eip21.status == 0, TRANSLATE('Success')); CONDITIONAL(eip21.status != 0, TRANSLATE('Error')); ENDTRANSLATIONBLOCK EC BLOCK: 03130021 SCID_SCS_SNAPCLONE_UNSHARE_DONE TRANSLATIONBLOCK TRANSLATE('Snapclone Storage System Virtual Disk: %[tag]', eip21.target_tag); TRANSLATE('Parent Storage System Virtual Disk: %[tag]', eip21.parent_tag); ENDTRANSLATIONBLOCK EC BLOCK: 03140021 SCID_SCS_MIRROR_CLONE_DETACH_DONE TRANSLATIONBLOCK TRANSLATE('Mirror Clone Storage System Virtual Disk: %[tag]', eip21.target_tag); TRANSLATE('Parent Storage System Virtual Disk: %[tag]', eip21.parent_tag); TRANSLATE( 'State: %[scmi_scvd_condition] --> %[scmi_scvd_condition]', eip21.prev_state, eip21.new_state); TRANSLATE('Status: %d', eip21.status); CONDITIONAL(eip21.status == 0, TRANSLATE('Success')); CONDITIONAL(eip21.status != 0, TRANSLATE('Error')); ENDTRANSLATIONBLOCK EC BLOCK: 03150021 SCID_SCS_MIRROR_CLONE_FRACTURE_DONE TRANSLATIONBLOCK TRANSLATE('Mirror Clone Storage System Virtual Disk: %[tag]', eip21.target_tag); TRANSLATE('Parent Storage System Virtual Disk: %[tag]', eip21.parent_tag); TRANSLATE('Status: %d', eip21.status); CONDITIONAL(eip21.status == 0, TRANSLATE('Success')); CONDITIONAL(eip21.status != 0, TRANSLATE('Error')); ENDTRANSLATIONBLOCK EC BLOCK: 03160021 SCID_SCS_MIRROR_CLONE_RESYNC_DONE TRANSLATIONBLOCK TRANSLATE('Mirror Clone Storage System Virtual Disk: %[tag]', eip21.target_tag); TRANSLATE('Parent Storage System Virtual Disk: %[tag]', eip21.parent_tag); TRANSLATE('Status: %d', eip21.status); CONDITIONAL(eip21.status == 0, TRANSLATE('Success')); CONDITIONAL(eip21.status != 0, TRANSLATE('Error')); ENDTRANSLATIONBLOCK EC BLOCK: 03170021 SCID_SCS_INSTANT_RESTORE_DONE TRANSLATIONBLOCK TRANSLATE('Original Storage System Virtual Disk: %[tag]', eip21.target_tag); TRANSLATE('Source Storage System Virtual Disk: %[tag]', eip21.parent_tag); TRANSLATE('Status: %d', eip21.status); CONDITIONAL(eip21.status == 0, TRANSLATE('Success')); CONDITIONAL(eip21.status != 0, TRANSLATE('Error')); CONDITIONAL( eip21.operation == 1, TRANSLATE('This was a high performance instant restore operation') ); CONDITIONAL(

eip21.operation != 1, TRANSLATE('This was a normal performance instant restore operation') ); ENDTRANSLATIONBLOCK EC BLOCK: 03189513 SCID_SCS_ENCLOSURE_INIT_FAILED TRANSLATIONBLOCK TRANSLATE('Enclousre tag: %[tag]', eip13.device); TRANSLATE('Enclosure Port: %d', eip13.port); TRANSLATE('Enclosure Shelf Number: %d', eip13.dencl_num); CONDITIONAL(eip13.num_times == 0x01, TRANSLATE('Enclosure Error Status: TDS_LDN_ABORTED') ); CONDITIONAL(eip13.num_times == 0x02, TRANSLATE('Enclosure Error Status: TDS_SCS_ABORTED') ); CONDITIONAL(eip13.num_times == 0x03, TRANSLATE('Enclosure Error Status: TDS_BAD_ALPA') ); CONDITIONAL(eip13.num_times == 0x04, TRANSLATE('Enclosure Error Status: TDS_REPLY_FAILURE') ); CONDITIONAL(eip13.num_times == 0x05, TRANSLATE('Enclosure Error Status: TDS_DRIVE_SENSE') ); CONDITIONAL(eip13.num_times == 0x06, TRANSLATE('Enclosure Error Status: TDS_FAILURE') ); CONDITIONAL(eip13.num_times == 0x07, TRANSLATE('Enclosure Error Status: TDS_BBR_NEEDED') ); CONDITIONAL(eip13.num_times == 0x08, TRANSLATE('Enclosure Error Status: TDS_RESERVED') ); CONDITIONAL(eip13.num_times == 0x09, TRANSLATE('Enclosure Error Status: TDS_SKIPPED') ); CONDITIONAL(eip13.num_times > 0x09 || eip13.num_times < 0x01, TRANSLATE('Enclosure Error Status: Unknown 0x%02X', eip13.num_times) ); ENDTRANSLATIONBLOCK EC BLOCK: 0319000a SCID_SCS_START_OF_DEVICE_DISCOVERY TRANSLATIONBLOCK TRANSLATE('Controller: %[wwn]', eip0A.node_name); TRANSLATE('DebugFlags: %08X PrintFlags: %08X', eip0A.debug_flags, eip0A.print_flags); ENDTRANSLATIONBLOCK EC BLOCK: 031a000a SCID_SCS_COMPLETION_OF_DEVICE_DISCOVERY TRANSLATIONBLOCK TRANSLATE('Controller: %[wwn]', eip0A.node_name); TRANSLATE('DebugFlags: %08X PrintFlags: %08X', eip0A.debug_flags, eip0A.print_flags); ENDTRANSLATIONBLOCK EC BLOCK: 031b0d23 SCID_SCS_SYSTEM_INOPERATIVE TRANSLATIONBLOCK TRANSLATE('Controller: %[wwn]', eip23.device_wwn); TRANSLATE('scs_flags: 0x%08X scs_flags2: 0x%08X',

eip23.scs_flags, eip23.scs_flags2); TRANSLATE('Port 0 state: %d', eip23.port_state[0]); TRANSLATE('Port 1 state: %d', eip23.port_state[1]); CONDITIONAL(eip23.port_state[2] != 0, TRANSLATE('Port 2 state: %d', eip23.port_state[2])); CONDITIONAL(eip23.port_state[3] != 0, TRANSLATE('Port 3 state: %d', eip23.port_state[3])); CONDITIONAL(eip23.port_state[4] != 0, TRANSLATE('Port 4 state: %d', eip23.port_state[4])); CONDITIONAL(eip23.port_state[5] != 0, TRANSLATE('Port 5 state: %d', eip23.port_state[5])); CONDITIONAL(eip23.port_state[6] != 0, TRANSLATE('Port 6 state: %d', eip23.port_state[6])); CONDITIONAL(eip23.port_state[7] != 0, TRANSLATE('Port 7 state: %d', eip23.port_state[7])); TRANSLATE('Inop code: %[sys_inop_failure_codes]', eip23.data); ENDTRANSLATIONBLOCK EC BLOCK: 031c4a23 SCID_SCS_PORTS_DISABLED TRANSLATIONBLOCK TRANSLATE('Controller: %[wwn]', eip23.device_wwn); TRANSLATE('scs_flags: 0x%08X scs_flags2: 0x%08X', eip23.scs_flags, eip23.scs_flags2); TRANSLATE('Port 0 state: %d', eip23.port_state[0]); TRANSLATE('Port 1 state: %d', eip23.port_state[1]); CONDITIONAL(eip23.port_state[2] != 0, TRANSLATE('Port 2 state: %d', eip23.port_state[2])); CONDITIONAL(eip23.port_state[3] != 0, TRANSLATE('Port 3 state: %d', eip23.port_state[3])); CONDITIONAL(eip23.port_state[4] != 0, TRANSLATE('Port 4 state: %d', eip23.port_state[4])); CONDITIONAL(eip23.port_state[5] != 0, TRANSLATE('Port 5 state: %d', eip23.port_state[5])); CONDITIONAL(eip23.port_state[6] != 0, TRANSLATE('Port 6 state: %d', eip23.port_state[6])); CONDITIONAL(eip23.port_state[7] != 0, TRANSLATE('Port 7 state: %d', eip23.port_state[7])); CONDITIONAL(eip23.port_state[0] == 3, TRANSLATE('Port 0 has been disabled')); CONDITIONAL(eip23.port_state[1] == 3, TRANSLATE('Port 1 has been disabled')); CONDITIONAL(eip23.port_state[2] == 3, TRANSLATE('Port 2 has been disabled')); CONDITIONAL(eip23.port_state[3] == 3, TRANSLATE('Port 3 has been disabled')); CONDITIONAL(eip23.port_state[4] == 3, TRANSLATE('Port 4 has been disabled')); CONDITIONAL(eip23.port_state[5] == 3, TRANSLATE('Port 5 has been disabled')); CONDITIONAL(eip23.port_state[6] == 3, TRANSLATE('Port 6 has been disabled')); CONDITIONAL(eip23.port_state[7] == 3, TRANSLATE('Port 7 has been disabled')); ENDTRANSLATIONBLOCK EC BLOCK: 031d9923 SCID_SCS_PORT_MISCONFIGURATION TRANSLATIONBLOCK TRANSLATE('Controller: %[wwn]', eip23.device_wwn); TRANSLATE('scs_flags: 0x%08X scs_flags2: 0x%08X', eip23.scs_flags, eip23.scs_flags2);

TRANSLATE('Port 0 state: %d', eip23.port_state[0]); TRANSLATE('Port 1 state: %d', eip23.port_state[1]); CONDITIONAL(eip23.port_state[2] != 0, TRANSLATE('Port 2 state: %d', eip23.port_state[2])); CONDITIONAL(eip23.port_state[3] != 0, TRANSLATE('Port 3 state: %d', eip23.port_state[3])); CONDITIONAL(eip23.port_state[4] != 0, TRANSLATE('Port 4 state: %d', eip23.port_state[4])); CONDITIONAL(eip23.port_state[5] != 0, TRANSLATE('Port 5 state: %d', eip23.port_state[5])); CONDITIONAL(eip23.port_state[6] != 0, TRANSLATE('Port 6 state: %d', eip23.port_state[6])); CONDITIONAL(eip23.port_state[7] != 0, TRANSLATE('Port 7 state: %d', eip23.port_state[7])); CONDITIONAL(eip23.master_port_state[0] != 0, TRANSLATE('Port 0 misconfigured on master')); CONDITIONAL(eip23.master_port_state[1] != 0, TRANSLATE('Port 1 misconfigured on master')); CONDITIONAL(eip23.master_port_state[2] != 0, TRANSLATE('Port 2 misconfigured on master')); CONDITIONAL(eip23.master_port_state[3] != 0, TRANSLATE('Port 3 misconfigured on master')); CONDITIONAL(eip23.master_port_state[4] != 0, TRANSLATE('Port 4 misconfigured on master')); CONDITIONAL(eip23.master_port_state[5] != 0, TRANSLATE('Port 5 misconfigured on master')); CONDITIONAL(eip23.master_port_state[6] != 0, TRANSLATE('Port 6 misconfigured on master')); CONDITIONAL(eip23.master_port_state[7] != 0, TRANSLATE('Port 7 misconfigured on master')); CONDITIONAL(eip23.slave_port_state[0] != 0, TRANSLATE('Port 0 misconfigured on slave')); CONDITIONAL(eip23.slave_port_state[1] != 0, TRANSLATE('Port 1 misconfigured on slave')); CONDITIONAL(eip23.slave_port_state[2] != 0, TRANSLATE('Port 2 misconfigured on slave')); CONDITIONAL(eip23.slave_port_state[3] != 0, TRANSLATE('Port 3 misconfigured on slave')); CONDITIONAL(eip23.slave_port_state[4] != 0, TRANSLATE('Port 4 misconfigured on slave')); CONDITIONAL(eip23.slave_port_state[5] != 0, TRANSLATE('Port 5 misconfigured on slave')); CONDITIONAL(eip23.slave_port_state[6] != 0, TRANSLATE('Port 6 misconfigured on slave')); CONDITIONAL(eip23.slave_port_state[7] != 0, TRANSLATE('Port 7 misconfigured on slave')); ENDTRANSLATIONBLOCK EC BLOCK: 031e0d23 SCID_SCS_USER_CONFIRMATION TRANSLATIONBLOCK TRANSLATE('Controller: %[wwn]', eip23.device_wwn); TRANSLATE('scs_flags: 0x%08X scs_flags2: 0x%08X', eip23.scs_flags, eip23.scs_flags2); TRANSLATE('Port 0 state: %d', eip23.port_state[0]); TRANSLATE('Port 1 state: %d', eip23.port_state[1]); CONDITIONAL(eip23.port_state[2] != 0, TRANSLATE('Port 2 state: %d', eip23.port_state[2])); CONDITIONAL(eip23.port_state[3] != 0, TRANSLATE('Port 3 state: %d', eip23.port_state[3])); CONDITIONAL(eip23.port_state[4] != 0,

TRANSLATE('Port 4 state: %d', eip23.port_state[4])); CONDITIONAL(eip23.port_state[5] != 0, TRANSLATE('Port 5 state: %d', eip23.port_state[5])); CONDITIONAL(eip23.port_state[6] != 0, TRANSLATE('Port 6 state: %d', eip23.port_state[6])); CONDITIONAL(eip23.port_state[7] != 0, TRANSLATE('Port 7 state: %d', eip23.port_state[7])); TRANSLATE('Confirmation code: %[scs_confirmation_message]', eip23.data); CONDITIONAL(eip23.data >= 4, TRANSLATE('Unrecognized confirmation code: %d', eip23.data)); ENDTRANSLATIONBLOCK EC BLOCK: 031f9923 SCID_SCS_DEVICE_CONFIGURATION_ERROR TRANSLATIONBLOCK TRANSLATE('Device: %[wwn]', eip23.device_wwn); TRANSLATE('scs_flags: 0x%08X scs_flags2: 0x%08X', eip23.scs_flags, eip23.scs_flags2); TRANSLATE('Port 0 state: %d', eip23.port_state[0]); TRANSLATE('Port 1 state: %d', eip23.port_state[1]); CONDITIONAL(eip23.port_state[2] != 0, TRANSLATE('Port 2 state: %d', eip23.port_state[2])); CONDITIONAL(eip23.port_state[3] != 0, TRANSLATE('Port 3 state: %d', eip23.port_state[3])); CONDITIONAL(eip23.port_state[4] != 0, TRANSLATE('Port 4 state: %d', eip23.port_state[4])); CONDITIONAL(eip23.port_state[5] != 0, TRANSLATE('Port 5 state: %d', eip23.port_state[5])); CONDITIONAL(eip23.port_state[6] != 0, TRANSLATE('Port 6 state: %d', eip23.port_state[6])); CONDITIONAL(eip23.port_state[7] != 0, TRANSLATE('Port 7 state: %d', eip23.port_state[7])); CONDITIONAL(eip23.data != 0, TRANSLATE('Both controllers active')); CONDITIONAL(eip23.data == 0, TRANSLATE('Single controller active')); TRANSLATE('Current Port 0 master state: %d slave state: %d', eip23.master_port_state[0], eip23.slave_port_state[0]); TRANSLATE('Current Port 1 master state: %d slave state: %d', eip23.master_port_state[1], eip23.slave_port_state[1]); CONDITIONAL(eip23.port_state[2] != 0, TRANSLATE('Current Port 2 master state: %d slave state: %d', eip23.master_port_state[2], eip23.slave_port_state[2])); CONDITIONAL(eip23.port_state[3] != 0, TRANSLATE('Current Port 3 master state: %d slave state: %d', eip23.master_port_state[3], eip23.slave_port_state[3])); CONDITIONAL(eip23.port_state[4] != 0, TRANSLATE('Current Port 4 master state: %d slave state: %d', eip23.master_port_state[4], eip23.slave_port_state[4])); CONDITIONAL(eip23.port_state[5] != 0, TRANSLATE('Current Port 5 master state: %d slave state: %d', eip23.master_port_state[5], eip23.slave_port_state[5])); CONDITIONAL(eip23.port_state[6] != 0, TRANSLATE('Current Port 6 master state: %d slave state: %d', eip23.master_port_state[6], eip23.slave_port_state[6])); CONDITIONAL(eip23.port_state[7] != 0, TRANSLATE('Current Port 7 master state: %d slave state: %d', eip23.master_port_state[7], eip23.slave_port_state[7])); TRANSLATE('Previous Port 0 master state: %d slave state: %d', eip23.master_prev_port_state[0], eip23.slave_prev_port_state[0]); TRANSLATE('Previous Port 1 master state: %d slave state: %d', eip23.master_prev_port_state[1], eip23.slave_prev_port_state[1]); CONDITIONAL(eip23.port_state[2] != 0,

TRANSLATE('Previous Port 2 master state: %d slave state: %d', eip23.master_prev_port_state[2], eip23.slave_prev_port_state[2])); CONDITIONAL(eip23.port_state[3] != 0, TRANSLATE('Previous Port 3 master state: %d slave state: %d', eip23.master_prev_port_state[3], eip23.slave_prev_port_state[3])); CONDITIONAL(eip23.port_state[4] != 0, TRANSLATE('Previous Port 4 master state: %d slave state: %d', eip23.master_prev_port_state[4], eip23.slave_prev_port_state[4])); CONDITIONAL(eip23.port_state[5] != 0, TRANSLATE('Previous Port 5 master state: %d slave state: %d', eip23.master_prev_port_state[5], eip23.slave_prev_port_state[5])); CONDITIONAL(eip23.port_state[6] != 0, TRANSLATE('Previous Port 6 master state: %d slave state: %d', eip23.master_prev_port_state[6], eip23.slave_prev_port_state[6])); CONDITIONAL(eip23.port_state[7] != 0, TRANSLATE('Previous Port 7 master state: %d slave state: %d', eip23.master_prev_port_state[7], eip23.slave_prev_port_state[7])); ENDTRANSLATIONBLOCK EC BLOCK: 0320000a SCID_SCS_DELAYED_SLAVE_JOIN TRANSLATIONBLOCK TRANSLATE('Controller: %[wwn]', eip0A.node_name); TRANSLATE('DebugFlags: %08X PrintFlags: %08X', eip0A.debug_flags, eip0A.print_flags); ENDTRANSLATIONBLOCK EC BLOCK: 0321f113 SCID_SCS_TOO_MANY_ENCLOSURES TRANSLATIONBLOCK TRANSLATE('Enclosure WWN: %[tag]', eip13.device); TRANSLATE('Enclosure Shelf Number: %d', eip13.dencl_num); ENDTRANSLATIONBLOCK EC BLOCK: 0322000f SCID_SCS_PORT_ROUTING_CHANGE TRANSLATIONBLOCK TRANSLATE('The CA port routing value has changed from %d to %d.', eip0F.old_attr .value.u32[0], eip0F.new_attr.value.u32[0]); ENDTRANSLATIONBLOCK EC BLOCK: 0323000a SCID_SCS_PRESERVING_RESYNC_OCCURRED TRANSLATIONBLOCK TRANSLATE('Controller: %[wwn]', eip0A.node_name); TRANSLATE('Storage System: %[tag]', eip0A.scell_tag); ENDTRANSLATIONBLOCK EC BLOCK: 0324400b SCID_SCS_DRIVE_UNSUPPORTED_CAPACITY TRANSLATIONBLOCK TRANSLATE('Max Supported Device Capacity (blocks): %d', eip0B.supported_capacity ); TRANSLATE('Device: %[uuid]', eip0B.device); TRANSLATE('Port ID: %s', eip0B.cerp_id); CONDITIONAL(eip0B.dencl_num != 99, TRANSLATE('Rack: %d.', eip0B.rack_num), TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip0B.dencl_num != 99, TRANSLATE('Enclosure: %d.', eip0B.dencl_num) ); CONDITIONAL(eip0B.dencl_num != 99, TRANSLATE('Bay: %d.', eip0B.bay) );

CONDITIONAL(eip0B.flags.inq_state != 0, TRANSLATE( 'Inquiry data is valid (get more details)' ); TRANSLATE( 'Device capacity (blocks): %d.', eip0B.capacity ) ); ENDTRANSLATIONBLOCK EC BLOCK: 0325000a SCID_SCS_ID_WRITE_FOR_DELETED_SCELL TRANSLATIONBLOCK TRANSLATE('Device: %[wwn]', eip0A.node_name); TRANSLATE('Storage System: %[tag]', eip0A.scell_tag); ENDTRANSLATIONBLOCK EC BLOCK: 03260027 SCID_SCS_BATTERY_POLICY_CHANGED TRANSLATIONBLOCK TRANSLATE('Controller: %[wwn]', eip27.node_name); TRANSLATE('Old Battery State This: %d', eip27.old_battery_state_this); TRANSLATE('Old Battery State Other: %d', eip27.old_battery_state_other); TRANSLATE('Old Battery Cache Policy State: %d', eip27.old_battery_cache_state); TRANSLATE('New Battery State This: %d', eip27.new_battery_state_this); TRANSLATE('New Battery State Other: %d', eip27.new_battery_state_other); TRANSLATE('New Battery Cache Policy State: %d', eip27.new_battery_cache_state); ENDTRANSLATIONBLOCK EC BLOCK: 03270129 SCID_SCS_DRIVE_ID_MISMATCH TRANSLATIONBLOCK TRANSLATE('Instance: %X', eip29.instance); TRANSLATE('ID Block Write: %X', eip29.idb_write_status); TRANSLATE('Cached Name: %[wwn]', eip29.cached_node_name); TRANSLATE('Last Poll node name: %[wwn]', eip29.last_poll_node_name); TRANSLATE('Cached PS TAG: %[tag]', eip29.cached_ps_tag); TRANSLATE('IDB PS TAG: %[tag]', eip29.id_ps_tag); TRANSLATE('Cached VOL TAG: %[tag]', eip29.cached_vol_tag); TRANSLATE('IDB VOL TAG: %[tag]', eip29.id_vol_tag); CONDITIONAL(eip29.enclosure != 99, TRANSLATE('Enclosure: %d.', eip29.enclosure )); CONDITIONAL(eip29.bay != 99, TRANSLATE('Bay: %d.', eip29.bay )); ENDTRANSLATIONBLOCK EC BLOCK: 03280029 SCID_SCS_DRIVE_ID_MISMATCH_NO_ACTION TRANSLATIONBLOCK TRANSLATE('Instance: %X', eip29.instance); TRANSLATE('ID Block Write: %X', eip29.idb_write_status); TRANSLATE('Cached Name: %[wwn]', eip29.cached_node_name); TRANSLATE('Last Poll node name: %[wwn]', eip29.last_poll_node_name); TRANSLATE('Cached PS TAG: %[tag]', eip29.cached_ps_tag); TRANSLATE('IDB PS TAG: %[tag]', eip29.id_ps_tag); TRANSLATE('Cached VOL TAG: %[tag]', eip29.cached_vol_tag); TRANSLATE('IDB VOL TAG: %[tag]', eip29.id_vol_tag); CONDITIONAL(eip29.enclosure != 99, TRANSLATE('Enclosure: %d.', eip29.enclosure )); CONDITIONAL(eip29.bay != 99, TRANSLATE('Bay: %d.', eip29.bay )); ENDTRANSLATIONBLOCK

EC BLOCK: 0329002a SCID_SCS_CVM_COMMIT_RECOVERY TRANSLATIONBLOCK TRANSLATE('RSS0 Member mask: %08X', eip2A.rss0_member_mask); TRANSLATE('CVM IO mask: %08X', eip2A.io_mask); TRANSLATE('CVM Success Rewrite: %08X', eip2A.success_rewrite); TRANSLATE('CVM Incarnation: %d', eip2A.incarnation); ENDTRANSLATIONBLOCK EC BLOCK: 032a0018 SCID_SCS_MIGRATION_FAILURE TRANSLATIONBLOCK TRANSLATE('Disk Group tag: %[tag]', eip18.ldad_tag); TRANSLATE('Source Redundant Storage Set: %04X', eip18.source_rss); TRANSLATE('Target Redundant Storage Set: %04X', eip18.target_rss); ENDTRANSLATIONBLOCK EC BLOCK: 0330000a SCID_SCS_SCRUB_REQUEST TRANSLATIONBLOCK TRANSLATE('Storage System: %[tag]', eip0A.scell_tag); TRANSLATE('Requestor Program Counter: %08x (%s)', eip0A.pc, XLATE_PC_CURRENT(eip0A.pc)); TRANSLATE('Requestor Scrub Type: %d (%[scs_scrub_types])', eip0A.scrub_type, eip0A.scrub_type); TRANSLATE('DebugFlags: %08X', eip0A.debug_flags); ENDTRANSLATIONBLOCK EC BLOCK: 0331000a SCID_SCS_SCRUBBED TRANSLATIONBLOCK TRANSLATE('Requestor Program Counter: %08x (%s)', eip0A.pc, XLATE_PC_CURRENT(eip0A.pc)); TRANSLATE('Requestor Scrub Type: %d (%[scs_scrub_types])', eip0A.scrub_type, eip0A.scrub_type); TRANSLATE('DebugFlags: %08X', eip0A.debug_flags); ENDTRANSLATIONBLOCK EC BLOCK: 0332000a SCID_SCS_INVALID_SCRUB TRANSLATIONBLOCK TRANSLATE('Requestor Program Counter: %08x', eip0A.pc); TRANSLATE('Requestor Scrub Type: %d', eip0A.scrub_type); TRANSLATE('DebugFlags: %08X', eip0A.debug_flags); TRANSLATE('Reboot Flags: %08X', eip0A.reboot_flags); TRANSLATE('fm_fatal_scrub: %d', eip0A.fm_fatal_scrub); TRANSLATE('scrub_valid: %08X', eip0A.scrub_valid); ENDTRANSLATIONBLOCK EC BLOCK: 03400021 SCID_SCS_CACHE_FAST_FAILOVER_DONE TRANSLATIONBLOCK TRANSLATE('Storage System Virtual Disk: %[tag]', eip21.target_tag); TRANSLATE('Status: %d', eip21.status); CONDITIONAL(eip21.status == 0, TRANSLATE('Success')); CONDITIONAL(eip21.status != 0, TRANSLATE('Error')); ENDTRANSLATIONBLOCK EC BLOCK: 03410021 SCID_SCS_CLEAR_CONTAINER_DONE TRANSLATIONBLOCK TRANSLATE('Storage System Virtual Disk: %[tag]', eip21.target_tag); TRANSLATE('Status: %d', eip21.status); CONDITIONAL(eip21.status == 0, TRANSLATE('Success')); CONDITIONAL(eip21.status != 0, TRANSLATE('Error')); ENDTRANSLATIONBLOCK

EC BLOCK: 03420021 SCID_SCS_SCVD_SNAP_DELETE_DONE TRANSLATIONBLOCK TRANSLATE('Storage System Virtual Disk: %[tag]', eip21.target_tag); TRANSLATE('Snap Storage System Virtual Disk: %[tag]', eip21.aux_tag); TRANSLATE('Status: %d', eip21.status); CONDITIONAL(eip21.status == 0, TRANSLATE('Success')); CONDITIONAL(eip21.status != 0, TRANSLATE('Error')); ENDTRANSLATIONBLOCK EC BLOCK: 03430021 SCID_SCS_SCVD_SET_CAPACITY_DONE TRANSLATIONBLOCK TRANSLATE('Storage System Virtual Disk: %[tag]', eip21.target_tag); TRANSLATE('Size: %z', eip21.size); TRANSLATE('Status: %d', eip21.status); CONDITIONAL(eip21.status == 0, TRANSLATE('Success')); CONDITIONAL(eip21.status != 0, TRANSLATE('Error')); ENDTRANSLATIONBLOCK EC BLOCK: 03440021 SCID_SCS_SCVD_RESERVE_CAPACITY_DONE TRANSLATIONBLOCK TRANSLATE('Storage System Virtual Disk: %[tag]', eip21.target_tag); TRANSLATE('Size: %z', eip21.size); TRANSLATE('Status: %d', eip21.status); CONDITIONAL(eip21.status == 0, TRANSLATE('Success')); CONDITIONAL(eip21.status != 0, TRANSLATE('Error')); ENDTRANSLATIONBLOCK EC BLOCK: 03450021 SCID_SCS_SCVD_CACHE_FLUSH_DONE TRANSLATIONBLOCK TRANSLATE('Storage System Virtual Disk: %[tag]', eip21.target_tag); TRANSLATE('Status: %d', eip21.status); CONDITIONAL(eip21.status == 0, TRANSLATE('Success')); CONDITIONAL(eip21.status != 0, TRANSLATE('Error')); ENDTRANSLATIONBLOCK EC BLOCK: 03600021 SCID_SCS_LDISK_OPERATION_DONE TRANSLATIONBLOCK TRANSLATE('Logical Disk: %[tag]', eip21.target_tag); TRANSLATE('Storage System Virtual Disk: %[tag]', eip21.parent_tag); TRANSLATE('Operation: %[scmi_scvd_operation]', eip21.operation); ENDTRANSLATIONBLOCK EC BLOCK: 0400031c SCID_FM_TE TRANSLATIONBLOCK TRANSLATE( 'Termination code: 0x%08x (%s)', eip1C.lter.termination_event.u.value, XLATE_TC_FLO( eip1C.lter.termination_event.u.value, eip1C.lter.ctrlr_model_id, eip1C.lter.baselevel_id, eip1C.lter.sw_version ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 0, TRANSLATE( 'Termination parameter[0]: 0x%08x', eip1C.lter.termination_event.params.param[0]

) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 1, TRANSLATE( 'Termination parameter[1]: 0x%08x', eip1C.lter.termination_event.params.param[1] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 2, TRANSLATE( 'Termination parameter[2]: 0x%08x', eip1C.lter.termination_event.params.param[2] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 3, TRANSLATE( 'Termination parameter[3]: 0x%08x', eip1C.lter.termination_event.params.param[3] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 4, TRANSLATE( 'Termination parameter[4]: 0x%08x', eip1C.lter.termination_event.params.param[4] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 5, TRANSLATE( 'Termination parameter[5]: 0x%08x', eip1C.lter.termination_event.params.param[5] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 6, TRANSLATE( 'Termination parameter[6]: 0x%08x', eip1C.lter.termination_event.params.param[6] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 7, TRANSLATE( 'Termination parameter[7]: 0x%08x', eip1C.lter.termination_event.params.param[7] ) ); CONDITIONAL( eip1C.header.revision > 0 &&

eip1C.lter.termination_event.u.code.parc > 8, TRANSLATE( 'Termination parameter[8]: 0x%08x', eip1C.lter.termination_event.params.param[8] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 9, TRANSLATE( 'Termination parameter[9]: 0x%08x', eip1C.lter.termination_event.params.param[9] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 10, TRANSLATE( 'Termination parameter[10]: 0x%08x', eip1C.lter.termination_event.params.param[10] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 11, TRANSLATE( 'Termination parameter[11]: 0x%08x', eip1C.lter.termination_event.params.param[11] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 12, TRANSLATE( 'Termination parameter[12]: 0x%08x', eip1C.lter.termination_event.params.param[12] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 13, TRANSLATE( 'Termination parameter[13]: 0x%08x', eip1C.lter.termination_event.params.param[13] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 14, TRANSLATE( 'Termination parameter[14]: 0x%08x', eip1C.lter.termination_event.params.param[14] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 15, TRANSLATE( 'Termination parameter[15]: 0x%08x', eip1C.lter.termination_event.params.param[15]

) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 16, TRANSLATE( 'Termination parameter[16]: 0x%08x', eip1C.lter.termination_event.params.param[16] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 17, TRANSLATE( 'Termination parameter[17]: 0x%08x', eip1C.lter.termination_event.params.param[17] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 18, TRANSLATE( 'Termination parameter[18]: 0x%08x', eip1C.lter.termination_event.params.param[18] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 19, TRANSLATE( 'Termination parameter[19]: 0x%08x', eip1C.lter.termination_event.params.param[19] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 20, TRANSLATE( 'Termination parameter[20]: 0x%08x', eip1C.lter.termination_event.params.param[20] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 21, TRANSLATE( 'Termination parameter[21]: 0x%08x', eip1C.lter.termination_event.params.param[21] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 22, TRANSLATE( 'Termination parameter[22]: 0x%08x', eip1C.lter.termination_event.params.param[22] ) ); CONDITIONAL( eip1C.header.revision > 0 &&

eip1C.lter.termination_event.u.code.parc > 23, TRANSLATE( 'Termination parameter[23]: 0x%08x', eip1C.lter.termination_event.params.param[23] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 24, TRANSLATE( 'Termination parameter[24]: 0x%08x', eip1C.lter.termination_event.params.param[24] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 25, TRANSLATE( 'Termination parameter[25]: 0x%08x', eip1C.lter.termination_event.params.param[25] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 26, TRANSLATE( 'Termination parameter[26]: 0x%08x', eip1C.lter.termination_event.params.param[26] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 27, TRANSLATE( 'Termination parameter[27]: 0x%08x', eip1C.lter.termination_event.params.param[27] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 28, TRANSLATE( 'Termination parameter[28]: 0x%08x', eip1C.lter.termination_event.params.param[28] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 29, TRANSLATE( 'Termination parameter[29]: 0x%08x', eip1C.lter.termination_event.params.param[29] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 30, TRANSLATE( 'Termination parameter[30]: 0x%08x', eip1C.lter.termination_event.params.param[30]

) ); TRANSLATE( 'Termination corrective action code: 0x%02x', eip1C.lter.termination_event.u.code.cac ); TRANSLATE( 'Termination location: 0x%08x', eip1C.lter.termination_event.termination_location ); TRANSLATE( 'Termination date/time: %[scmitim]', eip1C.lter.termination_time ); TRANSLATE( 'Terminating controller: %[scmi_obj_hnd]', eip1C.lter.terminating_ctrlr ); TRANSLATE( 'Termination event sequence number: %d.', eip1C.lter.seq ); TRANSLATE( 'Terminating controller's software version: %s', eip1C.lter.sw_version ); TRANSLATE( 'Terminating controller's baselevel ID: %s', eip1C.lter.baselevel_id ); TRANSLATE( 'Controller uptime: %y. seconds', eip1C.lter.uptime ); ENDTRANSLATIONBLOCK EC BLOCK: 0401031c SCID_FM_LAST_GASP TRANSLATIONBLOCK TRANSLATE( 'Termination code: 0x%08x (%s)', eip1C.lter.termination_event.u.value, XLATE_TC_FLO( eip1C.lter.termination_event.u.value, eip1C.lter.ctrlr_model_id, eip1C.lter.baselevel_id, eip1C.lter.sw_version ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 0, TRANSLATE( 'Termination parameter[0]: 0x%08x', eip1C.lter.termination_event.params.param[0] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 1, TRANSLATE(

'Termination parameter[1]: 0x%08x', eip1C.lter.termination_event.params.param[1] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 2, TRANSLATE( 'Termination parameter[2]: 0x%08x', eip1C.lter.termination_event.params.param[2] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 3, TRANSLATE( 'Termination parameter[3]: 0x%08x', eip1C.lter.termination_event.params.param[3] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 4, TRANSLATE( 'Termination parameter[4]: 0x%08x', eip1C.lter.termination_event.params.param[4] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 5, TRANSLATE( 'Termination parameter[5]: 0x%08x', eip1C.lter.termination_event.params.param[5] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 6, TRANSLATE( 'Termination parameter[6]: 0x%08x', eip1C.lter.termination_event.params.param[6] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 7, TRANSLATE( 'Termination parameter[7]: 0x%08x', eip1C.lter.termination_event.params.param[7] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 8, TRANSLATE( 'Termination parameter[8]: 0x%08x', eip1C.lter.termination_event.params.param[8] ) );

CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 9, TRANSLATE( 'Termination parameter[9]: 0x%08x', eip1C.lter.termination_event.params.param[9] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 10, TRANSLATE( 'Termination parameter[10]: 0x%08x', eip1C.lter.termination_event.params.param[10] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 11, TRANSLATE( 'Termination parameter[11]: 0x%08x', eip1C.lter.termination_event.params.param[11] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 12, TRANSLATE( 'Termination parameter[12]: 0x%08x', eip1C.lter.termination_event.params.param[12] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 13, TRANSLATE( 'Termination parameter[13]: 0x%08x', eip1C.lter.termination_event.params.param[13] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 14, TRANSLATE( 'Termination parameter[14]: 0x%08x', eip1C.lter.termination_event.params.param[14] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 15, TRANSLATE( 'Termination parameter[15]: 0x%08x', eip1C.lter.termination_event.params.param[15] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 16, TRANSLATE(

'Termination parameter[16]: 0x%08x', eip1C.lter.termination_event.params.param[16] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 17, TRANSLATE( 'Termination parameter[17]: 0x%08x', eip1C.lter.termination_event.params.param[17] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 18, TRANSLATE( 'Termination parameter[18]: 0x%08x', eip1C.lter.termination_event.params.param[18] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 19, TRANSLATE( 'Termination parameter[19]: 0x%08x', eip1C.lter.termination_event.params.param[19] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 20, TRANSLATE( 'Termination parameter[20]: 0x%08x', eip1C.lter.termination_event.params.param[20] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 21, TRANSLATE( 'Termination parameter[21]: 0x%08x', eip1C.lter.termination_event.params.param[21] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 22, TRANSLATE( 'Termination parameter[22]: 0x%08x', eip1C.lter.termination_event.params.param[22] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 23, TRANSLATE( 'Termination parameter[23]: 0x%08x', eip1C.lter.termination_event.params.param[23] ) );

CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 24, TRANSLATE( 'Termination parameter[24]: 0x%08x', eip1C.lter.termination_event.params.param[24] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 25, TRANSLATE( 'Termination parameter[25]: 0x%08x', eip1C.lter.termination_event.params.param[25] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 26, TRANSLATE( 'Termination parameter[26]: 0x%08x', eip1C.lter.termination_event.params.param[26] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 27, TRANSLATE( 'Termination parameter[27]: 0x%08x', eip1C.lter.termination_event.params.param[27] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 28, TRANSLATE( 'Termination parameter[28]: 0x%08x', eip1C.lter.termination_event.params.param[28] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 29, TRANSLATE( 'Termination parameter[29]: 0x%08x', eip1C.lter.termination_event.params.param[29] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 30, TRANSLATE( 'Termination parameter[30]: 0x%08x', eip1C.lter.termination_event.params.param[30] ) ); TRANSLATE( 'Termination corrective action code: 0x%02x', eip1C.lter.termination_event.u.code.cac );

TRANSLATE( 'Termination location: %08x', eip1C.lter.termination_event.termination_location ); TRANSLATE( 'Termination date/time: %[scmitim]', eip1C.lter.termination_time ); TRANSLATE( 'Terminating controller: %[scmi_obj_hnd]', eip1C.lter.terminating_ctrlr ); TRANSLATE( 'Terminating controller's software version: %s', eip1C.lter.sw_version ); TRANSLATE( 'Terminating controller's baselevel ID: %s', eip1C.lter.baselevel_id ); TRANSLATE( 'Controller uptime: %y. seconds', eip1C.lter.uptime ); ENDTRANSLATIONBLOCK EC BLOCK: 04020101 SCID_FM_TPRE TRANSLATIONBLOCK TRANSLATE( 'Termination code: 0x%08x (%s)', eip01.ru.lter.termination_event.u.value, XLATE_TC_FLO( eip01.ru.lter.termination_event.u.value, eip01.ru.lter.ctrlr_model_id, eip01.ru.lter.baselevel_id, eip01.ru.lter.sw_version ) ); TRANSLATE( 'Termination location: 0x%08x', eip01.ru.lter.termination_event.termination_location ); TRANSLATE( 'Termination date/time: %[scmitim]', eip01.ru.lter.termination_time ); TRANSLATE( 'Terminating controller: %[scmi_obj_hnd]', eip01.ru.lter.terminating_ctrlr ); TRANSLATE( 'Terminating controller's software version: %s', eip01.ru.lter.sw_version ); TRANSLATE( 'Controller uptime: %y. seconds', eip01.ru.lter.uptime ); TRANSLATE( 'Post termination operation: %d. (%[fm_terminate_routines])',

eip01.ru.lter.reuea_index, eip01.ru.lter.reuea_index ); TRANSLATE( 'Trap type: 0x%08x', eip01.rei.tt ); TRANSLATE( 'Termination code: 0x%08x', eip01.rei.tc ); TRANSLATE( 'SRR0 register: 0x%08x', eip01.rei.srr0 ); TRANSLATE( 'LR register: 0x%08x', eip01.rei.lr ); TRANSLATE( 'Exception code: 0x%08x', eip01.rei.exception ); ENDTRANSLATIONBLOCK EC BLOCK: 04030102 SCID_FM_TPUE TRANSLATIONBLOCK TRANSLATE( 'Termination code: 0x%08x (%s)', eip02.ru.lter.termination_event.u.value, XLATE_TC_FLO( eip02.ru.lter.termination_event.u.value, eip02.ru.lter.ctrlr_model_id, eip02.ru.lter.baselevel_id, eip02.ru.lter.sw_version ) ); TRANSLATE( 'Termination location: 0x%08x', eip02.ru.lter.termination_event.termination_location ); TRANSLATE( 'Termination date/time: %[scmitim]', eip02.ru.lter.termination_time ); TRANSLATE( 'Terminating controller: %[scmi_obj_hnd]', eip02.ru.lter.terminating_ctrlr ); TRANSLATE( 'Terminating controller's software version: %s', eip02.ru.lter.sw_version ); TRANSLATE( 'Controller uptime: %y. seconds', eip02.ru.lter.uptime ); TRANSLATE( 'Unexpected event type: %d. (%[fm_ue])', eip02.uei.type,

eip02.uei.type ); TRANSLATE( 'Post termination operation: %d. (%[fm_terminate_routines])', eip02.uei.pto, eip02.uei.pto ); TRANSLATE( 'Parameter[0]: 0x%08x', eip02.uei.param[0] ); TRANSLATE( 'Parameter[1]: 0x%08x', eip02.uei.param[1] ); TRANSLATE( 'Parameter[2]: 0x%08x', eip02.uei.param[2] ); TRANSLATE( 'Parameter[3]: 0x%08x', eip02.uei.param[3] ); TRANSLATE( 'Parameter[3]: 0x%08x', eip02.uei.param[3] ); ENDTRANSLATIONBLOCK EC BLOCK: 04040003 SCID_FM_SCEL_VALIDATED TRANSLATIONBLOCK CONDITIONAL( eip03.cinfo.scelcbi.status == 0, TRANSLATE('Status: 0. (No problems found)'), TRANSLATE( 'Unexpected status: %d.', eip03.cinfo.scelcbi.status ) ); TRANSLATE( 'Current offset: %d.', eip03.cinfo.scelcbi.current_offset ); CONDITIONAL( eip03.cinfo.scelcbi.flags.time_set != 0, TRANSLATE('Time set'), TRANSLATE('Time not set') ); CONDITIONAL( eip03.cinfo.scelcbi.flags.time_synched != 0, TRANSLATE('Time synchronized'), TRANSLATE('Time not synchronized') ); CONDITIONAL( eip03.cinfo.scelcbi.flags.seq_reset != 0, TRANSLATE('Sequence number reset'), TRANSLATE('Sequence number not reset') ); CONDITIONAL( eip03.cinfo.scelcbi.flags.wrapped != 0,

TRANSLATE('Events wrapped'), TRANSLATE('Events not wrapped') ); TRANSLATE( 'Current EDBN: %d.', eip03.cinfo.scelcbi.current_edbn ); TRANSLATE( 'Start EDBN: %d.', eip03.cinfo.scelcbi.start_edbn ); TRANSLATE( 'End EDBN: %d.', eip03.cinfo.scelcbi.end_edbn ); TRANSLATE( 'Sequence reset EDBN: %d.', eip03.cinfo.scelcbi.seq_reset_edbn ); TRANSLATE( 'Event count: %d.', eip03.cinfo.scelcbi.event_count ); TRANSLATE( 'Sequence number: %d.', eip03.cinfo.scelcbi.sequence_number ); TRANSLATE( 'Loop index: %d.', eip03.minfo.scelmi.index ); TRANSLATE( 'Zero test buffer pointer: 0x%08x', eip03.minfo.scelmi.utp ); TRANSLATE( 'Current event pointer: 0x%08x', eip03.minfo.scelmi.current_eventp ); TRANSLATE( 'Current EDBN: %d.', eip03.minfo.scelmi.current_edbn ); TRANSLATE( 'Current sequence number: %d.', eip03.minfo.scelmi.current_seqn ); TRANSLATE( 'Previous offset: %d., 0x%04x', eip03.minfo.scelmi.previous_offset, eip03.minfo.scelmi.previous_offset ); TRANSLATE( 'Current offset: %d., 0x%04x', eip03.minfo.scelmi.current_offset, eip03.minfo.scelmi.current_offset ); TRANSLATE( 'Previous EDBN: %d.', eip03.minfo.scelmi.previous_edbn

); TRANSLATE( 'Previous sequence number: %d.', eip03.minfo.scelmi.previous_seqn ); CONDITIONAL( eip03.minfo.scelmi.end_found != 0, TRANSLATE('End found'), TRANSLATE('End not found') ); CONDITIONAL( eip03.minfo.scelmi.accept_new_to_old != 0, TRANSLATE('New to old acceptable'), TRANSLATE('New to old not acceptable') ); CONDITIONAL( eip03.minfo.scelmi.unequal_found != 0, TRANSLATE('Sequence number not as expected'), TRANSLATE('Sequence number as expected') ); TRANSLATE( 'I/O status: %d., 0x%08x', eip03.minfo.scelmi.iostatus, eip03.minfo.scelmi.iostatus ); ENDTRANSLATIONBLOCK EC BLOCK: 04050003 SCID_FM_SCEL_INITED TRANSLATIONBLOCK TRANSLATE( 'Status: 0x%02x (%[fm_mpvfc])', eip03.cinfo.scelcbi.status, eip03.cinfo.scelcbi.status ); TRANSLATE( 'Current offset: %d.', eip03.cinfo.scelcbi.current_offset ); CONDITIONAL( eip03.cinfo.scelcbi.flags.time_set != 0, TRANSLATE('Time set'), TRANSLATE('Time not set') ); CONDITIONAL( eip03.cinfo.scelcbi.flags.time_synched != 0, TRANSLATE('Time synchronized'), TRANSLATE('Time not synchronized') ); CONDITIONAL( eip03.cinfo.scelcbi.flags.seq_reset != 0, TRANSLATE('Sequence number reset'), TRANSLATE('Sequence number not reset') ); CONDITIONAL( eip03.cinfo.scelcbi.flags.wrapped != 0, TRANSLATE('Events wrapped'), TRANSLATE('Events not wrapped') ); TRANSLATE( 'Current EDBN: %d.',

eip03.cinfo.scelcbi.current_edbn ); TRANSLATE( 'Start EDBN: %d.', eip03.cinfo.scelcbi.start_edbn ); TRANSLATE( 'End EDBN: %d.', eip03.cinfo.scelcbi.end_edbn ); TRANSLATE( 'Sequence reset EDBN: %d.', eip03.cinfo.scelcbi.seq_reset_edbn ); TRANSLATE( 'Event count: %d.', eip03.cinfo.scelcbi.event_count ); TRANSLATE( 'Sequence number: %d.', eip03.cinfo.scelcbi.sequence_number ); TRANSLATE( 'Loop index: %d.', eip03.minfo.scelmi.index ); TRANSLATE( 'Zero test buffer pointer: 0x%08x', eip03.minfo.scelmi.utp ); TRANSLATE( 'Current event pointer: 0x%08x', eip03.minfo.scelmi.current_eventp ); TRANSLATE( 'Current EDBN: %d.', eip03.minfo.scelmi.current_edbn ); TRANSLATE( 'Current sequence number: %d.', eip03.minfo.scelmi.current_seqn ); TRANSLATE( 'Previous offset: %d., 0x%04X', eip03.minfo.scelmi.previous_offset, eip03.minfo.scelmi.previous_offset ); TRANSLATE( 'Current offset: %d., 0x%04X', eip03.minfo.scelmi.current_offset, eip03.minfo.scelmi.current_offset ); TRANSLATE( 'Previous EDBN: %d.', eip03.minfo.scelmi.previous_edbn ); TRANSLATE( 'Previous sequence number: %d.', eip03.minfo.scelmi.previous_seqn );

CONDITIONAL( eip03.minfo.scelmi.end_found != 0, TRANSLATE('End found'), TRANSLATE('End not found') ); CONDITIONAL( eip03.minfo.scelmi.accept_new_to_old != 0, TRANSLATE('New to old acceptable'), TRANSLATE('New to old not acceptable') ); CONDITIONAL( eip03.minfo.scelmi.unequal_found != 0, TRANSLATE('Sequence number not as expected'), TRANSLATE('Sequence number as expected') ); TRANSLATE( 'I/O status: %d., 0x%08x', eip03.minfo.scelmi.iostatus, eip03.minfo.scelmi.iostatus ); ENDTRANSLATIONBLOCK EC BLOCK: 04060803 SCID_FM_LOCAL_EVENTS_NR TRANSLATIONBLOCK TRANSLATE( 'Local events not reported: %d.', eip03.ainfo.events_not_reported ); ENDTRANSLATIONBLOCK EC BLOCK: 04070803 SCID_FM_REMOTE_EVENTS_NR TRANSLATIONBLOCK TRANSLATE( 'Remote events not reported: %d.', eip03.ainfo.events_not_reported ); ENDTRANSLATIONBLOCK EC BLOCK: 04080003 SCID_FM_SCTEL_INACC TRANSLATIONBLOCK TRANSLATE( 'Status: 0x%02x (%[fm_mpvfc])', eip03.cinfo.sctelcbi.status, eip03.cinfo.sctelcbi.status ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.time_set != 0, TRANSLATE('Time set'), TRANSLATE('Time not set') ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.time_synched != 0, TRANSLATE('Time synchronized'), TRANSLATE('Time not synchronized') ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.bctrlr_wrapped != 0, TRANSLATE('B events wrapped'), TRANSLATE('B events not wrapped') );

CONDITIONAL( eip03.cinfo.sctelcbi.flags.bctrlr_valid != 0, TRANSLATE('B events valid'), TRANSLATE('B events not valid') ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.actrlr_wrapped != 0, TRANSLATE('A events wrapped'), TRANSLATE('A events not wrapped') ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.actrlr_valid != 0, TRANSLATE('A events valid'), TRANSLATE('A events not valid') ); TRANSLATE( 'A Controller: %[uuid]', eip03.cinfo.sctelcbi.actrlr_id ); TRANSLATE( 'A MRU TEDBN: %d.', eip03.cinfo.sctelcbi.actrlr_mru_edbn ); TRANSLATE( 'B Controller: %[uuid]', eip03.cinfo.sctelcbi.bctrlr_id ); TRANSLATE( 'B MRU TEDBN: %d.', eip03.cinfo.sctelcbi.bctrlr_mru_edbn ); TRANSLATE( 'Loop index: %d.', eip03.minfo.sctelmi.index ); TRANSLATE( 'Current TEDBN: %d.', eip03.minfo.sctelmi.current_edbn ); TRANSLATE( 'End TEDBN: %d.', eip03.minfo.sctelmi.end_edbn ); CONDITIONAL( eip03.minfo.sctelmi.actrlr != 0, TRANSLATE('Is A controller'), TRANSLATE('Is not A controller') ); TRANSLATE( 'I/O status: %d., 0x%08x', eip03.minfo.sctelmi.iostatus, eip03.minfo.sctelmi.iostatus ); TRANSLATE( 'Hold buffer offset: %d., 0x%08x', eip03.minfo.sctelmi.hold_offset, eip03.minfo.sctelmi.hold_offset ); ENDTRANSLATIONBLOCK

EC BLOCK: 04090003 SCID_FM_SCTEL_VALIDATED TRANSLATIONBLOCK CONDITIONAL( eip03.cinfo.sctelcbi.status == 0, TRANSLATE('Status: 0. (No problems found)'), TRANSLATE( 'Unexpected status: %d.', eip03.cinfo.sctelcbi.status ) ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.time_set != 0, TRANSLATE('Time set'), TRANSLATE('Time not set') ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.time_synched != 0, TRANSLATE('Time synchronized'), TRANSLATE('Time not synchronized') ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.bctrlr_wrapped != 0, TRANSLATE('B events wrapped'), TRANSLATE('B events not wrapped') ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.bctrlr_valid != 0, TRANSLATE('B events valid'), TRANSLATE('B events not valid') ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.actrlr_wrapped != 0, TRANSLATE('A events wrapped'), TRANSLATE('A events not wrapped') ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.actrlr_valid != 0, TRANSLATE('A events valid'), TRANSLATE('A events not valid') ); TRANSLATE( 'A Controller: %[uuid]', eip03.cinfo.sctelcbi.actrlr_id ); TRANSLATE( 'A MRU TEDBN: %d.', eip03.cinfo.sctelcbi.actrlr_mru_edbn ); TRANSLATE( 'B Controller: %[uuid]', eip03.cinfo.sctelcbi.bctrlr_id ); TRANSLATE( 'B MRU TEDBN: %d.', eip03.cinfo.sctelcbi.bctrlr_mru_edbn ); TRANSLATE( 'Loop index: %d.', eip03.minfo.sctelmi.index );

TRANSLATE( 'Current TEDBN: %d.', eip03.minfo.sctelmi.current_edbn ); TRANSLATE( 'End TEDBN: %d.', eip03.minfo.sctelmi.end_edbn ); CONDITIONAL( eip03.minfo.sctelmi.actrlr != 0, TRANSLATE('Is A controller'), TRANSLATE('Is not A controller') ); TRANSLATE( 'I/O status: %d., 0x%08x', eip03.minfo.sctelmi.iostatus, eip03.minfo.sctelmi.iostatus ); TRANSLATE( 'Hold buffer offset: %d., 0x%08x', eip03.minfo.sctelmi.hold_offset, eip03.minfo.sctelmi.hold_offset ); ENDTRANSLATIONBLOCK EC BLOCK: 040a0003 SCID_FM_SCTEL_INITED TRANSLATIONBLOCK TRANSLATE( 'Status: 0x%02x (%[fm_mpvfc])', eip03.cinfo.sctelcbi.status, eip03.cinfo.sctelcbi.status ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.time_set != 0, TRANSLATE('Time set'), TRANSLATE('Time not set') ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.time_synched != 0, TRANSLATE('Time synchronized'), TRANSLATE('Time not synchronized') ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.bctrlr_wrapped != 0, TRANSLATE('B events wrapped'), TRANSLATE('B events not wrapped') ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.bctrlr_valid != 0, TRANSLATE('B events valid'), TRANSLATE('B events not valid') ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.actrlr_wrapped != 0, TRANSLATE('A events wrapped'), TRANSLATE('A events not wrapped') ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.actrlr_valid != 0, TRANSLATE('A events valid'),

TRANSLATE('A events not valid') ); TRANSLATE( 'A Controller: %[uuid]', eip03.cinfo.sctelcbi.actrlr_id ); TRANSLATE( 'A MRU TEDBN: %d.', eip03.cinfo.sctelcbi.actrlr_mru_edbn ); TRANSLATE( 'B Controller: %[uuid]', eip03.cinfo.sctelcbi.bctrlr_id ); TRANSLATE( 'B MRU TEDBN: %d.', eip03.cinfo.sctelcbi.bctrlr_mru_edbn ); TRANSLATE( 'Loop index: %d.', eip03.minfo.sctelmi.index ); TRANSLATE( 'Current TEDBN: %d.', eip03.minfo.sctelmi.current_edbn ); TRANSLATE( 'End TEDBN: %d.', eip03.minfo.sctelmi.end_edbn ); CONDITIONAL( eip03.minfo.sctelmi.actrlr != 0, TRANSLATE('Is A controller'), TRANSLATE('Is not A controller') ); TRANSLATE( 'I/O status: %d., 0x%08x', eip03.minfo.sctelmi.iostatus, eip03.minfo.sctelmi.iostatus ); TRANSLATE( 'Hold buffer offset: %d., 0x%08x', eip03.minfo.sctelmi.hold_offset, eip03.minfo.sctelmi.hold_offset ); ENDTRANSLATIONBLOCK EC BLOCK: 040b0003 SCID_FM_SCTEL_UPDATED TRANSLATIONBLOCK CONDITIONAL( eip03.cinfo.sctelcbi.status == 0, TRANSLATE('Status: 0. (No problems found)'), TRANSLATE( 'Unexpected status: %d.', eip03.cinfo.sctelcbi.status ) ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.time_set != 0, TRANSLATE('Time set'),

TRANSLATE('Time not set') ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.time_synched != 0, TRANSLATE('Time synchronized'), TRANSLATE('Time not synchronized') ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.bctrlr_wrapped != 0, TRANSLATE('B events wrapped'), TRANSLATE('B events not wrapped') ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.bctrlr_valid != 0, TRANSLATE('B events valid'), TRANSLATE('B events not valid') ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.actrlr_wrapped != 0, TRANSLATE('A events wrapped'), TRANSLATE('A events not wrapped') ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.actrlr_valid != 0, TRANSLATE('A events valid'), TRANSLATE('A events not valid') ); TRANSLATE( 'A Controller: %[uuid]', eip03.cinfo.sctelcbi.actrlr_id ); TRANSLATE( 'A MRU TEDBN: %d.', eip03.cinfo.sctelcbi.actrlr_mru_edbn ); TRANSLATE( 'B Controller: %[uuid]', eip03.cinfo.sctelcbi.bctrlr_id ); TRANSLATE( 'B MRU TEDBN: %d.', eip03.cinfo.sctelcbi.bctrlr_mru_edbn ); TRANSLATE( 'Loop index: %d.', eip03.minfo.sctelmi.index ); TRANSLATE( 'Current TEDBN: %d.', eip03.minfo.sctelmi.current_edbn ); TRANSLATE( 'End TEDBN: %d.', eip03.minfo.sctelmi.end_edbn ); CONDITIONAL( eip03.minfo.sctelmi.actrlr != 0, TRANSLATE('Is A controller'), TRANSLATE('Is not A controller') );

TRANSLATE( 'I/O status: %d., 0x%08x', eip03.minfo.sctelmi.iostatus, eip03.minfo.sctelmi.iostatus ); TRANSLATE( 'Hold buffer offset: %d., 0x%08x', eip03.minfo.sctelmi.hold_offset, eip03.minfo.sctelmi.hold_offset ); ENDTRANSLATIONBLOCK EC BLOCK: 040c0803 SCID_FM_BAD_REMOTE_EVENT TRANSLATIONBLOCK TRANSLATE( 'EIP event code: 0x%08x', eip03.ainfo.remote_event.u.value ); TRANSLATE( 'EIP type: 0x%02x', eip03.ainfo.remote_event.type ); TRANSLATE( 'EIP revision number: 0x%02x', eip03.ainfo.remote_event.revision ); TRANSLATE('EIP count: %d.', eip03.ainfo.remote_event.count); ENDTRANSLATIONBLOCK EC BLOCK: 040d0003 SCID_FM_QUIESCED TRANSLATIONBLOCK TRANSLATE( 'Quiescent type: %[fm_quiesce]', eip03.ainfo.quiesce_type ); ENDTRANSLATIONBLOCK EC BLOCK: 040e031c SCID_FM_TE_CPLD TRANSLATIONBLOCK TRANSLATE( 'Termination code: 0x%08x (%s)', eip1C.lter.termination_event.u.value, XLATE_TC_FLO( eip1C.lter.termination_event.u.value, eip1C.lter.ctrlr_model_id, eip1C.lter.baselevel_id, eip1C.lter.sw_version ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 0, TRANSLATE( 'Termination parameter[0]: 0x%08x', eip1C.lter.termination_event.params.param[0] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 1,

TRANSLATE( 'Termination parameter[1]: 0x%08x', eip1C.lter.termination_event.params.param[1] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 2, TRANSLATE( 'Termination parameter[2]: 0x%08x', eip1C.lter.termination_event.params.param[2] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 3, TRANSLATE( 'Termination parameter[3]: 0x%08x', eip1C.lter.termination_event.params.param[3] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 4, TRANSLATE( 'Termination parameter[4]: 0x%08x', eip1C.lter.termination_event.params.param[4] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 5, TRANSLATE( 'Termination parameter[5]: 0x%08x', eip1C.lter.termination_event.params.param[5] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 6, TRANSLATE( 'Termination parameter[6]: 0x%08x', eip1C.lter.termination_event.params.param[6] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 7, TRANSLATE( 'Termination parameter[7]: 0x%08x', eip1C.lter.termination_event.params.param[7] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 8, TRANSLATE( 'Termination parameter[8]: 0x%08x', eip1C.lter.termination_event.params.param[8] )

); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 9, TRANSLATE( 'Termination parameter[9]: 0x%08x', eip1C.lter.termination_event.params.param[9] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 10, TRANSLATE( 'Termination parameter[10]: 0x%08x', eip1C.lter.termination_event.params.param[10] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 11, TRANSLATE( 'Termination parameter[11]: 0x%08x', eip1C.lter.termination_event.params.param[11] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 12, TRANSLATE( 'Termination parameter[12]: 0x%08x', eip1C.lter.termination_event.params.param[12] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 13, TRANSLATE( 'Termination parameter[13]: 0x%08x', eip1C.lter.termination_event.params.param[13] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 14, TRANSLATE( 'Termination parameter[14]: 0x%08x', eip1C.lter.termination_event.params.param[14] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 15, TRANSLATE( 'Termination parameter[15]: 0x%08x', eip1C.lter.termination_event.params.param[15] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 16,

TRANSLATE( 'Termination parameter[16]: 0x%08x', eip1C.lter.termination_event.params.param[16] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 17, TRANSLATE( 'Termination parameter[17]: 0x%08x', eip1C.lter.termination_event.params.param[17] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 18, TRANSLATE( 'Termination parameter[18]: 0x%08x', eip1C.lter.termination_event.params.param[18] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 19, TRANSLATE( 'Termination parameter[19]: 0x%08x', eip1C.lter.termination_event.params.param[19] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 20, TRANSLATE( 'Termination parameter[20]: 0x%08x', eip1C.lter.termination_event.params.param[20] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 21, TRANSLATE( 'Termination parameter[21]: 0x%08x', eip1C.lter.termination_event.params.param[21] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 22, TRANSLATE( 'Termination parameter[22]: 0x%08x', eip1C.lter.termination_event.params.param[22] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 23, TRANSLATE( 'Termination parameter[23]: 0x%08x', eip1C.lter.termination_event.params.param[23] )

); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 24, TRANSLATE( 'Termination parameter[24]: 0x%08x', eip1C.lter.termination_event.params.param[24] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 25, TRANSLATE( 'Termination parameter[25]: 0x%08x', eip1C.lter.termination_event.params.param[25] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 26, TRANSLATE( 'Termination parameter[26]: 0x%08x', eip1C.lter.termination_event.params.param[26] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 27, TRANSLATE( 'Termination parameter[27]: 0x%08x', eip1C.lter.termination_event.params.param[27] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 28, TRANSLATE( 'Termination parameter[28]: 0x%08x', eip1C.lter.termination_event.params.param[28] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 29, TRANSLATE( 'Termination parameter[29]: 0x%08x', eip1C.lter.termination_event.params.param[29] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 30, TRANSLATE( 'Termination parameter[30]: 0x%08x', eip1C.lter.termination_event.params.param[30] ) ); TRANSLATE( 'Termination corrective action code: 0x%02x', eip1C.lter.termination_event.u.code.cac

); TRANSLATE( 'Termination location: 0x%08x', eip1C.lter.termination_event.termination_location ); TRANSLATE( 'Termination date/time: %[scmitim]', eip1C.lter.termination_time ); TRANSLATE( 'Second terminating controller: %[scmi_obj_hnd]', eip1C.lter.terminating_ctrlr ); TRANSLATE( 'Terminating controller's software version: %s', eip1C.lter.sw_version ); TRANSLATE( 'Controller uptime: %y. seconds', eip1C.lter.uptime ); ENDTRANSLATIONBLOCK EC BLOCK: 040f0003 SCID_FM_TEISP_SENT TRANSLATIONBLOCK CONDITIONAL( eip03.cinfo.sctelcbi.status == 0, TRANSLATE('Status: 0. (No problems found)'), TRANSLATE( 'Unexpected status: %d.', eip03.cinfo.sctelcbi.status ) ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.time_set != 0, TRANSLATE('Time set'), TRANSLATE('Time not set') ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.time_synched != 0, TRANSLATE('Time synchronized'), TRANSLATE('Time not synchronized') ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.bctrlr_wrapped != 0, TRANSLATE('B events wrapped'), TRANSLATE('B events not wrapped') ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.bctrlr_valid != 0, TRANSLATE('B events valid'), TRANSLATE('B events not valid') ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.actrlr_wrapped != 0, TRANSLATE('A events wrapped'), TRANSLATE('A events not wrapped') ); CONDITIONAL( eip03.cinfo.sctelcbi.flags.actrlr_valid != 0,

TRANSLATE('A events valid'), TRANSLATE('A events not valid') ); TRANSLATE( 'A Controller: %[uuid]', eip03.cinfo.sctelcbi.actrlr_id ); TRANSLATE( 'A MRU TEDBN: %d.', eip03.cinfo.sctelcbi.actrlr_mru_edbn ); TRANSLATE( 'B Controller: %[uuid]', eip03.cinfo.sctelcbi.bctrlr_id ); TRANSLATE( 'B MRU TEDBN: %d.', eip03.cinfo.sctelcbi.bctrlr_mru_edbn ); TRANSLATE( 'Loop index: %d.', eip03.minfo.sctelmi.index ); TRANSLATE( 'Current TEDBN: %d.', eip03.minfo.sctelmi.current_edbn ); TRANSLATE( 'End TEDBN: %d.', eip03.minfo.sctelmi.end_edbn ); CONDITIONAL( eip03.minfo.sctelmi.actrlr != 0, TRANSLATE('Is A controller'), TRANSLATE('Is not A controller') ); TRANSLATE( 'I/O status: %d., 0x%08x', eip03.minfo.sctelmi.iostatus, eip03.minfo.sctelmi.iostatus ); TRANSLATE( 'Hold buffer offset: %d., 0x%08x', eip03.minfo.sctelmi.hold_offset, eip03.minfo.sctelmi.hold_offset ); ENDTRANSLATIONBLOCK EC BLOCK: 04100803 SCID_FM_LOCAL_ISR_EVENTS_NR TRANSLATIONBLOCK TRANSLATE( 'ISR events not reported: %d.', eip03.ainfo.events_not_reported ); ENDTRANSLATIONBLOCK EC BLOCK: 04110803 SCID_FM_REMOTE_ISR_EVENTS_NR TRANSLATIONBLOCK TRANSLATE( 'ISR events not reported: %d.',

eip03.ainfo.events_not_reported ); ENDTRANSLATIONBLOCK EC BLOCK: 04120003 SCID_FM_LER_INTERVAL_CHANGED TRANSLATIONBLOCK CONDITIONAL( eip03.minfo.lerinfo.reporting_interval != 0, TRANSLATE( 'Last event reporting enabled, interval: %d. minutes', eip03.minfo.lerinfo.reporting_interval * 15 ), TRANSLATE('Last event reporting disabled') ); ENDTRANSLATIONBLOCK EC BLOCK: 04130003 SCID_FM_LAST_EVENT_REPORTED TRANSLATIONBLOCK TRANSLATE('Last event information - '); TRANSLATE( ' Reporting interval: %d. minutes', eip03.minfo.lerinfo.reporting_interval * 15 ); TRANSLATE( ' Sequence number: %d.', eip03.minfo.lerinfo.sequence_number ); TRANSLATE( ' Report time: %[scmitim]', eip03.minfo.lerinfo.report_time ); TRANSLATE( ' Event code: %08X', eip03.minfo.lerinfo.header.u.value ); TRANSLATE('Primary controller last 30 seconds activity summary - '); TRANSLATE( ' Total requests per second: %d.', eip03.cinfo.stats30.total.rps ); TRANSLATE( ' Total KB per second: %d.', eip03.cinfo.stats30.total.kbs ); TRANSLATE( ' Host requests per second: %d.', eip03.cinfo.stats30.host.rps ); TRANSLATE( ' Host KB per second: %d.', eip03.cinfo.stats30.host.kbs ); ENDTRANSLATIONBLOCK EC BLOCK: 0414031d SCID_FM_TE_OLD TRANSLATIONBLOCK TRANSLATE( 'Termination code: 0x%08x (%s)', eip1D.lter.termination_event.u.value, XLATE_TC_FLO(

eip1D.lter.termination_event.u.value, eip1D.lter.ctrlr_model_id, eip1D.lter.baselevel_id, eip1D.lter.sw_version ) ); TRANSLATE( 'Termination corrective action code: 0x%02x', eip1D.lter.termination_event.u.code.cac ); TRANSLATE( 'Termination location: 0x%08x', eip1D.lter.termination_event.termination_location ); TRANSLATE( 'Termination date/time: %[scmitim]', eip1D.lter.termination_time ); TRANSLATE( 'Terminating controller: %[scmi_obj_hnd]', eip1D.lter.terminating_ctrlr ); TRANSLATE( 'Termination event sequence number: %d.', eip1D.lter.seq ); TRANSLATE( 'Terminating controller's software version: %s', eip1D.lter.sw_version ); TRANSLATE( 'Terminating controller's baselevel ID: %s', eip1D.lter.baselevel_id ); TRANSLATE( 'Controller uptime: %y. seconds', eip1D.lter.uptime ); ENDTRANSLATIONBLOCK EC BLOCK: 0415031d SCID_FM_LAST_GASP_OLD TRANSLATIONBLOCK TRANSLATE( 'Termination code: 0x%08x (%s)', eip1D.lter.termination_event.u.value, XLATE_TC_FLO( eip1D.lter.termination_event.u.value, eip1D.lter.ctrlr_model_id, eip1D.lter.baselevel_id, eip1D.lter.sw_version ) ); TRANSLATE( 'Termination corrective action code: 0x%02x', eip1D.lter.termination_event.u.code.cac ); TRANSLATE( 'Termination location: %08x', eip1D.lter.termination_event.termination_location );

TRANSLATE( 'Termination date/time: %[scmitim]', eip1D.lter.termination_time ); TRANSLATE( 'Terminating controller: %[scmi_obj_hnd]', eip1D.lter.terminating_ctrlr ); TRANSLATE( 'Terminating controller's software version: %s', eip1D.lter.sw_version ); TRANSLATE( 'Terminating controller's baselevel ID: %s', eip1D.lter.baselevel_id ); TRANSLATE( 'Controller uptime: %y. seconds', eip1D.lter.uptime ); ENDTRANSLATIONBLOCK EC BLOCK: 0416031d SCID_FM_TE_CPLD_OLD TRANSLATIONBLOCK TRANSLATE( 'Termination code: 0x%08x (%s)', eip1D.lter.termination_event.u.value, XLATE_TC_FLO( eip1D.lter.termination_event.u.value, eip1D.lter.ctrlr_model_id, eip1D.lter.baselevel_id, eip1D.lter.sw_version ) ); TRANSLATE( 'Termination corrective action code: 0x%02x', eip1D.lter.termination_event.u.code.cac ); TRANSLATE( 'Termination location: 0x%08x', eip1D.lter.termination_event.termination_location ); TRANSLATE( 'Termination date/time: %[scmitim]', eip1D.lter.termination_time ); TRANSLATE( 'Second terminating controller: %[scmi_obj_hnd]', eip1D.lter.terminating_ctrlr ); TRANSLATE( 'Terminating controller's software version: %s', eip1D.lter.sw_version ); TRANSLATE( 'Controller uptime: %y. seconds', eip1D.lter.uptime ); ENDTRANSLATIONBLOCK

EC BLOCK: 04180003 SCID_FM_MEAL_VALIDATED TRANSLATIONBLOCK CONDITIONAL( eip03.cinfo.mealcbi.status == 0, TRANSLATE('Status: 0. (No problems found)'), TRANSLATE( 'Unexpected status: %d.', eip03.cinfo.mealcbi.status ) ); TRANSLATE( 'Current offset: %d.', eip03.cinfo.mealcbi.current_offset ); CONDITIONAL( eip03.cinfo.mealcbi.flags.time_set != 0, TRANSLATE('Time set'), TRANSLATE('Time not set') ); CONDITIONAL( eip03.cinfo.mealcbi.flags.time_synched != 0, TRANSLATE('Time synchronized'), TRANSLATE('Time not synchronized') ); CONDITIONAL( eip03.cinfo.mealcbi.flags.seq_reset != 0, TRANSLATE('Sequence number reset'), TRANSLATE('Sequence number not reset') ); CONDITIONAL( eip03.cinfo.mealcbi.flags.wrapped != 0, TRANSLATE('Events wrapped'), TRANSLATE('Events not wrapped') ); TRANSLATE( 'Current EDBN: %d.', eip03.cinfo.mealcbi.current_edbn ); TRANSLATE( 'Start EDBN: %d.', eip03.cinfo.mealcbi.start_edbn ); TRANSLATE( 'End EDBN: %d.', eip03.cinfo.mealcbi.end_edbn ); TRANSLATE( 'Sequence reset EDBN: %d.', eip03.cinfo.mealcbi.seq_reset_edbn ); TRANSLATE( 'Event count: %d.', eip03.cinfo.mealcbi.event_count ); TRANSLATE( 'Sequence number: %d.', eip03.cinfo.mealcbi.sequence_number ); TRANSLATE( 'Loop index: %d.',

eip03.minfo.mealmi.index ); TRANSLATE( 'Zero test buffer pointer: 0x%08x', eip03.minfo.mealmi.utp ); TRANSLATE( 'Current event pointer: 0x%08x', eip03.minfo.mealmi.current_eventp ); TRANSLATE( 'Current EDBN: %d.', eip03.minfo.mealmi.current_edbn ); TRANSLATE( 'Current sequence number: %d.', eip03.minfo.mealmi.current_seqn ); TRANSLATE( 'Previous offset: %d., 0x%04x', eip03.minfo.mealmi.previous_offset, eip03.minfo.mealmi.previous_offset ); TRANSLATE( 'Current offset: %d., 0x%04x', eip03.minfo.mealmi.current_offset, eip03.minfo.mealmi.current_offset ); TRANSLATE( 'Previous EDBN: %d.', eip03.minfo.mealmi.previous_edbn ); TRANSLATE( 'Previous sequence number: %d.', eip03.minfo.mealmi.previous_seqn ); TRANSLATE( 'First sequence number: %d.', eip03.minfo.mealmi.first_seqn ); CONDITIONAL( eip03.minfo.mealmi.end_found != 0, TRANSLATE('End found'), TRANSLATE('End not found') ); CONDITIONAL( eip03.minfo.mealmi.accept_new_to_old != 0, TRANSLATE('New to old acceptable'), TRANSLATE('New to old not acceptable') ); CONDITIONAL( eip03.minfo.mealmi.unequal_found != 0, TRANSLATE('Sequence number not as expected'), TRANSLATE('Sequence number as expected') ); ENDTRANSLATIONBLOCK EC BLOCK: 04190003 SCID_FM_MEAL_INITED TRANSLATIONBLOCK TRANSLATE(

'Status: 0x%02x (%[fm_mpvfc])', eip03.cinfo.mealcbi.status, eip03.cinfo.mealcbi.status ); TRANSLATE( 'Current offset: %d.', eip03.cinfo.mealcbi.current_offset ); CONDITIONAL( eip03.cinfo.mealcbi.flags.time_set != 0, TRANSLATE('Time set'), TRANSLATE('Time not set') ); CONDITIONAL( eip03.cinfo.mealcbi.flags.time_synched != 0, TRANSLATE('Time synchronized'), TRANSLATE('Time not synchronized') ); CONDITIONAL( eip03.cinfo.mealcbi.flags.seq_reset != 0, TRANSLATE('Sequence number reset'), TRANSLATE('Sequence number not reset') ); CONDITIONAL( eip03.cinfo.mealcbi.flags.wrapped != 0, TRANSLATE('Events wrapped'), TRANSLATE('Events not wrapped') ); TRANSLATE( 'Current EDBN: %d.', eip03.cinfo.mealcbi.current_edbn ); TRANSLATE( 'Start EDBN: %d.', eip03.cinfo.mealcbi.start_edbn ); TRANSLATE( 'End EDBN: %d.', eip03.cinfo.mealcbi.end_edbn ); TRANSLATE( 'Sequence reset EDBN: %d.', eip03.cinfo.mealcbi.seq_reset_edbn ); TRANSLATE( 'Event count: %d.', eip03.cinfo.mealcbi.event_count ); TRANSLATE( 'Sequence number: %d.', eip03.cinfo.mealcbi.sequence_number ); TRANSLATE( 'Loop index: %d.', eip03.minfo.mealmi.index ); TRANSLATE( 'Zero test buffer pointer: 0x%08x', eip03.minfo.mealmi.utp );

TRANSLATE( 'Current event pointer: 0x%08x', eip03.minfo.mealmi.current_eventp ); TRANSLATE( 'Current EDBN: %d.', eip03.minfo.mealmi.current_edbn ); TRANSLATE( 'Current sequence number: %d.', eip03.minfo.mealmi.current_seqn ); TRANSLATE( 'Previous offset: %d., 0x%04X', eip03.minfo.mealmi.previous_offset, eip03.minfo.mealmi.previous_offset ); TRANSLATE( 'Current offset: %d., 0x%04X', eip03.minfo.mealmi.current_offset, eip03.minfo.mealmi.current_offset ); TRANSLATE( 'Previous EDBN: %d.', eip03.minfo.mealmi.previous_edbn ); TRANSLATE( 'Previous sequence number: %d.', eip03.minfo.mealmi.previous_seqn ); TRANSLATE( 'First sequence number: %d.', eip03.minfo.mealmi.first_seqn ); CONDITIONAL( eip03.minfo.mealmi.end_found != 0, TRANSLATE('End found'), TRANSLATE('End not found') ); CONDITIONAL( eip03.minfo.mealmi.accept_new_to_old != 0, TRANSLATE('New to old acceptable'), TRANSLATE('New to old not acceptable') ); CONDITIONAL( eip03.minfo.mealmi.unequal_found != 0, TRANSLATE('Sequence number not as expected'), TRANSLATE('Sequence number as expected') ); ENDTRANSLATIONBLOCK EC BLOCK: 041a031c SCID_FM_TE_PRETEND TRANSLATIONBLOCK TRANSLATE( 'Termination code: 0x%08x (%s)', eip1C.lter.termination_event.u.value, XLATE_TC_FLO( eip1C.lter.termination_event.u.value, eip1C.lter.ctrlr_model_id, eip1C.lter.baselevel_id,

eip1C.lter.sw_version ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 0, TRANSLATE( 'Termination parameter[0]: 0x%08x', eip1C.lter.termination_event.params.param[0] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 1, TRANSLATE( 'Termination parameter[1]: 0x%08x', eip1C.lter.termination_event.params.param[1] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 2, TRANSLATE( 'Termination parameter[2]: 0x%08x', eip1C.lter.termination_event.params.param[2] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 3, TRANSLATE( 'Termination parameter[3]: 0x%08x', eip1C.lter.termination_event.params.param[3] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 4, TRANSLATE( 'Termination parameter[4]: 0x%08x', eip1C.lter.termination_event.params.param[4] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 5, TRANSLATE( 'Termination parameter[5]: 0x%08x', eip1C.lter.termination_event.params.param[5] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 6, TRANSLATE( 'Termination parameter[6]: 0x%08x', eip1C.lter.termination_event.params.param[6] ) ); CONDITIONAL(

eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 7, TRANSLATE( 'Termination parameter[7]: 0x%08x', eip1C.lter.termination_event.params.param[7] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 8, TRANSLATE( 'Termination parameter[8]: 0x%08x', eip1C.lter.termination_event.params.param[8] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 9, TRANSLATE( 'Termination parameter[9]: 0x%08x', eip1C.lter.termination_event.params.param[9] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 10, TRANSLATE( 'Termination parameter[10]: 0x%08x', eip1C.lter.termination_event.params.param[10] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 11, TRANSLATE( 'Termination parameter[11]: 0x%08x', eip1C.lter.termination_event.params.param[11] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 12, TRANSLATE( 'Termination parameter[12]: 0x%08x', eip1C.lter.termination_event.params.param[12] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 13, TRANSLATE( 'Termination parameter[13]: 0x%08x', eip1C.lter.termination_event.params.param[13] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 14, TRANSLATE( 'Termination parameter[14]: 0x%08x',

eip1C.lter.termination_event.params.param[14] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 15, TRANSLATE( 'Termination parameter[15]: 0x%08x', eip1C.lter.termination_event.params.param[15] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 16, TRANSLATE( 'Termination parameter[16]: 0x%08x', eip1C.lter.termination_event.params.param[16] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 17, TRANSLATE( 'Termination parameter[17]: 0x%08x', eip1C.lter.termination_event.params.param[17] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 18, TRANSLATE( 'Termination parameter[18]: 0x%08x', eip1C.lter.termination_event.params.param[18] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 19, TRANSLATE( 'Termination parameter[19]: 0x%08x', eip1C.lter.termination_event.params.param[19] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 20, TRANSLATE( 'Termination parameter[20]: 0x%08x', eip1C.lter.termination_event.params.param[20] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 21, TRANSLATE( 'Termination parameter[21]: 0x%08x', eip1C.lter.termination_event.params.param[21] ) ); CONDITIONAL(

eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 22, TRANSLATE( 'Termination parameter[22]: 0x%08x', eip1C.lter.termination_event.params.param[22] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 23, TRANSLATE( 'Termination parameter[23]: 0x%08x', eip1C.lter.termination_event.params.param[23] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 24, TRANSLATE( 'Termination parameter[24]: 0x%08x', eip1C.lter.termination_event.params.param[24] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 25, TRANSLATE( 'Termination parameter[25]: 0x%08x', eip1C.lter.termination_event.params.param[25] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 26, TRANSLATE( 'Termination parameter[26]: 0x%08x', eip1C.lter.termination_event.params.param[26] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 27, TRANSLATE( 'Termination parameter[27]: 0x%08x', eip1C.lter.termination_event.params.param[27] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 28, TRANSLATE( 'Termination parameter[28]: 0x%08x', eip1C.lter.termination_event.params.param[28] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 29, TRANSLATE( 'Termination parameter[29]: 0x%08x',

eip1C.lter.termination_event.params.param[29] ) ); CONDITIONAL( eip1C.header.revision > 0 && eip1C.lter.termination_event.u.code.parc > 30, TRANSLATE( 'Termination parameter[30]: 0x%08x', eip1C.lter.termination_event.params.param[30] ) ); TRANSLATE( 'Termination corrective action code: 0x%02x', eip1C.lter.termination_event.u.code.cac ); TRANSLATE( 'Termination location: 0x%08x', eip1C.lter.termination_event.termination_location ); TRANSLATE( 'Termination date/time: %[scmitim]', eip1C.lter.termination_time ); TRANSLATE( 'Terminating controller: %[scmi_obj_hnd]', eip1C.lter.terminating_ctrlr ); TRANSLATE( 'Termination event sequence number: %d.', eip1C.lter.seq ); TRANSLATE( 'Terminating controller's software version: %s', eip1C.lter.sw_version ); TRANSLATE( 'Terminating controller's baselevel ID: %s', eip1C.lter.baselevel_id ); TRANSLATE( 'Controller uptime: %y. seconds', eip1C.lter.uptime ); ENDTRANSLATIONBLOCK EC BLOCK: 041b031d SCID_FM_TE_OLD_PRETEND TRANSLATIONBLOCK TRANSLATE( 'Termination code: 0x%08x (%s)', eip1D.lter.termination_event.u.value, XLATE_TC_FLO( eip1D.lter.termination_event.u.value, eip1D.lter.ctrlr_model_id, eip1D.lter.baselevel_id, eip1D.lter.sw_version ) ); TRANSLATE( 'Termination corrective action code: 0x%02x', eip1D.lter.termination_event.u.code.cac

); TRANSLATE( 'Termination location: 0x%08x', eip1D.lter.termination_event.termination_location ); TRANSLATE( 'Termination date/time: %[scmitim]', eip1D.lter.termination_time ); TRANSLATE( 'Terminating controller: %[scmi_obj_hnd]', eip1D.lter.terminating_ctrlr ); TRANSLATE( 'Termination event sequence number: %d.', eip1D.lter.seq ); TRANSLATE( 'Terminating controller's software version: %s', eip1D.lter.sw_version ); TRANSLATE( 'Terminating controller's baselevel ID: %s', eip1D.lter.baselevel_id ); TRANSLATE( 'Controller uptime: %y. seconds', eip1D.lter.uptime ); ENDTRANSLATIONBLOCK EC BLOCK: 06000009 SCID_FCS_SMART_FAILURE TRANSLATIONBLOCK TRANSLATE('Physical disk drive: %[tag]', eip09.device); TRANSLATE('Port ID: %s', eip09.cerp_id); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE('Last known enclosure: %d.', eip09.dencl_num - 100 ) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE('Last known bay: %d.', eip09.bay - 100)

); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE('Enclosure: %d.', eip09.dencl_num) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE('Bay: %d.', eip09.bay) ); CONDITIONAL(eip09.drv_fw_rev ne 'nofwrev', TRANSLATE('Unit Firmware Version: %s', eip09.drv_fw_rev) ); TRANSLATE('AL_PA: 0x%04x', eip09.al_pa); TRANSLATE('%s', XLATE_EIP09_OPCODE( eip09.fed_class, eip09.cmd.cdb10.opcode ) ); TRANSLATE( 'Sense Key: %1X (%[scsi_sensekey])', eip09.error.sense_data.sense_key, eip09.error.sense_data.sense_key ); TRANSLATE( 'ASC: 0x%02x ASCQ: 0x%02x (%[scsi_asc_ascq])', eip09.error.sense_data.sns.bytes.asc, eip09.error.sense_data.sns.bytes.asq, eip09.error.sense_data.sns.asc_asq ); TRANSLATE( 'FRU Code: 0x%02x', eip09.error.sense_data.fru_code ); TRANSLATE('Bay Bypass Mask Loop A 0x%X',eip09.bypassa); TRANSLATE('Bay Bypass Mask Loop B 0x%X',eip09.bypassb); TRANSLATE('Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information', eip09.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06014a08 SCID_FCS_LINK_FAILURE TRANSLATIONBLOCK TRANSLATE('Port ID: %s', eip08.cerp_id); TRANSLATE('Failure cause: %[fcs_fail]', eip08.failure_cause); TRANSLATE('Producer index: 0x%04x', eip08.peq_prod_index); TRANSLATE('Consumer index: 0x%04x', eip08.peq_cons_index); TRANSLATE('Frozen index: 0x%04x', eip08.peq_frz_prod_index); TRANSLATE('Port event block(s):'); CONDITIONAL( eip08.peb[0].type != 0, TRANSLATE( ' [0] Type: %08X Context: %08X',

eip08.peb[0].type, eip08.peb[0].context ) ); CONDITIONAL( eip08.peb[1].type != 0, TRANSLATE( ' [1] Type: %08X Context: %08X', eip08.peb[1].type, eip08.peb[1].context ) ); CONDITIONAL( eip08.peb[2].type != 0, TRANSLATE( ' [2] Type: %08X Context: %08X', eip08.peb[2].type, eip08.peb[2].context ) ); CONDITIONAL( eip08.peb[3].type != 0, TRANSLATE( ' [3] Type: %08X Context: %08X', eip08.peb[3].type, eip08.peb[3].context ) ); CONDITIONAL( eip08.peb[4].type != 0, TRANSLATE( ' [4] Type: %08X Context: %08X', eip08.peb[4].type, eip08.peb[4].context ) ); CONDITIONAL( eip08.peb[5].type != 0, TRANSLATE( ' [5] Type: %08X Context: %08X', eip08.peb[5].type, eip08.peb[5].context ) ); CONDITIONAL( eip08.peb[6].type != 0, TRANSLATE( ' [6] Type: %08X Context: %08X', eip08.peb[6].type, eip08.peb[6].context ) ); CONDITIONAL( eip08.peb[7].type != 0, TRANSLATE( ' [7] Type: %08X Context: %08X', eip08.peb[7].type, eip08.peb[7].context ) ); TRANSLATE('Retry Timer: %d seconds', eip08.time ); ENDTRANSLATIONBLOCK EC BLOCK: 06020009 SCID_FCS_CHECK_CONDITION TRANSLATIONBLOCK TRANSLATE('Target device: %[tag]', eip09.device); TRANSLATE('Port ID: %s', eip09.cerp_id);

CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE('Last known enclosure: %d.', eip09.dencl_num - 100 ) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.bay != 0x00 && eip09.dencl_num > 99, TRANSLATE('Last known bay: %d.', eip09.bay - 100) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num != 0x00 && eip09.dencl_num < 99, TRANSLATE('Enclosure: %d.', eip09.dencl_num) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.bay != 0x00 && eip09.dencl_num < 99, TRANSLATE('Bay: %d.', eip09.bay) ); CONDITIONAL(eip09.drv_fw_rev ne 'nofwrev', TRANSLATE('Unit Firmware Version: %s', eip09.drv_fw_rev) ); TRANSLATE('AL_PA: 0x%04x', eip09.al_pa); TRANSLATE('%s', XLATE_EIP09_OPCODE( eip09.fed_class, eip09.cmd.cdb10.opcode ) ); TRANSLATE( 'Sense Key: %1X (%[scsi_sensekey])', eip09.error.sense_data.sense_key, eip09.error.sense_data.sense_key

); TRANSLATE( 'ASC: 0x%02x ASCQ: 0x%02x (%[scsi_asc_ascq])', eip09.error.sense_data.sns.bytes.asc, eip09.error.sense_data.sns.bytes.asq, eip09.error.sense_data.sns.asc_asq ); TRANSLATE( 'FRU Code: 0x%02x', eip09.error.sense_data.fru_code ); TRANSLATE( 'LBA: 0x%02x%02x%02x%02x', eip09.cmd.cdb10.lba0, eip09.cmd.cdb10.lba1, eip09.cmd.cdb10.lba2, eip09.cmd.cdb10.lba3 ); TRANSLATE( 'Info: 0x%02x%02x%02x%02x', eip09.error.sense_data.info_0, eip09.error.sense_data.info_1, eip09.error.sense_data.info_2, eip09.error.sense_data.info_3 ); TRANSLATE('Bay Bypass Mask Loop A 0x%X',eip09.bypassa); TRANSLATE('Bay Bypass Mask Loop B 0x%X',eip09.bypassb); TRANSLATE('Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information', eip09.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06034713 SCID_FCS_DATA_EXCHANGE_TIMEOUT TRANSLATIONBLOCK TRANSLATE('Intended recipient: %[tag]', eip13.device); TRANSLATE('Port ID: %s', eip13.cerp_id); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE('Last known enclosure: %d.', eip13.dencl_num - 100 ) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE('Last known bay: %d.', eip13.bay - 100) );

CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE('Enclosure: %d.', eip13.dencl_num) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE('Bay: %d.', eip13.bay) ); TRANSLATE('AL_PA: 0x%04x', eip13.al_pa); TRANSLATE('Number of timeouts detected: %d.', eip13.num_times); TRANSLATE('Bay Bypass Mask Loop A 0x%X',eip13.bypassa); TRANSLATE('Bay Bypass Mask Loop B 0x%X',eip13.bypassb); TRANSLATE('Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information', eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06044812 SCID_FCS_UNEXPECTED_WORK TRANSLATIONBLOCK TRANSLATE('Sender: %[tag]', eip12.device); TRANSLATE('Port ID: %s', eip12.cerp_id); CONDITIONAL(eip12.al_pa != 0x01 && eip12.al_pa != 0x02 && eip12.al_pa != 0xEE && eip12.dencl_num == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip12.al_pa != 0x01 && eip12.al_pa != 0x02 && eip12.al_pa != 0xEE && eip12.dencl_num > 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip12.al_pa != 0x01 && eip12.al_pa != 0x02 && eip12.al_pa != 0xEE && eip12.dencl_num > 99, TRANSLATE('Last known enclosure: %d.', eip12.dencl_num - 100 ) ); CONDITIONAL(eip12.al_pa != 0x01 && eip12.al_pa != 0x02 && eip12.al_pa != 0xEE && eip12.dencl_num > 99, TRANSLATE('Last known bay: %d.', eip12.bay - 100) ); CONDITIONAL(eip12.al_pa != 0x01 && eip12.al_pa != 0x02 && eip12.al_pa != 0xEE && eip12.dencl_num < 99,

TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip12.al_pa != 0x01 && eip12.al_pa != 0x02 && eip12.al_pa != 0xEE && eip12.dencl_num < 99, TRANSLATE('Enclosure: %d.', eip12.dencl_num) ); CONDITIONAL(eip12.al_pa != 0x01 && eip12.al_pa != 0x02 && eip12.al_pa != 0xEE && eip12.dencl_num < 99, TRANSLATE('Bay: %d.', eip12.bay) ); TRANSLATE('AL_PA: 0x%04x', eip12.al_pa); TRANSLATE( 'Command descriptor block and Fibre Channel header information:' ); TRANSLATE('hdr_cdb[0]: %08X', eip12.hdr_cdb[0]); TRANSLATE('hdr_cdb[1]: %08X', eip12.hdr_cdb[1]); TRANSLATE('hdr_cdb[2]: %08X', eip12.hdr_cdb[2]); TRANSLATE('hdr_cdb[3]: %08X', eip12.hdr_cdb[3]); TRANSLATE('hdr_cdb[4]: %08X', eip12.hdr_cdb[4]); TRANSLATE('hdr_cdb[5]: %08X', eip12.hdr_cdb[5]); TRANSLATE('hdr_cdb[6]: %08X', eip12.hdr_cdb[6]); TRANSLATE('hdr_cdb[7]: %08X', eip12.hdr_cdb[7]); TRANSLATE('hdr_cdb[8]: %08X', eip12.hdr_cdb[8]); TRANSLATE('hdr_cdb[9]: %08X', eip12.hdr_cdb[9]); TRANSLATE('hdr_cdb[10]: %08X', eip12.hdr_cdb[10]); TRANSLATE('hdr_cdb[11]: %08X', eip12.hdr_cdb[11]); TRANSLATE('hdr_cdb[12]: %08X', eip12.hdr_cdb[12]); TRANSLATE('hdr_cdb[13]: %08X', eip12.hdr_cdb[13]); TRANSLATE('Bay Bypass Mask Loop A 0x%X',eip12.bypassa); TRANSLATE('Bay Bypass Mask Loop B 0x%X',eip12.bypassb); ENDTRANSLATIONBLOCK EC BLOCK: 06054909 SCID_FCS_BAD_ALPA TRANSLATIONBLOCK TRANSLATE('Intended target: %[tag]', eip09.device); TRANSLATE('Port ID: %s', eip09.cerp_id); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE('Last known enclosure: %d.', eip09.dencl_num - 100 ) );

CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE('Last known bay: %d.', eip09.bay - 100) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE('Enclosure: %d.', eip09.dencl_num) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE('Bay: %d.', eip09.bay) ); CONDITIONAL(eip09.drv_fw_rev ne 'nofwrev', TRANSLATE('Unit Firmware Version: %s', eip09.drv_fw_rev) ); TRANSLATE('AL_PA: 0x%04x', eip09.al_pa); TRANSLATE('%s', XLATE_EIP09_OPCODE( eip09.fed_class, eip09.cmd.cdb10.opcode ) ); TRANSLATE('Bay Bypass Mask Loop A 0x%X',eip09.bypassa); TRANSLATE('Bay Bypass Mask Loop B 0x%X',eip09.bypassb); TRANSLATE('Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information', eip09.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06074709 SCID_FCS_TDS_TIMEOUT TRANSLATIONBLOCK TRANSLATE('Physical disk drive: %[tag]', eip09.device); TRANSLATE('Port ID: %s', eip09.cerp_id); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE('Last known enclosure: %d.',

eip09.dencl_num - 100 ) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE('Last known bay: %d.', eip09.bay - 100) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE('Enclosure: %d.', eip09.dencl_num) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE('Bay: %d.', eip09.bay) ); CONDITIONAL(eip09.drv_fw_rev ne 'nofwrev', TRANSLATE('Unit Firmware Version: %s', eip09.drv_fw_rev) ); TRANSLATE('AL_PA: 0x%04x', eip09.al_pa); TRANSLATE('%s', XLATE_EIP09_OPCODE( eip09.fed_class, eip09.cmd.cdb10.opcode ) ); TRANSLATE('Bay Bypass Mask Loop A 0x%X',eip09.bypassa); TRANSLATE('Bay Bypass Mask Loop B 0x%X',eip09.bypassb); TRANSLATE('Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information', eip09.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06080007 SCID_FCS_LINK_ERRORS TRANSLATIONBLOCK TRANSLATE('Port ID: %s', eip07.cerp_id); TRANSLATE('Non-zero error counts:'); CONDITIONAL( eip07.loss_of_signal != 0, TRANSLATE('Loss of signal: %d.', eip07.loss_of_signal) ); CONDITIONAL( eip07.bad_rx_char != 0, TRANSLATE('Bad RX character: %d.', eip07.bad_rx_char) ); CONDITIONAL( eip07.loss_of_sync != 0, TRANSLATE('Loss of synch: %d.', eip07.loss_of_sync) ); CONDITIONAL( eip07.link_fail != 0, TRANSLATE('Link failure: %d.', eip07.link_fail) ); CONDITIONAL( eip07.rx_eofa != 0, TRANSLATE('RX EOFa delimiter: %d.', eip07.rx_eofa)

); CONDITIONAL( eip07.dis_frm != 0, TRANSLATE('Discarded frame: %d.', eip07.dis_frm) ); CONDITIONAL( eip07.bad_crc != 0, TRANSLATE('Frames with bad CRC and valid EOF: %d.', eip07.bad_crc) ); CONDITIONAL( eip07.proto_err != 0, TRANSLATE('N_Port protocol error: %d.', eip07.proto_err) ); CONDITIONAL( eip07.exp_frm != 0, TRANSLATE('Expired outbound frame: %d.', eip07.exp_frm) ); ENDTRANSLATIONBLOCK EC BLOCK: 06090013 SCID_FCS_SMART_FAILURE_COUNT TRANSLATIONBLOCK TRANSLATE('Physical disk drive: %[tag]', eip13.device); TRANSLATE('Port ID: %s', eip13.cerp_id); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE('Last known enclosure: %d.', eip13.dencl_num - 100 ) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE('Last known bay: %d.', eip13.bay - 100) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE('Enclosure: %d.', eip13.dencl_num) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE &&

eip13.dencl_num < 99, TRANSLATE('Bay: %d.', eip13.bay) ); TRANSLATE('AL_PA: 0x%04x', eip13.al_pa); TRANSLATE('Number of failure prediction threshold exceeded errors: %d.', eip13.num_times ); TRANSLATE('Bay Bypass Mask Loop A 0x%X',eip13.bypassa); TRANSLATE('Bay Bypass Mask Loop B 0x%X',eip13.bypassb); TRANSLATE('Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information', eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 060a0013 SCID_FCS_CHECK_CONDITION_COUNT TRANSLATIONBLOCK TRANSLATE('Physical disk drive: %[tag]', eip13.device); TRANSLATE('Port ID: %s', eip13.cerp_id); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE('Last known enclosure: %d.', eip13.dencl_num - 100 ) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE('Last known bay: %d.', eip13.bay - 100) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE('Enclosure: %d.', eip13.dencl_num) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE('Bay: %d.', eip13.bay)

); TRANSLATE('AL_PA: 0x%04x', TRANSLATE('Number of check eip13.num_times ); TRANSLATE('Bay Bypass Mask TRANSLATE('Bay Bypass Mask ENDTRANSLATIONBLOCK

eip13.al_pa); condition errors in last minute: %d.', Loop A 0x%X',eip13.bypassa); Loop B 0x%X',eip13.bypassb);

EC BLOCK: 060b4709 SCID_FCS_NONDATA_EXCH_TIMEOUT TRANSLATIONBLOCK TRANSLATE('Physical disk drive: %[tag]', eip09.device); TRANSLATE('Port ID: %s', eip09.cerp_id); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE('Last known enclosure: %d.', eip09.dencl_num - 100 ) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE('Last known bay: %d.', eip09.bay - 100) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE('Enclosure: %d.', eip09.dencl_num) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE('Bay: %d.', eip09.bay) ); CONDITIONAL(eip09.drv_fw_rev ne 'nofwrev', TRANSLATE('Unit Firmware Version: %s', eip09.drv_fw_rev) );

TRANSLATE('AL_PA: 0x%04x', eip09.al_pa); TRANSLATE('%s', XLATE_EIP09_OPCODE( eip09.fed_class, eip09.cmd.cdb10.opcode ) ); TRANSLATE('Bay Bypass Mask Loop A 0x%X',eip09.bypassa); TRANSLATE('Bay Bypass Mask Loop B 0x%X',eip09.bypassb); TRANSLATE('Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information', eip09.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 060c0013 SCID_FCS_LOOP_SWITCH TRANSLATIONBLOCK CONDITIONAL( eip13.switch_type == 1 , TRANSLATE('Switch Type: 3XX Family') ); CONDITIONAL( eip13.switch_type == 2 , TRANSLATE('Switch Type: 8XX Family') ); CONDITIONAL( eip13.switch_type == 2 , TRANSLATE('Node Name: %[tag]', eip13.device) ); CONDITIONAL( eip13.switch_type == 2 , TRANSLATE('AL_PA: 0x%04x', eip13.al_pa) ); TRANSLATE('Port ID: %s', eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 061a0009 SCID_FCS_DRIVE_SOFT_ERRORS TRANSLATIONBLOCK TRANSLATE('Physical disk drive: %[tag]', eip09.device); TRANSLATE('Port ID: %s', eip09.cerp_id); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE('Last known enclosure: %d.', eip09.dencl_num - 100 ) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE &&

eip09.dencl_num > 99, TRANSLATE('Last known bay: %d.', eip09.bay - 100) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE('Enclosure: %d.', eip09.dencl_num) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE('Bay: %d.', eip09.bay) ); CONDITIONAL(eip09.drv_fw_rev ne 'nofwrev', TRANSLATE('Unit Firmware Version: %s', eip09.drv_fw_rev) ); TRANSLATE('AL_PA: 0x%04x', eip09.al_pa); TRANSLATE('Bay Bypass Mask Loop A 0x%X',eip09.bypassa); TRANSLATE('Bay Bypass Mask Loop B 0x%X',eip09.bypassb); TRANSLATE('Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information', eip09.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 061c4709 SCID_FCS_FRAME_TIMEOUT TRANSLATIONBLOCK TRANSLATE('Physical disk drive: %[tag]', eip09.device); TRANSLATE('Port ID: %s', eip09.cerp_id); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE('Last known enclosure: %d.', eip09.dencl_num - 100 ) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE('Last known bay: %d.', eip09.bay - 100)

); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE('Enclosure: %d.', eip09.dencl_num) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE('Bay: %d.', eip09.bay) ); CONDITIONAL(eip09.drv_fw_rev ne 'nofwrev', TRANSLATE('Unit Firmware Version: %s', eip09.drv_fw_rev) ); TRANSLATE('AL_PA: 0x%04x', eip09.al_pa); TRANSLATE('%s', XLATE_EIP09_OPCODE( eip09.fed_class, eip09.cmd.cdb10.opcode ) ); TRANSLATE('Bay Bypass Mask Loop A 0x%X',eip09.bypassa); TRANSLATE('Bay Bypass Mask Loop B 0x%X',eip09.bypassb); TRANSLATE('Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information', eip09.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 061d4709 SCID_FCS_DROPPED_FRAME TRANSLATIONBLOCK TRANSLATE('Physical disk drive: %[tag]', eip09.device); TRANSLATE('Port ID: %s', eip09.cerp_id); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE('Last known enclosure: %d.', eip09.dencl_num - 100 ) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 &&

eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE('Last known bay: %d.', eip09.bay - 100) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE('Enclosure: %d.', eip09.dencl_num) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE('Bay: %d.', eip09.bay) ); CONDITIONAL(eip09.drv_fw_rev ne 'nofwrev', TRANSLATE('Unit Firmware Version: %s', eip09.drv_fw_rev) ); TRANSLATE('AL_PA: 0x%04x', eip09.al_pa); TRANSLATE('%s', XLATE_EIP09_OPCODE( eip09.fed_class, eip09.cmd.cdb10.opcode ) ); TRANSLATE('Bay Bypass Mask Loop A 0x%X',eip09.bypassa); TRANSLATE('Bay Bypass Mask Loop B 0x%X',eip09.bypassb); TRANSLATE('Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information', eip09.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 061e4c13 SCID_FCS_DRIVE_SPOF TRANSLATIONBLOCK TRANSLATE('Physical disk drive: %[tag]', eip13.device); TRANSLATE('Good port ID: %s', eip13.cerp_id); TRANSLATE('Missing port ID: %s', eip13.missing_cerp_id); TRANSLATE('Bypass Reason: 0x%02x', eip13.bypass_reason); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE('Last known enclosure: %d.',

eip13.dencl_num - 100 ) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE('Last known bay: %d.', eip13.bay - 100) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE('Enclosure: %d.', eip13.dencl_num) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE('Bay: %d.', eip13.bay) ); TRANSLATE('AL_PA: 0x%04x', eip13.al_pa); TRANSLATE('Bay Bypass Mask Loop A 0x%X',eip13.bypassa); TRANSLATE('Bay Bypass Mask Loop B 0x%X',eip13.bypassb); TRANSLATE('Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information', eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 061f0013 SCID_FCS_DRIVE_SPOF_FIXED TRANSLATIONBLOCK TRANSLATE('Physical disk drive: %[tag]', eip13.device); TRANSLATE('Port ID: %s', eip13.cerp_id); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE('Last known enclosure: %d.', eip13.dencl_num - 100 ) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 &&

eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE('Last known bay: %d.', eip13.bay - 100) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE('Enclosure: %d.', eip13.dencl_num) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE('Bay: %d.', eip13.bay) ); TRANSLATE('AL_PA: 0x%04x', eip13.al_pa); TRANSLATE('Bay Bypass Mask Loop A 0x%X',eip13.bypassa); TRANSLATE('Bay Bypass Mask Loop B 0x%X',eip13.bypassb); TRANSLATE('Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information', eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06204013 SCID_FCS_UNSUPPORTED_DRIVE TRANSLATIONBLOCK TRANSLATE('Physical disk drive: %[tag]', eip13.device); TRANSLATE('Port ID: %s', eip13.cerp_id); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE('Last known enclosure: %d.', eip13.dencl_num - 100 ) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE('Last known bay: %d.', eip13.bay - 100) ); CONDITIONAL(eip13.al_pa != 0x01 &&

eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE('Enclosure: %d.', eip13.dencl_num) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE('Bay: %d.', eip13.bay) ); TRANSLATE('AL_PA: 0x%04x', eip13.al_pa); TRANSLATE('Bay Bypass Mask Loop A 0x%X',eip13.bypassa); TRANSLATE('Bay Bypass Mask Loop B 0x%X',eip13.bypassb); TRANSLATE('Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information', eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06210013 SCID_FCS_WRONG_BLOCK_SIZE TRANSLATIONBLOCK TRANSLATE('Physical disk drive: %[tag]', eip13.device); TRANSLATE('Port ID: %s', eip13.cerp_id); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE('Last known enclosure: %d.', eip13.dencl_num - 100 ) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE('Last known bay: %d.', eip13.bay - 100) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE('Rack number not valid in this release') );

CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE('Enclosure: %d.', eip13.dencl_num) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE('Bay: %d.', eip13.bay) ); TRANSLATE('AL_PA: 0x%04x', eip13.al_pa); TRANSLATE('Bay Bypass Mask Loop A 0x%X',eip13.bypassa); TRANSLATE('Bay Bypass Mask Loop B 0x%X',eip13.bypassb); TRANSLATE('Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information', eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06230013 SCID_FCS_LINK_IS_RESTARTED TRANSLATIONBLOCK TRANSLATE('Port ID: %s', eip13.cerp_id); TRANSLATE('Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information', eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06280008 SCID_FCS_EMU_OB_RETRIES_EXHAUSTED TRANSLATIONBLOCK TRANSLATE('Port ID: %s', eip08.cerp_id); TRANSLATE('Enclosure: %d.', eip08.peq_prod_index); TRANSLATE('Bay: %d.', eip08.failure_cause); CONDITIONAL(eip08.peq_cons_index == 0, TRANSLATE('Loop: A')); CONDITIONAL(eip08.peq_cons_index == 1, TRANSLATE('Loop: B')); TRANSLATE('Retried task: 0x%04x', eip08.peq_frz_prod_index); TRANSLATE('Task list:'); CONDITIONAL( eip08.peb[0].type != 0, TRANSLATE( ' [0] Type: %08X Context: %08X', eip08.peb[0].type, eip08.peb[0].context ) ); CONDITIONAL( eip08.peb[1].type != 0, TRANSLATE( ' [1] Type: %08X Context: %08X', eip08.peb[1].type, eip08.peb[1].context ) ); CONDITIONAL( eip08.peb[2].type != 0, TRANSLATE( ' [2] Type: %08X Context: %08X', eip08.peb[2].type, eip08.peb[2].context ) ); CONDITIONAL( eip08.peb[3].type != 0, TRANSLATE( ' [3] Type: %08X Context: %08X', eip08.peb[3].type,

eip08.peb[3].context ) ); CONDITIONAL( eip08.peb[4].type != TRANSLATE( ' [4] Type: %08X Context: %08X', eip08.peb[4].type, eip08.peb[4].context ) ); CONDITIONAL( eip08.peb[5].type != TRANSLATE( ' [5] Type: %08X Context: %08X', eip08.peb[5].type, eip08.peb[5].context ) ); CONDITIONAL( eip08.peb[6].type != TRANSLATE( ' [6] Type: %08X Context: %08X', eip08.peb[6].type, eip08.peb[6].context ) ); CONDITIONAL( eip08.peb[7].type != TRANSLATE( ' [7] Type: %08X Context: %08X', eip08.peb[7].type, eip08.peb[7].context ) ); ENDTRANSLATIONBLOCK

0,

0,

0,

0,

EC BLOCK: 06290009 SCID_FCS_ABORT TRANSLATIONBLOCK TRANSLATE('Intended target: %[tag]', eip09.device); TRANSLATE('Port ID: %s', eip09.cerp_id); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE('Last known enclosure: %d.', eip09.dencl_num - 100 ) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE &&

eip09.dencl_num > 99, TRANSLATE('Last known bay: %d.', eip09.bay - 100) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE('Enclosure: %d.', eip09.dencl_num) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE('Bay: %d.', eip09.bay) ); CONDITIONAL(eip09.drv_fw_rev ne 'nofwrev', TRANSLATE('Unit Firmware Version: %s', eip09.drv_fw_rev) ); TRANSLATE('AL_PA: 0x%04x', eip09.al_pa); TRANSLATE('%s', XLATE_EIP09_OPCODE( eip09.fed_class, eip09.cmd.cdb10.opcode ) ); TRANSLATE('Bay Bypass Mask Loop A 0x%X',eip09.bypassa); TRANSLATE('Bay Bypass Mask Loop B 0x%X',eip09.bypassb); TRANSLATE('Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information', eip09.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 062a0009 SCID_FCS_RRQ TRANSLATIONBLOCK TRANSLATE('Intended target: %[tag]', eip09.device); TRANSLATE('Port ID: %s', eip09.cerp_id); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE('Last known enclosure: %d.', eip09.dencl_num - 100 ) );

CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE('Last known bay: %d.', eip09.bay - 100) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE('Enclosure: %d.', eip09.dencl_num) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE('Bay: %d.', eip09.bay) ); CONDITIONAL(eip09.drv_fw_rev ne 'nofwrev', TRANSLATE('Unit Firmware Version: %s', eip09.drv_fw_rev) ); TRANSLATE('AL_PA: 0x%04x', eip09.al_pa); TRANSLATE('%s', XLATE_EIP09_OPCODE( eip09.fed_class, eip09.cmd.cdb10.opcode ) ); TRANSLATE('Bay Bypass Mask Loop A 0x%X',eip09.bypassa); TRANSLATE('Bay Bypass Mask Loop B 0x%X',eip09.bypassb); TRANSLATE('Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information', eip09.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 062c0012 SCID_FCS_BBR TRANSLATIONBLOCK TRANSLATE('Physical disk drive: %[tag]', eip12.device); TRANSLATE('Port ID: %s', eip12.cerp_id); CONDITIONAL(eip12.al_pa != 0x01 && eip12.al_pa != 0x02 && eip12.al_pa != 0xEE && eip12.dencl_num == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip12.al_pa != 0x01 && eip12.al_pa != 0x02 && eip12.al_pa != 0xEE && eip12.dencl_num > 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip12.al_pa != 0x01 && eip12.al_pa != 0x02 && eip12.al_pa != 0xEE && eip12.dencl_num > 99, TRANSLATE('Last known enclosure: %d.',

eip12.dencl_num - 100 ) ); CONDITIONAL(eip12.al_pa != 0x01 && eip12.al_pa != 0x02 && eip12.al_pa != 0xEE && eip12.dencl_num > 99, TRANSLATE('Last known bay: %d.', eip12.bay - 100) ); CONDITIONAL(eip12.al_pa != 0x01 && eip12.al_pa != 0x02 && eip12.al_pa != 0xEE && eip12.dencl_num < 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip12.al_pa != 0x01 && eip12.al_pa != 0x02 && eip12.al_pa != 0xEE && eip12.dencl_num < 99, TRANSLATE('Enclosure: %d.', eip12.dencl_num) ); CONDITIONAL(eip12.al_pa != 0x01 && eip12.al_pa != 0x02 && eip12.al_pa != 0xEE && eip12.dencl_num < 99, TRANSLATE('Bay: %d.', eip12.bay) ); TRANSLATE('AL_PA: 0x%04x', eip12.al_pa); TRANSLATE('Media defects:'); CONDITIONAL( eip12.hdr_cdb[0] != 0, TRANSLATE( ' [0] LBA: %08X', eip12.hdr_cdb[0] ) ); CONDITIONAL( eip12.hdr_cdb[1] != 0, TRANSLATE( ' [1] LBA: %08X', eip12.hdr_cdb[1] ) ); CONDITIONAL( eip12.hdr_cdb[2] != 0, TRANSLATE( ' [2] LBA: %08X', eip12.hdr_cdb[2] ) ); CONDITIONAL( eip12.hdr_cdb[3] != 0, TRANSLATE( ' [3] LBA: %08X', eip12.hdr_cdb[3] ) ); CONDITIONAL( eip12.hdr_cdb[4] != 0, TRANSLATE( ' [4] LBA: %08X', eip12.hdr_cdb[4] ) ); CONDITIONAL( eip12.hdr_cdb[5] != 0,

TRANSLATE( ' [5] LBA: %08X', eip12.hdr_cdb[5] ) ); CONDITIONAL( eip12.hdr_cdb[6] != 0, TRANSLATE( ' [6] LBA: %08X', eip12.hdr_cdb[6] ) ); CONDITIONAL( eip12.hdr_cdb[7] != 0, TRANSLATE( ' [7] LBA: %08X', eip12.hdr_cdb[7] ) ); CONDITIONAL( eip12.hdr_cdb[8] != 0, TRANSLATE( ' [8] LBA: %08X', eip12.hdr_cdb[8] ) ); CONDITIONAL( eip12.hdr_cdb[9] != 0, TRANSLATE( ' [9] LBA: %08X', eip12.hdr_cdb[9] ) ); CONDITIONAL( eip12.hdr_cdb[10] != 0, TRANSLATE( ' [10] LBA: %08X', eip12.hdr_cdb[10] ) ); CONDITIONAL( eip12.hdr_cdb[11] != 0, TRANSLATE( ' [11] LBA: %08X', eip12.hdr_cdb[11] ) ); CONDITIONAL( eip12.hdr_cdb[12] != 0, TRANSLATE( ' [12] LBA: %08X', eip12.hdr_cdb[12] ) ); CONDITIONAL( eip12.hdr_cdb[13] != 0, TRANSLATE( ' [13] LBA: %08X', eip12.hdr_cdb[13] ) ); TRANSLATE('Bay Bypass Mask Loop A 0x%X',eip12.bypassa); TRANSLATE('Bay Bypass Mask Loop B 0x%X',eip12.bypassb); ENDTRANSLATIONBLOCK EC BLOCK: 062d0012 SCID_FCS_DIRECTED_LIP TRANSLATIONBLOCK TRANSLATE('Port ID: %s', eip12.cerp_id);

TRANSLATE('AL_PA: 0x%04x', eip12.al_pa); TRANSLATE('LIP Type:'); CONDITIONAL( eip12.hdr_cdb[0] == 0, TRANSLATE( ' LIP(F7,F7)' ) ); CONDITIONAL( eip12.hdr_cdb[0] == 1, TRANSLATE( ' DIRECTED RESET' ) ); TRANSLATE('Caller PC: 0x%08X', eip12.hdr_cdb[1]); ENDTRANSLATIONBLOCK EC BLOCK: 062e0012 SCID_FCS_LIP_F8 TRANSLATIONBLOCK TRANSLATE('Port ID: %s', eip12.cerp_id); TRANSLATE('Controller affected: %[tag]', eip12.device); CONDITIONAL( eip12.hdr_cdb[0] != 0, TRANSLATE( ' [0] Count/AL_PA (ccccaaaa): %08X', eip12.hdr_cdb[0] ) ); CONDITIONAL( eip12.hdr_cdb[1] != 0, TRANSLATE( ' [1] Count/AL_PA (ccccaaaa): %08X', eip12.hdr_cdb[1] ) ); CONDITIONAL( eip12.hdr_cdb[2] != 0, TRANSLATE( ' [2] Count/AL_PA (ccccaaaa): %08X', eip12.hdr_cdb[2] ) ); CONDITIONAL( eip12.hdr_cdb[3] != 0, TRANSLATE( ' [3] Count/AL_PA (ccccaaaa): %08X', eip12.hdr_cdb[3] ) ); CONDITIONAL( eip12.hdr_cdb[4] != 0, TRANSLATE( ' [4] Count/AL_PA (ccccaaaa): %08X', eip12.hdr_cdb[4] ) ); CONDITIONAL( eip12.hdr_cdb[5] != 0, TRANSLATE( ' [5] Count/AL_PA (ccccaaaa): %08X', eip12.hdr_cdb[5] ) ); CONDITIONAL( eip12.hdr_cdb[6] != 0, TRANSLATE( ' [6] Count/AL_PA (ccccaaaa): %08X', eip12.hdr_cdb[6] )

); CONDITIONAL( eip12.hdr_cdb[7] != 0, TRANSLATE( ' [7] Count/AL_PA (ccccaaaa): %08X', eip12.hdr_cdb[7] ) ); CONDITIONAL( eip12.hdr_cdb[8] != 0, TRANSLATE( ' [8] Count/AL_PA (ccccaaaa): %08X', eip12.hdr_cdb[8] ) ); CONDITIONAL( eip12.hdr_cdb[9] != 0, TRANSLATE( ' [9] Count/AL_PA (ccccaaaa): %08X', eip12.hdr_cdb[9] ) ); CONDITIONAL( eip12.hdr_cdb[10] != 0, TRANSLATE( ' [10] Count/AL_PA (ccccaaaa): %08X', eip12.hdr_cdb[10] ) ); CONDITIONAL( eip12.hdr_cdb[11] != 0, TRANSLATE( ' [11] Count/AL_PA (ccccaaaa): %08X', eip12.hdr_cdb[11] ) ); CONDITIONAL( eip12.hdr_cdb[12] != 0, TRANSLATE( ' [12] Count/AL_PA (ccccaaaa): %08X', eip12.hdr_cdb[12] ) ); CONDITIONAL( eip12.hdr_cdb[13] != 0, TRANSLATE( ' [13] Count/AL_PA (ccccaaaa): %08X', eip12.hdr_cdb[13] ) ); ENDTRANSLATIONBLOCK EC BLOCK: 06304e13 SCID_FCS_SHELF_SPOF TRANSLATIONBLOCK TRANSLATE('Enclosure: %[tag]', eip13.device); TRANSLATE('Good port ID: %s', eip13.cerp_id); TRANSLATE('Missing port ID: %s', eip13.missing_cerp_id); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num == 99, TRANSLATE('Rack and enclosure not known') ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99,

TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE('Last known enclosure: %d.', eip13.dencl_num - 100 ) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE('Enclosure: %d.', eip13.dencl_num) ); TRANSLATE('AL_PA: 0x%04x', eip13.al_pa); TRANSLATE('Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information', eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06310013 SCID_FCS_SHELF_SPOF_FIXED TRANSLATIONBLOCK TRANSLATE('Enclosure: %[tag]', eip13.device); TRANSLATE('Port ID: %s', eip13.cerp_id); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num == 99, TRANSLATE('Rack and enclosure not known') ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE('Last known enclosure: %d.', eip13.dencl_num - 100 ) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE &&

eip13.dencl_num < 99, TRANSLATE('Enclosure: %d.', eip13.dencl_num) ); TRANSLATE('Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information', eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06324e13 SCID_FCS_PORT_SPOF TRANSLATIONBLOCK TRANSLATE('Good port ID: %s', eip13.cerp_id); TRANSLATE('Missing port ID: %s', eip13.missing_cerp_id); TRANSLATE('Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information', eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06330013 SCID_FCS_PORT_SPOF_FIXED TRANSLATIONBLOCK TRANSLATE('Port ID: %s', eip13.cerp_id); TRANSLATE('Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information', eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06340013 SCID_FCS_ENABLE_DP TRANSLATIONBLOCK TRANSLATE('Port ID: %s', eip13.cerp_id); TRANSLATE('Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information', eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06364d04 SCID_FCS_UNSUPPORTED_FIRMWARE TRANSLATIONBLOCK TRANSLATE('Physical disk drive: %[tag]', eip04.device); TRANSLATE('Port ID: %s', eip04.cerp_id); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE('Last known enclosure: %d.', eip04.dencl_num - 100 ) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE('Last known bay: %d.', eip04.bay - 100) ); CONDITIONAL(eip04.al_pa != 0x01 &&

eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE('Enclosure: %d.', eip04.dencl_num) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE('Bay: %d.', eip04.bay) ); TRANSLATE('AL_PA: 0x%04x', eip04.al_pa); TRANSLATE('SCSI Product ID: %s', eip04.pid); TRANSLATE('Current firmware revision: %s', eip04.rev); TRANSLATE('Latest known revision: %s', eip04.new_rev); TRANSLATE('Bay Bypass Mask Loop A 0x%X',eip04.bypassa); TRANSLATE('Bay Bypass Mask Loop B 0x%X',eip04.bypassb); TRANSLATE('Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information', eip04.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 0637c404 SCID_FCS_LATER_FIRMWARE TRANSLATIONBLOCK TRANSLATE('Physical disk drive: %[tag]', eip04.device); TRANSLATE('Port ID: %s', eip04.cerp_id); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE('Last known enclosure: %d.', eip04.dencl_num - 100 ) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE('Last known bay: %d.', eip04.bay - 100) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE &&

eip04.dencl_num < 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE('Enclosure: %d.', eip04.dencl_num) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE('Bay: %d.', eip04.bay) ); TRANSLATE('AL_PA: 0x%04x', eip04.al_pa); TRANSLATE('SCSI Product ID: %s', eip04.pid); TRANSLATE('Current firmware revision: %s', eip04.rev); TRANSLATE('Latest known revision: %s', eip04.new_rev); TRANSLATE('Bay Bypass Mask Loop A 0x%X',eip04.bypassa); TRANSLATE('Bay Bypass Mask Loop B 0x%X',eip04.bypassb); TRANSLATE('Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information', eip04.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 0638c404 SCID_FCS_NEWER_FIRMWARE TRANSLATIONBLOCK TRANSLATE('Physical disk drive: %[tag]', eip04.device); TRANSLATE('Port ID: %s', eip04.cerp_id); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE('Last known enclosure: %d.', eip04.dencl_num - 100 ) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE('Last known bay: %d.', eip04.bay - 100) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE('Rack number not valid in this release')

); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE('Enclosure: %d.', eip04.dencl_num) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE('Bay: %d.', eip04.bay) ); TRANSLATE('AL_PA: 0x%04x', eip04.al_pa); TRANSLATE('SCSI Product ID: %s', eip04.pid); TRANSLATE('Current firmware revision: %s', eip04.rev); TRANSLATE('Latest known revision: %s', eip04.new_rev); TRANSLATE('Bay Bypass Mask Loop A 0x%X',eip04.bypassa); TRANSLATE('Bay Bypass Mask Loop B 0x%X',eip04.bypassb); TRANSLATE('Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information', eip04.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06394008 SCID_FCS_LOOP_RECOVERY_SLOT_BYPASSED TRANSLATIONBLOCK TRANSLATE('Port IDs: %s %s', eip08.cerp_id, eip08.other_cerp_id); TRANSLATE('Cabinet ID: %d', eip08.recovery.cab); TRANSLATE('Enclosure ID: %d', eip08.recovery.shelf); TRANSLATE('Bay: %d', eip08.recovery.slot); ENDTRANSLATIONBLOCK EC BLOCK: 063a0008 SCID_FCS_LOOP_RECOVERY_ENTERED TRANSLATIONBLOCK TRANSLATE('Port IDs: %s %s', eip08.cerp_id, eip08.other_cerp_id); TRANSLATE('Reason Code: %d', eip08.failure_cause); CONDITIONAL(eip08.failure_cause == 0x03, TRANSLATE('LID Recovery')); CONDITIONAL(eip08.failure_cause == 0x05, TRANSLATE('DDD Recovery')); ENDTRANSLATIONBLOCK EC BLOCK: 063b0008 SCID_FCS_LOOP_RECOVERY_EXIT TRANSLATIONBLOCK TRANSLATE('Port IDs: %s %s', eip08.cerp_id, eip08.other_cerp_id); TRANSLATE('Recovery Status: 0x%x', eip08.failure_cause); CONDITIONAL(eip08.failure_cause == 0, TRANSLATE('Recovery Status Text: Success')); CONDITIONAL(eip08.failure_cause == 1, TRANSLATE('Recovery Status Text: Exhausted retry count for FNB')); CONDITIONAL(eip08.failure_cause == 2, TRANSLATE('Recovery Status Text: No valid FNBs')); CONDITIONAL(eip08.failure_cause == 3, TRANSLATE('Recovery Status Text: No open DUB gates')); CONDITIONAL(eip08.failure_cause == 4, TRANSLATE('Recovery Status Text: Fibre channel error')); CONDITIONAL(eip08.failure_cause == 5, TRANSLATE('Recovery Status Text: CBIC codeload in progress')); CONDITIONAL(eip08.failure_cause == 6, TRANSLATE('Recovery Status Text: CBIC communications over IIC')); CONDITIONAL(eip08.failure_cause == 7,

TRANSLATE('Recovery Status Text: Failed to enter FCS Maint Mode')); CONDITIONAL(eip08.failure_cause == 8, TRANSLATE('Recovery Status Text: Partial success')); CONDITIONAL(eip08.failure_cause == 9, TRANSLATE('Recovery Status Text: Task aborted')); CONDITIONAL(eip08.failure_cause == 10, TRANSLATE('Recovery Status Text: No progress made')); CONDITIONAL(eip08.failure_cause == 11, TRANSLATE('Recovery Status Text: Semaphore wait timed out')); CONDITIONAL(eip08.failure_cause == 12, TRANSLATE('Recovery Status Text: Exceeded max failure threshold for loop recover y')); CONDITIONAL(eip08.failure_cause == 13, TRANSLATE('Recovery Status Text: User disabled loop recoveries')); ENDTRANSLATIONBLOCK EC BLOCK: 063c0008 SCID_FCS_LOOP_RECOVERY_ABORT TRANSLATIONBLOCK TRANSLATE('Port IDs: %s %s', eip08.cerp_id, eip08.other_cerp_id); TRANSLATE('Progress: %x', eip08.recovery.progress); TRANSLATE('Abort Status: %x', eip08.failure_cause); ENDTRANSLATIONBLOCK EC BLOCK: 06404d04 SCID_FCS_PROVISIONAL_DRIVE TRANSLATIONBLOCK TRANSLATE('Physical disk drive: %[tag]', eip04.device); TRANSLATE('Port ID: %s', eip04.cerp_id); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE('Last known enclosure: %d.', eip04.dencl_num - 100 ) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE('Last known bay: %d.', eip04.bay - 100) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip04.al_pa != 0x01 &&

eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE('Enclosure: %d.', eip04.dencl_num) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE('Bay: %d.', eip04.bay) ); TRANSLATE('AL_PA: 0x%04x', eip04.al_pa); TRANSLATE('SCSI Product ID: %s', eip04.pid); TRANSLATE('Current firmware revision: %s', eip04.rev); TRANSLATE('Latest known revision: %s', eip04.new_rev); TRANSLATE('Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information', eip04.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06410017 SCID_FCS_LOOP_CONFIG TRANSLATIONBLOCK TRANSLATE('Port ID: %s', eip17.cerp_id); TRANSLATE('Map ID: %u', eip17.map_id); TRANSLATE('Loop map page: %d of %d', eip17.page, eip17.total_pages); TRANSLATE('Entries in this page: %d', eip17.entries); CONDITIONAL(eip17.loop_map[0] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[00] ALPA: 0x%X', eip17.loop_map[0]) ); CONDITIONAL(eip17.loop_map[0] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[92] ALPA: 0x%X', eip17.loop_map[0]) ); CONDITIONAL(eip17.loop_map[1] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[01] ALPA: 0x%X', eip17.loop_map[1]) ); CONDITIONAL(eip17.loop_map[1] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[93] ALPA: 0x%X', eip17.loop_map[1]) ); CONDITIONAL(eip17.loop_map[2] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[02] ALPA: 0x%X', eip17.loop_map[2]) ); CONDITIONAL(eip17.loop_map[2] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[94] ALPA: 0x%X', eip17.loop_map[2]) ); CONDITIONAL(eip17.loop_map[3] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[03] ALPA: 0x%X', eip17.loop_map[3]) ); CONDITIONAL(eip17.loop_map[3] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[95] ALPA: 0x%X', eip17.loop_map[3]) ); CONDITIONAL(eip17.loop_map[4] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[04] ALPA: 0x%X', eip17.loop_map[4])

); CONDITIONAL(eip17.loop_map[4] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[96] ALPA: 0x%X', eip17.loop_map[4]) ); CONDITIONAL(eip17.loop_map[5] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[05] ALPA: 0x%X', eip17.loop_map[5]) ); CONDITIONAL(eip17.loop_map[5] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[97] ALPA: 0x%X', eip17.loop_map[5]) ); CONDITIONAL(eip17.loop_map[6] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[06] ALPA: 0x%X', eip17.loop_map[6]) ); CONDITIONAL(eip17.loop_map[6] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[98] ALPA: 0x%X', eip17.loop_map[6]) ); CONDITIONAL(eip17.loop_map[7] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[07] ALPA: 0x%X', eip17.loop_map[7]) ); CONDITIONAL(eip17.loop_map[7] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[99] ALPA: 0x%X', eip17.loop_map[7]) ); CONDITIONAL(eip17.loop_map[8] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[08] ALPA: 0x%X', eip17.loop_map[8]) ); CONDITIONAL(eip17.loop_map[8] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[100] ALPA: 0x%X', eip17.loop_map[8]) ); CONDITIONAL(eip17.loop_map[9] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[09] ALPA: 0x%X', eip17.loop_map[9]) ); CONDITIONAL(eip17.loop_map[9] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[101] ALPA: 0x%X', eip17.loop_map[9]) ); CONDITIONAL(eip17.loop_map[10] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[10] ALPA: 0x%X', eip17.loop_map[10]) ); CONDITIONAL(eip17.loop_map[10] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[102] ALPA: 0x%X', eip17.loop_map[10]) ); CONDITIONAL(eip17.loop_map[11] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[11] ALPA: 0x%X', eip17.loop_map[11]) ); CONDITIONAL(eip17.loop_map[11] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[103] ALPA: 0x%X', eip17.loop_map[11])

); CONDITIONAL(eip17.loop_map[12] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[12] ALPA: 0x%X', eip17.loop_map[12]) ); CONDITIONAL(eip17.loop_map[12] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[104] ALPA: 0x%X', eip17.loop_map[12]) ); CONDITIONAL(eip17.loop_map[13] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[13] ALPA: 0x%X', eip17.loop_map[13]) ); CONDITIONAL(eip17.loop_map[13] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[105] ALPA: 0x%X', eip17.loop_map[13]) ); CONDITIONAL(eip17.loop_map[14] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[14] ALPA: 0x%X', eip17.loop_map[14]) ); CONDITIONAL(eip17.loop_map[14] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[106] ALPA: 0x%X', eip17.loop_map[14]) ); CONDITIONAL(eip17.loop_map[15] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[15] ALPA: 0x%X', eip17.loop_map[15]) ); CONDITIONAL(eip17.loop_map[15] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[107] ALPA: 0x%X', eip17.loop_map[15]) ); CONDITIONAL(eip17.loop_map[16] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[16] ALPA: 0x%X', eip17.loop_map[16]) ); CONDITIONAL(eip17.loop_map[16] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[108] ALPA: 0x%X', eip17.loop_map[16]) ); CONDITIONAL(eip17.loop_map[17] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[17] ALPA: 0x%X', eip17.loop_map[17]) ); CONDITIONAL(eip17.loop_map[17] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[109] ALPA: 0x%X', eip17.loop_map[17]) ); CONDITIONAL(eip17.loop_map[18] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[18] ALPA: 0x%X', eip17.loop_map[18]) ); CONDITIONAL(eip17.loop_map[18] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[110] ALPA: 0x%X', eip17.loop_map[18]) ); CONDITIONAL(eip17.loop_map[19] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[19] ALPA: 0x%X', eip17.loop_map[19])

); CONDITIONAL(eip17.loop_map[19] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[111] ALPA: 0x%X', eip17.loop_map[19]) ); CONDITIONAL(eip17.loop_map[20] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[20] ALPA: 0x%X', eip17.loop_map[20]) ); CONDITIONAL(eip17.loop_map[20] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[112] ALPA: 0x%X', eip17.loop_map[20]) ); CONDITIONAL(eip17.loop_map[21] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[21] ALPA: 0x%X', eip17.loop_map[21]) ); CONDITIONAL(eip17.loop_map[21] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[113] ALPA: 0x%X', eip17.loop_map[21]) ); CONDITIONAL(eip17.loop_map[22] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[22] ALPA: 0x%X', eip17.loop_map[22]) ); CONDITIONAL(eip17.loop_map[22] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[114] ALPA: 0x%X', eip17.loop_map[22]) ); CONDITIONAL(eip17.loop_map[23] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[23] ALPA: 0x%X', eip17.loop_map[23]) ); CONDITIONAL(eip17.loop_map[23] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[115] ALPA: 0x%X', eip17.loop_map[23]) ); CONDITIONAL(eip17.loop_map[24] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[24] ALPA: 0x%X', eip17.loop_map[24]) ); CONDITIONAL(eip17.loop_map[24] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[116] ALPA: 0x%X', eip17.loop_map[24]) ); CONDITIONAL(eip17.loop_map[25] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[25] ALPA: 0x%X', eip17.loop_map[25]) ); CONDITIONAL(eip17.loop_map[25] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[117] ALPA: 0x%X', eip17.loop_map[25]) ); CONDITIONAL(eip17.loop_map[26] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[26] ALPA: 0x%X', eip17.loop_map[26]) ); CONDITIONAL(eip17.loop_map[26] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[118] ALPA: 0x%X', eip17.loop_map[26])

); CONDITIONAL(eip17.loop_map[27] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[27] ALPA: 0x%X', eip17.loop_map[27]) ); CONDITIONAL(eip17.loop_map[27] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[119] ALPA: 0x%X', eip17.loop_map[27]) ); CONDITIONAL(eip17.loop_map[28] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[28] ALPA: 0x%X', eip17.loop_map[28]) ); CONDITIONAL(eip17.loop_map[28] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[120] ALPA: 0x%X', eip17.loop_map[28]) ); CONDITIONAL(eip17.loop_map[29] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[29] ALPA: 0x%X', eip17.loop_map[29]) ); CONDITIONAL(eip17.loop_map[29] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[121] ALPA: 0x%X', eip17.loop_map[29]) ); CONDITIONAL(eip17.loop_map[30] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[30] ALPA: 0x%X', eip17.loop_map[30]) ); CONDITIONAL(eip17.loop_map[30] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[122] ALPA: 0x%X', eip17.loop_map[30]) ); CONDITIONAL(eip17.loop_map[31] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[31] ALPA: 0x%X', eip17.loop_map[31]) ); CONDITIONAL(eip17.loop_map[31] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[123] ALPA: 0x%X', eip17.loop_map[31]) ); CONDITIONAL(eip17.loop_map[32] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[32] ALPA: 0x%X', eip17.loop_map[32]) ); CONDITIONAL(eip17.loop_map[32] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[124] ALPA: 0x%X', eip17.loop_map[32]) ); CONDITIONAL(eip17.loop_map[33] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[33] ALPA: 0x%X', eip17.loop_map[33]) ); CONDITIONAL(eip17.loop_map[33] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[125] ALPA: 0x%X', eip17.loop_map[33]) ); CONDITIONAL(eip17.loop_map[34] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[34] ALPA: 0x%X', eip17.loop_map[34])

); CONDITIONAL(eip17.loop_map[34] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[126] ALPA: 0x%X', eip17.loop_map[34]) ); CONDITIONAL(eip17.loop_map[35] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[35] ALPA: 0x%X', eip17.loop_map[35]) ); CONDITIONAL(eip17.loop_map[35] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[127] ALPA: 0x%X', eip17.loop_map[35]) ); CONDITIONAL(eip17.loop_map[36] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[36] ALPA: 0x%X', eip17.loop_map[36]) ); CONDITIONAL(eip17.loop_map[36] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[128] ALPA: 0x%X', eip17.loop_map[36]) ); CONDITIONAL(eip17.loop_map[37] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[37] ALPA: 0x%X', eip17.loop_map[37]) ); CONDITIONAL(eip17.loop_map[37] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[129] ALPA: 0x%X', eip17.loop_map[37]) ); CONDITIONAL(eip17.loop_map[38] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[38] ALPA: 0x%X', eip17.loop_map[38]) ); CONDITIONAL(eip17.loop_map[38] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[130] ALPA: 0x%X', eip17.loop_map[38]) ); CONDITIONAL(eip17.loop_map[39] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[39] ALPA: 0x%X', eip17.loop_map[39]) ); CONDITIONAL(eip17.loop_map[39] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[131] ALPA: 0x%X', eip17.loop_map[39]) ); CONDITIONAL(eip17.loop_map[40] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[40] ALPA: 0x%X', eip17.loop_map[40]) ); CONDITIONAL(eip17.loop_map[40] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[132] ALPA: 0x%X', eip17.loop_map[40]) ); CONDITIONAL(eip17.loop_map[41] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[41] ALPA: 0x%X', eip17.loop_map[41]) ); CONDITIONAL(eip17.loop_map[41] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[133] ALPA: 0x%X', eip17.loop_map[41])

); CONDITIONAL(eip17.loop_map[42] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[42] ALPA: 0x%X', eip17.loop_map[42]) ); CONDITIONAL(eip17.loop_map[42] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[134] ALPA: 0x%X', eip17.loop_map[42]) ); CONDITIONAL(eip17.loop_map[43] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[43] ALPA: 0x%X', eip17.loop_map[43]) ); CONDITIONAL(eip17.loop_map[43] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[135] ALPA: 0x%X', eip17.loop_map[43]) ); CONDITIONAL(eip17.loop_map[44] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[44] ALPA: 0x%X', eip17.loop_map[44]) ); CONDITIONAL(eip17.loop_map[44] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[136] ALPA: 0x%X', eip17.loop_map[44]) ); CONDITIONAL(eip17.loop_map[45] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[45] ALPA: 0x%X', eip17.loop_map[45]) ); CONDITIONAL(eip17.loop_map[45] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[137] ALPA: 0x%X', eip17.loop_map[45]) ); CONDITIONAL(eip17.loop_map[46] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[46] ALPA: 0x%X', eip17.loop_map[46]) ); CONDITIONAL(eip17.loop_map[46] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[138] ALPA: 0x%X', eip17.loop_map[46]) ); CONDITIONAL(eip17.loop_map[47] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[47] ALPA: 0x%X', eip17.loop_map[47]) ); CONDITIONAL(eip17.loop_map[47] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[139] ALPA: 0x%X', eip17.loop_map[47]) ); CONDITIONAL(eip17.loop_map[48] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[48] ALPA: 0x%X', eip17.loop_map[48]) ); CONDITIONAL(eip17.loop_map[48] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[140] ALPA: 0x%X', eip17.loop_map[48]) ); CONDITIONAL(eip17.loop_map[49] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[49] ALPA: 0x%X', eip17.loop_map[49])

); CONDITIONAL(eip17.loop_map[49] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[141] ALPA: 0x%X', eip17.loop_map[49]) ); CONDITIONAL(eip17.loop_map[50] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[50] ALPA: 0x%X', eip17.loop_map[50]) ); CONDITIONAL(eip17.loop_map[50] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[142] ALPA: 0x%X', eip17.loop_map[50]) ); CONDITIONAL(eip17.loop_map[51] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[51] ALPA: 0x%X', eip17.loop_map[51]) ); CONDITIONAL(eip17.loop_map[51] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[143] ALPA: 0x%X', eip17.loop_map[51]) ); CONDITIONAL(eip17.loop_map[52] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[52] ALPA: 0x%X', eip17.loop_map[52]) ); CONDITIONAL(eip17.loop_map[52] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[144] ALPA: 0x%X', eip17.loop_map[52]) ); CONDITIONAL(eip17.loop_map[53] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[53] ALPA: 0x%X', eip17.loop_map[53]) ); CONDITIONAL(eip17.loop_map[53] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[145] ALPA: 0x%X', eip17.loop_map[53]) ); CONDITIONAL(eip17.loop_map[54] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[54] ALPA: 0x%X', eip17.loop_map[54]) ); CONDITIONAL(eip17.loop_map[54] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[146] ALPA: 0x%X', eip17.loop_map[54]) ); CONDITIONAL(eip17.loop_map[55] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[55] ALPA: 0x%X', eip17.loop_map[55]) ); CONDITIONAL(eip17.loop_map[55] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[147] ALPA: 0x%X', eip17.loop_map[55]) ); CONDITIONAL(eip17.loop_map[56] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[56] ALPA: 0x%X', eip17.loop_map[56]) ); CONDITIONAL(eip17.loop_map[56] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[148] ALPA: 0x%X', eip17.loop_map[56])

); CONDITIONAL(eip17.loop_map[57] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[57] ALPA: 0x%X', eip17.loop_map[57]) ); CONDITIONAL(eip17.loop_map[57] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[149] ALPA: 0x%X', eip17.loop_map[57]) ); CONDITIONAL(eip17.loop_map[58] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[58] ALPA: 0x%X', eip17.loop_map[58]) ); CONDITIONAL(eip17.loop_map[58] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[150] ALPA: 0x%X', eip17.loop_map[58]) ); CONDITIONAL(eip17.loop_map[59] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[59] ALPA: 0x%X', eip17.loop_map[59]) ); CONDITIONAL(eip17.loop_map[59] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[151] ALPA: 0x%X', eip17.loop_map[59]) ); CONDITIONAL(eip17.loop_map[60] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[60] ALPA: 0x%X', eip17.loop_map[60]) ); CONDITIONAL(eip17.loop_map[60] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[152] ALPA: 0x%X', eip17.loop_map[60]) ); CONDITIONAL(eip17.loop_map[61] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[61] ALPA: 0x%X', eip17.loop_map[61]) ); CONDITIONAL(eip17.loop_map[61] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[153] ALPA: 0x%X', eip17.loop_map[61]) ); CONDITIONAL(eip17.loop_map[62] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[62] ALPA: 0x%X', eip17.loop_map[62]) ); CONDITIONAL(eip17.loop_map[62] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[154] ALPA: 0x%X', eip17.loop_map[62]) ); CONDITIONAL(eip17.loop_map[63] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[63] ALPA: 0x%X', eip17.loop_map[63]) ); CONDITIONAL(eip17.loop_map[63] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[155] ALPA: 0x%X', eip17.loop_map[63]) ); CONDITIONAL(eip17.loop_map[64] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[64] ALPA: 0x%X', eip17.loop_map[64])

); CONDITIONAL(eip17.loop_map[64] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[156] ALPA: 0x%X', eip17.loop_map[64]) ); CONDITIONAL(eip17.loop_map[65] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[65] ALPA: 0x%X', eip17.loop_map[65]) ); CONDITIONAL(eip17.loop_map[65] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[157] ALPA: 0x%X', eip17.loop_map[65]) ); CONDITIONAL(eip17.loop_map[66] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[66] ALPA: 0x%X', eip17.loop_map[66]) ); CONDITIONAL(eip17.loop_map[66] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[158] ALPA: 0x%X', eip17.loop_map[66]) ); CONDITIONAL(eip17.loop_map[67] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[67] ALPA: 0x%X', eip17.loop_map[67]) ); CONDITIONAL(eip17.loop_map[67] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[159] ALPA: 0x%X', eip17.loop_map[67]) ); CONDITIONAL(eip17.loop_map[68] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[68] ALPA: 0x%X', eip17.loop_map[68]) ); CONDITIONAL(eip17.loop_map[68] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[160] ALPA: 0x%X', eip17.loop_map[68]) ); CONDITIONAL(eip17.loop_map[69] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[69] ALPA: 0x%X', eip17.loop_map[69]) ); CONDITIONAL(eip17.loop_map[69] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[161] ALPA: 0x%X', eip17.loop_map[69]) ); CONDITIONAL(eip17.loop_map[70] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[70] ALPA: 0x%X', eip17.loop_map[70]) ); CONDITIONAL(eip17.loop_map[70] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[162] ALPA: 0x%X', eip17.loop_map[70]) ); CONDITIONAL(eip17.loop_map[71] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[71] ALPA: 0x%X', eip17.loop_map[71]) ); CONDITIONAL(eip17.loop_map[71] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[163] ALPA: 0x%X', eip17.loop_map[71])

); CONDITIONAL(eip17.loop_map[72] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[72] ALPA: 0x%X', eip17.loop_map[72]) ); CONDITIONAL(eip17.loop_map[72] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[164] ALPA: 0x%X', eip17.loop_map[72]) ); CONDITIONAL(eip17.loop_map[73] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[73] ALPA: 0x%X', eip17.loop_map[73]) ); CONDITIONAL(eip17.loop_map[73] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[165] ALPA: 0x%X', eip17.loop_map[73]) ); CONDITIONAL(eip17.loop_map[74] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[74] ALPA: 0x%X', eip17.loop_map[74]) ); CONDITIONAL(eip17.loop_map[74] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[166] ALPA: 0x%X', eip17.loop_map[74]) ); CONDITIONAL(eip17.loop_map[75] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[75] ALPA: 0x%X', eip17.loop_map[75]) ); CONDITIONAL(eip17.loop_map[75] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[167] ALPA: 0x%X', eip17.loop_map[75]) ); CONDITIONAL(eip17.loop_map[76] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[76] ALPA: 0x%X', eip17.loop_map[76]) ); CONDITIONAL(eip17.loop_map[76] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[168] ALPA: 0x%X', eip17.loop_map[76]) ); CONDITIONAL(eip17.loop_map[77] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[77] ALPA: 0x%X', eip17.loop_map[77]) ); CONDITIONAL(eip17.loop_map[77] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[169] ALPA: 0x%X', eip17.loop_map[77]) ); CONDITIONAL(eip17.loop_map[78] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[78] ALPA: 0x%X', eip17.loop_map[78]) ); CONDITIONAL(eip17.loop_map[78] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[170] ALPA: 0x%X', eip17.loop_map[78]) ); CONDITIONAL(eip17.loop_map[79] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[79] ALPA: 0x%X', eip17.loop_map[79])

); CONDITIONAL(eip17.loop_map[79] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[171] ALPA: 0x%X', eip17.loop_map[79]) ); CONDITIONAL(eip17.loop_map[80] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[80] ALPA: 0x%X', eip17.loop_map[80]) ); CONDITIONAL(eip17.loop_map[80] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[172] ALPA: 0x%X', eip17.loop_map[80]) ); CONDITIONAL(eip17.loop_map[81] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[81] ALPA: 0x%X', eip17.loop_map[81]) ); CONDITIONAL(eip17.loop_map[81] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[173] ALPA: 0x%X', eip17.loop_map[81]) ); CONDITIONAL(eip17.loop_map[82] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[82] ALPA: 0x%X', eip17.loop_map[82]) ); CONDITIONAL(eip17.loop_map[82] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[174] ALPA: 0x%X', eip17.loop_map[82]) ); CONDITIONAL(eip17.loop_map[83] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[83] ALPA: 0x%X', eip17.loop_map[83]) ); CONDITIONAL(eip17.loop_map[83] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[175] ALPA: 0x%X', eip17.loop_map[83]) ); CONDITIONAL(eip17.loop_map[84] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[84] ALPA: 0x%X', eip17.loop_map[84]) ); CONDITIONAL(eip17.loop_map[84] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[176] ALPA: 0x%X', eip17.loop_map[84]) ); CONDITIONAL(eip17.loop_map[85] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[85] ALPA: 0x%X', eip17.loop_map[85]) ); CONDITIONAL(eip17.loop_map[85] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[177] ALPA: 0x%X', eip17.loop_map[85]) ); CONDITIONAL(eip17.loop_map[86] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[86] ALPA: 0x%X', eip17.loop_map[86]) ); CONDITIONAL(eip17.loop_map[86] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[178] ALPA: 0x%X', eip17.loop_map[86])

); CONDITIONAL(eip17.loop_map[87] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[87] ALPA: 0x%X', eip17.loop_map[87]) ); CONDITIONAL(eip17.loop_map[87] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[179] ALPA: 0x%X', eip17.loop_map[87]) ); CONDITIONAL(eip17.loop_map[88] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[88] ALPA: 0x%X', eip17.loop_map[88]) ); CONDITIONAL(eip17.loop_map[88] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[180] ALPA: 0x%X', eip17.loop_map[88]) ); CONDITIONAL(eip17.loop_map[89] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[89] ALPA: 0x%X', eip17.loop_map[89]) ); CONDITIONAL(eip17.loop_map[89] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[181] ALPA: 0x%X', eip17.loop_map[89]) ); CONDITIONAL(eip17.loop_map[90] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[90] ALPA: 0x%X', eip17.loop_map[90]) ); CONDITIONAL(eip17.loop_map[90] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[182] ALPA: 0x%X', eip17.loop_map[90]) ); CONDITIONAL(eip17.loop_map[91] != 0xFF && eip17.page == 1, TRANSLATE('Loop Map[91] ALPA: 0x%X', eip17.loop_map[91]) ); CONDITIONAL(eip17.loop_map[91] != 0xFF && eip17.page == 2, TRANSLATE('Loop Map[183] ALPA: 0x%X', eip17.loop_map[91]) ); ENDTRANSLATIONBLOCK EC BLOCK: 06420009 SCID_FCS_PASSTHRU_CMD TRANSLATIONBLOCK TRANSLATE('Physical disk drive: %[tag]', eip09.device); TRANSLATE('Port ID: %s', eip09.cerp_id); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip09.al_pa != 0x01 &&

eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE('Last known enclosure: %d.', eip09.dencl_num - 100 ) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE('Last known bay: %d.', eip09.bay - 100) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE('Enclosure: %d.', eip09.dencl_num) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE('Bay: %d.', eip09.bay) ); CONDITIONAL(eip09.drv_fw_rev ne 'nofwrev', TRANSLATE('Unit Firmware Version: %s', eip09.drv_fw_rev) ); TRANSLATE('AL_PA: 0x%04x', eip09.al_pa); TRANSLATE('%s', XLATE_EIP09_OPCODE( eip09.fed_class, eip09.cmd.cdb10.opcode ) ); TRANSLATE('Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information', eip09.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06440008 SCID_FCS_LOOP_RECOVERY_SHELF TRANSLATIONBLOCK TRANSLATE('Port IDs: %s %s', eip08.cerp_id, eip08.other_cerp_id); TRANSLATE('Enclosure ID: %d', eip08.recovery.shelf); ENDTRANSLATIONBLOCK EC BLOCK: 064b0008 SCID_FCS_LOOP_RECOVERY TRANSLATIONBLOCK TRANSLATE('Loop Recoveries Flag: %d', eip08.recovery.progress); CONDITIONAL(eip08.recovery.progress == 0x01, TRANSLATE('ENABLE Loop Recovery Operations')); CONDITIONAL(eip08.recovery.progress == 0x00, TRANSLATE('DISABLE Loop Recovery Operations')); ENDTRANSLATIONBLOCK EC BLOCK: 064c0004 SCID_FCS_DSL_DRIVE

TRANSLATIONBLOCK TRANSLATE('Physical disk drive: %[tag]', eip04.device); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE('Last known enclosure: %d.', eip04.dencl_num - 100 ) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE('Last known bay: %d.', eip04.bay - 100) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE('Enclosure: %d.', eip04.dencl_num) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE('Bay: %d.', eip04.bay) ); TRANSLATE('Failure Reason Code: %d', eip04.bypass_reason); ENDTRANSLATIONBLOCK EC BLOCK: 064d0008 SCID_FCS_CODELOAD_COMPLETE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK EC BLOCK: 064e0009 SCID_FCS_NON_ZERO_RSP_CODE TRANSLATIONBLOCK TRANSLATE('Physical disk drive: %[tag]', eip09.device); TRANSLATE('Port ID: %s', eip09.cerp_id); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE &&

eip09.dencl_num == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE('Last known enclosure: %d.', eip09.dencl_num - 100 ) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num > 99, TRANSLATE('Last known bay: %d.', eip09.bay - 100) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE('Enclosure: %d.', eip09.dencl_num) ); CONDITIONAL(eip09.al_pa != 0x01 && eip09.al_pa != 0x02 && eip09.al_pa != 0xEE && eip09.dencl_num < 99, TRANSLATE('Bay: %d.', eip09.bay) ); CONDITIONAL(eip09.drv_fw_rev ne 'nofwrev', TRANSLATE('Unit Firmware Version: %s', eip09.drv_fw_rev) ); TRANSLATE('AL_PA: 0x%04x', eip09.al_pa); TRANSLATE('%s', XLATE_EIP09_OPCODE( eip09.fed_class, eip09.cmd.cdb10.opcode ) ); TRANSLATE( 'RSP Code: 0x%02x', eip09.error.sense_data.fru_code ); TRANSLATE('Bay Bypass Mask Loop A 0x%X',eip09.bypassa); TRANSLATE('Bay Bypass Mask Loop B 0x%X',eip09.bypassb); TRANSLATE('Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information', eip09.cerp_id); ENDTRANSLATIONBLOCK

EC BLOCK: 064f0006 SCID_FCS_ELMO_CODELOAD_START TRANSLATIONBLOCK TRANSLATE('Enclosure Vendor Identification: %s', eip06.vendor_id); TRANSLATE('Enclosure Product Identification: %s', eip06.product_id); TRANSLATE('Enclosure Product Revision: %s', eip06.product_rev); TRANSLATE('Enclosure Hardware Type: %s', eip06.enc_hw_type); TRANSLATE('Enclosure Hardware Revision: %s', eip06.enc_hw_rev); TRANSLATE('Enclosure Saleable Serial Number: %s', eip06.enc_serial_num); TRANSLATE('Enclosure WWID (node): %08x%08x', eip06.enc_wwn.hi, eip06.enc_wwn.lo) ; TRANSLATE('Enclosure Number: %d', eip06.enc_num); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo Firmware Revision: %s', eip06.loop_a_elmo_fw_rev), TRANSLATE('Loop B ELMo Firmware Revision: %s', eip06.loop_b_elmo_fw_rev) ); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo Hardware Type: %s', eip06.loop_a_elmo_hw_type), TRANSLATE('Loop B ELMo Hardware Type: %s', eip06.loop_b_elmo_hw_type) ); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo Hardware Revision: %s', eip06.loop_a_elmo_hw_rev), TRANSLATE('Loop B ELMo Hardware Revision: %s', eip06.loop_b_elmo_hw_rev) ); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo Module Serial Number: %s', eip06.loop_a_elmo_serial_num), TRANSLATE('Loop B ELMo Module Serial Number: %s', eip06.loop_b_elmo_serial_num) ); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo WWID (port): %08x%08x', eip06.loop_a_elmo_n_port_name.hi, eip06.loop_a_elmo_n_port_name.lo), TRANSLATE('Loop B ELMo WWID (port): %08x%08x', eip06.loop_b_elmo_n_port_name.hi, eip06.loop_b_elmo_n_port_name.lo) ); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo AL_PA: %4x', eip06.loop_a_elmo_n_port_id), TRANSLATE('Loop B ELMo AL_PA: %4x', eip06.loop_b_elmo_n_port_id) ); ENDTRANSLATIONBLOCK EC BLOCK: 06500006 SCID_FCS_ELMO_CODELOAD_DONE TRANSLATIONBLOCK TRANSLATE('Enclosure Vendor Identification: %s', eip06.vendor_id); TRANSLATE('Enclosure Product Identification: %s', eip06.product_id); TRANSLATE('Enclosure Product Revision: %s', eip06.product_rev); TRANSLATE('Enclosure Hardware Type: %s', eip06.enc_hw_type); TRANSLATE('Enclosure Hardware Revision: %s', eip06.enc_hw_rev); TRANSLATE('Enclosure Saleable Serial Number: %s', eip06.enc_serial_num); TRANSLATE('Enclosure WWID (node): %08x%08x', eip06.enc_wwn.hi, eip06.enc_wwn.lo) ; TRANSLATE('Enclosure Number: %d', eip06.enc_num); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo Firmware Revision: %s', eip06.loop_a_elmo_fw_rev), TRANSLATE('Loop B ELMo Firmware Revision: %s', eip06.loop_b_elmo_fw_rev) ); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo Hardware Type: %s', eip06.loop_a_elmo_hw_type), TRANSLATE('Loop B ELMo Hardware Type: %s', eip06.loop_b_elmo_hw_type) ); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo Hardware Revision: %s', eip06.loop_a_elmo_hw_rev),

TRANSLATE('Loop B ELMo Hardware Revision: %s', eip06.loop_b_elmo_hw_rev) ); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo Module Serial Number: %s', eip06.loop_a_elmo_serial_num), TRANSLATE('Loop B ELMo Module Serial Number: %s', eip06.loop_b_elmo_serial_num) ); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo WWID (port): %08x%08x', eip06.loop_a_elmo_n_port_name.hi, eip06.loop_a_elmo_n_port_name.lo), TRANSLATE('Loop B ELMo WWID (port): %08x%08x', eip06.loop_b_elmo_n_port_name.hi, eip06.loop_b_elmo_n_port_name.lo) ); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo AL_PA: %4x', eip06.loop_a_elmo_n_port_id), TRANSLATE('Loop B ELMo AL_PA: %4x', eip06.loop_b_elmo_n_port_id) ); ENDTRANSLATIONBLOCK EC BLOCK: 06510006 SCID_FCS_DRIVE_BAY_BYPASS TRANSLATIONBLOCK TRANSLATE('Enclosure Vendor Identification: %s', eip06.vendor_id); TRANSLATE('Enclosure Product Identification: %s', eip06.product_id); TRANSLATE('Enclosure Product Revision: %s', eip06.product_rev); TRANSLATE('Enclosure Saleable Serial Number: %s', eip06.enc_serial_num); TRANSLATE('Enclosure WWID (node): %08x%08x', eip06.enc_wwn.hi, eip06.enc_wwn.lo) ; TRANSLATE('Enclosure Number: %d', eip06.enc_num); TRANSLATE('Drive bay: %d', eip06.bypass_bay); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo WWID (port): %08x%08x', eip06.loop_a_elmo_n_port_name.hi, eip06.loop_a_elmo_n_port_name.lo), TRANSLATE('Loop B ELMo WWID (port): %08x%08x', eip06.loop_b_elmo_n_port_name.hi, eip06.loop_b_elmo_n_port_name.lo) ); ENDTRANSLATIONBLOCK EC BLOCK: 06520006 SCID_FCS_DRIVE_BAY_POWER TRANSLATIONBLOCK TRANSLATE('Enclosure Vendor Identification: %s', eip06.vendor_id); TRANSLATE('Enclosure Product Identification: %s', eip06.product_id); TRANSLATE('Enclosure Product Revision: %s', eip06.product_rev); TRANSLATE('Enclosure Saleable Serial Number: %s', eip06.enc_serial_num); TRANSLATE('Enclosure WWID (node): %08x%08x', eip06.enc_wwn.hi, eip06.enc_wwn.lo) ; TRANSLATE('Enclosure Number: %d', eip06.enc_num); TRANSLATE('Drive bay: %d', eip06.power_bay); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo WWID (port): %08x%08x', eip06.loop_a_elmo_n_port_name.hi, eip06.loop_a_elmo_n_port_name.lo), TRANSLATE('Loop B ELMo WWID (port): %08x%08x', eip06.loop_b_elmo_n_port_name.hi, eip06.loop_b_elmo_n_port_name.lo) ); ENDTRANSLATIONBLOCK EC BLOCK: 06530006 SCID_FCS_ENCLOSURE_NUMBER TRANSLATIONBLOCK TRANSLATE('Enclosure Vendor Identification: %s', eip06.vendor_id); TRANSLATE('Enclosure Product Identification: %s', eip06.product_id); TRANSLATE('Enclosure Product Revision: %s', eip06.product_rev); TRANSLATE('Enclosure Saleable Serial Number: %s', eip06.enc_serial_num);

TRANSLATE('Enclosure WWID (node): %08x%08x', eip06.enc_wwn.hi, eip06.enc_wwn.lo) ; TRANSLATE('Enclosure Former ID: %d', eip06.enc_num); TRANSLATE('Enclosure New ID : %d', eip06.data); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo WWID (port): %08x%08x', eip06.loop_a_elmo_n_port_name.hi, eip06.loop_a_elmo_n_port_name.lo), TRANSLATE('Loop B ELMo WWID (port): %08x%08x', eip06.loop_b_elmo_n_port_name.hi, eip06.loop_b_elmo_n_port_name.lo) ); ENDTRANSLATIONBLOCK EC BLOCK: 06540006 SCID_FCS_DISCOVER_ENCLOSURE TRANSLATIONBLOCK TRANSLATE('Enclosure WWID (node): %08x%08x', eip06.enc_wwn.hi, eip06.enc_wwn.lo) ; ENDTRANSLATIONBLOCK EC BLOCK: 06558906 SCID_FCS_FAILED_ENCLOSURE TRANSLATIONBLOCK TRANSLATE('Enclosure Vendor Identification: %s', eip06.vendor_id); TRANSLATE('Enclosure Product Identification: %s', eip06.product_id); TRANSLATE('Enclosure Product Revision: %s', eip06.product_rev); TRANSLATE('Enclosure Hardware Type: %s', eip06.enc_hw_type); TRANSLATE('Enclosure Hardware Revision: %s', eip06.enc_hw_rev); TRANSLATE('Enclosure Saleable Serial Number: %s', eip06.enc_serial_num); TRANSLATE('Enclosure WWID (node): %08x%08x', eip06.enc_wwn.hi, eip06.enc_wwn.lo) ; TRANSLATE('Enclosure Number: %d', eip06.enc_num); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo Firmware Revision: %s', eip06.loop_a_elmo_fw_rev), TRANSLATE('Loop B ELMo Firmware Revision: %s', eip06.loop_b_elmo_fw_rev) ); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo Hardware Type: %s', eip06.loop_a_elmo_hw_type), TRANSLATE('Loop B ELMo Hardware Type: %s', eip06.loop_b_elmo_hw_type) ); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo Hardware Revision: %s', eip06.loop_a_elmo_hw_rev), TRANSLATE('Loop B ELMo Hardware Revision: %s', eip06.loop_b_elmo_hw_rev) ); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo Module Serial Number: %s', eip06.loop_a_elmo_serial_num), TRANSLATE('Loop B ELMo Module Serial Number: %s', eip06.loop_b_elmo_serial_num) ); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo WWID (port): %08x%08x', eip06.loop_a_elmo_n_port_name.hi, eip06.loop_a_elmo_n_port_name.lo), TRANSLATE('Loop B ELMo WWID (port): %08x%08x', eip06.loop_b_elmo_n_port_name.hi, eip06.loop_b_elmo_n_port_name.lo) ); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo AL_PA: %4x', eip06.loop_a_elmo_n_port_id), TRANSLATE('Loop B ELMo AL_PA: %4x', eip06.loop_b_elmo_n_port_id) ); TRANSLATE('Failure cause: %[drv_inop]', eip06.data); ENDTRANSLATIONBLOCK EC BLOCK: 06560006 SCID_FCS_DRIVE_ENCLOSURE_SHUTDOWN TRANSLATIONBLOCK

TRANSLATE('Enclosure Vendor Identification: %s', eip06.vendor_id); TRANSLATE('Enclosure Product Identification: %s', eip06.product_id); TRANSLATE('Enclosure Product Revision: %s', eip06.product_rev); TRANSLATE('Enclosure Saleable Serial Number: %s', eip06.enc_serial_num); TRANSLATE('Enclosure WWID (node): %08x%08x', eip06.enc_wwn.hi, eip06.enc_wwn.lo) ; TRANSLATE('Enclosure Number: %d', eip06.enc_num); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo WWID (port): %08x%08x', eip06.loop_a_elmo_n_port_name.hi, eip06.loop_a_elmo_n_port_name.lo), TRANSLATE('Loop B ELMo WWID (port): %08x%08x', eip06.loop_b_elmo_n_port_name.hi, eip06.loop_b_elmo_n_port_name.lo) ); ENDTRANSLATIONBLOCK EC BLOCK: 06570006 SCID_FCS_ENCLOSURE_NUMBER_MISMATCH TRANSLATIONBLOCK TRANSLATE('Enclosure Vendor Identification: %s', eip06.vendor_id); TRANSLATE('Enclosure Product Identification: %s', eip06.product_id); TRANSLATE('Enclosure Product Revision: %s', eip06.product_rev); TRANSLATE('Enclosure Saleable Serial Number: %s', eip06.enc_serial_num); TRANSLATE('Enclosure WWID (node): %08x%08x', eip06.enc_wwn.hi, eip06.enc_wwn.lo) ; TRANSLATE('Enclosure Number: %d', eip06.enc_num); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo WWID (port): %08x%08x', eip06.loop_a_elmo_n_port_name.hi, eip06.loop_a_elmo_n_port_name.lo), TRANSLATE('Loop B ELMo WWID (port): %08x%08x', eip06.loop_b_elmo_n_port_name.hi, eip06.loop_b_elmo_n_port_name.lo) ); ENDTRANSLATIONBLOCK EC BLOCK: 06589906 SCID_FCS_ENCLOSURE_CROSS_CABLED TRANSLATIONBLOCK TRANSLATE('Enclosure Vendor Identification: %s', eip06.vendor_id); TRANSLATE('Enclosure Product Identification: %s', eip06.product_id); TRANSLATE('Enclosure Product Revision: %s', eip06.product_rev); TRANSLATE('Enclosure Saleable Serial Number: %s', eip06.enc_serial_num); TRANSLATE('Enclosure WWID (node): %08x%08x', eip06.enc_wwn.hi, eip06.enc_wwn.lo) ; TRANSLATE('Enclosure Number: %d', eip06.enc_num); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo WWID (port): %08x%08x', eip06.loop_a_elmo_n_port_name.hi, eip06.loop_a_elmo_n_port_name.lo), TRANSLATE('Loop B ELMo WWID (port): %08x%08x', eip06.loop_b_elmo_n_port_name.hi, eip06.loop_b_elmo_n_port_name.lo) ); ENDTRANSLATIONBLOCK EC BLOCK: 06590006 SCID_FCS_DRIVE_BAY_CONDITION_CHANGE TRANSLATIONBLOCK TRANSLATE('Enclosure Vendor Identification: %s', eip06.vendor_id); TRANSLATE('Enclosure Product Identification: %s', eip06.product_id); TRANSLATE('Enclosure Product Revision: %s', eip06.product_rev); TRANSLATE('Enclosure Saleable Serial Number: %s', eip06.enc_serial_num); TRANSLATE('Enclosure WWID (node): %08x%08x', eip06.enc_wwn.hi, eip06.enc_wwn.lo) ; TRANSLATE('Enclosure Number: %d', eip06.enc_num); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo WWID (port): %08x%08x', eip06.loop_a_elmo_n_port_name.hi,

eip06.loop_a_elmo_n_port_name.lo), TRANSLATE('Loop B ELMo WWID (port): %08x%08x', eip06.loop_b_elmo_n_port_name.hi, eip06.loop_b_elmo_n_port_name.lo) ); TRANSLATE('Enclosure %d Bay %d', eip06.enc_num, eip06.bypass_bay); CONDITIONAL(eip06.data == 0, TRANSLATE('Updated Condition: UNSUPPORTED') ); CONDITIONAL(eip06.data == 1, TRANSLATE('Updated Condition: OK') ); CONDITIONAL(eip06.data == 2, TRANSLATE('Updated Condition: CRITICAL') ); CONDITIONAL(eip06.data == 3, TRANSLATE('Updated Condition: NONCRITICAL') ); CONDITIONAL(eip06.data == 4, TRANSLATE('Updated Condition: UNRECOVERABLE') ); CONDITIONAL(eip06.data == 5, TRANSLATE('Updated Condition: NOT_INSTALLED') ); CONDITIONAL(eip06.data == 6, TRANSLATE('Updated Condition: UNKNOWN') ); CONDITIONAL(eip06.data == 7, TRANSLATE('Updated Condition: NOT_AVAILABLE') ); CONDITIONAL(eip06.data2 == 0, TRANSLATE('Previous Condition: UNSUPPORTED') ); CONDITIONAL(eip06.data2 == 1, TRANSLATE('Previous Condition: OK') ); CONDITIONAL(eip06.data2 == 2, TRANSLATE('Previous Condition: CRITICAL') ); CONDITIONAL(eip06.data2 == 3, TRANSLATE('Previous Condition: NONCRITICAL') ); CONDITIONAL(eip06.data2 == 4, TRANSLATE('Previous Condition: UNRECOVERABLE') ); CONDITIONAL(eip06.data2 == 5, TRANSLATE('Previous Condition: NOT_INSTALLED') ); CONDITIONAL(eip06.data2 == 6, TRANSLATE('Previous Condition: UNKNOWN') ); CONDITIONAL(eip06.data2 == 7, TRANSLATE('Previous Condition: NOT_AVAILABLE') ); ENDTRANSLATIONBLOCK EC BLOCK: 065a0006 SCID_FCS_ENCLOSURE_CONDITION_CHANGE TRANSLATIONBLOCK TRANSLATE('Enclosure Vendor Identification: %s', eip06.vendor_id); TRANSLATE('Enclosure Product Identification: %s', eip06.product_id); TRANSLATE('Enclosure Product Revision: %s', eip06.product_rev);

TRANSLATE('Enclosure WWID (node): %08x%08x', eip06.enc_wwn.hi, eip06.enc_wwn.lo) ; TRANSLATE('Enclosure Number: %d', eip06.enc_num); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo WWID (port): %08x%08x', eip06.loop_a_elmo_n_port_name.hi, eip06.loop_a_elmo_n_port_name.lo), TRANSLATE('Loop B ELMo WWID (port): %08x%08x', eip06.loop_b_elmo_n_port_name.hi, eip06.loop_b_elmo_n_port_name.lo) ); TRANSLATE('Enclosure %d', eip06.enc_num); CONDITIONAL(eip06.data == 0, TRANSLATE('Updated Condition: UNSUPPORTED') ); CONDITIONAL(eip06.data == 1, TRANSLATE('Updated Condition: OK') ); CONDITIONAL(eip06.data == 2, TRANSLATE('Updated Condition: CRITICAL') ); CONDITIONAL(eip06.data == 3, TRANSLATE('Updated Condition: NONCRITICAL') ); CONDITIONAL(eip06.data == 4, TRANSLATE('Updated Condition: UNRECOVERABLE') ); CONDITIONAL(eip06.data == 5, TRANSLATE('Updated Condition: NOT_INSTALLED') ); CONDITIONAL(eip06.data == 6, TRANSLATE('Updated Condition: UNKNOWN') ); CONDITIONAL(eip06.data == 7, TRANSLATE('Updated Condition: NOT_AVAILABLE') ); ENDTRANSLATIONBLOCK EC BLOCK: 065b0006 SCID_FCS_ENCLOSURE_PS_CONDITION_CHANGE TRANSLATIONBLOCK TRANSLATE('Enclosure Vendor Identification: %s', eip06.vendor_id); TRANSLATE('Enclosure Product Identification: %s', eip06.product_id); TRANSLATE('Enclosure Product Revision: %s', eip06.product_rev); TRANSLATE('Enclosure Saleable Serial Number: %s', eip06.enc_serial_num); TRANSLATE('Enclosure WWID (node): %08x%08x', eip06.enc_wwn.hi, eip06.enc_wwn.lo) ; TRANSLATE('Enclosure Number: %d', eip06.enc_num); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo WWID (port): %08x%08x', eip06.loop_a_elmo_n_port_name.hi, eip06.loop_a_elmo_n_port_name.lo), TRANSLATE('Loop B ELMo WWID (port): %08x%08x', eip06.loop_b_elmo_n_port_name.hi, eip06.loop_b_elmo_n_port_name.lo) ); TRANSLATE('Enclosure %d', eip06.enc_num); CONDITIONAL(eip06.data == 0, TRANSLATE('Updated Condition: UNSUPPORTED') ); CONDITIONAL(eip06.data == 1, TRANSLATE('Updated Condition: OK') ); CONDITIONAL(eip06.data == 2, TRANSLATE('Updated Condition: CRITICAL')

); CONDITIONAL(eip06.data == 3, TRANSLATE('Updated Condition: ); CONDITIONAL(eip06.data == 4, TRANSLATE('Updated Condition: ); CONDITIONAL(eip06.data == 5, TRANSLATE('Updated Condition: ); CONDITIONAL(eip06.data == 6, TRANSLATE('Updated Condition: ); CONDITIONAL(eip06.data == 7, TRANSLATE('Updated Condition: ); ENDTRANSLATIONBLOCK

NONCRITICAL') UNRECOVERABLE') NOT_INSTALLED') UNKNOWN') NOT_AVAILABLE')

EC BLOCK: 065c0006 SCID_FCS_ENCLOSURE_FAN1_CONDITION_CHANGE TRANSLATIONBLOCK TRANSLATE('Enclosure WWID (node): %08x%08x', eip06.enc_wwn.hi, eip06.enc_wwn.lo) ; TRANSLATE('Enclosure Number: %d', eip06.enc_num); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo WWID (port): %08x%08x', eip06.loop_a_elmo_n_port_name.hi, eip06.loop_a_elmo_n_port_name.lo), TRANSLATE('Loop B ELMo WWID (port): %08x%08x', eip06.loop_b_elmo_n_port_name.hi, eip06.loop_b_elmo_n_port_name.lo) ); TRANSLATE('Enclosure %d', eip06.enc_num); CONDITIONAL(eip06.data == 0, TRANSLATE('Updated Condition: UNSUPPORTED') ); CONDITIONAL(eip06.data == 1, TRANSLATE('Updated Condition: OK') ); CONDITIONAL(eip06.data == 2, TRANSLATE('Updated Condition: CRITICAL') ); CONDITIONAL(eip06.data == 3, TRANSLATE('Updated Condition: NONCRITICAL') ); CONDITIONAL(eip06.data == 4, TRANSLATE('Updated Condition: UNRECOVERABLE') ); CONDITIONAL(eip06.data == 5, TRANSLATE('Updated Condition: NOT_INSTALLED') ); CONDITIONAL(eip06.data == 6, TRANSLATE('Updated Condition: UNKNOWN') ); CONDITIONAL(eip06.data == 7, TRANSLATE('Updated Condition: NOT_AVAILABLE') ); ENDTRANSLATIONBLOCK EC BLOCK: 065d0006 SCID_FCS_ENCLOSURE_FAN2_CONDITION_CHANGE TRANSLATIONBLOCK TRANSLATE('Enclosure WWID (node): %08x%08x', eip06.enc_wwn.hi, eip06.enc_wwn.lo) ;

TRANSLATE('Enclosure Number: %d', eip06.enc_num); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo WWID (port): %08x%08x', eip06.loop_a_elmo_n_port_name.hi, eip06.loop_a_elmo_n_port_name.lo), TRANSLATE('Loop B ELMo WWID (port): %08x%08x', eip06.loop_b_elmo_n_port_name.hi, eip06.loop_b_elmo_n_port_name.lo) ); TRANSLATE('Enclosure %d', eip06.enc_num); CONDITIONAL(eip06.data == 0, TRANSLATE('Updated Condition: UNSUPPORTED') ); CONDITIONAL(eip06.data == 1, TRANSLATE('Updated Condition: OK') ); CONDITIONAL(eip06.data == 2, TRANSLATE('Updated Condition: CRITICAL') ); CONDITIONAL(eip06.data == 3, TRANSLATE('Updated Condition: NONCRITICAL') ); CONDITIONAL(eip06.data == 4, TRANSLATE('Updated Condition: UNRECOVERABLE') ); CONDITIONAL(eip06.data == 5, TRANSLATE('Updated Condition: NOT_INSTALLED') ); CONDITIONAL(eip06.data == 6, TRANSLATE('Updated Condition: UNKNOWN') ); CONDITIONAL(eip06.data == 7, TRANSLATE('Updated Condition: NOT_AVAILABLE') ); ENDTRANSLATIONBLOCK EC BLOCK: 065e0006 SCID_FCS_ENC_LINK_MODULE_A_CONDITION_CHANGE TRANSLATIONBLOCK TRANSLATE('Enclosure Vendor Identification: %s', eip06.vendor_id); TRANSLATE('Enclosure Product Identification: %s', eip06.product_id); TRANSLATE('Enclosure Product Revision: %s', eip06.product_rev); TRANSLATE('Enclosure Saleable Serial Number: %s', eip06.enc_serial_num); TRANSLATE('Enclosure WWID (node): %08x%08x', eip06.enc_wwn.hi, eip06.enc_wwn.lo) ; TRANSLATE('Enclosure Number: %d', eip06.enc_num); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo WWID (port): %08x%08x', eip06.loop_a_elmo_n_port_name.hi, eip06.loop_a_elmo_n_port_name.lo), TRANSLATE('Loop B ELMo WWID (port): %08x%08x', eip06.loop_b_elmo_n_port_name.hi, eip06.loop_b_elmo_n_port_name.lo) ); TRANSLATE('Enclosure %d', eip06.enc_num); CONDITIONAL(eip06.data == 0, TRANSLATE('Updated Condition: UNSUPPORTED') ); CONDITIONAL(eip06.data == 1, TRANSLATE('Updated Condition: OK') ); CONDITIONAL(eip06.data == 2, TRANSLATE('Updated Condition: CRITICAL') ); CONDITIONAL(eip06.data == 3,

TRANSLATE('Updated Condition: ); CONDITIONAL(eip06.data == 4, TRANSLATE('Updated Condition: ); CONDITIONAL(eip06.data == 5, TRANSLATE('Updated Condition: ); CONDITIONAL(eip06.data == 6, TRANSLATE('Updated Condition: ); CONDITIONAL(eip06.data == 7, TRANSLATE('Updated Condition: ); ENDTRANSLATIONBLOCK

NONCRITICAL') UNRECOVERABLE') NOT_INSTALLED') UNKNOWN') NOT_AVAILABLE')

EC BLOCK: 065f0006 SCID_FCS_ENC_LINK_MODULE_B_CONDITION_CHANGE TRANSLATIONBLOCK TRANSLATE('Enclosure Vendor Identification: %s', eip06.vendor_id); TRANSLATE('Enclosure Product Identification: %s', eip06.product_id); TRANSLATE('Enclosure Product Revision: %s', eip06.product_rev); TRANSLATE('Enclosure Saleable Serial Number: %s', eip06.enc_serial_num); TRANSLATE('Enclosure WWID (node): %08x%08x', eip06.enc_wwn.hi, eip06.enc_wwn.lo) ; TRANSLATE('Enclosure Number: %d', eip06.enc_num); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo WWID (port): %08x%08x', eip06.loop_a_elmo_n_port_name.hi, eip06.loop_a_elmo_n_port_name.lo), TRANSLATE('Loop B ELMo WWID (port): %08x%08x', eip06.loop_b_elmo_n_port_name.hi, eip06.loop_b_elmo_n_port_name.lo) ); TRANSLATE('Enclosure %d', eip06.enc_num); CONDITIONAL(eip06.data == 0, TRANSLATE('Updated Condition: UNSUPPORTED') ); CONDITIONAL(eip06.data == 1, TRANSLATE('Updated Condition: OK') ); CONDITIONAL(eip06.data == 2, TRANSLATE('Updated Condition: CRITICAL') ); CONDITIONAL(eip06.data == 3, TRANSLATE('Updated Condition: NONCRITICAL') ); CONDITIONAL(eip06.data == 4, TRANSLATE('Updated Condition: UNRECOVERABLE') ); CONDITIONAL(eip06.data == 5, TRANSLATE('Updated Condition: NOT_INSTALLED') ); CONDITIONAL(eip06.data == 6, TRANSLATE('Updated Condition: UNKNOWN') ); CONDITIONAL(eip06.data == 7, TRANSLATE('Updated Condition: NOT_AVAILABLE') ); ENDTRANSLATIONBLOCK EC BLOCK: 06600006 SCID_FCS_ENC_LOOP_A_TRANSCEIVER_CONDITION_CHANGE TRANSLATIONBLOCK

TRANSLATE('Enclosure Vendor Identification: %s', eip06.vendor_id); TRANSLATE('Enclosure Product Identification: %s', eip06.product_id); TRANSLATE('Enclosure Product Revision: %s', eip06.product_rev); TRANSLATE('Enclosure Saleable Serial Number: %s', eip06.enc_serial_num); TRANSLATE('Enclosure WWID (node): %08x%08x', eip06.enc_wwn.hi, eip06.enc_wwn.lo) ; CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo WWID (port): %08x%08x', eip06.loop_a_elmo_n_port_name.hi, eip06.loop_a_elmo_n_port_name.lo), TRANSLATE('Loop B ELMo WWID (port): %08x%08x', eip06.loop_b_elmo_n_port_name.hi, eip06.loop_b_elmo_n_port_name.lo) ); TRANSLATE('Enclosure %d', eip06.enc_num); CONDITIONAL(eip06.data == 0, TRANSLATE('Updated Condition: UNSUPPORTED') ); CONDITIONAL(eip06.data == 1, TRANSLATE('Updated Condition: OK') ); CONDITIONAL(eip06.data == 2, TRANSLATE('Updated Condition: CRITICAL') ); CONDITIONAL(eip06.data == 3, TRANSLATE('Updated Condition: NONCRITICAL') ); CONDITIONAL(eip06.data == 4, TRANSLATE('Updated Condition: UNRECOVERABLE') ); CONDITIONAL(eip06.data == 5, TRANSLATE('Updated Condition: NOT_INSTALLED') ); CONDITIONAL(eip06.data == 6, TRANSLATE('Updated Condition: UNKNOWN') ); CONDITIONAL(eip06.data == 7, TRANSLATE('Updated Condition: NOT_AVAILABLE') ); CONDITIONAL(eip06.data2 == 0, TRANSLATE('Previous Condition: UNSUPPORTED') ); CONDITIONAL(eip06.data2 == 1, TRANSLATE('Previous Condition: OK') ); CONDITIONAL(eip06.data2 == 2, TRANSLATE('Previous Condition: CRITICAL') ); CONDITIONAL(eip06.data2 == 3, TRANSLATE('Previous Condition: NONCRITICAL') ); CONDITIONAL(eip06.data2 == 4, TRANSLATE('Previous Condition: UNRECOVERABLE') ); CONDITIONAL(eip06.data2 == 5, TRANSLATE('Previous Condition: NOT_INSTALLED') ); CONDITIONAL(eip06.data2 == 6, TRANSLATE('Previous Condition: UNKNOWN') ); CONDITIONAL(eip06.data2 == 7, TRANSLATE('Previous Condition: NOT_AVAILABLE')

); ENDTRANSLATIONBLOCK EC BLOCK: 06610006 SCID_FCS_ENC_LOOP_B_TRANSCEIVER_CONDITION_CHANGE TRANSLATIONBLOCK TRANSLATE('Enclosure Vendor Identification: %s', eip06.vendor_id); TRANSLATE('Enclosure Product Identification: %s', eip06.product_id); TRANSLATE('Enclosure Product Revision: %s', eip06.product_rev); TRANSLATE('Enclosure Saleable Serial Number: %s', eip06.enc_serial_num); TRANSLATE('Enclosure WWID (node): %08x%08x', eip06.enc_wwn.hi, eip06.enc_wwn.lo) ; CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo WWID (port): %08x%08x', eip06.loop_a_elmo_n_port_name.hi, eip06.loop_a_elmo_n_port_name.lo), TRANSLATE('Loop B ELMo WWID (port): %08x%08x', eip06.loop_b_elmo_n_port_name.hi, eip06.loop_b_elmo_n_port_name.lo) ); TRANSLATE('Enclosure %d', eip06.enc_num); CONDITIONAL(eip06.data == 0, TRANSLATE('Updated Condition: UNSUPPORTED') ); CONDITIONAL(eip06.data == 1, TRANSLATE('Updated Condition: OK') ); CONDITIONAL(eip06.data == 2, TRANSLATE('Updated Condition: CRITICAL') ); CONDITIONAL(eip06.data == 3, TRANSLATE('Updated Condition: NONCRITICAL') ); CONDITIONAL(eip06.data == 4, TRANSLATE('Updated Condition: UNRECOVERABLE') ); CONDITIONAL(eip06.data == 5, TRANSLATE('Updated Condition: NOT_INSTALLED') ); CONDITIONAL(eip06.data == 6, TRANSLATE('Updated Condition: UNKNOWN') ); CONDITIONAL(eip06.data == 7, TRANSLATE('Updated Condition: NOT_AVAILABLE') ); CONDITIONAL(eip06.data2 == 0, TRANSLATE('Previous Condition: UNSUPPORTED') ); CONDITIONAL(eip06.data2 == 1, TRANSLATE('Previous Condition: OK') ); CONDITIONAL(eip06.data2 == 2, TRANSLATE('Previous Condition: CRITICAL') ); CONDITIONAL(eip06.data2 == 3, TRANSLATE('Previous Condition: NONCRITICAL') ); CONDITIONAL(eip06.data2 == 4, TRANSLATE('Previous Condition: UNRECOVERABLE') ); CONDITIONAL(eip06.data2 == 5, TRANSLATE('Previous Condition: NOT_INSTALLED') );

CONDITIONAL(eip06.data2 == 6, TRANSLATE('Previous Condition: UNKNOWN') ); CONDITIONAL(eip06.data2 == 7, TRANSLATE('Previous Condition: NOT_AVAILABLE') ); ENDTRANSLATIONBLOCK EC BLOCK: 06620006 SCID_FCS_ENC_LOOP_A_DISPLAY_CONDITION_CHANGE TRANSLATIONBLOCK TRANSLATE('Enclosure Vendor Identification: %s', eip06.vendor_id); TRANSLATE('Enclosure Product Identification: %s', eip06.product_id); TRANSLATE('Enclosure Product Revision: %s', eip06.product_rev); TRANSLATE('Enclosure Saleable Serial Number: %s', eip06.enc_serial_num); TRANSLATE('Enclosure WWID (node): %08x%08x', eip06.enc_wwn.hi, eip06.enc_wwn.lo) ; CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo WWID (port): %08x%08x', eip06.loop_a_elmo_n_port_name.hi, eip06.loop_a_elmo_n_port_name.lo), TRANSLATE('Loop B ELMo WWID (port): %08x%08x', eip06.loop_b_elmo_n_port_name.hi, eip06.loop_b_elmo_n_port_name.lo) ); TRANSLATE('Enclosure %d', eip06.enc_num); CONDITIONAL(eip06.data == 0, TRANSLATE('Updated Condition: UNSUPPORTED') ); CONDITIONAL(eip06.data == 1, TRANSLATE('Updated Condition: OK') ); CONDITIONAL(eip06.data == 2, TRANSLATE('Updated Condition: CRITICAL') ); CONDITIONAL(eip06.data == 3, TRANSLATE('Updated Condition: NONCRITICAL') ); CONDITIONAL(eip06.data == 4, TRANSLATE('Updated Condition: UNRECOVERABLE') ); CONDITIONAL(eip06.data == 5, TRANSLATE('Updated Condition: NOT_INSTALLED') ); CONDITIONAL(eip06.data == 6, TRANSLATE('Updated Condition: UNKNOWN') ); CONDITIONAL(eip06.data == 7, TRANSLATE('Updated Condition: NOT_AVAILABLE') ); ENDTRANSLATIONBLOCK EC BLOCK: 06630006 SCID_FCS_ENC_LOOP_B_DISPLAY_CONDITION_CHANGE TRANSLATIONBLOCK TRANSLATE('Enclosure Vendor Identification: %s', eip06.vendor_id); TRANSLATE('Enclosure Product Identification: %s', eip06.product_id); TRANSLATE('Enclosure Product Revision: %s', eip06.product_rev); TRANSLATE('Enclosure Saleable Serial Number: %s', eip06.enc_serial_num); TRANSLATE('Enclosure WWID (node): %08x%08x', eip06.enc_wwn.hi, eip06.enc_wwn.lo) ; CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo WWID (port): %08x%08x', eip06.loop_a_elmo_n_port_name.hi, eip06.loop_a_elmo_n_port_name.lo),

TRANSLATE('Loop B ELMo WWID (port): %08x%08x', eip06.loop_b_elmo_n_port_name.hi, eip06.loop_b_elmo_n_port_name.lo) ); TRANSLATE('Enclosure %d', eip06.enc_num); CONDITIONAL(eip06.data == 0, TRANSLATE('Updated Condition: UNSUPPORTED') ); CONDITIONAL(eip06.data == 1, TRANSLATE('Updated Condition: OK') ); CONDITIONAL(eip06.data == 2, TRANSLATE('Updated Condition: CRITICAL') ); CONDITIONAL(eip06.data == 3, TRANSLATE('Updated Condition: NONCRITICAL') ); CONDITIONAL(eip06.data == 4, TRANSLATE('Updated Condition: UNRECOVERABLE') ); CONDITIONAL(eip06.data == 5, TRANSLATE('Updated Condition: NOT_INSTALLED') ); CONDITIONAL(eip06.data == 6, TRANSLATE('Updated Condition: UNKNOWN') ); CONDITIONAL(eip06.data == 7, TRANSLATE('Updated Condition: NOT_AVAILABLE') ); ENDTRANSLATIONBLOCK EC BLOCK: 06640006 SCID_FCS_ENC_LOOP_A_TEMP_SENSOR_CONDITION_CHANGE TRANSLATIONBLOCK TRANSLATE('Enclosure Vendor Identification: %s', eip06.vendor_id); TRANSLATE('Enclosure Product Identification: %s', eip06.product_id); TRANSLATE('Enclosure Product Revision: %s', eip06.product_rev); TRANSLATE('Enclosure Saleable Serial Number: %s', eip06.enc_serial_num); TRANSLATE('Enclosure WWID (node): %08x%08x', eip06.enc_wwn.hi, eip06.enc_wwn.lo) ; CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo WWID (port): %08x%08x', eip06.loop_a_elmo_n_port_name.hi, eip06.loop_a_elmo_n_port_name.lo), TRANSLATE('Loop B ELMo WWID (port): %08x%08x', eip06.loop_b_elmo_n_port_name.hi, eip06.loop_b_elmo_n_port_name.lo) ); TRANSLATE('Enclosure %d', eip06.enc_num); CONDITIONAL(eip06.data == 0, TRANSLATE('Updated Condition: UNSUPPORTED') ); CONDITIONAL(eip06.data == 1, TRANSLATE('Updated Condition: OK') ); CONDITIONAL(eip06.data == 2, TRANSLATE('Updated Condition: CRITICAL') ); CONDITIONAL(eip06.data == 3, TRANSLATE('Updated Condition: NONCRITICAL') ); CONDITIONAL(eip06.data == 4, TRANSLATE('Updated Condition: UNRECOVERABLE') );

CONDITIONAL(eip06.data == 5, TRANSLATE('Updated Condition: NOT_INSTALLED') ); CONDITIONAL(eip06.data == 6, TRANSLATE('Updated Condition: UNKNOWN') ); CONDITIONAL(eip06.data == 7, TRANSLATE('Updated Condition: NOT_AVAILABLE') ); ENDTRANSLATIONBLOCK EC BLOCK: 06650006 SCID_FCS_ENC_LOOP_B_TEMP_SENSOR_CONDITION_CHANGE TRANSLATIONBLOCK TRANSLATE('Enclosure Vendor Identification: %s', eip06.vendor_id); TRANSLATE('Enclosure Product Identification: %s', eip06.product_id); TRANSLATE('Enclosure Product Revision: %s', eip06.product_rev); TRANSLATE('Enclosure Saleable Serial Number: %s', eip06.enc_serial_num); TRANSLATE('Enclosure WWID (node): %08x%08x', eip06.enc_wwn.hi, eip06.enc_wwn.lo) ; CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo WWID (port): %08x%08x', eip06.loop_a_elmo_n_port_name.hi, eip06.loop_a_elmo_n_port_name.lo), TRANSLATE('Loop B ELMo WWID (port): %08x%08x', eip06.loop_b_elmo_n_port_name.hi, eip06.loop_b_elmo_n_port_name.lo) ); TRANSLATE('Enclosure %d', eip06.enc_num); CONDITIONAL(eip06.data == 0, TRANSLATE('Updated Condition: UNSUPPORTED') ); CONDITIONAL(eip06.data == 1, TRANSLATE('Updated Condition: OK') ); CONDITIONAL(eip06.data == 2, TRANSLATE('Updated Condition: CRITICAL') ); CONDITIONAL(eip06.data == 3, TRANSLATE('Updated Condition: NONCRITICAL') ); CONDITIONAL(eip06.data == 4, TRANSLATE('Updated Condition: UNRECOVERABLE') ); CONDITIONAL(eip06.data == 5, TRANSLATE('Updated Condition: NOT_INSTALLED') ); CONDITIONAL(eip06.data == 6, TRANSLATE('Updated Condition: UNKNOWN') ); CONDITIONAL(eip06.data == 7, TRANSLATE('Updated Condition: NOT_AVAILABLE') ); ENDTRANSLATIONBLOCK EC BLOCK: 06660006 SCID_FCS_ENC_MIDPLANE_CONDITION_CHANGE TRANSLATIONBLOCK TRANSLATE('Enclosure Vendor Identification: %s', eip06.vendor_id); TRANSLATE('Enclosure Product Identification: %s', eip06.product_id); TRANSLATE('Enclosure Product Revision: %s', eip06.product_rev); TRANSLATE('Enclosure Saleable Serial Number: %s', eip06.enc_serial_num); TRANSLATE('Enclosure WWID (node): %08x%08x', eip06.enc_wwn.hi, eip06.enc_wwn.lo) ;

CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo WWID (port): %08x%08x', eip06.loop_a_elmo_n_port_name.hi, eip06.loop_a_elmo_n_port_name.lo), TRANSLATE('Loop B ELMo WWID (port): %08x%08x', eip06.loop_b_elmo_n_port_name.hi, eip06.loop_b_elmo_n_port_name.lo) ); TRANSLATE('Enclosure %d', eip06.enc_num); CONDITIONAL(eip06.data == 0, TRANSLATE('Updated Condition: UNSUPPORTED') ); CONDITIONAL(eip06.data == 1, TRANSLATE('Updated Condition: OK') ); CONDITIONAL(eip06.data == 2, TRANSLATE('Updated Condition: CRITICAL') ); CONDITIONAL(eip06.data == 3, TRANSLATE('Updated Condition: NONCRITICAL') ); CONDITIONAL(eip06.data == 4, TRANSLATE('Updated Condition: UNRECOVERABLE') ); CONDITIONAL(eip06.data == 5, TRANSLATE('Updated Condition: NOT_INSTALLED') ); CONDITIONAL(eip06.data == 6, TRANSLATE('Updated Condition: UNKNOWN') ); CONDITIONAL(eip06.data == 7, TRANSLATE('Updated Condition: NOT_AVAILABLE') ); ENDTRANSLATIONBLOCK EC BLOCK: 06670006 SCID_FCS_ENC_MIDPLANE_TEMP_SENSOR_CONDITION_CHANGE TRANSLATIONBLOCK TRANSLATE('Enclosure Vendor Identification: %s', eip06.vendor_id); TRANSLATE('Enclosure Product Identification: %s', eip06.product_id); TRANSLATE('Enclosure Product Revision: %s', eip06.product_rev); TRANSLATE('Enclosure WWID (node): %08x%08x', eip06.enc_wwn.hi, eip06.enc_wwn.lo) ; CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo WWID (port): %08x%08x', eip06.loop_a_elmo_n_port_name.hi, eip06.loop_a_elmo_n_port_name.lo), TRANSLATE('Loop B ELMo WWID (port): %08x%08x', eip06.loop_b_elmo_n_port_name.hi, eip06.loop_b_elmo_n_port_name.lo) ); TRANSLATE('Enclosure %d', eip06.enc_num); CONDITIONAL(eip06.data == 0, TRANSLATE('Updated Condition: UNSUPPORTED') ); CONDITIONAL(eip06.data == 1, TRANSLATE('Updated Condition: OK') ); CONDITIONAL(eip06.data == 2, TRANSLATE('Updated Condition: CRITICAL') ); CONDITIONAL(eip06.data == 3, TRANSLATE('Updated Condition: NONCRITICAL') ); CONDITIONAL(eip06.data == 4,

TRANSLATE('Updated Condition: ); CONDITIONAL(eip06.data == 5, TRANSLATE('Updated Condition: ); CONDITIONAL(eip06.data == 6, TRANSLATE('Updated Condition: ); CONDITIONAL(eip06.data == 7, TRANSLATE('Updated Condition: ); ENDTRANSLATIONBLOCK

UNRECOVERABLE') NOT_INSTALLED') UNKNOWN') NOT_AVAILABLE')

EC BLOCK: 06684c13 SCID_FCS_IOMODULE_SPOF TRANSLATIONBLOCK TRANSLATE('Good port ID: %s', eip13.cerp_id); TRANSLATE('Missing port ID: %s', eip13.missing_cerp_id); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE('Last known enclosure: %d.', eip13.dencl_num - 100 ) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE('Enclosure: %d.', eip13.dencl_num) ); TRANSLATE('Bay Bypass Mask Loop A 0x%X',eip13.bypassa); TRANSLATE('Bay Bypass Mask Loop B 0x%X',eip13.bypassb); TRANSLATE('Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information', eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 06690013 SCID_FCS_IOMODULE_SPOF_FIXED TRANSLATIONBLOCK TRANSLATE('Port ID: %s', eip13.cerp_id); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 &&

eip13.al_pa != 0xEE && eip13.dencl_num == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num > 99, TRANSLATE('Last known enclosure: %d.', eip13.dencl_num - 100 ) ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip13.al_pa != 0x01 && eip13.al_pa != 0x02 && eip13.al_pa != 0xEE && eip13.dencl_num < 99, TRANSLATE('Enclosure: %d.', eip13.dencl_num) ); TRANSLATE('Bay Bypass Mask Loop A 0x%X',eip13.bypassa); TRANSLATE('Bay Bypass Mask Loop B 0x%X',eip13.bypassb); TRANSLATE('Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information', eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 066a0028 SCID_FCS_LINK_TRANSITION TRANSLATIONBLOCK TRANSLATE('Controller: %[wwn]', eip28.node_name); TRANSLATE('Port ID: %s', eip28.cerp_id); CONDITIONAL(eip28.status == 2, TRANSLATE('Link came up') ); CONDITIONAL(eip28.status == 1, TRANSLATE('Link went down') ); CONDITIONAL(eip28.level == 1, TRANSLATE('State-level transition') ); CONDITIONAL(eip28.level == 0, TRANSLATE('Transport-level transition') ); CONDITIONAL(eip28.port_count > 0, TRANSLATE('Port 0 FM status: 0x%08X', eip28.fm_status[0]) ); CONDITIONAL(eip28.port_count > 1, TRANSLATE('Port 1 FM status: 0x%08X', eip28.fm_status[1]) ); CONDITIONAL(eip28.port_count > 2, TRANSLATE('Port 2 FM status: 0x%08X', eip28.fm_status[2])

); CONDITIONAL(eip28.port_count > 3, TRANSLATE('Port 3 FM status: 0x%08X', eip28.fm_status[3]) ); CONDITIONAL(eip28.port_count > 4, TRANSLATE('Port 4 FM status: 0x%08X', eip28.fm_status[4]) ); CONDITIONAL(eip28.port_count > 5, TRANSLATE('Port 5 FM status: 0x%08X', eip28.fm_status[5]) ); CONDITIONAL(eip28.port_count > 6, TRANSLATE('Port 6 FM status: 0x%08X', eip28.fm_status[6]) ); CONDITIONAL(eip28.port_count > 7, TRANSLATE('Port 7 FM status: 0x%08X', eip28.fm_status[7]) ); ENDTRANSLATIONBLOCK EC BLOCK: 066b0028 SCID_FCS_LINK_STO TRANSLATIONBLOCK TRANSLATE('Controller: %[wwn]', eip28.node_name); TRANSLATE('Port ID: %s', eip28.cerp_id); TRANSLATE('LPSM: 0x%2X', eip28.level); CONDITIONAL(eip28.status == 0, TRANSLATE('No Reset Done') ); CONDITIONAL(eip28.status == 1, TRANSLATE('Link was Reset') ); CONDITIONAL(eip28.port_count > 0, TRANSLATE('Port 0 FM status: 0x%08X', eip28.fm_status[0]) ); CONDITIONAL(eip28.port_count > 1, TRANSLATE('Port 1 FM status: 0x%08X', eip28.fm_status[1]) ); CONDITIONAL(eip28.port_count > 2, TRANSLATE('Port 2 FM status: 0x%08X', eip28.fm_status[2]) ); CONDITIONAL(eip28.port_count > 3, TRANSLATE('Port 3 FM status: 0x%08X', eip28.fm_status[3]) ); CONDITIONAL(eip28.port_count > 4, TRANSLATE('Port 4 FM status: 0x%08X', eip28.fm_status[4]) ); CONDITIONAL(eip28.port_count > 5, TRANSLATE('Port 5 FM status: 0x%08X', eip28.fm_status[5]) ); CONDITIONAL(eip28.port_count > 6, TRANSLATE('Port 6 FM status: 0x%08X', eip28.fm_status[6]) ); CONDITIONAL(eip28.port_count > 7, TRANSLATE('Port 7 FM status: 0x%08X', eip28.fm_status[7]) ); ENDTRANSLATIONBLOCK EC BLOCK: 066c0008 SCID_FCS_ELMO_CODELOAD_COMPLETE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK EC BLOCK: 066df308 SCID_FCS_ELMO_CODELOAD_BLOCKED

TRANSLATIONBLOCK ENDTRANSLATIONBLOCK EC BLOCK: 066e0008 SCID_FCS_ELMO_CODELOAD_CONTINUE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK EC BLOCK: 066f0009 SCID_FCS_PRLI_FAILURE TRANSLATIONBLOCK TRANSLATE('Port ID: %s', eip09.cerp_id); TRANSLATE('Count: %d', eip09.al_pa); ENDTRANSLATIONBLOCK EC BLOCK: 06700009 SCID_FCS_PLOGI_FAILURE TRANSLATIONBLOCK TRANSLATE('Port ID: %s', eip09.cerp_id); TRANSLATE('Count: %d', eip09.al_pa); ENDTRANSLATIONBLOCK EC BLOCK: 0671f406 SCID_FCS_ENCLOSURE_PS_CONDITION_CRITICAL TRANSLATIONBLOCK TRANSLATE('Enclosure Vendor Identification: %s', eip06.vendor_id); TRANSLATE('Enclosure Product Identification: %s', eip06.product_id); TRANSLATE('Enclosure Product Revision: %s', eip06.product_rev); TRANSLATE('Enclosure Saleable Serial Number: %s', eip06.enc_serial_num); TRANSLATE('Enclosure WWID (node): %08x%08x', eip06.enc_wwn.hi, eip06.enc_wwn.lo) ; TRANSLATE('Enclosure Number: %d', eip06.enc_num); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo WWID (port): %08x%08x', eip06.loop_a_elmo_n_port_name.hi, eip06.loop_a_elmo_n_port_name.lo), TRANSLATE('Loop B ELMo WWID (port): %08x%08x', eip06.loop_b_elmo_n_port_name.hi, eip06.loop_b_elmo_n_port_name.lo) ); TRANSLATE('Enclosure %d', eip06.enc_num); CONDITIONAL(eip06.data2 == 1, TRANSLATE('Power Supply: PS 1')); CONDITIONAL(eip06.data2 == 2, TRANSLATE('Power Supply: PS 2')); CONDITIONAL(eip06.data2 != 1 && eip06.data2 != 2, TRANSLATE('Power Supply: PS Un known')); ENDTRANSLATIONBLOCK EC BLOCK: 0700b515 SCID_CS_ALLOCATION_STALL TRANSLATIONBLOCK TRANSLATE('Virtual Disk: %[tag]', eip15.tag1); TRANSLATE('Disk Group: %[tag]', eip15.tag2); CONDITIONAL(eip15.state == 0, TRANSLATE('State: Attempting to retry allocation') ); CONDITIONAL(eip15.state == 1, TRANSLATE('State: Awaiting a leveling event') ); ENDTRANSLATIONBLOCK EC BLOCK: 0701b515 SCID_CS_EXPANSION_STALL TRANSLATIONBLOCK TRANSLATE('Virtual Disk: %[tag]', eip15.tag1); TRANSLATE('Disk Group: %[tag]', eip15.tag2); CONDITIONAL(eip15.state == 0, TRANSLATE('State: Attempting to retry allocation') );

CONDITIONAL(eip15.state == 1, TRANSLATE('State: Awaiting a leveling event') ); ENDTRANSLATIONBLOCK EC BLOCK: 07020015 SCID_CS_LEVELING_START TRANSLATIONBLOCK TRANSLATE('Disk Group: %[tag]', eip15.tag1); ENDTRANSLATIONBLOCK EC BLOCK: 07030015 SCID_CS_LEVELING_END TRANSLATIONBLOCK TRANSLATE('Disk Group: %[tag]', eip15.tag1); CONDITIONAL(eip15.state == 0, TRANSLATE('Not Level'), TRANSLATE('Level') ); CONDITIONAL(eip15.status == 0, TRANSLATE('No Data Moved'), TRANSLATE('Data Moved') ); ENDTRANSLATIONBLOCK EC BLOCK: 07040015 SCID_CS_MEMBER_MANAGER_OP_START TRANSLATIONBLOCK CONDITIONAL(eip15.tag1 eq '0000-0000-0000-0000-0000-0000-0000-0000', TRANSLATE('Volume identity unavailable'), TRANSLATE('Volume: %[tag]', eip15.tag1) ); TRANSLATE('Physical Disk Drive: %[tag]', eip15.tag2); CONDITIONAL(eip15.state == 2, TRANSLATE('State: Reconstructing') ); CONDITIONAL(eip15.state == 4, TRANSLATE('State: Migrating') ); CONDITIONAL(eip15.state == 6, TRANSLATE('State: Reverting') ); ENDTRANSLATIONBLOCK EC BLOCK: 07050015 SCID_CS_MEMBER_MANAGER_OP_END TRANSLATIONBLOCK CONDITIONAL(eip15.tag1 eq '0000-0000-0000-0000-0000-0000-0000-0000', TRANSLATE('Volume identity unavailable'), TRANSLATE('Volume: %[tag]', eip15.tag1) ); TRANSLATE('Physical Disk Drive: %[tag]', eip15.tag2); CONDITIONAL(eip15.state == 2, TRANSLATE('State: Reconstructing') ); CONDITIONAL(eip15.state == 4, TRANSLATE('State: Migrating') ); CONDITIONAL(eip15.state == 6, TRANSLATE('State: Reverting') ); CONDITIONAL(eip15.status == 1, TRANSLATE('Status: success') );

CONDITIONAL(eip15.status TRANSLATE('Status: RAID0 ); CONDITIONAL(eip15.status TRANSLATE('Status: RAID5 ); CONDITIONAL(eip15.status TRANSLATE('Status: RAID1 ); ENDTRANSLATIONBLOCK

== 2, reconstruct failed') == 4, reconstruct failed') == 8, reconstruct failed')

EC BLOCK: 07060015 SCID_CS_MIGRATION_START TRANSLATIONBLOCK TRANSLATE('Disk Group: %[tag]', eip15.tag1); CONDITIONAL(eip15.state == 4, TRANSLATE('State: Merge began') ); CONDITIONAL(eip15.state == 8, TRANSLATE('State: Split began') ); ENDTRANSLATIONBLOCK EC BLOCK: 07070015 SCID_CS_MIGRATION_END TRANSLATIONBLOCK TRANSLATE('Disk Group: %[tag]', eip15.tag1); CONDITIONAL(eip15.state == 4, TRANSLATE('State: Merge complete') ); CONDITIONAL(eip15.state == 8, TRANSLATE('State: Split complete') ); ENDTRANSLATIONBLOCK EC BLOCK: 07080015 SCID_CS_DELETION_FAILED TRANSLATIONBLOCK TRANSLATE('Virtual Disk: %[tag]', eip15.tag1); TRANSLATE('Disk group: %[tag]', eip15.tag2); TRANSLATE('Status: %d', eip15.status); ENDTRANSLATIONBLOCK EC BLOCK: 0709b515 SCID_CS_MEMBER_MANAGER_OP_STALL TRANSLATIONBLOCK CONDITIONAL(eip15.tag1 eq '0000-0000-0000-0000-0000-0000-0000-0000', TRANSLATE('Volume identity unavailable'), TRANSLATE('Volume: %[tag]', eip15.tag1) ); TRANSLATE('Physical Disk Drive: %[tag]', eip15.tag2); CONDITIONAL(eip15.state == 4, TRANSLATE('State: Migrating') ); CONDITIONAL(eip15.status == 1, TRANSLATE('Status: Awaiting additional storage') ); ENDTRANSLATIONBLOCK EC BLOCK: 070a0015 SCID_CS_MEMBER_MANAGER_OP_RESTART TRANSLATIONBLOCK CONDITIONAL(eip15.tag1 eq '0000-0000-0000-0000-0000-0000-0000-0000', TRANSLATE('Volume identity unavailable'), TRANSLATE('Volume: %[tag]', eip15.tag1)

); TRANSLATE('Physical Disk Drive: %[tag]', eip15.tag2); CONDITIONAL(eip15.state == 4, TRANSLATE('State: Migrating') ); CONDITIONAL(eip15.status == 0, TRANSLATE('Status: Retrying the operation') ); ENDTRANSLATIONBLOCK EC BLOCK: 070d0015 SCID_CS_MEMBER_MANAGER_OP_ERROR TRANSLATIONBLOCK TRANSLATE('Logical Disk: %[tag]', eip15.tag1); TRANSLATE('Volume: %[tag]', eip15.tag2); CONDITIONAL(eip15.state == 2, TRANSLATE('State: Reconstructing') ); CONDITIONAL(eip15.state == 4, TRANSLATE('State: Migrating') ); CONDITIONAL(eip15.state == 6, TRANSLATE('State: Reverting') ); TRANSLATE('Error: 0x%x', eip15.status); TRANSLATE('Error: 0x01 = Missing Drive'); TRANSLATE('Error: 0x02 = Invalid RAID type'); TRANSLATE('Error: 0x04 = Invalid member management opeartion'); TRANSLATE('Error: 0x08 = Invalid RStore'); TRANSLATE('Error: 0x10 = LD Realization Failed'); ENDTRANSLATIONBLOCK EC BLOCK: 070e0015 SCID_CS_EBIT_OPERATION TRANSLATIONBLOCK CONDITIONAL(eip15.state == 1, TRANSLATE('E-bit SET') ); CONDITIONAL(eip15.state == 2, TRANSLATE('E-bit CLEAR') ); CONDITIONAL(eip15.state == 5, TRANSLATE('E-bit CHANGE') ); CONDITIONAL(eip15.state == 6, TRANSLATE('E-bit COPY') ); TRANSLATE('Logical Disk: %[tag]', eip15.tag1); TRANSLATE('LBA: %[tag]', eip15.tag2); TRANSLATE('Blocks: 0x%8x', eip15.status); ENDTRANSLATIONBLOCK EC BLOCK: 070f0015 SCID_CS_MEMBER_MANAGER_OP_WARNING TRANSLATIONBLOCK CONDITIONAL(eip15.tag1 eq '0000-0000-0000-0000-0000-0000-0000-0000', TRANSLATE('Volume identity unavailable'), TRANSLATE('Volume: %[tag]', eip15.tag1) ); TRANSLATE('Physical Disk Drive: %[tag]', eip15.tag2); CONDITIONAL(eip15.state == 2, TRANSLATE('State: Reconstructing') );

CONDITIONAL(eip15.state == 4, TRANSLATE('State: Migrating') ); CONDITIONAL(eip15.state == 6, TRANSLATE('State: Reverting') ); TRANSLATE('Status: 0x%8x', eip15.status); ENDTRANSLATIONBLOCK EC BLOCK: 07110015 SCID_CS_MIGRATION_LEVELING_WARNING TRANSLATIONBLOCK TRANSLATE('Disk Group: %[tag]', eip15.tag1); TRANSLATE('Virtual Disk: %[tag]', eip15.tag2); TRANSLATE('Max RSDM: 0x%08x', eip15.state); TRANSLATE('Data Moved/RaidType/Bad RSDMs: 0x%08x', eip15.status); TRANSLATE(' Data Moved Bit 31'); TRANSLATE(' Raid Type (2=R1MD, 4=R1, 5=R5, 6=R6) Bits 24-27'); TRANSLATE(' Bad RSDMs Bits 0-19'); ENDTRANSLATIONBLOCK EC BLOCK: 07120015 SCID_CS_MIGRATION_RESCAN_WARNING TRANSLATIONBLOCK TRANSLATE('Disk Group: %[tag]', eip15.tag1); TRANSLATE('Virtual Disk: %[tag]', eip15.tag2); TRANSLATE('Level: 0x%08x', eip15.state); TRANSLATE('No_Data_Moved: 0x%08x', eip15.status); ENDTRANSLATIONBLOCK EC BLOCK: 07130715 SCID_CS_PLDMC_HOLE TRANSLATIONBLOCK TRANSLATE('Virtual Disk: %[tag]', eip15.tag1); TRANSLATE('Num. RSTOREs (from ldcapacity): 0x%x', eip15.state); TRANSLATE('Status: 0x%x', eip15.status); TRANSLATE(' DR Log: Bits 30-31' ); TRANSLATE(' 0 = Not DR Log' ); TRANSLATE(' 1 = DR Log ' ); TRANSLATE(' 3 = NULL SCVD ' ); TRANSLATE(' LDAD: Bits 24-29' ); TRANSLATE(' 0x3f = NULL SCVD ' ); TRANSLATE(' RAID Type: Bits 16-23' ); TRANSLATE(' 0 = UNALLOC ' ); TRANSLATE(' 1 = Quorum Space ' ); TRANSLATE(' 2 = RAID1MD ' ); TRANSLATE(' 3 = RAID-0 (4+0) ' ); TRANSLATE(' 4 = RAID-0+1 (4x2)' ); TRANSLATE(' 5 = RAID-5 (4+1) ' ); TRANSLATE(' 6 = RAID-6 (4+2) ' ); TRANSLATE(' 7 = Physical Drive' ); TRANSLATE(' Count: Bits 0-15' ); TRANSLATE('RSIDX array (1/byte): %[tag]', eip15.tag2); ENDTRANSLATIONBLOCK EC BLOCK: 07140715 SCID_CS_PSAS_CHECK TRANSLATIONBLOCK TRANSLATE('physical disk drive: %[tag]', eip15.tag1); CONDITIONAL(eip15.status == 0, TRANSLATE('Count: 0x%x', eip15.state) ); CONDITIONAL(eip15.status != 0, TRANSLATE('PSAS scan skipped: Failed to allocate memory')

); ENDTRANSLATIONBLOCK EC BLOCK: 07150015 SCID_CS_EXPAND_SHRINK_FAILED TRANSLATIONBLOCK CONDITIONAL(eip15.state == 100, TRANSLATE('Operation type: Shrink.') ); CONDITIONAL(eip15.state == 0x01, TRANSLATE(' Operation type: Expand Normal.') ); CONDITIONAL(eip15.state == 0x04, TRANSLATE(' Operation type: Expand DRM.') ); CONDITIONAL(eip15.state == 0x20, TRANSLATE(' Operation type: Reserve.') ); CONDITIONAL(eip15.state == 0x40, TRANSLATE(' Operation type: Unreserve.') ); TRANSLATE('Virtual Disk: %[tag]', eip15.tag1 ); TRANSLATE('Logical Disk: %[tag]', eip15.tag2 ); TRANSLATE('Status: %X.', eip15.status ); CONDITIONAL(eip15.status == 100, TRANSLATE(' (The ldad has no capacity to request raid type).') ); CONDITIONAL(eip15.status == 130, TRANSLATE(' (Allocation has exceeded the supported limit).') ); CONDITIONAL(eip15.status == 128, TRANSLATE(' (Delete in progress).') ); CONDITIONAL(eip15.status == 109, TRANSLATE(' (Invalid object ID).') ); CONDITIONAL(eip15.status == 237, TRANSLATE(' (LBA not found).') ); CONDITIONAL(eip15.status == 133, TRANSLATE( ' (LD or VD associated with SCVD has predecessor/successor).') ); CONDITIONAL(eip15.status == 1, TRANSLATE(' (Metadata Inoperative - Initiating cell resync).') ); ENDTRANSLATIONBLOCK EC BLOCK: 09010005 SCID_SCMI_PS_CONDITION_CHANGE_NOACT TRANSLATIONBLOCK TRANSLATE('Physical disk drive: %[scmi_obj_hnd]', eip05.handle ); TRANSLATE( 'State: %[scmi_physical_store_condition] --> %[scmi_physical_store_condition]', eip05.value.ul2, eip05.value.ul1 );

CONDITIONAL(eip05.attribute.value.u32[0] == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE('Enclosure: %d.', eip05.attribute.value.u32[0]) ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE('Bay: %d.', eip05.attribute.value.u32[1]) ); ENDTRANSLATIONBLOCK EC BLOCK: 09020005 SCID_SCMI_VOL_CONDITION_CHANGE_NOACT TRANSLATIONBLOCK TRANSLATE('Volume: %[scmi_obj_hnd]', eip05.handle); TRANSLATE('Associated physical disk drive: %[scmi_obj_hnd]', eip05.add_handle ); TRANSLATE( 'State: %[scmi_volume_condition] --> %[scmi_volume_condition]', eip05.value.ul2, eip05.value.ul1 ); CONDITIONAL(eip05.attribute.value.u32[0] == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE('Enclosure: %d.', eip05.attribute.value.u32[0]) ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE('Bay: %d.', eip05.attribute.value.u32[1]) ); TRANSLATE('Redundant Storage Set Identification: 0x%04x, (%d)', eip05.attribute.value.u16[6], eip05.attribute.value.u16[6] ); TRANSLATE('Redundant Storage Set Index: 0x%04x, (%d)', eip05.attribute.value.u16[7], eip05.attribute.value.u16[7] ); ENDTRANSLATIONBLOCK EC BLOCK: 09040005 SCID_SCMI_NSC_CONDITION_CHANGE_NORMAL TRANSLATIONBLOCK TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE( 'State: %[scmi_nsc_condition] --> %[scmi_nsc_condition]', eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09050005 SCID_SCMI_NSC_CACHE_BATT_CONDITION_CHANGE_NOACT TRANSLATIONBLOCK TRANSLATE('Controller containing battery: %[scmi_obj_hnd]',

eip05.handle ); TRANSLATE( 'State: %[scmi_nsc_battery_system_condition] --> %[scmi_nsc_battery_system_condi tion]', eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 0906bf05 SCID_SCMI_VOL_CONDITION_CHANGE_MISSING TRANSLATIONBLOCK TRANSLATE('Volume: %[scmi_obj_hnd]', eip05.handle); TRANSLATE('Associated physical disk drive: %[scmi_obj_hnd]', eip05.add_handle ); TRANSLATE( 'State: %[scmi_volume_condition] --> %[scmi_volume_condition]', eip05.value.ul2, eip05.value.ul1 ); CONDITIONAL(eip05.attribute.value.u32[0] == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE('Enclosure: %d.', eip05.attribute.value.u32[0]) ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE('Bay: %d.', eip05.attribute.value.u32[1]) ); TRANSLATE('Redundant Storage Set Identification: 0x%04x, (%d)', eip05.attribute.value.u16[6], eip05.attribute.value.u16[6] ); TRANSLATE('Redundant Storage Set Index: 0x%04x, (%d)', eip05.attribute.value.u16[7], eip05.attribute.value.u16[7] ); ENDTRANSLATIONBLOCK EC BLOCK: 09070005 SCID_SCMI_NSC_FC_PORT_CONDITION_CHANGE_NORMAL TRANSLATIONBLOCK TRANSLATE('Fibre Channel port: %s (%d.)', eip05.attribute.value.str, eip05.secondary_id ); TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE( 'State: %[scmi_nsc_fc_port_condition] --> %[scmi_nsc_fc_port_condition]', eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 0908b405 SCID_SCMI_LDAD_OCCUPANCY_HIGHWATER TRANSLATIONBLOCK TRANSLATE('Disk Group: %[scmi_obj_hnd]',

eip05.handle ); TRANSLATE('State: Normal --> Threshold reached'); ENDTRANSLATIONBLOCK EC BLOCK: 09090005 SCID_SCMI_VOL_INSUFF_RESOURCE_CHANGE_SUFFICIENT TRANSLATIONBLOCK TRANSLATE('Volume: %[scmi_obj_hnd]', eip05.handle); TRANSLATE('Associated physical disk drive: %[scmi_obj_hnd]', eip05.add_handle ); TRANSLATE( 'State: %[scmi_volume_resource_availability_condition] --> %[scmi_volume_resourc e_availability_condition]', eip05.value.ul2, eip05.value.ul1 ); CONDITIONAL(eip05.attribute.value.u32[0] == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE('Enclosure: %d.', eip05.attribute.value.u32[0]) ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE('Bay: %d.', eip05.attribute.value.u32[1]) ); TRANSLATE('Redundant Storage Set Identification: 0x%04x, (%d)', eip05.attribute.value.u16[6], eip05.attribute.value.u16[6] ); TRANSLATE('Redundant Storage Set Index: 0x%04x, (%d)', eip05.attribute.value.u16[7], eip05.attribute.value.u16[7] ); ENDTRANSLATIONBLOCK EC BLOCK: 090c0005 SCID_SCMI_LDISK_SNAPCLONE_UNSHARE_DONE TRANSLATIONBLOCK TRANSLATE('Snapclone Logical Disk: %[scmi_obj_hnd]', eip05.handle); TRANSLATE('Noid of parent internal Logical Disk: 0x%04x', eip05.secondary_id ); ENDTRANSLATIONBLOCK EC BLOCK: 090d0005 SCID_SCMI_VOL_QUORUM_DISK_CHANGE TRANSLATIONBLOCK TRANSLATE('Volume: %[scmi_obj_hnd]', eip05.handle); TRANSLATE( 'State: %[scmi_volume_quorum_disk_condition] --> %[scmi_volume_quorum_disk_condi tion]', eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 090e3605 SCID_SCMI_NSC_TEMP_TRIP_REACHED TRANSLATIONBLOCK

TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE( 'Sensor 1 current temperature: %d. degrees Celsius', eip05.value.ul1 ); TRANSLATE( 'Sensor 2 adjusted temperature: %d. degrees Celsius', eip05.value.ul2 ); TRANSLATE( 'Trip point temperature: %d. degrees Celsius', eip05.secondary_id ); ENDTRANSLATIONBLOCK EC BLOCK: 090f2e05 SCID_SCMI_NSC_CLOSE_TO_TEMP_TRIP TRANSLATIONBLOCK TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE( 'Sensor 1 current temperature: %d. degrees Celsius', eip05.value.ul1 ); TRANSLATE( 'Sensor 2 adjusted temperature: %d. degrees Celsius', eip05.value.ul2 ); TRANSLATE( 'Trip point temperature: %d. degrees Celsius', eip05.secondary_id ); ENDTRANSLATIONBLOCK EC BLOCK: 09110005 SCID_SCMI_NSC_FANA_PRESENT_CHANGE_NPP TRANSLATIONBLOCK TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE('Blower assembly: %d.', eip05.secondary_id); TRANSLATE( 'State: %[scmi_nsc_fan_present_condition] --> %[scmi_nsc_fan_present_condition]' , eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09122405 SCID_SCMI_NSC_FANA_SPEED_SLOW TRANSLATIONBLOCK TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE('Blower assembly: %d.', eip05.secondary_id); TRANSLATE('Current speed: %d. RPM', eip05.value.ul1); TRANSLATE('Lowest acceptable speed: %d. RPM', eip05.value.ul2); ENDTRANSLATIONBLOCK EC BLOCK: 09132005 SCID_SCMI_NSC_VOLTAGE_OUT_OF_RANGE TRANSLATIONBLOCK CONDITIONAL( eip05.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) );

TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE('Out of range voltage: %d. millivolts', eip05.value.ul1); TRANSLATE('Voltage threshold: %d. millivolts', eip05.secondary_id); TRANSLATE('Policy memory size: %d MB', eip05.add_data[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 0914bf05 SCID_SCMI_VOL_CONDITION_CHANGE_FAILED TRANSLATIONBLOCK TRANSLATE('Volume: %[scmi_obj_hnd]', eip05.handle); TRANSLATE( 'State: %[scmi_volume_condition] --> %[scmi_volume_condition]', eip05.value.ul2, eip05.value.ul1 ); CONDITIONAL(eip05.attribute.value.u32[0] == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE('Enclosure: %d.', eip05.attribute.value.u32[0]) ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE('Bay: %d.', eip05.attribute.value.u32[1]) ); TRANSLATE('Redundant Storage Set Identification: 0x%04x, (%d)', eip05.attribute.value.u16[6], eip05.attribute.value.u16[6] ); TRANSLATE('Redundant Storage Set Index: 0x%04x, (%d)', eip05.attribute.value.u16[7], eip05.attribute.value.u16[7] ); ENDTRANSLATIONBLOCK EC BLOCK: 0915b905 SCID_SCMI_NSC_CONDITION_CHANGE_FAILED TRANSLATIONBLOCK TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE( 'State: %[scmi_nsc_condition] --> %[scmi_nsc_condition]', eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09160005 SCID_SCMI_NSC_TEMP_NORMAL TRANSLATIONBLOCK TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE( 'Sensor 1 current temperature: %d. degrees Celsius', eip05.value.ul1 ); TRANSLATE( 'Sensor 2 adjusted temperature: %d. degrees Celsius', eip05.value.ul2 ); ENDTRANSLATIONBLOCK EC BLOCK: 09172805 SCID_SCMI_NSC_BATTERYA_PRESENT_CHANGE_PNP

TRANSLATIONBLOCK TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE('Battery assembly: %d.', eip05.secondary_id); TRANSLATE( 'State: %[scmi_nsc_battery_present_condition] --> %[scmi_nsc_battery_present_con dition]', eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09180005 SCID_SCMI_NSC_BATTERYA_IN_USE_CHANGE TRANSLATIONBLOCK TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE('Battery assembly: %d.', eip05.secondary_id); TRANSLATE( 'State: %[scmi_nsc_battery_use_condition] --> %[scmi_nsc_battery_use_condition]' , eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09190005 SCID_SCMI_NSC_VOLTAGE_NORMAL TRANSLATIONBLOCK TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE('Normal range voltage: %d. millivolts', eip05.value.ul1); TRANSLATE('Voltage threshold: %d. millivolts', eip05.secondary_id); ENDTRANSLATIONBLOCK EC BLOCK: 091a2005 SCID_SCMI_NSC_VOLTAGE_REGULATOR_FAILURE TRANSLATIONBLOCK CONDITIONAL( eip05.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE('Policy memory size: %d MB', eip05.add_data[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 091b0005 SCID_SCMI_LDAD_CONDITION_CHANGE_NORMAL TRANSLATIONBLOCK TRANSLATE('Disk Group: %[scmi_obj_hnd]', eip05.handle ); TRANSLATE( 'State: %[scmi_ldad_condition] --> %[scmi_ldad_condition]', eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 091c0005 SCID_SCMI_LDAD_OCCUPANCY_HIGHWATER_NORMAL TRANSLATIONBLOCK TRANSLATE('Disk Group: %[scmi_obj_hnd]', eip05.handle ); TRANSLATE('State: Threshold reached --> Normal');

ENDTRANSLATIONBLOCK EC BLOCK: 091d2205 SCID_SCMI_NSC_BATTERYA_BAD TRANSLATIONBLOCK TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE('Battery assembly: %d.', eip05.secondary_id); TRANSLATE( 'State: %[scmi_nsc_battery_use_condition] --> %[scmi_nsc_battery_use_condition]' , eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 091e0005 SCID_SCMI_NSC_BATTERYA_PRESENT_CHANGE_NPP TRANSLATIONBLOCK TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE('Battery assembly: %d.', eip05.secondary_id); TRANSLATE( 'State: %[scmi_nsc_battery_present_condition] --> %[scmi_nsc_battery_present_con dition]', eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 091f2905 SCID_SCMI_NSC_BATTERYB_PRESENT_CHANGE_PNP TRANSLATIONBLOCK TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE('Battery assembly: %d.', eip05.secondary_id); TRANSLATE( 'State: %[scmi_nsc_battery_present_condition] --> %[scmi_nsc_battery_present_con dition]', eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09200005 SCID_SCMI_NSC_BATTERYB_PRESENT_CHANGE_NPP TRANSLATIONBLOCK TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE('Battery assembly: %d.', eip05.secondary_id); TRANSLATE( 'State: %[scmi_nsc_battery_present_condition] --> %[scmi_nsc_battery_present_con dition]', eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09210005 SCID_SCMI_NSC_BATTERYB_IN_USE_CHANGE TRANSLATIONBLOCK TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE('Battery assembly: %d.', eip05.secondary_id); TRANSLATE( 'State: %[scmi_nsc_battery_use_condition] --> %[scmi_nsc_battery_use_condition]' , eip05.value.ul2, eip05.value.ul1 );

ENDTRANSLATIONBLOCK EC BLOCK: 09222305 SCID_SCMI_NSC_BATTERYB_BAD TRANSLATIONBLOCK TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE('Battery assembly: %d.', eip05.secondary_id); TRANSLATE( 'State: %[scmi_nsc_battery_use_condition] --> %[scmi_nsc_battery_use_condition]' , eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09232b05 SCID_SCMI_NSC_FANB_PRESENT_CHANGE_PNP TRANSLATIONBLOCK TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE('Blower assembly: %d.', eip05.secondary_id); TRANSLATE( 'State: %[scmi_nsc_fan_present_condition] --> %[scmi_nsc_fan_present_condition]' , eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09240005 SCID_SCMI_NSC_FANB_PRESENT_CHANGE_NPP TRANSLATIONBLOCK TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE('Blower assembly: %d.', eip05.secondary_id); TRANSLATE( 'State: %[scmi_nsc_fan_present_condition] --> %[scmi_nsc_fan_present_condition]' , eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09252505 SCID_SCMI_NSC_FANB_SPEED_SLOW TRANSLATIONBLOCK TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE('Blower assembly: %d.', eip05.secondary_id); TRANSLATE('Current speed: %d. RPM', eip05.value.ul1); TRANSLATE('Lowest acceptable speed: %d. RPM', eip05.value.ul2); ENDTRANSLATIONBLOCK EC BLOCK: 09262c05 SCID_SCMI_NSC_FANA_PRESENT_CHANGE_PNP__POWER_SUPPLY TRANSLATIONBLOCK TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE('Blower/Power Supply assembly: %d.', eip05.secondary_id); TRANSLATE( 'State: %[scmi_nsc_fanps_present_condition] --> %[scmi_nsc_fanps_present_conditi on]', eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09270005 SCID_SCMI_NSC_FANA_PRESENT_CHANGE_NPP__POWER_SUPPLY TRANSLATIONBLOCK

TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE('Blower/Power Supply assembly: %d.', eip05.secondary_id); TRANSLATE( 'State: %[scmi_nsc_fanps_present_condition] --> %[scmi_nsc_fanps_present_conditi on]', eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09282d05 SCID_SCMI_NSC_FANB_PRESENT_CHANGE_PNP__POWER_SUPPLY TRANSLATIONBLOCK TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE('Blower/Power Supply assembly: %d.', eip05.secondary_id); TRANSLATE( 'State: %[scmi_nsc_fanps_present_condition] --> %[scmi_nsc_fanps_present_conditi on]', eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09290005 SCID_SCMI_NSC_FANB_PRESENT_CHANGE_NPP__POWER_SUPPLY TRANSLATIONBLOCK TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE('Blower/Power Supply assembly: %d.', eip05.secondary_id); TRANSLATE( 'State: %[scmi_nsc_fanps_present_condition] --> %[scmi_nsc_fanps_present_conditi on]', eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 092a2605 SCID_SCMI_NSC_FANA_SPEED_SLOW__POWER_SUPPLY TRANSLATIONBLOCK TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE('Blower/Power Supply assembly: %d.', eip05.secondary_id); TRANSLATE('Current speed: %d. RPM', eip05.value.ul1); TRANSLATE('Lowest acceptable speed: %d. RPM', eip05.value.ul2); ENDTRANSLATIONBLOCK EC BLOCK: 092b2705 SCID_SCMI_NSC_FANB_SPEED_SLOW__POWER_SUPPLY TRANSLATIONBLOCK TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE('Blower/Power Supply assembly: %d.', eip05.secondary_id); TRANSLATE('Current speed: %d. RPM', eip05.value.ul1); TRANSLATE('Lowest acceptable speed: %d. RPM', eip05.value.ul2); ENDTRANSLATIONBLOCK EC BLOCK: 092c2f05 SCID_SCMI_NSC_CACHE_BATT_CONDITION_CHANGE_BAD TRANSLATIONBLOCK TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE( 'State: %[scmi_nsc_battery_system_condition] --> %[scmi_nsc_battery_system_condi tion]', eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK

EC BLOCK: 092dbf05 SCID_SCMI_VOL_INSUFF_RESOURCE_CHANGE_INSUFFICIENT TRANSLATIONBLOCK TRANSLATE('Volume: %[scmi_obj_hnd]', eip05.handle); TRANSLATE('Associated physical disk drive: %[scmi_obj_hnd]', eip05.add_handle ); TRANSLATE( 'State: %[scmi_volume_resource_availability_condition] --> %[scmi_volume_resourc e_availability_condition]', eip05.value.ul2, eip05.value.ul1 ); CONDITIONAL(eip05.attribute.value.u32[0] == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE('Enclosure: %d.', eip05.attribute.value.u32[0]) ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE('Bay: %d.', eip05.attribute.value.u32[1]) ); TRANSLATE('Redundant Storage Set Identification: 0x%04x, (%d)', eip05.attribute.value.u16[6], eip05.attribute.value.u16[6] ); TRANSLATE('Redundant Storage Set Index: 0x%04x, (%d)', eip05.attribute.value.u16[7], eip05.attribute.value.u16[7] ); ENDTRANSLATIONBLOCK EC BLOCK: 092e0005 SCID_SCMI_NSC_LOGIN_FAILURE TRANSLATIONBLOCK TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE( 'Storage System Management Interface command: %[scmi_object_function_code]', eip05.value.ul1 ); TRANSLATE('Host Adapter: %[scmi_obj_hnd]', eip05.attribute.value.obj.handle); TRANSLATE( 'Reject reason: %[scmi_response_status_value]', eip05.secondary_id ); ENDTRANSLATIONBLOCK EC BLOCK: 092f0005 SCID_SCMI_NSC_COMMAND_ERROR_RETURN TRANSLATIONBLOCK TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE( 'Storage System Management Interface command: %[scmi_object_function_code]', eip05.value.ul1 ); TRANSLATE( 'Return code: %[scmi_response_status_value]', eip05.value.ul2 );

TRANSLATE( 'Internal command version: 0x%08x', eip05.secondary_id ); TRANSLATE( 'Internal target: %[scmi_obj_hnd]', eip05.add_handle ); TRANSLATE( 'scmicp.parms.u32[0]: %d', eip05.attribute.value.u32[0] ); TRANSLATE( 'scmicp.parms.u32[1]: %d', eip05.attribute.value.u32[1] ); TRANSLATE( 'scmicp.parms.u32[2]: %d', eip05.attribute.value.u32[2] ); TRANSLATE( 'scmicp.parms.u32[3]: %d', eip05.attribute.value.u32[3] ); TRANSLATE( 'scmicp.parms.u32[4]: %d', eip05.attribute.value.u32[4] ); TRANSLATE( 'scmicp.parms.u32[5]: %d', eip05.attribute.value.u32[5] ); TRANSLATE( 'Remote Error: %d', eip05.add_data[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 09300005 SCID_SCMI_NSC_LOOP_MAPGEN_CHANGE TRANSLATIONBLOCK TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE('Loop pair: %d.', eip05.secondary_id); TRANSLATE( 'Map generation number change: %d. --> %d.', eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09314205 SCID_SCMI_PS_CONDITION_CHANGE_DEGRADED TRANSLATIONBLOCK TRANSLATE('physical disk drive: %[scmi_obj_hnd]', eip05.handle ); TRANSLATE( 'State: %[scmi_physical_store_condition] --> %[scmi_physical_store_condition]', eip05.value.ul2, eip05.value.ul1 ); CONDITIONAL(eip05.attribute.value.u32[0] == 99,

TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE('Enclosure: %d.', eip05.attribute.value.u32[0]) ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE('Bay: %d.', eip05.attribute.value.u32[1]) ); ENDTRANSLATIONBLOCK EC BLOCK: 09324005 SCID_SCMI_PS_CONDITION_CHANGE_FAILED TRANSLATIONBLOCK TRANSLATE('physical disk drive: %[scmi_obj_hnd]', eip05.handle ); TRANSLATE( 'State: %[scmi_physical_store_condition] --> %[scmi_physical_store_condition]', eip05.value.ul2, eip05.value.ul1 ); CONDITIONAL(eip05.attribute.value.u32[0] == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE('Enclosure: %d.', eip05.attribute.value.u32[0]) ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE('Bay: %d.', eip05.attribute.value.u32[1]) ); ENDTRANSLATIONBLOCK EC BLOCK: 0935000e SCID_SCMI_LDAD_CREATED TRANSLATIONBLOCK TRANSLATE('Disk Group: %[scmi_obj_hnd]', eip0E.handle ); TRANSLATE('Number of disks in group: %d.', eip0E.attribute.value.u32[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 0936000e SCID_SCMI_PS_DISCOVERED TRANSLATIONBLOCK TRANSLATE('Physical disk drive: %[scmi_obj_hnd]', eip0E.handle ); CONDITIONAL(eip0E.attribute.value.u32[0] == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip0E.attribute.value.u32[0] != 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip0E.attribute.value.u32[0] != 99, TRANSLATE('Enclosure: %d.', eip0E.attribute.value.u32[0])

); CONDITIONAL(eip0E.attribute.value.u32[0] != 99, TRANSLATE('Bay: %d.', eip0E.attribute.value.u32[1]) ); ENDTRANSLATIONBLOCK EC BLOCK: 0937000e SCID_SCMI_PU_CREATED TRANSLATIONBLOCK TRANSLATE('Presented unit: %[scmi_obj_hnd]', eip0E.handle); TRANSLATE( 'Associated Storage System Virtual Disk: %[scmi_obj_hnd]', eip0E.add_handle ); TRANSLATE( 'Host path: %[scmi_obj_hnd]', eip0E.add_handle2 ); TRANSLATE( 'Host LUN number [0]: 0x%08x', eip0E.add_data[0] ); TRANSLATE( 'Host LUN number [1]: 0x%08x', eip0E.add_data[1] ); ENDTRANSLATIONBLOCK EC BLOCK: 0938000e SCID_SCMI_SCELL_CLIENT_CREATED TRANSLATIONBLOCK TRANSLATE( 'Storage System Host Path: %[scmi_obj_hnd]', eip0E.handle ); ENDTRANSLATIONBLOCK EC BLOCK: 0939000e SCID_SCMI_SCVD_CREATED TRANSLATIONBLOCK TRANSLATE('Storage System Virtual Disk: %[scmi_obj_hnd]', eip0E.handle); TRANSLATE('Disk Group: %[scmi_obj_hnd]', eip0E.add_handle); TRANSLATE('Size in blocks: %y.',eip0E.attribute.value.u64[0]); TRANSLATE('Redundancy type: %[scmi_scvd_redundancy_type]', eip0E.attribute.value.u32[2]); TRANSLATE('Container type: %[scmi_scvd_type]', eip0E.attribute.value.u32[3]); ENDTRANSLATIONBLOCK EC BLOCK: 093a000e SCID_SCMI_VOL_CREATED TRANSLATIONBLOCK TRANSLATE('Volume: %[scmi_obj_hnd]', eip0E.handle); TRANSLATE('Associated physical disk drive: %[scmi_obj_hnd]', eip0E.add_handle ); CONDITIONAL(eip0E.attribute.value.u32[0] == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip0E.attribute.value.u32[0] != 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip0E.attribute.value.u32[0] != 99, TRANSLATE('Enclosure: %d.', eip0E.attribute.value.u32[0]) );

CONDITIONAL(eip0E.attribute.value.u32[0] != 99, TRANSLATE('Bay: %d.', eip0E.attribute.value.u32[1]) ); ENDTRANSLATIONBLOCK EC BLOCK: 093d000e SCID_SCMI_LDAD_DELETED TRANSLATIONBLOCK TRANSLATE('Disk Group: %[scmi_obj_hnd]', eip0E.handle ); ENDTRANSLATIONBLOCK EC BLOCK: 093e420e SCID_SCMI_PS_DISAPPEARED TRANSLATIONBLOCK TRANSLATE('Physical disk drive: %[scmi_obj_hnd]', eip0E.handle ); CONDITIONAL(eip0E.attribute.value.u32[0] == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip0E.attribute.value.u32[0] != 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip0E.attribute.value.u32[0] != 99, TRANSLATE('Enclosure: %d.', eip0E.attribute.value.u32[0]) ); CONDITIONAL(eip0E.attribute.value.u32[0] != 99, TRANSLATE('Bay: %d.', eip0E.attribute.value.u32[1]) ); CONDITIONAL(eip0E.attribute.value.u32[2] == eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[2] == 0x00, TRANSLATE('Reason: Not Bypassed') ); CONDITIONAL(eip0E.attribute.value.u32[2] == eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[2] == 0xC1, TRANSLATE('Reason: Loss of Sync > 100ms') ); CONDITIONAL(eip0E.attribute.value.u32[2] == eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[2] == 0xC2, TRANSLATE('Reason: Line Code Violations over Threshold') ); CONDITIONAL(eip0E.attribute.value.u32[2] == eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[2] == 0xC3, TRANSLATE('Reason: Comma Density Violation') ); CONDITIONAL(eip0E.attribute.value.u32[2] == eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[2] == 0xC4, TRANSLATE('Reason: Reserved(0xC4)') ); CONDITIONAL(eip0E.attribute.value.u32[2] == eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[2] == 0xC5, TRANSLATE('Reason: Analog Signal Amplitute too low') ); CONDITIONAL(eip0E.attribute.value.u32[2] == eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[2] == 0xC6, TRANSLATE('Reason: Idle Monitor') ); CONDITIONAL(eip0E.attribute.value.u32[2] == eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[2] == 0xC7, TRANSLATE('Reason: Drive Requested')

); CONDITIONAL(eip0E.attribute.value.u32[2] == eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[2] == 0xC8, TRANSLATE('Reason: LIP sequence failure') ); CONDITIONAL(eip0E.attribute.value.u32[2] == eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[2] == 0xC9, TRANSLATE('Reason: GUI or UART') ); CONDITIONAL(eip0E.attribute.value.u32[2] == eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[2] == 0xCA, TRANSLATE('Reason: App Client Bypass') ); CONDITIONAL(eip0E.attribute.value.u32[2] == eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[2] == 0xCB, TRANSLATE('Reason: Drive not Present') ); CONDITIONAL(eip0E.attribute.value.u32[2] == eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[2] == 0xCC, TRANSLATE('Reason: SFP bypass') ); CONDITIONAL(eip0E.attribute.value.u32[2] == eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[2] == 0xCD, TRANSLATE('Reason: Drive Bypassed too many times without being removed') ); CONDITIONAL(eip0E.attribute.value.u32[2] == eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[2] == 0xCE, TRANSLATE('Reason: Drive requested off, then on the loop too many times') ); CONDITIONAL(eip0E.attribute.value.u32[2] == eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[2] == 0xCF, TRANSLATE('Reason: Reboot') ); CONDITIONAL(eip0E.attribute.value.u32[2] == eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[2] == 0xD0, TRANSLATE('Reason: App Client powered off the drive') ); CONDITIONAL(eip0E.attribute.value.u32[2] == eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[2] == 0xD1, TRANSLATE('Reason: SFP bypassed because it doesn't support shelf speed') ); CONDITIONAL(eip0E.attribute.value.u32[2] == eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[2] == 0xD2, TRANSLATE('Reason: LIP timeout') ); CONDITIONAL(eip0E.attribute.value.u32[2] != eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[2] == 0x00, TRANSLATE('Reason A-side: Not Bypassed') ); CONDITIONAL(eip0E.attribute.value.u32[2] != eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[2] == 0xC1, TRANSLATE('Reason A-side: Loss of Sync > 100ms') ); CONDITIONAL(eip0E.attribute.value.u32[2] != eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[2] == 0xC2, TRANSLATE('Reason A-side: Line Code Violations over Threshold') ); CONDITIONAL(eip0E.attribute.value.u32[2] != eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[2] == 0xC3, TRANSLATE('Reason A-side: Comma Density Violation')

); CONDITIONAL(eip0E.attribute.value.u32[2] != eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[2] == 0xC4, TRANSLATE('Reason A-side: Reserved(0xC4)') ); CONDITIONAL(eip0E.attribute.value.u32[2] != eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[2] == 0xC5, TRANSLATE('Reason A-side: Analog Signal Amplitute too low') ); CONDITIONAL(eip0E.attribute.value.u32[2] != eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[2] == 0xC6, TRANSLATE('Reason A-side: Idle Monitor') ); CONDITIONAL(eip0E.attribute.value.u32[2] != eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[2] == 0xC7, TRANSLATE('Reason A-side: Drive Requested') ); CONDITIONAL(eip0E.attribute.value.u32[2] != eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[2] == 0xC8, TRANSLATE('Reason A-side: LIP sequence failure') ); CONDITIONAL(eip0E.attribute.value.u32[2] != eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[2] == 0xC9, TRANSLATE('Reason A-side: GUI or UART') ); CONDITIONAL(eip0E.attribute.value.u32[2] != eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[2] == 0xCA, TRANSLATE('Reason A-side: App Client Bypass') ); CONDITIONAL(eip0E.attribute.value.u32[2] != eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[2] == 0xCB, TRANSLATE('Reason A-side: Drive not Present') ); CONDITIONAL(eip0E.attribute.value.u32[2] != eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[2] == 0xCC, TRANSLATE('Reason A-side: SFP bypass') ); CONDITIONAL(eip0E.attribute.value.u32[2] != eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[2] == 0xCD, TRANSLATE('Reason A-side: Drive Bypassed too many times without being removed') ); CONDITIONAL(eip0E.attribute.value.u32[2] != eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[2] == 0xCE, TRANSLATE('Reason A-side: Drive requested off, then on the loop too many times') ); CONDITIONAL(eip0E.attribute.value.u32[2] != eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[2] == 0xCF, TRANSLATE('Reason A-side: Reboot') ); CONDITIONAL(eip0E.attribute.value.u32[2] != eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[2] == 0xD0, TRANSLATE('Reason A-side: App Client powered off the drive') ); CONDITIONAL(eip0E.attribute.value.u32[2] != eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[2] == 0xD1, TRANSLATE('Reason A-side: SFP bypassed because it doesn't support shelf speed') ); CONDITIONAL(eip0E.attribute.value.u32[2] != eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[2] == 0xD2, TRANSLATE('Reason A-side: LIP timeout')

); CONDITIONAL(eip0E.attribute.value.u32[2] != eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[3] == 0x00, TRANSLATE('Reason B-side: Not Bypassed') ); CONDITIONAL(eip0E.attribute.value.u32[2] != eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[3] == 0xC1, TRANSLATE('Reason B-side: Loss of Sync > 100ms') ); CONDITIONAL(eip0E.attribute.value.u32[2] != eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[3] == 0xC2, TRANSLATE('Reason B-side: Line Code Violations over Threshold') ); CONDITIONAL(eip0E.attribute.value.u32[2] != eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[3] == 0xC3, TRANSLATE('Reason B-side: Comma Density Violation') ); CONDITIONAL(eip0E.attribute.value.u32[2] != eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[3] == 0xC4, TRANSLATE('Reason B-side: Reserved(0xC4)') ); CONDITIONAL(eip0E.attribute.value.u32[2] != eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[3] == 0xC5, TRANSLATE('Reason B-side: Analog Signal Amplitute too low') ); CONDITIONAL(eip0E.attribute.value.u32[2] != eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[3] == 0xC6, TRANSLATE('Reason B-side: Idle Monitor') ); CONDITIONAL(eip0E.attribute.value.u32[2] != eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[3] == 0xC7, TRANSLATE('Reason B-side: Drive Requested') ); CONDITIONAL(eip0E.attribute.value.u32[2] != eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[3] == 0xC8, TRANSLATE('Reason B-side: LIP sequence failure') ); CONDITIONAL(eip0E.attribute.value.u32[2] != eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[3] == 0xC9, TRANSLATE('Reason B-side: GUI or UART') ); CONDITIONAL(eip0E.attribute.value.u32[2] != eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[3] == 0xCA, TRANSLATE('Reason B-side: App Client Bypass') ); CONDITIONAL(eip0E.attribute.value.u32[2] != eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[3] == 0xCB, TRANSLATE('Reason B-side: Drive not Present') ); CONDITIONAL(eip0E.attribute.value.u32[2] != eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[3] == 0xCC, TRANSLATE('Reason B-side: SFP bypass') ); CONDITIONAL(eip0E.attribute.value.u32[2] != eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[3] == 0xCD, TRANSLATE('Reason B-side: Drive Bypassed too many times without being removed') ); CONDITIONAL(eip0E.attribute.value.u32[2] != eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[3] == 0xCE, TRANSLATE('Reason B-side: Drive requested off, then on the loop too many times')

); CONDITIONAL(eip0E.attribute.value.u32[2] != eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[3] == 0xCF, TRANSLATE('Reason B-side: Reboot') ); CONDITIONAL(eip0E.attribute.value.u32[2] != eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[3] == 0xD0, TRANSLATE('Reason B-side: App Client powered off the drive') ); CONDITIONAL(eip0E.attribute.value.u32[2] != eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[3] == 0xD1, TRANSLATE('Reason B-side: SFP bypassed because it doesn't support shelf speed') ); CONDITIONAL(eip0E.attribute.value.u32[2] != eip0E.attribute.value.u32[3] && eip0E.attribute.value.u32[3] == 0xD2, TRANSLATE('Reason B-side: LIP timeout') ); ENDTRANSLATIONBLOCK EC BLOCK: 093f000e SCID_SCMI_PU_DELETED TRANSLATIONBLOCK TRANSLATE('Presented unit: %[scmi_obj_hnd]', eip0E.handle); TRANSLATE('Associated Storage System Virtual Disk: %[scmi_obj_hnd]', eip0E.add_handle); ENDTRANSLATIONBLOCK EC BLOCK: 0940000e SCID_SCMI_SCELL_CLIENT_DELETED TRANSLATIONBLOCK TRANSLATE( 'Storage System Host Path: %[scmi_obj_hnd]', eip0E.handle ); ENDTRANSLATIONBLOCK EC BLOCK: 0941000e SCID_SCMI_SCVD_DELETED TRANSLATIONBLOCK TRANSLATE('Storage System Virtual Disk: %[scmi_obj_hnd]',eip0E.handle); ENDTRANSLATIONBLOCK EC BLOCK: 0943000e SCID_SCMI_SCELL_OTHER_JOINED TRANSLATIONBLOCK CONDITIONAL( eip0E.handle eq '0000-0000-0000-0000-0000-0000-0000-0000', TRANSLATE('Controller ID not available'), TRANSLATE('Controller: %[scmi_obj_hnd]', eip0E.handle) ); ENDTRANSLATIONBLOCK EC BLOCK: 0944ba0e SCID_SCMI_SCELL_OTHER_GONE TRANSLATIONBLOCK CONDITIONAL( eip0E.handle eq '0000-0000-0000-0000-0000-0000-0000-0000', TRANSLATE('Controller ID not available'), TRANSLATE('Controller: %[scmi_obj_hnd]', eip0E.handle) ); ENDTRANSLATIONBLOCK EC BLOCK: 0945000e SCID_SCMI_SCELL_DELETED TRANSLATIONBLOCK CONDITIONAL(

eip0E.handle eq '0000-0000-0000-0000-0000-0000-0000-0000', TRANSLATE('Storage System ID not available'), TRANSLATE('Storage System: %[scmi_obj_hnd]', eip0E.add_handle ) ); CONDITIONAL( eip0E.add_handle eq '0000-0000-0000-0000-0000-0000-0000-0000', TRANSLATE('Controller ID not available'), TRANSLATE('Controller: %[scmi_obj_hnd]', eip0E.add_handle) ); ENDTRANSLATIONBLOCK EC BLOCK: 0946000e SCID_SCMI_GROUP_CREATED TRANSLATIONBLOCK TRANSLATE( 'Data Replication Group: %[scmi_obj_hnd]', eip0E.handle ); TRANSLATE( 'Mode: %[scmi_group_drm_mode]',eip0E.add_data[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 0947000e SCID_SCMI_GROUP_DELETED TRANSLATIONBLOCK TRANSLATE( 'Data Replication Group: %[scmi_obj_hnd]', eip0E.handle ); ENDTRANSLATIONBLOCK EC BLOCK: 0948000e SCID_SCMI_SNAP_SCVD_CREATED TRANSLATIONBLOCK TRANSLATE('Snapshot Storage System Virtual Disk: %[scmi_obj_hnd]', eip0E.handle) ; TRANSLATE('Disk Group: %[scmi_obj_hnd]', eip0E.add_handle); TRANSLATE('Parent Storage System Virtual Disk: %[scmi_obj_hnd]', eip0E.add_handl e2); TRANSLATE('Size in blocks: %y.',eip0E.attribute.value.u64[0]); TRANSLATE('Redundancy type: %[scmi_scvd_redundancy_type]', eip0E.attribute.value.u32[2]); TRANSLATE('Container type: %[scmi_scvd_type]', eip0E.attribute.value.u32[3]); ENDTRANSLATIONBLOCK EC BLOCK: 0949000e SCID_SCMI_CLONE_SCVD_CREATED TRANSLATIONBLOCK TRANSLATE('Clone Storage System Virtual Disk: %[scmi_obj_hnd]', eip0E.handle); TRANSLATE('Disk Group: %[scmi_obj_hnd]', eip0E.add_handle); TRANSLATE('Parent Storage System Virtual Disk: %[scmi_obj_hnd]', eip0E.add_handl e2); TRANSLATE('Size in blocks: %y.',eip0E.attribute.value.u64[0]); TRANSLATE('Redundancy type: %[scmi_scvd_redundancy_type]', eip0E.attribute.value.u32[2]); TRANSLATE('Container type: %[scmi_scvd_type]', eip0E.attribute.value.u32[3]); ENDTRANSLATIONBLOCK EC BLOCK: 094a000e SCID_SCMI_GROUP_DELETE_INCOMPLETE TRANSLATIONBLOCK TRANSLATE( 'Destination Data Replication Group: %[scmi_obj_hnd]', eip0E.handle

); ENDTRANSLATIONBLOCK EC BLOCK: 094b000e SCID_SCMI_VOL_REMOVED TRANSLATIONBLOCK TRANSLATE('Volume: %[scmi_obj_hnd]', eip0E.handle); TRANSLATE('Associated Disk Group: %[scmi_obj_hnd]', eip0E.add_handle ); ENDTRANSLATIONBLOCK EC BLOCK: 094c000e SCID_SCMI_RMTNODE_CREATED TRANSLATIONBLOCK TRANSLATE('Remote Node: %[scmi_obj_hnd]', eip0E.handle); TRANSLATE('Storage System UUID: %[scmi_obj_hnd]', eip0E.add_handle); ENDTRANSLATIONBLOCK EC BLOCK: 094d000e SCID_SCMI_RMTNODE_DELETED TRANSLATIONBLOCK TRANSLATE('Remote Node: %[scmi_obj_hnd]', eip0E.handle); TRANSLATE('Storage System UUID: %[scmi_obj_hnd]', eip0E.add_handle); ENDTRANSLATIONBLOCK EC BLOCK: 094e000e SCID_SCMI_RMTNODE_UPDATED TRANSLATIONBLOCK TRANSLATE('Remote Node: %[scmi_obj_hnd]', eip0E.handle); TRANSLATE('Storage System UUID: %[scmi_obj_hnd]', eip0E.add_handle); ENDTRANSLATIONBLOCK EC BLOCK: 094f000e SCID_SCMI_ENCLOSURE_APPEARED TRANSLATIONBLOCK TRANSLATE('Enclosure: %[scmi_obj_hnd]', eip0E.handle ); CONDITIONAL(eip0E.attribute.value.u32[0] == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip0E.attribute.value.u32[0] != 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip0E.attribute.value.u32[0] != 99, TRANSLATE('Enclosure: %d.', eip0E.attribute.value.u32[0]) ); ENDTRANSLATIONBLOCK EC BLOCK: 0950000e SCID_SCMI_ENCLOSURE_DISAPPEARED TRANSLATIONBLOCK TRANSLATE('Enclosure: %[scmi_obj_hnd]', eip0E.handle ); CONDITIONAL(eip0E.attribute.value.u32[0] == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip0E.attribute.value.u32[0] != 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip0E.attribute.value.u32[0] != 99,

TRANSLATE('Enclosure: %d.', eip0E.attribute.value.u32[0]) ); ENDTRANSLATIONBLOCK EC BLOCK: 0951000e SCID_SCMI_IOMODULE_APPEARED TRANSLATIONBLOCK TRANSLATE('Enclosure: %[scmi_obj_hnd]', eip0E.handle ); CONDITIONAL(eip0E.attribute.value.u32[0] == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip0E.attribute.value.u32[0] != 99, TRANSLATE('PORT: %d.', eip0E.attribute.value.u32[1]) ); CONDITIONAL(eip0E.attribute.value.u32[0] != 99, TRANSLATE('Enclosure: %d.', eip0E.attribute.value.u32[0]) ); ENDTRANSLATIONBLOCK EC BLOCK: 0952000e SCID_SCMI_IOMODULE_DISAPPEARED TRANSLATIONBLOCK TRANSLATE('Enclosure: %[scmi_obj_hnd]', eip0E.handle ); CONDITIONAL(eip0E.attribute.value.u32[0] == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip0E.attribute.value.u32[0] != 99, TRANSLATE('PORT: %d.', eip0E.attribute.value.u32[1]) ); CONDITIONAL(eip0E.attribute.value.u32[0] != 99, TRANSLATE('Enclosure: %d.', eip0E.attribute.value.u32[0]) ); ENDTRANSLATIONBLOCK EC BLOCK: 0965000f SCID_SCMI_SCELL_CLIENT_MODE_CHANGE TRANSLATIONBLOCK TRANSLATE( 'Storage System Host Path: %[scmi_obj_hnd]', eip0F.handle ); TRANSLATE( 'Mode: %[scmi_client_mode] --> %[scmi_client_mode]', eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 0966000f SCID_SCMI_STORAGECELL_TIME_SET TRANSLATIONBLOCK CONDITIONAL( eip0F.handle eq '0000-0000-0000-0000-0000-0000-0000-0000', TRANSLATE( 'Storage System identity unavailable' ), TRANSLATE( 'Storage System: %[scmi_obj_hnd]', eip0F.handle )

); ENDTRANSLATIONBLOCK EC BLOCK: 0967000f SCID_SCMI_PU_LUN_CHANGE TRANSLATIONBLOCK TRANSLATE('Presented unit: %[scmi_obj_hnd]', eip0F.handle); TRANSLATE( 'LUN: %y. --> %y.', eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); TRANSLATE('Associated Storage System Virtual Disk: %[scmi_obj_hnd]',eip0F.add_ha ndle); ENDTRANSLATIONBLOCK EC BLOCK: 0968000f SCID_SCMI_STORAGECELL_DEV_ADDITION_CHANGE TRANSLATIONBLOCK TRANSLATE( 'Storage System: %[scmi_obj_hnd]', eip0F.handle ); TRANSLATE( 'Policy: %[scmi_storagecell_device_addition_policy] --> %[scmi_storagecell_devic e_addition_policy]', eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 0969000f SCID_SCMI_SCVD_QUIESCED_CHANGE TRANSLATIONBLOCK TRANSLATE('Storage System Virtual Disk: %[scmi_obj_hnd]',eip0F.handle); TRANSLATE( 'State: %[scmi_scvd_quiescent_condition] --> %[scmi_scvd_quiescent_condition]', eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 096a000f SCID_SCMI_SCVD_STATE_CHANGE TRANSLATIONBLOCK TRANSLATE('Storage System Virtual Disk: %[scmi_obj_hnd]',eip0F.handle); TRANSLATE( 'State: %[scmi_state] --> %[scmi_state]', eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 096b000f SCID_SCMI_SCVD_CACHE_POLICY_CHANGE TRANSLATIONBLOCK TRANSLATE('Storage System Virtual Disk: %[scmi_obj_hnd]',eip0F.handle); TRANSLATE( 'Write cache policy: %[scmi_write_disk_cache_policy_type] --> %[scmi_write_disk_ cache_policy_type]', eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); TRANSLATE( 'Read cache policy: %[scmi_read_disk_cache_policy_type] --> %[scmi_read_disk_cac

he_policy_type]', eip0F.old_attr.value.u32[1], eip0F.new_attr.value.u32[1] ); TRANSLATE( 'Cache mirroring policy: %[scmi_mirror_disk_cache_policy_type] --> %[scmi_mirror _disk_cache_policy_type]', eip0F.old_attr.value.u32[2], eip0F.new_attr.value.u32[2] ); ENDTRANSLATIONBLOCK EC BLOCK: 096c000f SCID_SCMI_VOL_USAGE_CHANGE TRANSLATIONBLOCK TRANSLATE( 'Volume: %[scmi_obj_hnd]', eip0F.handle ); TRANSLATE( 'State: %[scmi_volume_usage] --> %[scmi_volume_usage]', eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); CONDITIONAL( eip0F.old_attr.value.u32[0] == 1 || eip0F.new_attr.value.u32[0] == 1, TRANSLATE( 'Disk Group: %[scmi_obj_hnd]', eip0F.add_handle ) ); TRANSLATE('Redundant Storage Set Identification: 0x%04x, (%d)', eip0F.secondary_id.rss_data.Id, eip0F.secondary_id.rss_data.Id ); TRANSLATE('Redundant Storage Set Index: 0x%04x, (%d)', eip0F.secondary_id.rss_data.Index, eip0F.secondary_id.rss_data.Index ); ENDTRANSLATIONBLOCK EC BLOCK: 096d000f SCID_SCMI_LDAD_SPARE_CHANGE TRANSLATIONBLOCK TRANSLATE( 'Disk Group: %[scmi_obj_hnd]', eip0F.handle ); CONDITIONAL( eip0F.new_attr.value.u32[0] > eip0F.old_attr.value.u32[0], TRANSLATE( 'Disk Failure Protection Level increased' ), TRANSLATE( 'Disk Failure Protection Level decreased' ) ); TRANSLATE( 'Disk Failure Protection Level: %d. --> %d.', eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0]

); ENDTRANSLATIONBLOCK EC BLOCK: 096e000f SCID_SCMI_SCVD_WRITE_PROTECTED_CHANGE TRANSLATIONBLOCK TRANSLATE('Storage System Virtual Disk: %[scmi_obj_hnd]', eip0F.handle); TRANSLATE( 'State: %[scmi_scvd_write_protect_condition] --> %[scmi_scvd_write_protect_condition]', eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 0970460f SCID_SCMI_PS_DRIVE_PORT_FAILURE TRANSLATIONBLOCK TRANSLATE('Physical disk drive: %[scmi_obj_hnd]', eip0F.handle ); TRANSLATE('Port: %s', eip0F.new_attr.value.str); CONDITIONAL(eip0F.old_attr.value.u32[1] == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip0F.old_attr.value.u32[1] != 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip0F.old_attr.value.u32[1] != 99, TRANSLATE('Enclosure: %d.', eip0F.old_attr.value.u32[1]) ); CONDITIONAL(eip0F.old_attr.value.u32[1] != 99, TRANSLATE('Bay: %d.', eip0F.old_attr.value.u32[2]) ); TRANSLATE( 'Reason code: 0x%04X (%[drv_inop])', eip0F.old_attr.value.u32[3], eip0F.old_attr.value.u32[3] ); ENDTRANSLATIONBLOCK EC BLOCK: 0971000f SCID_SCMI_NSC_SHUTDOWN_REQUEST TRANSLATIONBLOCK TRANSLATE('Controller: %[scmi_obj_hnd]', eip0F.handle); TRANSLATE( 'Restart type: %[scmi_nsc_restart_option]', eip0F.old_attr.value.u32[0] ); TRANSLATE( 'Other controller action: %[scmi_nsc_shutdown_other_option]', eip0F.old_attr.value.u32[1] ); TRANSLATE( 'Controller power state: %[scmi_nsc_shutdown_poweroff_option]', eip0F.old_attr.value.u32[2] ); TRANSLATE( 'Physical disk drive enclosures power state: %[scmi_nsc_shutdown_encl_poweroff_o ption]', eip0F.old_attr.value.u32[3] ); TRANSLATE(

'Battery assembly state: %[scmi_nsc_shutdown_battass_option]', eip0F.old_attr.value.u32[4] ); TRANSLATE( 'Shutdown delay: %d. seconds', eip0F.old_attr.value.u32[5] ); CONDITIONAL(eip0F.new_attr.value.u32[0] == 0, TRANSLATE( 'NOT in Locate (warm removal) mode' ), TRANSLATE( 'Locate (warm removal) mode' ) ); TRANSLATE( 'Requester: %[scmi_nsc_shutdown_requester]', eip0F.new_attr.value.u32[1] ); ENDTRANSLATIONBLOCK EC BLOCK: 0972000f SCID_SCMI_NSC_SHUTDOWN TRANSLATIONBLOCK TRANSLATE('Controller: %[scmi_obj_hnd]', eip0F.handle); TRANSLATE( 'Cache memory shutdown result: %[scmi_shutdown]', eip0F.old_attr.value.u32[0] ); TRANSLATE( 'Cache memory shutdown internal status: %d.', eip0F.old_attr.value.u32[1] ); TRANSLATE( 'Physical disk drive enclosures power off result: %[scmi_shutdown]', eip0F.old_attr.value.u32[2] ); TRANSLATE( 'Physical disk drive enclosures power off internal status: %[scmi_shutdown]', eip0F.old_attr.value.u32[3] ); TRANSLATE( 'Battery assemblies disable result: %[scmi_shutdown]', eip0F.old_attr.value.u32[4] ); TRANSLATE( 'Battery assemblies disable failure mode: %[scmi_nsc_shutdown_battass_failure_mo de]', eip0F.old_attr.value.u32[5] ); ENDTRANSLATIONBLOCK EC BLOCK: 0973000f SCID_SCMI_DRM_FAILSAFE_CHANGED TRANSLATIONBLOCK TRANSLATE( 'Data Replication Group: %[scmi_obj_hnd]', eip0F.handle ); TRANSLATE( 'State: %[scmi_state] --> %[scmi_state]', eip0F.old_attr.value.u32[0],

eip0F.new_attr.value.u32[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 0974000f SCID_SCMI_DRM_MODE_CHANGED TRANSLATIONBLOCK TRANSLATE( 'Data Replication Group: %[scmi_obj_hnd]', eip0F.handle ); TRANSLATE( 'Mode: %[scmi_group_drm_mode] --> %[scmi_group_drm_mode]', eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 0975000f SCID_SCMI_DRM_OPERATION_CHANGED TRANSLATIONBLOCK TRANSLATE( 'Data Replication Group: %[scmi_obj_hnd]', eip0F.handle ); TRANSLATE( 'Actual State: %[scmi_group_operation_type] --> %[scmi_group_operation_type]', eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); TRANSLATE( 'Requested State: %[scmi_group_operation_type] --> %[scmi_group_operation_type]' , eip0F.old_attr.value.u32[1], eip0F.new_attr.value.u32[1] ); TRANSLATE( 'Async Rundown State: %[scmi_rundown_flag] --> %[scmi_rundown_flag]', eip0F.old_attr.value.u32[2], eip0F.new_attr.value.u32[2] ); ENDTRANSLATIONBLOCK EC BLOCK: 0976000f SCID_SCMI_DRM_READ_ONLY_CHANGED TRANSLATIONBLOCK TRANSLATE( 'Data Replication Group: %[scmi_obj_hnd]', eip0F.handle ); TRANSLATE( 'Attribute: %[scmi_group_readonly_type] --> %[scmi_group_readonly_type]', eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 0977000f SCID_SCMI_DRM_SITE_FAILOVER_CHANGED TRANSLATIONBLOCK TRANSLATE( 'Data Replication Group: %[scmi_obj_hnd]', eip0F.handle );

TRANSLATE( 'Role: %[scmi_group_drm_mode] --> %[scmi_group_drm_mode]', eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 0978000f SCID_SCMI_DRM_SUSPEND_CHANGED TRANSLATIONBLOCK TRANSLATE( 'Data Replication Group: %[scmi_obj_hnd]', eip0F.handle ); TRANSLATE( 'State: %[scmi_group_suspend_state] --> %[scmi_group_suspend_state]', eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 0979000f SCID_SCMI_DRM_SCVD_ADDED_TO_GROUP TRANSLATIONBLOCK TRANSLATE( 'Data Replication Group: %[scmi_obj_hnd]', eip0F.handle ); TRANSLATE( 'Storage System Virtual Disk: %[scmi_obj_hnd]', eip0F.add_handle ); ENDTRANSLATIONBLOCK EC BLOCK: 097a000f SCID_SCMI_DRM_SCVD_REMOVED_FROM_GROUP TRANSLATIONBLOCK TRANSLATE( 'Data Replication Group: %[scmi_obj_hnd]', eip0F.handle ); TRANSLATE( 'Storage System Virtual Disk: %[scmi_obj_hnd]', eip0F.add_handle ); ENDTRANSLATIONBLOCK EC BLOCK: 097b000f SCID_SCMI_DRM_AUTO_SUSPEND_CHANGED TRANSLATIONBLOCK TRANSLATE( 'Data Replication Group: %[scmi_obj_hnd]', eip0F.handle ); TRANSLATE( 'State: %[scmi_group_auto_suspend_state] --> %[scmi_group_auto_suspend_state]', eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 097c000f SCID_SCMI_DRM_DEST_PRESENT_CHANGED TRANSLATIONBLOCK TRANSLATE(

'Data Replication Group: %[scmi_obj_hnd]', eip0F.handle ); TRANSLATE( 'State: %[scmi_group_dest_present_state] --> %[scmi_group_dest_present_state]', eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 097d000f SCID_SCMI_PS_FLAGS_CHANGED TRANSLATIONBLOCK TRANSLATE('Physical disk drive: %[scmi_obj_hnd]', eip0F.handle ); TRANSLATE('Old ps_flags value: 0x%08x.', eip0F.old_attr.value.u32[0]); TRANSLATE('New ps_flags value: 0x%08x.', eip0F.new_attr.value.u32[0]); ENDTRANSLATIONBLOCK EC BLOCK: 097e000f SCID_SCMI_DRM_DEFER_COPY_CHANGED TRANSLATIONBLOCK TRANSLATE( 'Data Replication Group: %[scmi_obj_hnd]', eip0F.handle ); TRANSLATE( 'State: %[scmi_group_defer_copy_state] --> %[scmi_group_defer_copy_state]', eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 097f000f SCID_SCMI_DRM_LINK_DOWN_SUSPEND_CHANGED TRANSLATIONBLOCK TRANSLATE( 'Data Replication Group: %[scmi_obj_hnd]', eip0F.handle ); TRANSLATE( 'State: %[scmi_group_suspend_state] --> %[scmi_group_suspend_state]', eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 0980000f SCID_SCMI_DRM_SITE_FAILOVER_SUSPEND_CHANGED TRANSLATIONBLOCK TRANSLATE( 'Data Replication Group: %[scmi_obj_hnd]', eip0F.handle ); TRANSLATE( 'State: %[scmi_group_suspend_state] --> %[scmi_group_suspend_state]', eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 0981000f SCID_SCMI_DRM_DEFER_COPY_SUSPEND_CHANGED TRANSLATIONBLOCK

TRANSLATE( 'Data Replication Group: %[scmi_obj_hnd]', eip0F.handle ); TRANSLATE( 'State: %[scmi_group_suspend_state] --> %[scmi_group_suspend_state]', eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 0982000f SCID_SCMI_DRM_SPLIT_BRAIN_ALLOW_CHANGED TRANSLATIONBLOCK TRANSLATE( 'Data Replication Group: %[scmi_obj_hnd]', eip0F.handle ); TRANSLATE( 'State: %[scmi_group_split_brain_allow_state] --> %[scmi_group_split_brain_allow _state]', eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 0983000f SCID_SCMI_DRM_DEST_INSTANCE_RESTORE_SUSPEND_CHANGED TRANSLATIONBLOCK TRANSLATE( 'Data Replication Group: %[scmi_obj_hnd]', eip0F.handle ); TRANSLATE( 'State: %[scmi_group_suspend_state] --> %[scmi_group_suspend_state]', eip0F.old_attr.value.u32[0], eip0F.new_attr.value.u32[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 09c95105 SCID_SCMI_LDAD_CONDITION_CHANGE_INOP TRANSLATIONBLOCK TRANSLATE('Disk Group: %[scmi_obj_hnd]', eip05.handle ); TRANSLATE( 'State: %[scmi_ldad_condition] --> %[scmi_ldad_condition]', eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09ca5105 SCID_SCMI_SCVD_CONDITION_CHANGE_FAILED TRANSLATIONBLOCK TRANSLATE('Storage System Virtual Disk: %[scmi_obj_hnd]', eip05.handle); TRANSLATE( 'State: %[scmi_scvd_condition] --> %[scmi_scvd_condition]', eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK

EC BLOCK: 09cb5005 SCID_SCMI_SCVD_CONDITION_CHANGE_OVERCOMMIT TRANSLATIONBLOCK TRANSLATE('Storage System Virtual Disk: %[scmi_obj_hnd]', eip05.handle); TRANSLATE( 'State: %[scmi_scvd_condition] --> %[scmi_scvd_condition]', eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09cc5105 SCID_SCMI_SCVD_CONDITION_CHANGE_DATA_LOST TRANSLATIONBLOCK TRANSLATE('Storage System Virtual Disk: %[scmi_obj_hnd]', eip05.handle); TRANSLATE( 'State: %[scmi_scvd_condition] --> %[scmi_scvd_condition]', eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09cdc305 SCID_SCMI_NSC_FC_PORT_CONDITION_CHANGE_FAILED TRANSLATIONBLOCK CONDITIONAL( eip05.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE( 'Port: %s', eip05.attribute.value.str ); TRANSLATE( 'State: %[scmi_nsc_fc_port_condition] --> %[scmi_nsc_fc_port_condition]', eip05.value.ul2, eip05.value.ul1 ); TRANSLATE('Policy memory size: %d MB', eip05.add_data[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 09ce0005 SCID_SCMI_LDAD_CONDITION_CHANGE_INOP_MARKED TRANSLATIONBLOCK TRANSLATE('Disk Group: %[scmi_obj_hnd]', eip05.handle ); TRANSLATE( 'State: %[scmi_ldad_condition] --> %[scmi_ldad_condition]', eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09cf4105 SCID_SCMI_PS_CONDITION_CHANGE_NOT_PRESENT TRANSLATIONBLOCK TRANSLATE('Physical disk drive: %[scmi_obj_hnd]', eip05.handle ); TRANSLATE( 'State: %[scmi_physical_store_condition] --> %[scmi_physical_store_condition]',

eip05.value.ul2, eip05.value.ul1 ); CONDITIONAL(eip05.attribute.value.u32[0] == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE('Enclosure: %d.', eip05.attribute.value.u32[0]) ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE('Bay: %d.', eip05.attribute.value.u32[1]) ); ENDTRANSLATIONBLOCK EC BLOCK: 09d00005 SCID_SCMI_NSC_ICON_YELLOW_OFF_CHANGE TRANSLATIONBLOCK TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); ENDTRANSLATIONBLOCK EC BLOCK: 09d1b905 SCID_SCMI_NSC_ICON_YELLOW_ON_CHANGE TRANSLATIONBLOCK TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); ENDTRANSLATIONBLOCK EC BLOCK: 09d22a05 SCID_SCMI_NSC_FANA_PRESENT_CHANGE_PNP TRANSLATIONBLOCK TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE('Blower assembly: %d.', eip05.secondary_id); TRANSLATE( 'State: %[scmi_nsc_fan_present_condition] --> %[scmi_nsc_fan_present_condition]' , eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09d35105 SCID_SCMI_DRM_GROUP_INOP TRANSLATIONBLOCK TRANSLATE( 'Data Replication Group: %[scmi_obj_hnd]', eip05.handle ); TRANSLATE( 'State: %[scmi_group_drm_ld_state] --> %[scmi_group_drm_ld_state]', eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09d40005 SCID_SCMI_DRM_GROUP_OPERATIVE TRANSLATIONBLOCK TRANSLATE( 'Data Replication Group: %[scmi_obj_hnd]', eip05.handle ); TRANSLATE( 'State: %[scmi_group_drm_ld_state] --> %[scmi_group_drm_ld_state]',

eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09d50005 SCID_SCMI_PS_CONDITION_CHANGE_SPOF TRANSLATIONBLOCK TRANSLATE('Physical disk drive: %[scmi_obj_hnd]', eip05.handle ); TRANSLATE( 'State: %[scmi_physical_store_condition] --> %[scmi_physical_store_condition]', eip05.value.ul2, eip05.value.ul1 ); CONDITIONAL(eip05.attribute.value.u32[0] == 99, TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE('Enclosure: %d.', eip05.attribute.value.u32[0]) ); CONDITIONAL(eip05.attribute.value.u32[0] != 99, TRANSLATE('Bay: %d.', eip05.attribute.value.u32[1]) ); ENDTRANSLATIONBLOCK EC BLOCK: 09d63705 SCID_SCMI_NSC_TEMP_SNSR_DONT_AGREE TRANSLATIONBLOCK CONDITIONAL( eip05.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE( 'Sensor 1 current reading: %d. degrees Celsius', eip05.value.ul1 ); TRANSLATE( 'Sensor 2 current reading: %d. degrees Celsius', eip05.value.ul2 ); TRANSLATE('Policy memory size: %d MB', eip05.add_data[0] ); ENDTRANSLATIONBLOCK EC BLOCK: 09d73705 SCID_SCMI_NSC_TEMP_SNSR_FAILURE TRANSLATIONBLOCK CONDITIONAL( eip05.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE('I2C status: %x', eip05.value.ul1); TRANSLATE('Policy memory size: %d MB', eip05.add_data[0] );

ENDTRANSLATIONBLOCK EC BLOCK: 09d8b605 SCID_SCMI_SRC_LOST TRANSLATIONBLOCK TRANSLATE('Disk Group: %[scmi_obj_hnd]', eip05.handle ); ENDTRANSLATIONBLOCK EC BLOCK: 09d90005 SCID_SCMI_SRC_ATTAINED TRANSLATIONBLOCK TRANSLATE('Disk Group: %[scmi_obj_hnd]', eip05.handle ); ENDTRANSLATIONBLOCK EC BLOCK: 09da0005 SCID_SCMI_NSC_FANA_SPEED_NORMAL TRANSLATIONBLOCK TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE('Blower assembly: %d.', eip05.secondary_id); TRANSLATE('Current speed: %d. RPM', eip05.value.ul1); TRANSLATE('Lowest acceptable speed: %d. RPM', eip05.value.ul2); ENDTRANSLATIONBLOCK EC BLOCK: 09db0005 SCID_SCMI_NSC_FANB_SPEED_NORMAL TRANSLATIONBLOCK TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE('Blower assembly: %d.', eip05.secondary_id); TRANSLATE('Current speed: %d. RPM', eip05.value.ul1); TRANSLATE('Lowest acceptable speed: %d. RPM', eip05.value.ul2); ENDTRANSLATIONBLOCK EC BLOCK: 09dd0005 SCID_SCMI_NSC_MAINTENANCE_INVOKE_CALL TRANSLATIONBLOCK TRANSLATE('Controller: %[scmi_obj_hnd]', eip05.handle); TRANSLATE('Function Called: 0x%x.', eip05.value.ul1); TRANSLATE('Parameter 1: 0x%x.', eip05.value.ul2); TRANSLATE('Parameter 2: 0x%x.', eip05.add_data[0]); TRANSLATE('Parameter 3: 0x%x.', eip05.add_data[1]); ENDTRANSLATIONBLOCK EC BLOCK: 09de5205 SCID_SCMI_SCVD_CONDITION_CHANGE_INVALIDATED TRANSLATIONBLOCK TRANSLATE('Storage System Virtual Disk: %[scmi_obj_hnd]', eip05.handle); TRANSLATE( 'State: %[scmi_scvd_condition] --> %[scmi_scvd_condition]', eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09e30005 SCID_SCMI_SCVD_CONDITION_CHANGE_NOACT TRANSLATIONBLOCK TRANSLATE('Storage System Virtual Disk: %[scmi_obj_hnd]', eip05.handle); TRANSLATE( 'State: %[scmi_scvd_condition] --> %[scmi_scvd_condition]', eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK

EC BLOCK: 09e45105 SCID_SCMI_SCVD_DATA_LOST_CHANGE_LOST TRANSLATIONBLOCK TRANSLATE('Storage System Virtual Disk: %[scmi_obj_hnd]', eip05.handle); TRANSLATE( 'State: %[scmi_scvd_data_availability_condition] --> %[scmi_scvd_data_availability_condition]', eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 09e50005 SCID_SCMI_SCVD_DATA_LOST_CHANGE_NORMAL TRANSLATIONBLOCK TRANSLATE('Storage System Virtual Disk: %[scmi_obj_hnd]', eip05.handle); TRANSLATE( 'State: %[scmi_scvd_data_availability_condition] --> %[scmi_scvd_data_availability_condition]', eip05.value.ul2, eip05.value.ul1 ); ENDTRANSLATIONBLOCK EC BLOCK: 0b000010 SCID_SYS_RESYNCH TRANSLATIONBLOCK TRANSLATE('Controller: %[wwn]', eip10.node_name); TRANSLATE('Program Counter: 0x%08x', eip10.information.pc); TRANSLATE( 'Code: %d., 0x%08x (%[rcse])', eip10.information.code, eip10.information.code, eip10.information.code ); TRANSLATE('Flags: 0x%08x', eip10.information.flags); TRANSLATE('Flag meanings:'); TRANSLATE( '0x00000001 = Do not turn off host port LASERs' ); TRANSLATE( '0x00000010 = Do not prompt for GO' ); TRANSLATE( '0x00000020 = Bypass card boot and diagnostics' ); TRANSLATE( '0x00000040 = Use image in memory' ); TRANSLATE( '0x00000400 = Emergency drive firmware upgrade' ); TRANSLATE( '0x00001000 = Old - Preserve host port 0 at 2 gigabyte' ); TRANSLATE( '0x00002000 = Old - Preserve host port 1 at 2 gigabyte' ); TRANSLATE( '0x00003000 = Old - Preserve host port 2 at 2 gigabyte' ); TRANSLATE(

'0x00002000 = Old - Preserve host port 3 at 2 gigabyte' ); TRANSLATE( '0x00003000 = Preserve host port 0' ); TRANSLATE( '0x0000C000 = Preserve host port 1' ); TRANSLATE( '0x00030000 = Preserve host port 2' ); TRANSLATE( '0x000C0000 = Preserve host port 3' ); TRANSLATE( '0x02000000 = Use bypass to send resynchronization MFC' ); TRANSLATE( '0x04000000 = Storage System scrub by this controller' ); TRANSLATE( '0x08000000 = Storage System scrub by other controller' ); TRANSLATE( '0x10000000 = Retention of preserved image through resync requested' ); TRANSLATE( '0x20000000 = Storage System resynchronization' ); TRANSLATE( '0x40000000 = Fault Manager termination bypassed' ); TRANSLATE( '0x80000000 = Power on reboot occurred' ); ENDTRANSLATIONBLOCK EC BLOCK: 0b01b515 SCID_SYS_MIGRATE_DFW_STALLED TRANSLATIONBLOCK CONDITIONAL(eip15.tag1 eq '0000-0000-0000-0000-0000-0000-0000-0000', TRANSLATE('Volume identity unavailable'), TRANSLATE('Volume: %[tag]', eip15.tag1) ); TRANSLATE('Physical Disk Drive: %[tag]', eip15.tag2); CONDITIONAL(eip15.state == 4, TRANSLATE('State: Migrating') ); CONDITIONAL(eip15.status == 1, TRANSLATE('Status: Awaiting additional storage') ); ENDTRANSLATIONBLOCK EC BLOCK: 0b040004 SCID_SYS_CODELOAD_DRIVE TRANSLATIONBLOCK TRANSLATE('Physical disk drive: %[tag]', eip04.device); TRANSLATE('Port ID: %s', eip04.cerp_id); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num == 99,

TRANSLATE('Rack, enclosure, and bay not known') ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE('Last known enclosure: %d.', eip04.dencl_num - 100 ) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num > 99, TRANSLATE('Last known bay: %d.', eip04.bay - 100) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE('Rack number not valid in this release') ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE('Enclosure: %d.', eip04.dencl_num) ); CONDITIONAL(eip04.al_pa != 0x01 && eip04.al_pa != 0x02 && eip04.al_pa != 0xEE && eip04.dencl_num < 99, TRANSLATE('Bay: %d.', eip04.bay) ); TRANSLATE('AL_PA: 0x%04x', eip04.al_pa); TRANSLATE('SCSI Product ID: %s', eip04.pid); TRANSLATE('Current firmware revision: %s', eip04.rev); TRANSLATE('Target firmware revision: %s', eip04.new_rev); TRANSLATE('Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information', eip04.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 0b050004 SCID_SYS_DRIVE_LOADED TRANSLATIONBLOCK TRANSLATE('Physical disk drive: %[tag]', eip04.device); TRANSLATE('SCSI Product ID: %s', eip04.pid); TRANSLATE('Current firmware revision: %s', eip04.rev); TRANSLATE('Target firmware revision: %s', eip04.new_rev); TRANSLATE('Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information', eip04.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 0b06001a SCID_SYS_CODELOAD TRANSLATIONBLOCK

TRANSLATE('State: %s', eip1A.state); TRANSLATE('AddState/Version: %s %s', eip1A.hardware, eip1A.versions); ENDTRANSLATIONBLOCK EC BLOCK: 0b09001e SCID_SYS_PROCESS_WITH_WORK TRANSLATIONBLOCK CONDITIONAL(eip1E.data[0] != 0, TRANSLATE('Process: %s %02d', eip1E.info, eip1E.data[0]) ); CONDITIONAL(eip1E.data[0] == 0, TRANSLATE('Process: %s', eip1E.info) ); CONDITIONAL(eip1E.data[1] != 0, TRANSLATE('Stack[0]: %08x (%s)', eip1E.data[1], XLATE_PC_CURRENT(eip1E.data[1])) ); CONDITIONAL(eip1E.data[2] != 0, TRANSLATE('Stack[1]: %08x (%s)', eip1E.data[2], XLATE_PC_CURRENT(eip1E.data[2])) ); CONDITIONAL(eip1E.data[3] != 0, TRANSLATE('Stack[2]: %08x (%s)', eip1E.data[3], XLATE_PC_CURRENT(eip1E.data[3])) ); CONDITIONAL(eip1E.data[4] != 0, TRANSLATE('Stack[3]: %08x (%s)', eip1E.data[4], XLATE_PC_CURRENT(eip1E.data[4])) ); CONDITIONAL(eip1E.data[5] != 0, TRANSLATE('Stack[4]: %08x (%s)', eip1E.data[5], XLATE_PC_CURRENT(eip1E.data[5])) ); CONDITIONAL(eip1E.data[6] != 0, TRANSLATE('Stack[5]: %08x (%s)', eip1E.data[6], XLATE_PC_CURRENT(eip1E.data[6])) ); CONDITIONAL(eip1E.data[7] != 0, TRANSLATE('Stack[6]: %08x (%s)', eip1E.data[7], XLATE_PC_CURRENT(eip1E.data[7])) ); CONDITIONAL(eip1E.data[8] != 0, TRANSLATE('Stack[7]: %08x (%s)', eip1E.data[8], XLATE_PC_CURRENT(eip1E.data[8])) ); CONDITIONAL(eip1E.data[9] != 0, TRANSLATE('Stack[8]: %08x (%s)', eip1E.data[9], XLATE_PC_CURRENT(eip1E.data[9])) ); CONDITIONAL(eip1E.data[10] != 0, TRANSLATE('Stack[9]: %08x (%s)', eip1E.data[10], XLATE_PC_CURRENT(eip1E.data[10])) ); CONDITIONAL(eip1E.data[11] != 0, TRANSLATE('Stack[10]: %08x (%s)', eip1E.data[11], XLATE_PC_CURRENT(eip1E.data[11])) ); CONDITIONAL(eip1E.data[12] != 0, TRANSLATE('Stack[11]: %08x (%s)', eip1E.data[12], XLATE_PC_CURRENT(eip1E.data[12])) );

CONDITIONAL(eip1E.data[13] != 0, TRANSLATE('Stack[12]: %08x (%s)', XLATE_PC_CURRENT(eip1E.data[13])) ); CONDITIONAL(eip1E.data[14] != 0, TRANSLATE('Stack[13]: %08x (%s)', XLATE_PC_CURRENT(eip1E.data[14])) ); CONDITIONAL(eip1E.data[15] != 0, TRANSLATE('Stack[14]: %08x (%s)', XLATE_PC_CURRENT(eip1E.data[15])) ); CONDITIONAL(eip1E.data[16] != 0, TRANSLATE('Stack[15]: %08x (%s)', XLATE_PC_CURRENT(eip1E.data[16])) ); CONDITIONAL(eip1E.data[17] != 0, TRANSLATE('Stack[16]: %08x (%s)', XLATE_PC_CURRENT(eip1E.data[17])) ); CONDITIONAL(eip1E.data[18] != 0, TRANSLATE('Stack[17]: %08x (%s)', XLATE_PC_CURRENT(eip1E.data[18])) ); CONDITIONAL(eip1E.data[19] != 0, TRANSLATE('Stack[18]: %08x (%s)', XLATE_PC_CURRENT(eip1E.data[19])) ); CONDITIONAL(eip1E.data[20] != 0, TRANSLATE('Stack[19]: %08x (%s)', XLATE_PC_CURRENT(eip1E.data[20])) ); CONDITIONAL(eip1E.data[21] != 0, TRANSLATE('Stack[20]: %08x (%s)', XLATE_PC_CURRENT(eip1E.data[21])) ); CONDITIONAL(eip1E.data[22] != 0, TRANSLATE('Stack[21]: %08x (%s)', XLATE_PC_CURRENT(eip1E.data[22])) ); CONDITIONAL(eip1E.data[23] != 0, TRANSLATE('Stack[22]: %08x (%s)', XLATE_PC_CURRENT(eip1E.data[23])) ); ENDTRANSLATIONBLOCK

eip1E.data[13],

eip1E.data[14],

eip1E.data[15],

eip1E.data[16],

eip1E.data[17],

eip1E.data[18],

eip1E.data[19],

eip1E.data[20],

eip1E.data[21],

eip1E.data[22],

eip1E.data[23],

EC BLOCK: 0b0af21e SCID_SYS_SPRITE_PENDING TRANSLATIONBLOCK TRANSLATE('Running version: %04x - %d', eip1E.data[0],eip1E.data[0]); TRANSLATE('Versions of waiting code: %04x:%04x - %d:%d', eip1E.data[1], eip1E.data[1], eip1E.data[2], eip1E.data[2]); ENDTRANSLATIONBLOCK EC BLOCK: 0b0b0024 SCID_SYS_RESYNC_PROCESS TRANSLATIONBLOCK TRANSLATE('Preserving resync step: %d', eip24.data[0]); ENDTRANSLATIONBLOCK EC BLOCK: 0c03000c SCID_DRM_MERGING TRANSLATIONBLOCK

TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Data Replication Destination Storage System: %[tag]', eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c045f0c SCID_DRM_FAILSAFE_LOCKED_SITE_INACCESS TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Data Replication Destination Storage System: %[tag]', eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c05610c SCID_DRM_FAILSAFE_LOCKED_UNIT_INACCESS TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Data Replication Destination Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Destination Virtual Disk: %[tag]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c06600c SCID_DRM_COPY_READ_ERROR TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Source Virtual Disk: %[tag]', eip0C.source_scvd_uuid); TRANSLATE('First block in error: 0x%08x', eip0C.vda); ENDTRANSLATIONBLOCK EC BLOCK: 0c075f0c SCID_DRM_COPY_WRITE_SITE_INACCESS TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Data Replication Destination Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Destination Virtual Disk: %[tag]', eip0C.dest_scvd_uuid); TRANSLATE('First block in error: 0x%08x', eip0C.vda); ENDTRANSLATIONBLOCK EC BLOCK: 0c08610c SCID_DRM_COPY_WRITE_UNIT_INACCESS TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Data Replication Destination Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Destination Virtual Disk: %[tag]', eip0C.dest_scvd_uuid); TRANSLATE('First block in error: 0x%08x', eip0C.vda); ENDTRANSLATIONBLOCK EC BLOCK: 0c09620c SCID_DRM_LOG_FULL TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Data Replication Destination Storage System: %[tag]', eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c0a000c SCID_DRM_LOG_RESET

TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Data Replication Destination Storage System: %[tag]', eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c0b620c SCID_DRM_LOG_READ_ERROR TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Data Replication Destination Storage System: %[tag]', eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c0c000c SCID_DRM_MERGE_DONE TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Data Replication Destination Storage System: %[tag]', eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c0f000c SCID_DRM_FAILSAFE_CLEARED TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Data Replication Destination Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Destination Virtual Disk: %[tag]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c10000c SCID_DRM_FULL_COPY TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Source Virtual Disk: %[tag]', eip0C.source_scvd_uuid); TRANSLATE('Data Replication Destination Storage System: %[tag]', eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c11000c SCID_DRM_SITE_FAILOVER_DEST_TO_SRC TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Destination Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Data Replication Source Storage System: %[tag]', eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c12000c SCID_DRM_SITE_FAILOVER_SRC_TO_DEST TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Data Replication Destination Storage System: %[tag]', eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c155f0c SCID_DRM_TUNNEL_CLOSED TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id);

TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c160016 SCID_DRM_TIME_REPORT TRANSLATIONBLOCK TRANSLATE('Message sender: %[uuid]', eip16.sender); TRANSLATE('Message receiver: %[uuid]', eip16.receiver); TRANSLATE('Message receiver's partner: %[uuid]', eip16.receiver_partner); TRANSLATE('Time message sent: %[scmitim]', eip16.sent_time); TRANSLATE('Time message received: %[scmitim]', eip16.received_time); ENDTRANSLATIONBLOCK EC BLOCK: 0c17630c SCID_DRM_COMM_PROTOCOL_MISMATCH TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid ); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c18640c SCID_DRM_SLOW_CROSS_SITE_RESPONSE TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Data Replication Destination Storage System: %[tag]', eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c19020c SCID_DRM_WRITE_COLLISION TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Source Virtual Disk: %[tag]', eip0C.source_scvd_uuid); TRANSLATE('Data Replication Destination Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Destination Virtual Disk: %[tag]', eip0C.dest_scvd_uuid); TRANSLATE('First overlapping block in error: 0x%08x', eip0C.vda); ENDTRANSLATIONBLOCK EC BLOCK: 0c1a000c SCID_DRM_COPY_DONE TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Source Virtual Disk: %[tag]', eip0C.source_scvd_uuid); TRANSLATE('Data Replication Destination Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Destination Virtual Disk: %[tag]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c1b5f0c SCID_DRM_LOGGING_SITE_INACCESS TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Data Replication Destination Storage System: %[tag]', eip0C.peer_scell_uuid);

ENDTRANSLATIONBLOCK EC BLOCK: 0c1c610c SCID_DRM_LOGGING_UNIT_INACCESS TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Data Replication Destination Storage System: %[tag]', eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c1d000c SCID_DRM_LOG_INCONSISTENT TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Data Replication Destination Storage System: %[tag]', eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c1e5f0c SCID_DRM_NOT_PRESENTING_UNITS TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Data Replication Destination Storage System: %[tag]', eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c1f000c SCID_DRM_REPRESENTING_UNITS TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Data Replication Destination Storage System: %[tag]', eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c20650c SCID_DRM_STUCK_CROSS_SITE_RESPONSE TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Data Replication Destination Storage System: %[tag]', eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c21660c SCID_DRM_STUCK_LOCAL_GSB_LOCK TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Data Replication Destination Storage System: %[tag]', eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c22000c SCID_DRM_TUNNEL_OPENED TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid ); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK

EC BLOCK: 0c23670c SCID_DRM_SLOW_ISL_RESPONSE TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Data Replication Destination Storage System: %[tag]', eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c24000c SCID_DRM_LOGGING_UNIT_STALLED TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Data Replication Destination Storage System: %[tag]', eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c25000c SCID_DRM_COPY_WRITE_UNIT_STALLED TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Source Virtual Disk: %[tag]', eip0C.source_scvd_uuid); TRANSLATE('Data Replication Destination Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Destination Virtual Disk: %[tag]', eip0C.dest_scvd_uuid); TRANSLATE('First block in error: 0x%08x', eip0C.vda); ENDTRANSLATIONBLOCK EC BLOCK: 0c26000c SCID_DRM_EXISTING_TUNNEL_OPENED TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid ); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c27000c SCID_DRM_TUNNEL_OPENED_BY_PEER TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid ); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c285f0c SCID_DRM_REMOTE_SITE_INACCESS TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c29000c SCID_DRM_TUNNEL_CLOSED_PREF_PORT TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]',

eip0C.peer_scell_uuid ); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c2a000c SCID_DRM_REMOTE_SITE_FOUND TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c2b600c SCID_DRM_MERGE_READ_ERROR TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c2c660c SCID_DRM_STUCK_DEST_GSB_LOCK TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Destination Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Data Replication Source Storage System: %[tag]', eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c2d000c SCID_DRM_DELETE_PORTWWN TRANSLATIONBLOCK TRANSLATE('Client Object: %[tag]', eip0C.group_uuid); TRANSLATE('Host index: 0x%04x', eip0C.blocks); TRANSLATE('Peer node: %[wwn]', eip0C.source_scvd_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c2e680c SCID_DRM_TOO_MANY_NODES TRANSLATIONBLOCK ENDTRANSLATIONBLOCK EC BLOCK: 0c2f000c SCID_DRM_AVAILABLE_NODES TRANSLATIONBLOCK ENDTRANSLATIONBLOCK EC BLOCK: 0c30000c SCID_DRM_INVALIDATE_LOG TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Data Replication Destination Storage System: %[tag]', eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c31000c SCID_DRM_COPY_RESTART TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Source Virtual Disk: %[tag]', eip0C.source_scvd_uuid); TRANSLATE('Data Replication Destination Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Destination Virtual Disk: %[tag]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK

EC BLOCK: 0c325f0c SCID_DRM_TUNNEL_CL_LNKDWN TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c335f0c SCID_DRM_TUNNEL_CL_STUCKTMO TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c345f0c SCID_DRM_TUNNEL_CL_FLTMO TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c35070c SCID_DRM_TUNNEL_CL_GSBLCK TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Destination Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c365f0c SCID_DRM_TUNNEL_CL_THRASH TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c375f0c SCID_DRM_TUNNEL_CL_PNGRTRY TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c38630c SCID_DRM_TUNNEL_CL_UNSUPPROTO TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id);

TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c39000c SCID_DRM_TUNNEL_CL_TEARDOWN TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c3a5f0c SCID_DRM_TUNNEL_CL_OPENTMO TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c3b000c SCID_DRM_TUNNEL_CL_RMTREOPEN TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c3c000c SCID_DRM_TUNNEL_CL_RMTOPN_DP TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c3d5f0c SCID_DRM_TUNNEL_CL_RSNDTMO TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c3e000c SCID_DRM_TUNNEL_CL_RMTREQ TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK

EC BLOCK: 0c3f000c SCID_DRM_TUNNEL_CL_NEWSID TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c40690c SCID_DRM_TUNNEL_CL_INVALIDSN TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c41000c SCID_DRM_TUNNEL_CL_CHGPROTO TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c42000c SCID_DRM_TUNNEL_CL_PEERDEL TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c43000c SCID_DRM_TUNNEL_CL_MAINT13 TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c49000c SCID_DRM_TUNNEL_CL_CCBDEL TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c4a000c SCID_DRM_CONN_RJT_RESYNC TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid);

TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c4b000c SCID_DRM_CONN_RJT_NOSCELL TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c4c000c SCID_DRM_CONN_RJT_NOPATH TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c4e000c SCID_DRM_CONN_RJT_NOTEVA TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c4f000c SCID_DRM_CONN_RJT_HOSTWWID TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c50000c SCID_DRM_CONN_RJT_BADUUID TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c51000c SCID_DRM_CONN_RJT_VERSION TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c52000c SCID_DRM_CONN_RJT_PRTDISABLE TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id);

TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c53000c SCID_DRM_CONN_RJT_NORESRC TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c54000c SCID_DRM_CONN_RJT_NEWVER TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c550016 SCID_DRM_TIME_SENT TRANSLATIONBLOCK TRANSLATE('Message sender: %[uuid]', eip16.sender); TRANSLATE('Message sender's partner: %[uuid]', eip16.receiver_partner); TRANSLATE('Message receiver: %[uuid]', eip16.receiver); TRANSLATE('Time message sent: %[scmitim]', eip16.sent_time); ENDTRANSLATIONBLOCK EC BLOCK: 0c56000c SCID_DRM_FL_TIMEOUT_CHANGE TRANSLATIONBLOCK TRANSLATE('The DRM forced logging timeout value has changed from %d seconds to % d seconds.', eip0C.port, eip0C.side); ENDTRANSLATIONBLOCK EC BLOCK: 0c57000c SCID_DRM_FL_TIMEOUT_RESET TRANSLATIONBLOCK TRANSLATE('The DRM forced logging timeout value has reset to %d seconds.',eip0C. side); ENDTRANSLATIONBLOCK EC BLOCK: 0c58690c SCID_DRM_HIGH_ISL_RETRY_RATE TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c59690c SCID_DRM_HIGH_OUT_OF_ORDER_RATE TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid);

ENDTRANSLATIONBLOCK EC BLOCK: 0c5a670c SCID_DRM_HIGH_ISL_PING_TIME TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c5b670c SCID_DRM_MIN_WRITE_RESOURCES TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c5c670c SCID_DRM_MIN_COPY_RESOURCES TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c5d000c SCID_DRM_ISL_QOS_HAS_IMPROVED TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c5e000c SCID_DRM_LOG_SHRINK_IN_PROGRESS TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Data Replication Destination Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Current Capacity: %d', eip0C.reserved1[1]); ENDTRANSLATIONBLOCK EC BLOCK: 0c5f000c SCID_DRM_LOG_SHRINK_FINISHED TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Data Replication Destination Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Current Capacity: %d', eip0C.reserved1[1]); ENDTRANSLATIONBLOCK EC BLOCK: 0c60000c SCID_DRM_HIGH_DST_VDISK_RESPONSE TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side);

TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c61000c SCID_DRM_TUNNEL_CL_RNIDRSP TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c62000c SCID_DRM_SPLIT_BRAIN_PRESENTING_UNITS TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c63000c SCID_DRM_SPLIT_BRAIN_NOT_PRESENTING_UNITS TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c64000c SCID_DRM_SPLIT_BRAIN_NOT_SETTABLE_ON_DEST TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Data Replication Destination Storage System: %[tag]', eip0C.peer_scell_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c65000c SCID_DRM_LOG_50_PERCENT_FULL TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c66000c SCID_DRM_LOG_75_PERCENT_FULL TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c67000c SCID_DRM_LOG_90_PERCENT_FULL TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c68000c SCID_DRM_LOG_95_PERCENT_FULL TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c69000c SCID_DRM_LOG_99_PERCENT_FULL TRANSLATIONBLOCK

TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c6f000c SCID_DRM_HIGH_SRC_VDISK_RESPONSE TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c70000c SCID_DRM_FRES_DONE TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Source Virtual Disk: %[tag]', eip0C.source_scvd_uuid); TRANSLATE('Data Replication Destination Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Destination Virtual Disk: %[tag]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c71000c SCID_DRM_MEMBER_REMOVAL_DONE TRANSLATIONBLOCK TRANSLATE('Source Virtual Disk: %[tag]', eip0C.source_scvd_uuid); TRANSLATE('Data Replication Group %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Destination Virtual Disk: %[tag]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c72000c SCID_DRM_MEMBER_REMOVAL_FAILED TRANSLATIONBLOCK TRANSLATE('Source Virtual Disk: %[tag]', eip0C.source_scvd_uuid); TRANSLATE('Data Replication Group %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Destination Virtual Disk: %[tag]', eip0C.dest_scvd_uuid); TRANSLATE('With status of %d', eip0C.status); ENDTRANSLATIONBLOCK EC BLOCK: 0c73000c SCID_DRM_MEMBER_REMOVAL_LOGFULL TRANSLATIONBLOCK TRANSLATE('Source Virtual Disk: %[tag]', eip0C.source_scvd_uuid); TRANSLATE('Data Replication Group %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c74000c SCID_DRM_MERGE_SYNC_START TRANSLATIONBLOCK TRANSLATE('Source Virtual Disk: %[tag]', eip0C.source_scvd_uuid); TRANSLATE('Data Replication Group %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c75000c SCID_DRM_MERGE_SYNC_DONE TRANSLATIONBLOCK TRANSLATE('Source Virtual Disk: %[tag]', eip0C.source_scvd_uuid); TRANSLATE('Data Replication Group %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); ENDTRANSLATIONBLOCK

EC BLOCK: 0c76000c SCID_DRM_LOG_ON_FATA_DSKGRP TRANSLATIONBLOCK TRANSLATE('Data Replication Source: %[tag]', eip0C.group_name_uuid); TRANSLATE('Local Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('The FATA Disk Group used for DR Log: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Assigned automatically (0) or by user (1): %d', eip0C.status); ENDTRANSLATIONBLOCK EC BLOCK: 0c77000c SCID_DRM_FAILOVER_DURING_NORMALIZATION TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c78000c SCID_DRM_MEMBER_SHRINK_DONE TRANSLATIONBLOCK TRANSLATE('Source Virtual Disk: %[tag]', eip0C.source_scvd_uuid); TRANSLATE('Data Replication Group %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c79000c SCID_DRM_MEMBER_SHRINK_FAILED TRANSLATIONBLOCK TRANSLATE('Source Virtual Disk: %[tag]', eip0C.source_scvd_uuid); TRANSLATE('Data Replication Group %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('With status of %d', eip0C.status); TRANSLATE('From remote site (0-local site, Non zero-remote site): %d', eip0C.sid e); ENDTRANSLATIONBLOCK EC BLOCK: 0c7a000c SCID_DRM_MEMBER_SHRINK_LOGFULL TRANSLATIONBLOCK TRANSLATE('Source Virtual Disk: %[tag]', eip0C.source_scvd_uuid); TRANSLATE('Data Replication Group %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c7b000c SCID_DRM_LOG_ON_SSD_DSKGRP TRANSLATIONBLOCK TRANSLATE('Data Replication Source: %[tag]', eip0C.group_name_uuid); TRANSLATE('Local Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('The SSD Disk Group used for DR Log: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Assigned automatically (0) or by user (1): %d', eip0C.status); ENDTRANSLATIONBLOCK EC BLOCK: 0c7c000c SCID_DRM_DEST_VDISK_ON_SSD_DSKGRP TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Local Data Replication Source: %[tag]', eip0C.group_uuid); TRANSLATE('The SSD Disk Group assigned: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('The added Destination Virtual Disk: %[tag]', eip0C.source_scvd_uuid); TRANSLATE('Assigned automatically (0) or by user (1): %d', eip0C.status); ENDTRANSLATIONBLOCK EC BLOCK: 0c7d000c SCID_DRM_SOURCE_VDISK_ON_SSD_DSKGRP

TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Local Data Replication Source: %[tag]', eip0C.group_uuid); TRANSLATE('The SSD Disk Group assigned: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('The added Source Virtual Disk: %[tag]', eip0C.source_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c7e5f0c SCID_DRM_TUNNEL_CL_PLOGO TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c7f5f0c SCID_DRM_TOO_MANY_NPORTS TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); ENDTRANSLATIONBLOCK EC BLOCK: 0c806a0c SCID_DRM_CONN_RJT_PROTOCOL_TYPE TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c815f0c SCID_DRM_TUNNEL_CL_NOPATH TRANSLATIONBLOCK TRANSLATE('Port: %s', eip0C.cerp_id); TRANSLATE('Controller: %d', eip0C.side); TRANSLATE('Peer Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Peer port: %[wwn]', eip0C.dest_scvd_uuid); ENDTRANSLATIONBLOCK EC BLOCK: 0c826b0c SCID_DRM_MEMBER_CAPACITY_MISMATCH TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Source Virtual Disk: %[tag]', eip0C.source_scvd_uuid); TRANSLATE('Data Replication Destination Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Destination Virtual Disk: %[tag]', eip0C.dest_scvd_uuid); TRANSLATE('Status: %d', eip0C.status); ENDTRANSLATIONBLOCK EC BLOCK: 0c83000c SCID_DRM_GROUP_FAILOVER TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); CONDITIONAL(eip0C.extra == 0, TRANSLATE('Failover Master to Slave')); CONDITIONAL(eip0C.extra == 4, TRANSLATE('Failover Master to Slave, Prefer Failback'));

CONDITIONAL(eip0C.extra == 1, TRANSLATE('Failover Slave to Master')); CONDITIONAL(eip0C.extra == 5, TRANSLATE('Failover Slave to Master, Prefer Failback')); TRANSLATE('Status: %d', eip0C.status); ENDTRANSLATIONBLOCK EC BLOCK: 0c84000c SCID_DRM_LOG_EXPAND_FINISHED TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('Data Replication Destination Storage System: %[tag]', eip0C.peer_scell_uuid); TRANSLATE('Original Capacity: %d', eip0C.reserved1[0]); TRANSLATE('Current Capacity: %d', eip0C.reserved1[1]); ENDTRANSLATIONBLOCK EC BLOCK: 0c86000c SCID_DRM_MEMBER_DEST_REMOVAL_FAILED TRANSLATIONBLOCK TRANSLATE('Source Virtual Disk: %[tag]', eip0C.source_scvd_uuid); TRANSLATE('Data Replication Group %[tag]', eip0C.group_name_uuid); TRANSLATE('Source Data Replication Group: %[tag]', eip0C.group_uuid); TRANSLATE('With status of %d', eip0C.status); ENDTRANSLATIONBLOCK EC BLOCK: 0d024106 SCID_DEEMU_DRIVE_MISSING TRANSLATIONBLOCK TRANSLATE('Enclosure Vendor Identification: %s', eip06.vendor_id); TRANSLATE('Enclosure Product Identification: %s', eip06.product_id); TRANSLATE('Enclosure Product Revision: %s', eip06.product_rev); TRANSLATE('Enclosure Saleable Serial Number: %s', eip06.enc_serial_num); TRANSLATE('Enclosure WWID (node): %08x%08x', eip06.enc_wwn.hi, eip06.enc_wwn.lo) ; TRANSLATE('Enclosure: %d Bay: %d', eip06.enc_num, eip06.bypass_bay); CONDITIONAL(eip06.port == 0, TRANSLATE('Loop A ELMo WWID (port): %08x%08x', eip06.loop_a_elmo_n_port_name.hi, eip06.loop_a_elmo_n_port_name.lo), TRANSLATE('Loop B ELMo WWID (port): %08x%08x', eip06.loop_b_elmo_n_port_name.hi, eip06.loop_b_elmo_n_port_name.lo) ); ENDTRANSLATIONBLOCK EC BLOCK: 0d348006 SCID_DEEMU_DEPS_MISSING TRANSLATIONBLOCK TRANSLATE('Enclosure Vendor Identification: %s', eip06.vendor_id); TRANSLATE('Enclosure Product Identification: %s', eip06.product_id); TRANSLATE('Enclosure Product Revision: %s', eip06.product_rev); TRANSLATE('Enclosure Saleable Serial Number: %s', eip06.enc_serial_num); TRANSLATE('Enclosure WWID (node): %08x%08x', eip06.enc_wwn.hi, eip06.enc_wwn.lo) ; TRANSLATE('Enclosure: %d', eip06.enc_num); TRANSLATE('Power Supply: %d', eip06.bypass_bay); CONDITIONAL(eip06.port == 0, TRANSLATE('Loop A ELMo WWID (port): %08x%08x', eip06.loop_a_elmo_n_port_name.hi, eip06.loop_a_elmo_n_port_name.lo), TRANSLATE('Loop B ELMo WWID (port): %08x%08x', eip06.loop_b_elmo_n_port_name.hi, eip06.loop_b_elmo_n_port_name.lo) ); ENDTRANSLATIONBLOCK

EC BLOCK: 0d359a06 SCID_DEEMU_LOAD_BALANCE TRANSLATIONBLOCK TRANSLATE('Enclosure Vendor Identification: %s', eip06.vendor_id); TRANSLATE('Enclosure Product Identification: %s', eip06.product_id); TRANSLATE('Enclosure Product Revision: %s', eip06.product_rev); TRANSLATE('Enclosure Saleable Serial Number: %s', eip06.enc_serial_num); TRANSLATE('Enclosure WWID (node): %08x%08x', eip06.enc_wwn.hi, eip06.enc_wwn.lo) ; TRANSLATE('Enclosure: %d', eip06.enc_num); TRANSLATE('Power Supply: %d', eip06.bypass_bay); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo WWID (port): %08x%08x', eip06.loop_a_elmo_n_port_name.hi, eip06.loop_a_elmo_n_port_name.lo), TRANSLATE('Loop B ELMo WWID (port): %08x%08x', eip06.loop_b_elmo_n_port_name.hi, eip06.loop_b_elmo_n_port_name.lo) ); ENDTRANSLATIONBLOCK EC BLOCK: 0d478306 SCID_DEEMU_DEBLWR_ERROR TRANSLATIONBLOCK TRANSLATE('Enclosure Vendor Identification: %s', eip06.vendor_id); TRANSLATE('Enclosure Product Identification: %s', eip06.product_id); TRANSLATE('Enclosure Product Revision: %s', eip06.product_rev); TRANSLATE('Enclosure Saleable Serial Number: %s', eip06.enc_serial_num); TRANSLATE('Enclosure WWID (node): %08x%08x', eip06.enc_wwn.hi, eip06.enc_wwn.lo) ; TRANSLATE('Enclosure: %d', eip06.enc_num); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo WWID (port): %08x%08x', eip06.loop_a_elmo_n_port_name.hi, eip06.loop_a_elmo_n_port_name.lo), TRANSLATE('Loop B ELMo WWID (port): %08x%08x', eip06.loop_b_elmo_n_port_name.hi, eip06.loop_b_elmo_n_port_name.lo) ); CONDITIONAL(eip06.bypass_bay == 1, TRANSLATE('Fan Module 1 Firmware Revision: %s', eip06.fan_module_1_fw_rev), TRANSLATE('Fan Module 2 Firmware Revision: %s', eip06.fan_module_2_fw_rev) ); CONDITIONAL(eip06.bypass_bay == 1, TRANSLATE('Fan Module 1 Hardware Revision: %s', eip06.fan_module_1_hw_rev), TRANSLATE('Fan Module 2 Hardware Revision: %s', eip06.fan_module_2_hw_rev) ); CONDITIONAL(eip06.bypass_bay == 1, TRANSLATE('Fan Module 1 Serial Number: %s', eip06.fan_module_1_serial_num), TRANSLATE('Fan Module 2 Serial Number: %s', eip06.fan_module_2_serial_num) ); ENDTRANSLATIONBLOCK EC BLOCK: 0d4b8206 SCID_DEEMU_DEBLWR_MISSING TRANSLATIONBLOCK TRANSLATE('Enclosure Vendor Identification: %s', eip06.vendor_id); TRANSLATE('Enclosure Product Identification: %s', eip06.product_id); TRANSLATE('Enclosure Product Revision: %s', eip06.product_rev); TRANSLATE('Enclosure WWID (node): %08x%08x', eip06.enc_wwn.hi, eip06.enc_wwn.lo) ; TRANSLATE('Enclosure: %d', eip06.enc_num); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo WWID (port): %08x%08x', eip06.loop_a_elmo_n_port_name.hi, eip06.loop_a_elmo_n_port_name.lo), TRANSLATE('Loop B ELMo WWID (port): %08x%08x', eip06.loop_b_elmo_n_port_name.hi, eip06.loop_b_elmo_n_port_name.lo)

); CONDITIONAL(eip06.bypass_bay == 1, TRANSLATE('Fan Module 1 Firmware Revision: %s', eip06.fan_module_1_fw_rev), TRANSLATE('Fan Module 2 Firmware Revision: %s', eip06.fan_module_2_fw_rev) ); CONDITIONAL(eip06.bypass_bay == 1, TRANSLATE('Fan Module 1 Hardware Revision: %s', eip06.fan_module_1_hw_rev), TRANSLATE('Fan Module 2 Hardware Revision: %s', eip06.fan_module_2_hw_rev) ); CONDITIONAL(eip06.bypass_bay == 1, TRANSLATE('Fan Module 1 Serial Number: %s', eip06.fan_module_1_serial_num), TRANSLATE('Fan Module 2 Serial Number: %s', eip06.fan_module_2_serial_num) ); ENDTRANSLATIONBLOCK EC BLOCK: 0d5b8606 SCID_DEEMU_DETS_OOR TRANSLATIONBLOCK TRANSLATE('Enclosure Vendor Identification: %s', eip06.vendor_id); TRANSLATE('Enclosure Product Identification: %s', eip06.product_id); TRANSLATE('Enclosure Product Revision: %s', eip06.product_rev); TRANSLATE('Enclosure Saleable Serial Number: %s', eip06.enc_serial_num); TRANSLATE('Enclosure WWID (node): %08x%08x', eip06.enc_wwn.hi, eip06.enc_wwn.lo) ; TRANSLATE('Enclosure: %d', eip06.enc_num); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo WWID (port): %08x%08x', eip06.loop_a_elmo_n_port_name.hi, eip06.loop_a_elmo_n_port_name.lo), TRANSLATE('Loop B ELMo WWID (port): %08x%08x', eip06.loop_b_elmo_n_port_name.hi, eip06.loop_b_elmo_n_port_name.lo) ); CONDITIONAL(eip06.data == 0, TRANSLATE('Updated Condition: UNSUPPORTED') ); CONDITIONAL(eip06.data == 1, TRANSLATE('Updated Condition: OK') ); CONDITIONAL(eip06.data == 2, TRANSLATE('Updated Condition: CRITICAL') ); CONDITIONAL(eip06.data == 3, TRANSLATE('Updated Condition: NONCRITICAL') ); CONDITIONAL(eip06.data == 4, TRANSLATE('Updated Condition: UNRECOVERABLE') ); CONDITIONAL(eip06.data == 5, TRANSLATE('Updated Condition: NOT_INSTALLED') ); CONDITIONAL(eip06.data == 6, TRANSLATE('Updated Condition: UNKNOWN') ); CONDITIONAL(eip06.data == 7, TRANSLATE('Updated Condition: NOT_AVAILABLE') ); TRANSLATE('Average temperature: %dC', eip06.data2); ENDTRANSLATIONBLOCK EC BLOCK: 0d5f8706 SCID_DEEMU_DETS_ATCRITICAL TRANSLATIONBLOCK TRANSLATE('Enclosure Vendor Identification: %s', eip06.vendor_id);

TRANSLATE('Enclosure Product Identification: %s', eip06.product_id); TRANSLATE('Enclosure Product Revision: %s', eip06.product_rev); TRANSLATE('Enclosure Saleable Serial Number: %s', eip06.enc_serial_num); TRANSLATE('Enclosure WWID (node): %08x%08x', eip06.enc_wwn.hi, eip06.enc_wwn.lo) ; TRANSLATE('Enclosure: %d', eip06.enc_num); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo WWID (port): %08x%08x', eip06.loop_a_elmo_n_port_name.hi, eip06.loop_a_elmo_n_port_name.lo), TRANSLATE('Loop B ELMo WWID (port): %08x%08x', eip06.loop_b_elmo_n_port_name.hi, eip06.loop_b_elmo_n_port_name.lo) ); CONDITIONAL(eip06.data == 0, TRANSLATE('Updated Condition: UNSUPPORTED') ); CONDITIONAL(eip06.data == 1, TRANSLATE('Updated Condition: OK') ); CONDITIONAL(eip06.data == 2, TRANSLATE('Updated Condition: CRITICAL') ); CONDITIONAL(eip06.data == 3, TRANSLATE('Updated Condition: NONCRITICAL') ); CONDITIONAL(eip06.data == 4, TRANSLATE('Updated Condition: UNRECOVERABLE') ); CONDITIONAL(eip06.data == 5, TRANSLATE('Updated Condition: NOT_INSTALLED') ); CONDITIONAL(eip06.data == 6, TRANSLATE('Updated Condition: UNKNOWN') ); CONDITIONAL(eip06.data == 7, TRANSLATE('Updated Condition: NOT_AVAILABLE') ); TRANSLATE('Average temperature: %dC', eip06.data2); ENDTRANSLATIONBLOCK EC BLOCK: 0d8d9006 SCID_DEEMU_DEXCVR_ERROR TRANSLATIONBLOCK TRANSLATE('Enclosure Vendor Identification: %s', eip06.vendor_id); TRANSLATE('Enclosure Product Identification: %s', eip06.product_id); TRANSLATE('Enclosure Product Revision: %s', eip06.product_rev); TRANSLATE('Enclosure Saleable Serial Number: %s', eip06.enc_serial_num); TRANSLATE('Enclosure WWID (node): %08x%08x', eip06.enc_wwn.hi, eip06.enc_wwn.lo) ; TRANSLATE('Enclosure: %d', eip06.enc_num); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo WWID (port): %08x%08x', eip06.loop_a_elmo_n_port_name.hi, eip06.loop_a_elmo_n_port_name.lo), TRANSLATE('Loop B ELMo WWID (port): %08x%08x', eip06.loop_b_elmo_n_port_name.hi, eip06.loop_b_elmo_n_port_name.lo) ); CONDITIONAL(eip06.port == 0 && eip06.bypass_bay == 1, TRANSLATE('Loop A Transceiver 1 Hardware Type: %s', eip06.loop_a_elmo_transceive r_1_hw_type) ); CONDITIONAL(eip06.port == 0 &&

eip06.bypass_bay == 2, TRANSLATE('Loop A Transceiver 2 Hardware Type: %s', eip06.loop_a_elmo_transceive r_2_hw_type) ); CONDITIONAL(eip06.port == 1 && eip06.bypass_bay == 1, TRANSLATE('Loop B Transceiver 1 Hardware Type: %s', eip06.loop_b_elmo_transceive r_1_hw_type) ); CONDITIONAL(eip06.port == 1 && eip06.bypass_bay == 2, TRANSLATE('Loop B Transceiver 2 Hardware Type: %s', eip06.loop_b_elmo_transceive r_2_hw_type) ); CONDITIONAL(eip06.data == 0, TRANSLATE('Updated Condition: UNSUPPORTED') ); CONDITIONAL(eip06.data == 1, TRANSLATE('Updated Condition: OK') ); CONDITIONAL(eip06.data == 2, TRANSLATE('Updated Condition: CRITICAL') ); CONDITIONAL(eip06.data == 3, TRANSLATE('Updated Condition: NONCRITICAL') ); CONDITIONAL(eip06.data == 4, TRANSLATE('Updated Condition: UNRECOVERABLE') ); CONDITIONAL(eip06.data == 5, TRANSLATE('Updated Condition: NOT_INSTALLED') ); CONDITIONAL(eip06.data == 6, TRANSLATE('Updated Condition: UNKNOWN') ); CONDITIONAL(eip06.data == 7, TRANSLATE('Updated Condition: NOT_AVAILABLE') ); CONDITIONAL(eip06.data2 == 0, TRANSLATE('Previous Condition: UNSUPPORTED') ); CONDITIONAL(eip06.data2 == 1, TRANSLATE('Previous Condition: OK') ); CONDITIONAL(eip06.data2 == 2, TRANSLATE('Previous Condition: CRITICAL') ); CONDITIONAL(eip06.data2 == 3, TRANSLATE('Previous Condition: NONCRITICAL') ); CONDITIONAL(eip06.data2 == 4, TRANSLATE('Previous Condition: UNRECOVERABLE') ); CONDITIONAL(eip06.data2 == 5, TRANSLATE('Previous Condition: NOT_INSTALLED') ); CONDITIONAL(eip06.data2 == 6, TRANSLATE('Previous Condition: UNKNOWN') ); CONDITIONAL(eip06.data2 == 7,

TRANSLATE('Previous Condition: NOT_AVAILABLE') ); ENDTRANSLATIONBLOCK EC BLOCK: 0ddd9306 SCID_DEEMU_DEIOM_ERROR_UNREC TRANSLATIONBLOCK TRANSLATE('Enclosure Vendor Identification: %s', eip06.vendor_id); TRANSLATE('Enclosure Product Identification: %s', eip06.product_id); TRANSLATE('Enclosure Product Revision: %s', eip06.product_rev); TRANSLATE('Enclosure Saleable Serial Number: %s', eip06.enc_serial_num); TRANSLATE('Enclosure WWID (node): %08x%08x', eip06.enc_wwn.hi, eip06.enc_wwn.lo) ; TRANSLATE('Enclosure: %d', eip06.enc_num); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo WWID (port): %08x%08x', eip06.loop_a_elmo_n_port_name.hi, eip06.loop_a_elmo_n_port_name.lo), TRANSLATE('Loop B ELMo WWID (port): %08x%08x', eip06.loop_b_elmo_n_port_name.hi, eip06.loop_b_elmo_n_port_name.lo) ); CONDITIONAL(eip06.data == 0, TRANSLATE('Updated Condition: UNSUPPORTED') ); CONDITIONAL(eip06.data == 1, TRANSLATE('Updated Condition: OK') ); CONDITIONAL(eip06.data == 2, TRANSLATE('Updated Condition: CRITICAL') ); CONDITIONAL(eip06.data == 3, TRANSLATE('Updated Condition: NONCRITICAL') ); CONDITIONAL(eip06.data == 4, TRANSLATE('Updated Condition: UNRECOVERABLE') ); CONDITIONAL(eip06.data == 5, TRANSLATE('Updated Condition: NOT_INSTALLED') ); CONDITIONAL(eip06.data == 6, TRANSLATE('Updated Condition: UNKNOWN') ); CONDITIONAL(eip06.data == 7, TRANSLATE('Updated Condition: NOT_AVAILABLE') ); ENDTRANSLATIONBLOCK EC BLOCK: 0dde0006 SCID_DEEMU_DEIOM_NOCOMM_ERROR TRANSLATIONBLOCK TRANSLATE('Enclosure WWID (node): %08x%08x', eip06.enc_wwn.hi, eip06.enc_wwn.lo) ; TRANSLATE('Enclosure: %d', eip06.enc_num); CONDITIONAL(eip06.port == 0 || eip06.port == 2 || eip06.port == 4, TRANSLATE('Loop A ELMo WWID (port): %08x%08x', eip06.loop_a_elmo_n_port_name.hi, eip06.loop_a_elmo_n_port_name.lo), TRANSLATE('Loop B ELMo WWID (port): %08x%08x', eip06.loop_b_elmo_n_port_name.hi, eip06.loop_b_elmo_n_port_name.lo) ); CONDITIONAL(eip06.data == 0, TRANSLATE('Updated Condition: UNSUPPORTED') ); CONDITIONAL(eip06.data == 1,

TRANSLATE('Updated Condition: ); CONDITIONAL(eip06.data == 2, TRANSLATE('Updated Condition: ); CONDITIONAL(eip06.data == 3, TRANSLATE('Updated Condition: ); CONDITIONAL(eip06.data == 4, TRANSLATE('Updated Condition: ); CONDITIONAL(eip06.data == 5, TRANSLATE('Updated Condition: ); CONDITIONAL(eip06.data == 6, TRANSLATE('Updated Condition: ); CONDITIONAL(eip06.data == 7, TRANSLATE('Updated Condition: ); ENDTRANSLATIONBLOCK

OK') CRITICAL') NONCRITICAL') UNRECOVERABLE') NOT_INSTALLED') UNKNOWN') NOT_AVAILABLE')

EC BLOCK: 0df00011 SCID_DEEMU_STATUS_CHANGE TRANSLATIONBLOCK CONDITIONAL(eip11.dencl_num > 0, TRANSLATE('Enclosure: %d.', eip11.dencl_num) ); CONDITIONAL(eip11.loop == 0, TRANSLATE('Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information'), TRANSL ATE('Drive enclosures available on loop B may be found in the enclosures array i n this event's detailed information')); ENDTRANSLATIONBLOCK EC BLOCK: 0e800019 SCID_SDC_BATT_SYS_BOOT_STATUS TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); TRANSLATE('Battery System State : %[scmi_nsc_battery_system_condition]', eip19.state.cur); TRANSLATE('Battery System HUT : %d',eip19.status_data.cur); TRANSLATE('Brick 0 State : %[scmi_battery_brick_state]', eip19.comp_states[0]); TRANSLATE('Brick 0 Overall Status : %[scmi_battery_brick_status_code]', eip19.comp_status_codes[0]); TRANSLATE('Brick 0 Combined Status : 0x%08X',eip19.comp_status_data[0]); TRANSLATE('Brick 1 State : %[scmi_battery_brick_state]', eip19.comp_states[1]); TRANSLATE('Brick 1 Overall Status : %[scmi_battery_brick_status_code]', eip19.comp_status_codes[1]); TRANSLATE('Brick 1 Combined Status : 0x%08X',eip19.comp_status_data[1]); TRANSLATE('Brick 2 State : %[scmi_battery_brick_state]', eip19.comp_states[2]); TRANSLATE('Brick 2 Overall Status : %[scmi_battery_brick_status_code]', eip19.comp_status_codes[2]); TRANSLATE('Brick 2 Combined Status : 0x%08X',eip19.comp_status_data[2]); TRANSLATE('Brick 3 State : %[scmi_battery_brick_state]', eip19.comp_states[3]); TRANSLATE('Brick 3 Overall Status : %[scmi_battery_brick_status_code]', eip19.comp_status_codes[3]); TRANSLATE('Brick 3 Combined Status : 0x%08X',eip19.comp_status_data[3]); ENDTRANSLATIONBLOCK

EC BLOCK: 0e810019 SCID_SDC_BATT_BRICK_0_INSERTED TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); TRANSLATE('State : %[scmi_battery_brick_state]', eip19.state.cur); TRANSLATE('Overall Status : %[scmi_battery_brick_status_code]', eip19.status_code.cur); TRANSLATE('Combined Status: 0x%08X',eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e82e119 SCID_SDC_BATT_BRICK_0_REMOVED TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); TRANSLATE('State : %[scmi_battery_brick_state] --> %[scmi_battery_brick _state]', eip19.state.old, eip19.state.cur); CONDITIONAL(eip19.status_code.cur == eip19.status_code.old, TRANSLATE('Overall Status : %[scmi_battery_brick_status_code]', eip19.status_code.cur), TRANSLATE('Overall Status : %[scmi_battery_brick_status_code] --> %[scmi_battery _brick_status_code]', eip19.status_code.old, eip19.status_code.cur) ); TRANSLATE('Combined Status: 0x%08X',eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e830019 SCID_SDC_BATT_BRICK_0_UPDATE_GOOD TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); CONDITIONAL(eip19.state.cur == eip19.state.old, TRANSLATE('State : %[scmi_battery_brick_state]', eip19.state.cur), TRANSLATE('State : %[scmi_battery_brick_state] --> %[scmi_battery_brick _state]', eip19.state.old, eip19.state.cur) ); CONDITIONAL(eip19.status_code.cur == eip19.status_code.old, TRANSLATE('Overall Status : %[scmi_battery_brick_status_code]', eip19.status_code.cur), TRANSLATE('Overall Status : %[scmi_battery_brick_status_code] --> %[scmi_battery _brick_status_code]', eip19.status_code.old, eip19.status_code.cur) ); TRANSLATE('Combined Status: 0x%08X',eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e84dd19 SCID_SDC_BATT_BRICK_0_UPDATE_BAD TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); CONDITIONAL(eip19.state.cur == eip19.state.old, TRANSLATE('State : %[scmi_battery_brick_state]', eip19.state.cur), TRANSLATE('State : %[scmi_battery_brick_state] --> %[scmi_battery_brick _state]', eip19.state.old,

eip19.state.cur) ); CONDITIONAL(eip19.status_code.cur == eip19.status_code.old, TRANSLATE('Overall Status : %[scmi_battery_brick_status_code]', eip19.status_code.cur), TRANSLATE('Overall Status : %[scmi_battery_brick_status_code] --> %[scmi_battery _brick_status_code]', eip19.status_code.old, eip19.status_code.cur) ); TRANSLATE('Combined Status: 0x%08X',eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e850019 SCID_SDC_BATT_BRICK_1_INSERTED TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); TRANSLATE('State : %[scmi_battery_brick_state]', eip19.state.cur); TRANSLATE('Overall Status : %[scmi_battery_brick_status_code]', eip19.status_code.cur); TRANSLATE('Combined Status: 0x%08X',eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e86e219 SCID_SDC_BATT_BRICK_1_REMOVED TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); TRANSLATE('State : %[scmi_battery_brick_state] --> %[scmi_battery_brick _state]', eip19.state.old, eip19.state.cur); CONDITIONAL(eip19.status_code.cur == eip19.status_code.old, TRANSLATE('Overall Status : %[scmi_battery_brick_status_code]', eip19.status_code.cur), TRANSLATE('Overall Status : %[scmi_battery_brick_status_code] --> %[scmi_battery _brick_status_code]', eip19.status_code.old, eip19.status_code.cur) ); TRANSLATE('Combined Status: 0x%08X',eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e870019 SCID_SDC_BATT_BRICK_1_UPDATE_GOOD TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); CONDITIONAL(eip19.state.cur == eip19.state.old, TRANSLATE('State : %[scmi_battery_brick_state]', eip19.state.cur), TRANSLATE('State : %[scmi_battery_brick_state] --> %[scmi_battery_brick _state]', eip19.state.old, eip19.state.cur) ); CONDITIONAL(eip19.status_code.cur == eip19.status_code.old, TRANSLATE('Overall Status : %[scmi_battery_brick_status_code]', eip19.status_code.cur), TRANSLATE('Overall Status : %[scmi_battery_brick_status_code] --> %[scmi_battery _brick_status_code]', eip19.status_code.old, eip19.status_code.cur) );

TRANSLATE('Combined Status: 0x%08X',eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e88de19 SCID_SDC_BATT_BRICK_1_UPDATE_BAD TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); CONDITIONAL(eip19.state.cur == eip19.state.old, TRANSLATE('State : %[scmi_battery_brick_state]', eip19.state.cur), TRANSLATE('State : %[scmi_battery_brick_state] --> %[scmi_battery_brick _state]', eip19.state.old, eip19.state.cur) ); CONDITIONAL(eip19.status_code.cur == eip19.status_code.old, TRANSLATE('Overall Status : %[scmi_battery_brick_status_code]', eip19.status_code.cur), TRANSLATE('Overall Status : %[scmi_battery_brick_status_code] --> %[scmi_battery _brick_status_code]', eip19.status_code.old, eip19.status_code.cur) ); TRANSLATE('Combined Status: 0x%08X',eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e890019 SCID_SDC_BATT_BRICK_2_INSERTED TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); TRANSLATE('State : %[scmi_battery_brick_state]', eip19.state.cur); TRANSLATE('Overall Status : %[scmi_battery_brick_status_code]', eip19.status_code.cur); TRANSLATE('Combined Status: 0x%08X',eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e8ae319 SCID_SDC_BATT_BRICK_2_REMOVED TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); TRANSLATE('State : %[scmi_battery_brick_state] --> %[scmi_battery_brick _state]', eip19.state.old, eip19.state.cur); CONDITIONAL(eip19.status_code.cur == eip19.status_code.old, TRANSLATE('Overall Status : %[scmi_battery_brick_status_code]', eip19.status_code.cur), TRANSLATE('Overall Status : %[scmi_battery_brick_status_code] --> %[scmi_battery _brick_status_code]', eip19.status_code.old, eip19.status_code.cur) ); TRANSLATE('Combined Status: 0x%08X',eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e8b0019 SCID_SDC_BATT_BRICK_2_UPDATE_GOOD TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); CONDITIONAL(eip19.state.cur == eip19.state.old, TRANSLATE('State : %[scmi_battery_brick_state]', eip19.state.cur), TRANSLATE('State : %[scmi_battery_brick_state] --> %[scmi_battery_brick

_state]', eip19.state.old, eip19.state.cur) ); CONDITIONAL(eip19.status_code.cur == eip19.status_code.old, TRANSLATE('Overall Status : %[scmi_battery_brick_status_code]', eip19.status_code.cur), TRANSLATE('Overall Status : %[scmi_battery_brick_status_code] --> %[scmi_battery _brick_status_code]', eip19.status_code.old, eip19.status_code.cur) ); TRANSLATE('Combined Status: 0x%08X',eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e8cdf19 SCID_SDC_BATT_BRICK_2_UPDATE_BAD TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); CONDITIONAL(eip19.state.cur == eip19.state.old, TRANSLATE('State : %[scmi_battery_brick_state]', eip19.state.cur), TRANSLATE('State : %[scmi_battery_brick_state] --> %[scmi_battery_brick _state]', eip19.state.old, eip19.state.cur) ); CONDITIONAL(eip19.status_code.cur == eip19.status_code.old, TRANSLATE('Overall Status : %[scmi_battery_brick_status_code]', eip19.status_code.cur), TRANSLATE('Overall Status : %[scmi_battery_brick_status_code] --> %[scmi_battery _brick_status_code]', eip19.status_code.old, eip19.status_code.cur) ); TRANSLATE('Combined Status: 0x%08X',eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e8d0019 SCID_SDC_BATT_BRICK_3_INSERTED TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); TRANSLATE('State : %[scmi_battery_brick_state]', eip19.state.cur); TRANSLATE('Overall Status : %[scmi_battery_brick_status_code]', eip19.status_code.cur); TRANSLATE('Combined Status: 0x%08X',eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e8ee419 SCID_SDC_BATT_BRICK_3_REMOVED TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); TRANSLATE('State : %[scmi_battery_brick_state] --> %[scmi_battery_brick _state]', eip19.state.old, eip19.state.cur); CONDITIONAL(eip19.status_code.cur == eip19.status_code.old, TRANSLATE('Overall Status : %[scmi_battery_brick_status_code]', eip19.status_code.cur), TRANSLATE('Overall Status : %[scmi_battery_brick_status_code] --> %[scmi_battery _brick_status_code]', eip19.status_code.old,

eip19.status_code.cur) ); TRANSLATE('Combined Status: 0x%08X',eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e8f0019 SCID_SDC_BATT_BRICK_3_UPDATE_GOOD TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); CONDITIONAL(eip19.state.cur == eip19.state.old, TRANSLATE('State : %[scmi_battery_brick_state]', eip19.state.cur), TRANSLATE('State : %[scmi_battery_brick_state] --> %[scmi_battery_brick _state]', eip19.state.old, eip19.state.cur) ); CONDITIONAL(eip19.status_code.cur == eip19.status_code.old, TRANSLATE('Overall Status : %[scmi_battery_brick_status_code]', eip19.status_code.cur), TRANSLATE('Overall Status : %[scmi_battery_brick_status_code] --> %[scmi_battery _brick_status_code]', eip19.status_code.old, eip19.status_code.cur) ); TRANSLATE('Combined Status: 0x%08X',eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e90e019 SCID_SDC_BATT_BRICK_3_UPDATE_BAD TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); CONDITIONAL(eip19.state.cur == eip19.state.old, TRANSLATE('State : %[scmi_battery_brick_state]', eip19.state.cur), TRANSLATE('State : %[scmi_battery_brick_state] --> %[scmi_battery_brick _state]', eip19.state.old, eip19.state.cur) ); CONDITIONAL(eip19.status_code.cur == eip19.status_code.old, TRANSLATE('Overall Status : %[scmi_battery_brick_status_code]', eip19.status_code.cur), TRANSLATE('Overall Status : %[scmi_battery_brick_status_code] --> %[scmi_battery _brick_status_code]', eip19.status_code.old, eip19.status_code.cur) ); TRANSLATE('Combined Status: 0x%08X',eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e910019 SCID_SDC_BATT_SYS_COND_GOOD TRANSLATIONBLOCK TRANSLATE('Battery System Hold-up Time is greater than %d hours', eip19.status_code.cur); TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); TRANSLATE('State : %[scmi_nsc_battery_system_condition] --> %[scmi_nsc_ba ttery_system_condition]', eip19.state.old, eip19.state.cur); TRANSLATE('Hold-up time : %d --> %d (hours)',eip19.status_data.old, eip19.status_data.cur);

ENDTRANSLATIONBLOCK EC BLOCK: 0e920019 SCID_SDC_BATT_SYS_COND_LOW TRANSLATIONBLOCK TRANSLATE('Battery System Hold-up Time is greater than %d and less than %d hours ', eip19.status_code.old, eip19.status_code.cur); TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); TRANSLATE('State : %[scmi_nsc_battery_system_condition] --> %[scmi_nsc_ba ttery_system_condition]', eip19.state.old, eip19.state.cur); TRANSLATE('Hold-up time : %d --> %d (hours)',eip19.status_data.old, eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e93e519 SCID_SDC_BATT_SYS_COND_BAD TRANSLATIONBLOCK TRANSLATE('Battery System Hold-up Time is zero hours'); TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); TRANSLATE('State : %[scmi_nsc_battery_system_condition] --> %[scmi_nsc_ba ttery_system_condition]', eip19.state.old, eip19.state.cur); TRANSLATE('Hold-up time : %d --> %d (hours)',eip19.status_data.old, eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e940019 SCID_SDC_BLOW_SYS_BOOT_STATUS TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); TRANSLATE('Blower 0 State : %[scmi_fan_status]', eip19.comp_states[0]); TRANSLATE('Blower 0 Initial Status : 0x%X',eip19.comp_status_codes[0]); TRANSLATE('Blower 0 RPM : %d',eip19.comp_status_data[0]); TRANSLATE('Blower 1 State : %[scmi_fan_status]', eip19.comp_states[1]); TRANSLATE('Blower 1 Initial Status : 0x%X',eip19.comp_status_codes[1]); TRANSLATE('Blower 1 RPM : %d',eip19.comp_status_data[1]); ENDTRANSLATIONBLOCK EC BLOCK: 0e950019 SCID_SDC_BLOWER_0_INSERTED TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); TRANSLATE('State : %[scmi_fan_status]',eip19.state.cur); TRANSLATE('Status Code : 0x%X',eip19.status_code.cur); TRANSLATE('RPM : %d',eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e96e919 SCID_SDC_BLOWER_0_REMOVED TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); TRANSLATE('State : %[scmi_fan_status] --> %[scmi_fan_status]', eip19.state.old, eip19.state.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e970019 SCID_SDC_BLOWER_0_UPDATE_GOOD TRANSLATIONBLOCK

TRANSLATE('Controller TRANSLATE('State eip19.state.old, eip19.state.cur); TRANSLATE('Status Code TRANSLATE('RPM ENDTRANSLATIONBLOCK

: %[scmi_obj_hnd]', eip19.handle); : %[scmi_fan_status] --> %[scmi_fan_status]', : 0x%X',eip19.status_code.cur); : %d',eip19.status_data.cur);

EC BLOCK: 0e98e719 SCID_SDC_BLOWER_0_UPDATE_BAD TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); TRANSLATE('State : %[scmi_fan_status] --> %[scmi_fan_status]', eip19.state.old, eip19.state.cur); TRANSLATE('Status Code : 0x%X',eip19.status_code.cur); TRANSLATE('RPM : %d',eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e990019 SCID_SDC_BLOWER_1_INSERTED TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); TRANSLATE('State : %[scmi_fan_status]',eip19.state.cur); TRANSLATE('Status Code : 0x%X',eip19.status_code.cur); TRANSLATE('RPM : %d',eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e9aea19 SCID_SDC_BLOWER_1_REMOVED TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); TRANSLATE('State : %[scmi_fan_status] --> %[scmi_fan_status]', eip19.state.old, eip19.state.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e9b0019 SCID_SDC_BLOWER_1_UPDATE_GOOD TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); TRANSLATE('State : %[scmi_fan_status] --> %[scmi_fan_status]', eip19.state.old, eip19.state.cur); TRANSLATE('Status Code : 0x%X',eip19.status_code.cur); TRANSLATE('RPM : %d',eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e9ce819 SCID_SDC_BLOWER_1_UPDATE_BAD TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); TRANSLATE('State : %[scmi_fan_status] --> %[scmi_fan_status]', eip19.state.old, eip19.state.cur); TRANSLATE('Status Code : 0x%X',eip19.status_code.cur); TRANSLATE('RPM : %d',eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e9def19 SCID_SDC_BATT_MEMORY_READ_FAILURE TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); TRANSLATE('Battery Brick Number : %d',eip19.status_data.cur); ENDTRANSLATIONBLOCK

EC BLOCK: 0e9e0019 SCID_SDC_TEMP_SYS_BOOT_STATUS TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); TRANSLATE('State : %[scmi_temp_system_state]',eip19.state.cur); TRANSLATE('Sensor 1 : %d C',eip19.comp_status_data[0]); TRANSLATE('Sensor 2 : %d C',eip19.comp_status_data[1]); TRANSLATE('Sensor 3 : %d C',eip19.comp_status_data[2]); TRANSLATE('Sensor Avg : %d C',eip19.comp_status_data[3]); TRANSLATE('Trip Temp. : %d C',eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0e9f0019 SCID_SDC_TEMP_NORMAL TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); TRANSLATE('State : %[scmi_temp_system_state] --> %[scmi_temp_system_state] ', eip19.state.old, eip19.state.cur); TRANSLATE('Sensor 1 : %d C',eip19.comp_status_data[0]); TRANSLATE('Sensor 2 : %d C',eip19.comp_status_data[1]); TRANSLATE('Sensor 3 : %d C',eip19.comp_status_data[2]); TRANSLATE('Sensor Avg : %d C',eip19.comp_status_data[3]); TRANSLATE('Trip Temp. : %d C',eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0ea02e19 SCID_SDC_TEMP_CLOSE_TO_TEMP_TRIP TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); TRANSLATE('State : %[scmi_temp_system_state] --> %[scmi_temp_system_state] ', eip19.state.old, eip19.state.cur); TRANSLATE('Sensor 1 : %d C',eip19.comp_status_data[0]); TRANSLATE('Sensor 2 : %d C',eip19.comp_status_data[1]); TRANSLATE('Sensor 3 : %d C',eip19.comp_status_data[2]); TRANSLATE('Sensor Avg : %d C',eip19.comp_status_data[3]); TRANSLATE('Trip Temp. : %d C',eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0ea13619 SCID_SDC_TEMP_OVER_TEMP TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); TRANSLATE('State : %[scmi_temp_system_state] --> %[scmi_temp_system_state] ', eip19.state.old, eip19.state.cur); TRANSLATE('Sensor 1 : %d C',eip19.comp_status_data[0]); TRANSLATE('Sensor 2 : %d C',eip19.comp_status_data[1]); TRANSLATE('Sensor 3 : %d C',eip19.comp_status_data[2]); TRANSLATE('Sensor Avg : %d C',eip19.comp_status_data[3]); TRANSLATE('Trip Temp. : %d C',eip19.status_data.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0ea20019 SCID_SDC_PWR_SUPPLY_BOOT_STATUS TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); TRANSLATE('Power Supply 0 State : %[scmi_power_supply_state]', eip19.comp_states[0]); TRANSLATE('Power Supply 1 State : %[scmi_power_supply_state]', eip19.comp_states[1]);

ENDTRANSLATIONBLOCK EC BLOCK: 0ea30019 SCID_SDC_PWR_SUPPLY_0_INSERTED TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); TRANSLATE('State : %[scmi_power_supply_state]',eip19.state.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0ea4ed19 SCID_SDC_PWR_SUPPLY_0_REMOVED TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); TRANSLATE('State : %[scmi_power_supply_state] --> %[scmi_power_supply_state ]', eip19.state.old, eip19.state.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0ea50019 SCID_SDC_PWR_SUPPLY_0_UPDATE_GOOD TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); TRANSLATE('State : %[scmi_power_supply_state] --> %[scmi_power_supply_state ]', eip19.state.old, eip19.state.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0ea6eb19 SCID_SDC_PWR_SUPPLY_0_UPDATE_BAD TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); TRANSLATE('State : %[scmi_power_supply_state] --> %[scmi_power_supply_state ]', eip19.state.old, eip19.state.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0ea70019 SCID_SDC_PWR_SUPPLY_1_INSERTED TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); TRANSLATE('State : %[scmi_power_supply_state]',eip19.state.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0ea8ee19 SCID_SDC_PWR_SUPPLY_1_REMOVED TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); TRANSLATE('State : %[scmi_power_supply_state] --> %[scmi_power_supply_state ]', eip19.state.old, eip19.state.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0ea90019 SCID_SDC_PWR_SUPPLY_1_UPDATE_GOOD TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); TRANSLATE('State : %[scmi_power_supply_state] --> %[scmi_power_supply_state ]', eip19.state.old, eip19.state.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0eaaec19 SCID_SDC_PWR_SUPPLY_1_UPDATE_BAD

TRANSLATIONBLOCK TRANSLATE('Controller : %[scmi_obj_hnd]', eip19.handle); TRANSLATE('State : %[scmi_power_supply_state] --> %[scmi_power_supply_state ]', eip19.state.old, eip19.state.cur); ENDTRANSLATIONBLOCK EC BLOCK: 0f004a08 SCID_MIRROR_LINK_FAILURE TRANSLATIONBLOCK TRANSLATE('Port ID: %s', eip08.cerp_id); TRANSLATE('Failure cause: %[mirror_fcs_fail]', eip08.failure_cause); TRANSLATE('Producer index: 0x%04x', eip08.peq_prod_index); TRANSLATE('Consumer index: 0x%04x', eip08.peq_cons_index); TRANSLATE('Frozen index: 0x%04x', eip08.peq_frz_prod_index); TRANSLATE('Port event block(s):'); CONDITIONAL( eip08.peb[0].type != 0, TRANSLATE( ' [0] Type: %08X Context: %08X', eip08.peb[0].type, eip08.peb[0].context ) ); CONDITIONAL( eip08.peb[1].type != 0, TRANSLATE( ' [1] Type: %08X Context: %08X', eip08.peb[1].type, eip08.peb[1].context ) ); CONDITIONAL( eip08.peb[2].type != 0, TRANSLATE( ' [2] Type: %08X Context: %08X', eip08.peb[2].type, eip08.peb[2].context ) ); CONDITIONAL( eip08.peb[3].type != 0, TRANSLATE( ' [3] Type: %08X Context: %08X', eip08.peb[3].type, eip08.peb[3].context ) ); CONDITIONAL( eip08.peb[4].type != 0, TRANSLATE( ' [4] Type: %08X Context: %08X', eip08.peb[4].type, eip08.peb[4].context ) ); CONDITIONAL( eip08.peb[5].type != 0, TRANSLATE( ' [5] Type: %08X Context: %08X', eip08.peb[5].type, eip08.peb[5].context ) ); CONDITIONAL( eip08.peb[6].type != 0, TRANSLATE(

' [6] Type: %08X Context: %08X', eip08.peb[6].type, eip08.peb[6].context ) ); CONDITIONAL( eip08.peb[7].type != 0, TRANSLATE( ' [7] Type: %08X Context: %08X', eip08.peb[7].type, eip08.peb[7].context ) ); TRANSLATE('Retry Timer: %d seconds', eip08.time ); ENDTRANSLATIONBLOCK EC BLOCK: 0f010007 SCID_MIRROR_LINK_ERRORS TRANSLATIONBLOCK TRANSLATE('Port ID: %s', eip07.cerp_id); TRANSLATE('Non-zero error counts:'); CONDITIONAL( eip07.loss_of_signal != 0, TRANSLATE('Loss of signal: %d.', eip07.loss_of_signal) ); CONDITIONAL( eip07.bad_rx_char != 0, TRANSLATE('Bad RX character: %d.', eip07.bad_rx_char) ); CONDITIONAL( eip07.loss_of_sync != 0, TRANSLATE('Loss of synch: %d.', eip07.loss_of_sync) ); CONDITIONAL( eip07.link_fail != 0, TRANSLATE('Link failure: %d.', eip07.link_fail) ); CONDITIONAL( eip07.rx_eofa != 0, TRANSLATE('RX EOFa delimiter: %d.', eip07.rx_eofa) ); CONDITIONAL( eip07.dis_frm != 0, TRANSLATE('Discarded frame: %d.', eip07.dis_frm) ); CONDITIONAL( eip07.bad_crc != 0, TRANSLATE('Frames with bad CRC and valid EOF: %d.', eip07.bad_crc) ); CONDITIONAL( eip07.proto_err != 0, TRANSLATE('N_Port protocol error: %d.', eip07.proto_err) ); CONDITIONAL( eip07.exp_frm != 0, TRANSLATE('Expired outbound frame: %d.', eip07.exp_frm) ); ENDTRANSLATIONBLOCK EC BLOCK: 0f020013 SCID_MIRROR_ENABLE_MP TRANSLATIONBLOCK TRANSLATE('Port ID: %s', eip13.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 0f034709 SCID_MIRROR_NONDATA_EXCH_TIMEOUT TRANSLATIONBLOCK TRANSLATE('mirror port: %[tag]', eip09.device); TRANSLATE('Port ID: %s', eip09.cerp_id); TRANSLATE('AL_PA: 0x%04x', eip09.al_pa); TRANSLATE('%s', XLATE_EIP09_OPCODE( eip09.fed_class,

eip09.cmd.cdb10.opcode ) ); ENDTRANSLATIONBLOCK EC BLOCK: 0f040009 SCID_MIRROR_RRQ TRANSLATIONBLOCK TRANSLATE('Intended target: %[tag]', eip09.device); TRANSLATE('Port ID: %s', eip09.cerp_id); TRANSLATE('AL_PA: 0x%04x', eip09.al_pa); TRANSLATE('%s', XLATE_EIP09_OPCODE( eip09.fed_class, eip09.cmd.cdb10.opcode ) ); ENDTRANSLATIONBLOCK EC BLOCK: 0f050009 SCID_MIRROR_ABORT TRANSLATIONBLOCK TRANSLATE('Intended target: %[tag]', eip09.device); TRANSLATE('Port ID: %s', eip09.cerp_id); TRANSLATE('AL_PA: 0x%04x', eip09.al_pa); TRANSLATE('%s', XLATE_EIP09_OPCODE( eip09.fed_class, eip09.cmd.cdb10.opcode ) ); ENDTRANSLATIONBLOCK EC BLOCK: 0f060024 SCID_MIRROR_TRANSPORT_STATUS TRANSLATIONBLOCK CONDITIONAL(eip24.data[0] == 0, TRANSLATE('Old Status: Default') ); CONDITIONAL(eip24.data[0] == 1, TRANSLATE('Old Status: Initialized') ); CONDITIONAL(eip24.data[0] == 2, TRANSLATE('Old Status: Hardware Link') ); CONDITIONAL(eip24.data[0] == 3, TRANSLATE('Old Status: SYNC1 Received') ); CONDITIONAL(eip24.data[0] == 4, TRANSLATE('Old Status: Link Transition') ); CONDITIONAL(eip24.data[0] == 5, TRANSLATE('Old Status: SYNC2 Received') ); CONDITIONAL(eip24.data[0] == 6, TRANSLATE('Old Status: Link Up') ); CONDITIONAL(eip24.data[0] == 7, TRANSLATE('Old Status: Breaking') ); CONDITIONAL(eip24.data[0] == 8, TRANSLATE('Old Status: Down') ); CONDITIONAL(eip24.data[0] == 9, TRANSLATE('Old Status: Disabled')

); CONDITIONAL(eip24.data[0] == 10, TRANSLATE('Old Status: Other Disabled') ); CONDITIONAL(eip24.data[1] == 0, TRANSLATE('New Status: Default') ); CONDITIONAL(eip24.data[1] == 1, TRANSLATE('New Status: Initialized') ); CONDITIONAL(eip24.data[1] == 2, TRANSLATE('New Status: Hardware Link') ); CONDITIONAL(eip24.data[1] == 3, TRANSLATE('New Status: SYNC1 Received') ); CONDITIONAL(eip24.data[1] == 4, TRANSLATE('New Status: Link Transition') ); CONDITIONAL(eip24.data[1] == 5, TRANSLATE('New Status: SYNC2 Received') ); CONDITIONAL(eip24.data[1] == 6, TRANSLATE('New Status: Link Up') ); CONDITIONAL(eip24.data[1] == 7, TRANSLATE('New Status: Breaking') ); CONDITIONAL(eip24.data[1] == 8, TRANSLATE('New Status: Down') ); CONDITIONAL(eip24.data[1] == 9, TRANSLATE('New Status: Disabled') ); CONDITIONAL(eip24.data[1] == 10, TRANSLATE('New Status: Other Disabled') ); CONDITIONAL(eip24.data[2] == 0, TRANSLATE('Transport Type: Invalid') ); CONDITIONAL(eip24.data[2] == 1, TRANSLATE('Transport Type: Fibre Channel') ); CONDITIONAL(eip24.data[2] == 2, TRANSLATE('Transport Type: PCIe') ); CONDITIONAL(eip24.data[2] == 3, TRANSLATE('Transport Type: SAS') ); CONDITIONAL(eip24.data[3] == 0, TRANSLATE('Primary Transport Type: Invalid') ); CONDITIONAL(eip24.data[3] == 1, TRANSLATE('Primary Transport Type: Fibre Channel') ); CONDITIONAL(eip24.data[3] == 2, TRANSLATE('Primary Transport Type: PCIe') ); CONDITIONAL(eip24.data[3] == 3, TRANSLATE('Primary Transport Type: SAS')

); TRANSLATE('pc: %08x', eip24.data[4]); ENDTRANSLATIONBLOCK EC BLOCK: 0f070724 SCID_MIRROR_INVALID_STATUS_CHANGE TRANSLATIONBLOCK CONDITIONAL(eip24.data[0] == 0, TRANSLATE('Old Status: Default') ); CONDITIONAL(eip24.data[0] == 1, TRANSLATE('Old Status: Initialized') ); CONDITIONAL(eip24.data[0] == 2, TRANSLATE('Old Status: Hardware Link') ); CONDITIONAL(eip24.data[0] == 3, TRANSLATE('Old Status: SYNC1 Received') ); CONDITIONAL(eip24.data[0] == 4, TRANSLATE('Old Status: Link Transition') ); CONDITIONAL(eip24.data[0] == 5, TRANSLATE('Old Status: SYNC2 Received') ); CONDITIONAL(eip24.data[0] == 6, TRANSLATE('Old Status: Link Up') ); CONDITIONAL(eip24.data[0] == 7, TRANSLATE('Old Status: Breaking') ); CONDITIONAL(eip24.data[0] == 8, TRANSLATE('Old Status: Down') ); CONDITIONAL(eip24.data[0] == 9, TRANSLATE('Old Status: Disabled') ); CONDITIONAL(eip24.data[0] == 10, TRANSLATE('Old Status: Other Disabled') ); CONDITIONAL(eip24.data[1] == 0, TRANSLATE('New Status: Default') ); CONDITIONAL(eip24.data[1] == 1, TRANSLATE('New Status: Initialized') ); CONDITIONAL(eip24.data[1] == 2, TRANSLATE('New Status: Hardware Link') ); CONDITIONAL(eip24.data[1] == 3, TRANSLATE('New Status: SYNC1 Received') ); CONDITIONAL(eip24.data[1] == 4, TRANSLATE('New Status: Link Transition') ); CONDITIONAL(eip24.data[1] == 5, TRANSLATE('New Status: SYNC2 Received') ); CONDITIONAL(eip24.data[1] == 6, TRANSLATE('New Status: Link Up') );

CONDITIONAL(eip24.data[1] == 7, TRANSLATE('New Status: Breaking') ); CONDITIONAL(eip24.data[1] == 8, TRANSLATE('New Status: Down') ); CONDITIONAL(eip24.data[1] == 9, TRANSLATE('New Status: Disabled') ); CONDITIONAL(eip24.data[1] == 10, TRANSLATE('New Status: Other Disabled') ); CONDITIONAL(eip24.data[2] == 0, TRANSLATE('Transport Type: Invalid') ); CONDITIONAL(eip24.data[2] == 1, TRANSLATE('Transport Type: Fibre Channel') ); CONDITIONAL(eip24.data[2] == 2, TRANSLATE('Transport Type: PCIe') ); CONDITIONAL(eip24.data[2] == 3, TRANSLATE('Transport Type: SAS') ); CONDITIONAL(eip24.data[3] == 0, TRANSLATE('Primary Transport Type: Invalid') ); CONDITIONAL(eip24.data[3] == 1, TRANSLATE('Primary Transport Type: Fibre Channel') ); CONDITIONAL(eip24.data[3] == 2, TRANSLATE('Primary Transport Type: PCIe') ); CONDITIONAL(eip24.data[3] == 3, TRANSLATE('Primary Transport Type: SAS') ); TRANSLATE('pc: %08x', eip24.data[4]); ENDTRANSLATIONBLOCK EC BLOCK: 42000008 SCID_HP_FC_LINK_DOWN TRANSLATIONBLOCK TRANSLATE('Port ID: %s', eip08.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 42010008 SCID_HP_FC_LINK_FAILED TRANSLATIONBLOCK TRANSLATE('Port ID: %s', eip08.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 42020008 SCID_HP_FC_LINK_UP TRANSLATIONBLOCK TRANSLATE('Port ID: %s', eip08.cerp_id); CONDITIONAL( eip08.reserved1 == 0, TRANSLATE(', as N_PORT') ); CONDITIONAL( eip08.reserved1 == 1, TRANSLATE(', as NL_PORT') ); ENDTRANSLATIONBLOCK EC BLOCK: 42030007 SCID_HP_LINK_ERRORS TRANSLATIONBLOCK TRANSLATE('Port ID: %s', eip07.cerp_id); CONDITIONAL( eip07.loss_of_signal != 0,

TRANSLATE('Loss of signal: %d.', eip07.loss_of_signal) ); CONDITIONAL( eip07.bad_rx_char != 0, TRANSLATE('Bad RX characters: %d.', eip07.bad_rx_char) ); CONDITIONAL( eip07.loss_of_sync != 0, TRANSLATE('Loss of synchs: %d.', eip07.loss_of_sync) ); CONDITIONAL( eip07.link_fail != 0, TRANSLATE('Link failures: %d.', eip07.link_fail) ); CONDITIONAL( eip07.rx_eofa != 0, TRANSLATE('RX EOFa delimiters: %d.', eip07.rx_eofa) ); CONDITIONAL( eip07.dis_frm != 0, TRANSLATE('Discarded frames: %d.', eip07.dis_frm) ); CONDITIONAL( eip07.bad_crc != 0, TRANSLATE('Frames with bad CRC and valid EOF: %d.', eip07.bad_crc) ); CONDITIONAL( eip07.proto_err != 0, TRANSLATE('N_Port protocol errors: %d.', eip07.proto_err) ); CONDITIONAL( eip07.exp_frm != 0, TRANSLATE('Expired outbound frames: %d.', eip07.exp_frm) ); ENDTRANSLATIONBLOCK EC BLOCK: 42044a08 SCID_HP_LINK_FAILURE TRANSLATIONBLOCK TRANSLATE('Port ID: %s', eip08.cerp_id); TRANSLATE('Producer index: %04X', eip08.peq_prod_index); TRANSLATE('Consumer index: %04X', eip08.peq_cons_index); TRANSLATE('Frozen index: %04X', eip08.peq_frz_prod_index); TRANSLATE('Port event block(s):'); CONDITIONAL( eip08.peb[0].type != 0, TRANSLATE( ' [0] Type: %08X Context: %08X', eip08.peb[0].type, eip08.peb[0].context ) ); CONDITIONAL( eip08.peb[1].type != 0, TRANSLATE( ' [1] Type: %08X Context: %08X', eip08.peb[1].type, eip08.peb[1].context ) ); CONDITIONAL( eip08.peb[2].type != 0, TRANSLATE( ' [2] Type: %08X Context: %08X', eip08.peb[2].type, eip08.peb[2].context ) ); CONDITIONAL( eip08.peb[3].type != 0, TRANSLATE( ' [3] Type: %08X Context: %08X', eip08.peb[3].type,

eip08.peb[3].context ) ); CONDITIONAL( eip08.peb[4].type != TRANSLATE( ' [4] Type: %08X Context: %08X', eip08.peb[4].type, eip08.peb[4].context ) ); CONDITIONAL( eip08.peb[5].type != TRANSLATE( ' [5] Type: %08X Context: %08X', eip08.peb[5].type, eip08.peb[5].context ) ); CONDITIONAL( eip08.peb[6].type != TRANSLATE( ' [6] Type: %08X Context: %08X', eip08.peb[6].type, eip08.peb[6].context ) ); CONDITIONAL( eip08.peb[7].type != TRANSLATE( ' [7] Type: %08X Context: %08X', eip08.peb[7].type, eip08.peb[7].context ) ); ENDTRANSLATIONBLOCK

0,

0,

0,

0,

EC BLOCK: 42050008 SCID_HP_FC_LINK_WEDGED TRANSLATIONBLOCK TRANSLATE('Port ID: %s', eip08.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 4206001b SCID_HP_UNIT_STALLED_TOO_LONG TRANSLATIONBLOCK TRANSLATE('Virtual Disk: %[tag]', eip1B.scvd_tag); TRANSLATE('LUN WWID: %[tag]', eip1B.lun_wwid); TRANSLATE('Pending Quiesces: %d', eip1B.pending); TRANSLATE('Pending Deferred Quiesces: %d', eip1B.deferred); TRANSLATE('Pending Host Quiesces: %d', eip1B.host); TRANSLATE('Active IO: %d', eip1B.active); TRANSLATE('Inactive IO: %d', eip1B.inactive); TRANSLATE('Suspended IO: %d', eip1B.suspended); TRANSLATE('VDSB Flags: %08X', eip1B.vdsb_flags); CONDITIONAL(eip1B.presented_this == 1, TRANSLATE('VDSB Presented THIS')); CONDITIONAL(eip1B.presented_other == 1, TRANSLATE('VDSB Presented OTHER')); CONDITIONAL(eip1B.group != 0, TRANSLATE('DRM Group %08X', eip1B.group)); CONDITIONAL(eip1B.group != 0, TRANSLATE('DRM IO: %d', eip1B.drmio)); CONDITIONAL(eip1B.group != 0, TRANSLATE('DRM CM Flushing: %d', eip1B.drmcmflushing)); CONDITIONAL(eip1B.group != 0,

TRANSLATE('DRM CM prefetching: %d', eip1B.drmcmprefetch)); ENDTRANSLATIONBLOCK EC BLOCK: 42080008 SCID_HP_FREEZE_TACH TRANSLATIONBLOCK TRANSLATE('Port ID: %s', eip08.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 42090008 SCID_HP_SOFT_RESET_TACH TRANSLATIONBLOCK TRANSLATE('Port ID: %s', eip08.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 420a001b SCID_HP_UNIT_STALLED_TOO_LONG_EXIT TRANSLATIONBLOCK TRANSLATE('Virtual Disk: %[tag]', eip1B.scvd_tag); ENDTRANSLATIONBLOCK EC BLOCK: 420b001b SCID_HP_LU_TRANSITION_DONE TRANSLATIONBLOCK TRANSLATE('Virtual Disk: %[tag]', eip1B.scvd_tag); ENDTRANSLATIONBLOCK EC BLOCK: 420c001b SCID_HP_LU_TRANSITION_FAILURE TRANSLATIONBLOCK TRANSLATE('Virtual Disk: %[tag]', eip1B.scvd_tag); ENDTRANSLATIONBLOCK EC BLOCK: 420e0024 SCID_HP_INFO TRANSLATIONBLOCK CONDITIONAL( eip24.data[0] == 42, TRANSLATE( 'IMQ CM consumptions forced after resync on FP%d. !', eip24.data[1]) ); CONDITIONAL( eip24.data[0] == 43, TRANSLATE( 'FP%d. Direct Connect misconfigured, goes link up to switch FL_Port !', eip24.data[1]) ); CONDITIONAL( eip24.data[0] == 44, TRANSLATE( 'FP%d. transitioned from ACTIVE TO LR1 or LR2 (link down) from LCR', eip24.data[1]) ); CONDITIONAL( eip24.data[0] == 45, TRANSLATE( 'FP%d. transitioned to ACTIVE in PSM (link up) from LCR', eip24.data[1]) ); CONDITIONAL( eip24.data[0] == 46, TRANSLATE( 'FP%d. FM transitioned to ERR IDLE, LPSM bits are OFFLINE', eip24.data[1]) );

CONDITIONAL( eip24.data[0] == 47, TRANSLATE( 'FP%d. LPSM in OFFLINE, SNENG=1: run next hp_once_a_second, HP_pi1', eip24.data[1]) ); CONDITIONAL( eip24.data[0] == 48, TRANSLATE('HP_FLT_XX executing, context parms:'), TRANSLATE('EP[1.]: %08X', eip24.data[1]), TRANSLATE('EP[2.]: %08X', eip24.data[2]), TRANSLATE('EP[3.]: %08X', eip24.data[3]), TRANSLATE('EP[4.]: %08X', eip24.data[4]) ); ENDTRANSLATIONBLOCK EC BLOCK: 420f0008 SCID_HP_FC_CLEAR_CREDIT_ERR TRANSLATIONBLOCK TRANSLATE('Port ID: %s', eip08.cerp_id); ENDTRANSLATIONBLOCK EC BLOCK: 42100008 SCID_HP_NS_REGISTRATION_DONE TRANSLATIONBLOCK TRANSLATE('Port ID: %s', eip08.cerp_id); CONDITIONAL(eip08.failure_cause == 1, TRANSLATE(' successfully.')); CONDITIONAL(eip08.failure_cause != 1 , TRANSLATE(' with error %d.', eip08.failure_cause)); ENDTRANSLATIONBLOCK EC BLOCK: 83002014 SCID_DOG_FAILURE TRANSLATIONBLOCK CONDITIONAL( eip14.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Test Element: %d.', eip14.eep_error.TE_num); CONDITIONAL(eip14.eep_error.TE_num == 0, TRANSLATE('(Error reporting for pre-MIST tests)') ); CONDITIONAL(eip14.eep_error.TE_num == 2, TRANSLATE('(HW code check and Operator Control Panel setup)') ); CONDITIONAL(eip14.eep_error.TE_num == 7, TRANSLATE('(Cache Memory test)') ); CONDITIONAL(eip14.eep_error.TE_num == 12, TRANSLATE('(Port 0 test)') ); CONDITIONAL(eip14.eep_error.TE_num == 13, TRANSLATE('(Port 1 test)') ); CONDITIONAL(eip14.eep_error.TE_num == 14, TRANSLATE('(Port 2 test)') ); CONDITIONAL(eip14.eep_error.TE_num == 15, TRANSLATE('(Port 3 test)') );

CONDITIONAL(eip14.eep_error.TE_num == 16, TRANSLATE('(Port 4 test)') ); CONDITIONAL(eip14.eep_error.TE_num == 17, TRANSLATE('(Port 5 test)') ); CONDITIONAL(eip14.eep_error.TE_num == 18, TRANSLATE('(Port 6 test)') ); CONDITIONAL(eip14.eep_error.TE_num == 19, TRANSLATE('(Port 7 test)') ); CONDITIONAL(eip14.eep_error.TE_num == 20, TRANSLATE('(Port 8 test)') ); CONDITIONAL(eip14.eep_error.TE_num == 21, TRANSLATE('(Port 9 test)') ); CONDITIONAL(eip14.eep_error.TE_num == 22, TRANSLATE('(All Ports test)') ); CONDITIONAL(eip14.eep_error.TE_num == 23, TRANSLATE('(Port-to-Port test)') ); CONDITIONAL(eip14.eep_error.TE_num == 24, TRANSLATE('(Config and Init Port regs)') ); CONDITIONAL(eip14.eep_error.TE_num == 28, TRANSLATE('(SDC test)') ); CONDITIONAL(eip14.eep_error.TE_num == 31, TRANSLATE('(Hardware Revision test)') ); TRANSLATE('Test number: %d.', eip14.eep_error.test_num); TRANSLATE('Duplicate error count: %d.', eip14.eep_error.count); TRANSLATE('Error code: %08X', eip14.eep_error.error_code); TRANSLATE('Address of error: %08X', eip14.eep_error.address); TRANSLATE('Expected data: %08X', eip14.eep_error.expected); TRANSLATE('Actual data: %08X', eip14.eep_error.actual); TRANSLATE( 'Controller uptime of failure: %y.', eip14.eep_error.uptime ); TRANSLATE('Policy memory size: %d MB', eip14.dimm_size ); ENDTRANSLATIONBLOCK EC BLOCK: 83013014 SCID_DOG_FAILURE_GBIC TRANSLATIONBLOCK CONDITIONAL( eip14.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Test Element: %d.', eip14.eep_error.TE_num); CONDITIONAL(eip14.eep_error.TE_num == 12, TRANSLATE('(Port 0 test)') ); CONDITIONAL(eip14.eep_error.TE_num == 13, TRANSLATE('(Port 1 test)')

); CONDITIONAL(eip14.eep_error.TE_num == 14, TRANSLATE('(Port 2 test)') ); CONDITIONAL(eip14.eep_error.TE_num == 15, TRANSLATE('(Port 3 test)') ); CONDITIONAL(eip14.eep_error.TE_num == 16, TRANSLATE('(Port 4 test)') ); CONDITIONAL(eip14.eep_error.TE_num == 17, TRANSLATE('(Port 5 test)') ); CONDITIONAL(eip14.eep_error.TE_num == 18, TRANSLATE('(Port 6 test)') ); CONDITIONAL(eip14.eep_error.TE_num == 19, TRANSLATE('(Port 7 test)') ); CONDITIONAL(eip14.eep_error.TE_num == 20, TRANSLATE('(Port 8 test)') ); CONDITIONAL(eip14.eep_error.TE_num == 21, TRANSLATE('(Port 9 test)') ); TRANSLATE('Test number: %d.', eip14.eep_error.test_num); TRANSLATE('Duplicate error count: %d.', eip14.eep_error.count); TRANSLATE('Error code: %08X', eip14.eep_error.error_code); TRANSLATE('Address of error: %08X', eip14.eep_error.address); TRANSLATE('Expected data: %08X', eip14.eep_error.expected); TRANSLATE('Actual data: %08X', eip14.eep_error.actual); TRANSLATE( 'Controller uptime of failure: %y.', eip14.eep_error.uptime ); TRANSLATE('Policy memory size: %d MB', eip14.dimm_size ); ENDTRANSLATIONBLOCK EC BLOCK: 83073a14 SCID_DOG_FAILURE_GBIC_MISSING TRANSLATIONBLOCK CONDITIONAL( eip14.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Test Element: %d.', eip14.eep_error.TE_num); CONDITIONAL(eip14.eep_error.TE_num == 12, TRANSLATE('(Port 0 test)') ); CONDITIONAL(eip14.eep_error.TE_num == 13, TRANSLATE('(Port 1 test)') ); CONDITIONAL(eip14.eep_error.TE_num == 14, TRANSLATE('(Port 2 test)') ); CONDITIONAL(eip14.eep_error.TE_num == 15, TRANSLATE('(Port 3 test)') ); CONDITIONAL(eip14.eep_error.TE_num == 16,

TRANSLATE('(Port 4 test)') ); CONDITIONAL(eip14.eep_error.TE_num == 17, TRANSLATE('(Port 5 test)') ); CONDITIONAL(eip14.eep_error.TE_num == 18, TRANSLATE('(Port 6 test)') ); CONDITIONAL(eip14.eep_error.TE_num == 19, TRANSLATE('(Port 7 test)') ); CONDITIONAL(eip14.eep_error.TE_num == 20, TRANSLATE('(Port 8 test)') ); CONDITIONAL(eip14.eep_error.TE_num == 21, TRANSLATE('(Port 9 test)') ); TRANSLATE('Test number: %d.', eip14.eep_error.test_num); TRANSLATE('Duplicate error count: %d.', eip14.eep_error.count); TRANSLATE('Error code: %08X', eip14.eep_error.error_code); TRANSLATE('Address of error: %08X', eip14.eep_error.address); TRANSLATE('Expected data: %08X', eip14.eep_error.expected); TRANSLATE('Actual data: %08X', eip14.eep_error.actual); TRANSLATE( 'Controller uptime of failure: %y.', eip14.eep_error.uptime ); TRANSLATE('Policy memory size: %d MB', eip14.dimm_size ); ENDTRANSLATIONBLOCK EC BLOCK: 83083b14 SCID_DOG_SRAM_TEST_ERROR TRANSLATIONBLOCK CONDITIONAL( eip14.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Test Element: %d.', eip14.eep_error.TE_num); TRANSLATE('Test number: %d.', eip14.eep_error.test_num); TRANSLATE('Duplicate error count: %d.', eip14.eep_error.count); TRANSLATE('Error code: %08X', eip14.eep_error.error_code); TRANSLATE('Address of error: %08X', eip14.eep_error.address); TRANSLATE('Expected data: %08X', eip14.eep_error.expected); TRANSLATE('Actual data: %08X', eip14.eep_error.actual); TRANSLATE( 'Controller uptime of failure: %y.', eip14.eep_error.uptime ); TRANSLATE('Policy memory size: %d MB', eip14.dimm_size ); ENDTRANSLATIONBLOCK EC BLOCK: 83093b14 SCID_DOG_SRAM_PARITY_ERROR TRANSLATIONBLOCK CONDITIONAL( eip14.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) );

TRANSLATE('Test Element: %d.', eip14.eep_error.TE_num); TRANSLATE('Test number: %d.', eip14.eep_error.test_num); TRANSLATE('Duplicate error count: %d.', eip14.eep_error.count); TRANSLATE('Error code: %08X', eip14.eep_error.error_code); TRANSLATE('Address of error: %08X', eip14.eep_error.address); TRANSLATE('Expected data: %08X', eip14.eep_error.expected); TRANSLATE('Actual data: %08X', eip14.eep_error.actual); TRANSLATE( 'Controller uptime of failure: %y.', eip14.eep_error.uptime ); TRANSLATE('Policy memory size: %d MB', eip14.dimm_size ); ENDTRANSLATIONBLOCK EC BLOCK: 830b0026 SCID_DOG_ECC_CACHE_DAILY_COUNT_ERROR TRANSLATIONBLOCK TRANSLATE('Policy memory size: %d MB', eip26.ecc_cnt.policy_mem_size); TRANSLATE('Cache memory size: %d MB', eip26.ecc_cnt.cache_mem_size); TRANSLATE('Cache ECC error count: %d', eip26.ecc_cnt.ecc_count); TRANSLATE('Previous ECC error count: %d', eip26.ecc_cnt.ecc_previous_count); TRANSLATE('Time since last reset: %d secs', eip26.ecc_cnt.time_since_reset); ENDTRANSLATIONBLOCK EC BLOCK: 830c0026 SCID_DOG_ECC_POLICY_DAILY_COUNT_ERROR TRANSLATIONBLOCK TRANSLATE('Policy memory size: %d MB', eip26.ecc_cnt.policy_mem_size); TRANSLATE('Cache memory size: %d MB', eip26.ecc_cnt.cache_mem_size); TRANSLATE('Policy ECC error count: %d', eip26.ecc_cnt.ecc_count); TRANSLATE('Previous ECC error count: %d', eip26.ecc_cnt.ecc_previous_count); TRANSLATE('Time since last ECC counters reset: %d secs', eip26.ecc_cnt.time_since_reset); ENDTRANSLATIONBLOCK EC BLOCK: 830d0026 SCID_DOG_ECC_CACHE_WEEKLY_COUNT_ERROR TRANSLATIONBLOCK TRANSLATE('Policy memory size: %d MB', eip26.ecc_cnt.policy_mem_size); TRANSLATE('Cache memory size: %d MB', eip26.ecc_cnt.cache_mem_size); TRANSLATE('Cache ECC error count: %d', eip26.ecc_cnt.ecc_count); TRANSLATE('Previous ECC error count: %d', eip26.ecc_cnt.ecc_previous_count); TRANSLATE('Time since last ECC counters reset: %d secs', eip26.ecc_cnt.time_since_reset); ENDTRANSLATIONBLOCK EC BLOCK: 830e0026 SCID_DOG_ECC_POLICY_WEEKLY_COUNT_ERROR TRANSLATIONBLOCK TRANSLATE('Policy memory size: %d MB', eip26.ecc_cnt.policy_mem_size);

TRANSLATE('Cache memory size: %d MB', eip26.ecc_cnt.cache_mem_size); TRANSLATE('Policy ECC error count: %d', eip26.ecc_cnt.ecc_count); TRANSLATE('Previous ECC error count: %d', eip26.ecc_cnt.ecc_previous_count); TRANSLATE('Time since last ECC counters reset: %d secs', eip26.ecc_cnt.time_since_reset); ENDTRANSLATIONBLOCK TERMINATION CODE TRANSLATION BLOCKS: TC BLOCK: 0101011f SCID_EXEC_FLT_UNKNOWN TRANSLATIONBLOCK TRANSLATE('TC [llistefc]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]);

TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0102011f SCID_EXEC_FLT_DLQ_ENTRY_CHECK TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]);

TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0103011f SCID_EXEC_FLT_TIMER_NOT_EXPIRED TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]);

TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0104011f SCID_EXEC_FLT_NOT_A_TIMER TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]);

TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0105011f SCID_EXEC_FLT_DLQ_LINKS_NOT_ZERO TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]);

TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0106011f SCID_EXEC_FLT_DLQ_HEAD_CHECK TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7]

); ); ); ); ); ); ); );

TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0107011f SCID_EXEC_FLT_SQ_LINK_NOT_ZERO TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]

); ); ); ); );

TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0108011f SCID_EXEC_FLT_NOT_A_BQUE TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] );

TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK

TC BLOCK: 0109011f SCID_EXEC_FLT_NOT_A_SEM TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]);

TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 010a011f SCID_EXEC_FLT_NYI TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]);

TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 010b011f SCID_EXEC_FLT_NOT_TWI_AS_EXPECTD TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]);

TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 010c011f SCID_EXEC_FLT_TOO_MANY_LOG_CALLS TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]);

TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 010d011f SCID_EXEC_FLT_UNKNOWN_LOG_CALL TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]);

TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 010e011f SCID_EXEC_FLT_NOT_A_AQUE TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]);

TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 010f011f SCID_EXEC_FLT_WAITERS_INVALID TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]);

TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0110011f SCID_EXEC_FLT_NOT_A_GATE TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7]

); ); ); ); ); ); ); );

TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0111011f SCID_EXEC_FLT_RECEIVERS_INVALID TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]

); ); ); ); );

TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0112011f SCID_EXEC_FLT_BQUE_HAS_ITEMS TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] );

TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK

TC BLOCK: 0113011f SCID_EXEC_FLT_NOT_A_ASEM TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]);

TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0114011f SCID_EXEC_FLT_UNKNOWNSYSTEM_TRAP TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]);

TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0115011f SCID_EXEC_FLT_ACTIVE_DMA_UNDRFLW TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]);

TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0116011f SCID_EXEC_FLT_UNEXPECTED_CDB TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]);

TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0117011f SCID_EXEC_FLT_BUFFER_IN_USE TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]);

TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0118011f SCID_EXEC_FLT_BUFFER_IS_FREE TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]);

TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0119011f SCID_EXEC_FLT_INTS_DISABLED TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]);

TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 011a011f SCID_EXEC_FLT_ZERO_PAGE_CORRUPT TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7]

); ); ); ); ); ); ); );

TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 011b011f SCID_EXEC_FLT_DCBZNOTCLALND TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]

); ); ); ); );

TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 011c0140 SCID_EXEC_FLT_CTRL_K_NOCC TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 011d01c0 SCID_EXEC_FLT_CTRL_K_CC TRANSLATIONBLOCK

ENDTRANSLATIONBLOCK TC BLOCK: 011e0120 SCID_EXEC_FLT_CTRL_R_NOCC TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 011f01a0 SCID_EXEC_FLT_CTRL_R_CC TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 01220105 SCID_EXEC_UNKNOWN_SMI TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('GLUE_SMI_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('GLUE_SMI_39_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ENDTRANSLATIONBLOCK TC BLOCK: 01250160 SCID_EXEC_FLT_CTRL_Z_NOCC TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 012601e0 SCID_EXEC_FLT_CTRL_Z_CC TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 01400100 SCID_EXEC_TIMER_NOT_BQUE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 015a0100 SCID_EXEC_SHEDULER_SUBP_QUE_EMPTY TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 02000100 SCID_CA_INSUFF_MEM TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 02010100 SCID_CA_BAD_GET_DATA TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 02020100 SCID_CA_DEFINE_BQ_NO_MEM TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0203010b SCID_CA_DUPLICATE_DIRTY TRANSLATIONBLOCK TRANSLATE('NOID: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('BMAE Address1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('Handle segNum: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] );

); ); ); ); );

TRANSLATE('Handle offset: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Block Address: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('BMAV: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('BMAE Address2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('Handle segNum: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('Handle offset: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('Block Address: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('BMAV: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10] ); ENDTRANSLATIONBLOCK TC BLOCK: 0204010a SCID_CA_BAD_MOP_STATE TRANSLATIONBLOCK TRANSLATE('Checkpoint: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('MOP/MNS State: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('HTB/MNP: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Additional debug value: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('Additional debug value: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('Additional debug value: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] TRANSLATE('Additional debug value: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] TRANSLATE('Additional debug value: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] TRANSLATE('Additional debug value: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] TRANSLATE('Additional debug value: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ENDTRANSLATIONBLOCK TC BLOCK: 0205010a SCID_CA_BAD_UNIT_STATE TRANSLATIONBLOCK TRANSLATE('Checkpoint: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Unit State: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('LDSB: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('NOID: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('Additional debug value: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('Additional debug value: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] TRANSLATE('Additional debug value: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] TRANSLATE('Additional debug value: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7]

); ); ); ); ); ); ); ); ); );

); ); ); ); ); ); ); );

TRANSLATE('Additional debug value: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('Additional debug value: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); ENDTRANSLATIONBLOCK TC BLOCK: 02070100 SCID_CA_BROKEN_TWICE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 02080100 SCID_CA_MIRROR_UUID_CHANGED TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 02090100 SCID_CA_INVALID_LOCK_META TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 020a0104 SCID_CA_INVALID_PARITY TRANSLATIONBLOCK TRANSLATE('chkpt: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('NOID: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('LDA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('BLKS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ENDTRANSLATIONBLOCK TC BLOCK: 020b0100 SCID_CA_BAD_POP_STATE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 020c0106 SCID_CA_BAD_GCOP_STATE TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %08x %08x %08x %08x', teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('oper: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('operation: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); ENDTRANSLATIONBLOCK TC BLOCK: 020d0104 SCID_CA_NCA_CORRUPTED TRANSLATIONBLOCK TRANSLATE('ncap: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('NCAE_NOID: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('index: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('NCAE state: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ENDTRANSLATIONBLOCK TC BLOCK: 020e0100 SCID_CA_FREE_DIAG_BUF

); ); ); );

); ); ); );

TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 020f0100 SCID_CA_IMPROPER_MWB_RECO TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 02100108 SCID_CA_DIFF_MNODE_MFC_NCAE TRANSLATIONBLOCK TRANSLATE('mnode ncae_index: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('mfc ncae_index: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('state: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('RIE index: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('lda: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('blocks: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] TRANSLATE('flags: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] TRANSLATE('unused: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ENDTRANSLATIONBLOCK TC BLOCK: 02110100 SCID_CA_IMPROPER_MWBF_RECO TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 02120100 SCID_CA_WRITE_HOLE_COLL TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 02150101 SCID_CA_CNODE_LEAK TRANSLATIONBLOCK TRANSLATE('Free cnodes: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 02160102 SCID_CA_VBUFF_LEAK TRANSLATIONBLOCK TRANSLATE('Requested buffers: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Free buffers: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 02180102 SCID_CA_BAD_PROXY_WRITE_STATE TRANSLATIONBLOCK TRANSLATE('Bad Proxy Write MFC State: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('State value: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 02190103 SCID_CA_BAD_PROXY_READ_STATE TRANSLATIONBLOCK TRANSLATE('Bad Proxy Read MFC State: 0x%08x',

); ); ); ); ); ); ); );

teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('State value: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('XDP: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); ENDTRANSLATIONBLOCK TC BLOCK: 021a0102 SCID_CA_BAD_PROXY_VERIFY_STATE TRANSLATIONBLOCK TRANSLATE('Bad Proxy Verify MFC State: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('State value: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 021b0100 SCID_CA_NOT_ENOUGH_XDS TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 021c0102 SCID_CA_INVALID_FLUSH_NODE TRANSLATIONBLOCK TRANSLATE('Flush Node Ptr: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Block Count: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 021e0100 SCID_CA_CACHE_LAYOUT_CHANGED TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 021f0100 SCID_CA_NV_BUFF_LEAK TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 02200100 SCID_CA_BAD_CACHE_ADDRESS TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 02210100 SCID_CA_INDEX_INCONSISTENT TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 03010104 SCID_SCS_INTERNAL_ERROR_SINGLE TRANSLATIONBLOCK TRANSLATE('PC of termination call: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('PC-specific parameter 1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('PC-specific parameter 2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('PC-specific parameter 3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ENDTRANSLATIONBLOCK

); ); ); );

TC BLOCK: 03020184 SCID_SCS_INTERNAL_ERROR_DUAL TRANSLATIONBLOCK TRANSLATE('PC of termination call: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('PC-specific parameter 1: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('PC-specific parameter 2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('PC-specific parameter 3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); ENDTRANSLATIONBLOCK TC BLOCK: 03030102 SCID_SCS_BAD_SWITCH_VALUE TRANSLATIONBLOCK TRANSLATE('PC of termination call: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Switch value: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 03040102 SCID_SCS_QUORUM_ACCESS_FAILURE TRANSLATIONBLOCK TRANSLATE('PC of termination call: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('QW block address where access failed: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 03060184 SCID_SCS_UNRECOVERABLE_ERROR TRANSLATIONBLOCK TRANSLATE('PC of termination call: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('PC-specific parameter 1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('PC-specific parameter 2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('PC-specific parameter 3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ENDTRANSLATIONBLOCK

); ); ); );

TC BLOCK: 030a0102 SCID_SCS_BAD_SCSDB_INDEX TRANSLATIONBLOCK TRANSLATE('area_offset: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('ds_index: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 030b0101 SCID_SCS_BAD_SCSDB_AREA_OFF TRANSLATIONBLOCK TRANSLATE('area_offset: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 030c0100 SCID_SCS_SCSDB_CACHE_FULL TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 030d0101 SCID_SCS_SCSDB_CACHE_FREE TRANSLATIONBLOCK TRANSLATE('cache page index: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 030e0102 SCID_SCS_SCSDB_CACHE_FLUSH

TRANSLATIONBLOCK TRANSLATE('cache page index: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('page offset: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 030f0101 SCID_SCS_SCSDB_CACHE_COMMIT TRANSLATIONBLOCK TRANSLATE('cache page index: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 03100102 SCID_SCS_BAD_CVMDB_INDEX TRANSLATIONBLOCK TRANSLATE('area_offset: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('ds_index: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 03110101 SCID_SCS_BAD_CVMDB_AREA_OFF TRANSLATIONBLOCK TRANSLATE('area_offset: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 03120100 SCID_SCS_CVMDB_CACHE_FULL TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 03130101 SCID_SCS_CVMDB_CACHE_FREE TRANSLATIONBLOCK TRANSLATE('Cache page index: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 03140102 SCID_SCS_CVMDB_CACHE_FLUSH TRANSLATIONBLOCK TRANSLATE('Cache page index: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Page offset: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 03150101 SCID_SCS_CVMDB_CACHE_COMMIT TRANSLATIONBLOCK TRANSLATE('Cache page index: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 03160100 SCID_SCS_PB_BUFFER_ALLOC_FAIL TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 031f0100 SCID_SCS_FC_OP_DESCS_ALLOC_FAIL TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 032a0000 SCID_SCS_MASTER_CONFLICT

TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 033c0106 SCID_SCS_BAD_RP_LOGIN_STATE TRANSLATIONBLOCK TRANSLATE('Invocation instance: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Port login state: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('Local port: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Port id value: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('Port name (low): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('Port name (high): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ENDTRANSLATIONBLOCK TC BLOCK: 033d0105 SCID_SCS_BAD_RP_LOGGEDIN_TMR_EXP TRANSLATIONBLOCK TRANSLATE('Port login state: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Local port: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('Port id value: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Port name (low): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('Port name (high): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ENDTRANSLATIONBLOCK TC BLOCK: 03500020 SCID_SCS_DEBUG_CRASH TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 03510141 SCID_SCS_KILLED_BY_OTHER TRANSLATIONBLOCK TRANSLATE('Reason code: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 03520144 SCID_SCS_KILL_OTHER TRANSLATIONBLOCK TRANSLATE('PC of termination call: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Reason code: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('Additional parameter 2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Additional parameter 3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ENDTRANSLATIONBLOCK

); ); ); ); ); );

); ); ); ); );

); ); ); );

TC BLOCK: 03640021 SCID_SCS_SHUTDOWN_RESTART TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[0] == 0, TRANSLATE('Request made via user agent (SCMI)')

); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[0] == 1, TRANSLATE('Request made via OCP') ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[0] == 2, TRANSLATE('Request made via TBM') ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[0] == 3, TRANSLATE('Request made via controller button') ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[0] == 4, TRANSLATE('Request made internally') ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[0] > 4, TRANSLATE('Unknown requester : 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0]) ); ENDTRANSLATIONBLOCK TC BLOCK: 03650061 SCID_SCS_SHUTDOWN_NORESTART TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[0] == 0, TRANSLATE('Request made via user agent (SCMI)') ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[0] == 1, TRANSLATE('Request made via OCP') ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[0] == 2, TRANSLATE('Request made via TBM') ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[0] == 3, TRANSLATE('Request made via controller button') ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[0] == 4, TRANSLATE('Request made internally') ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[0] > 4, TRANSLATE('Unknown requester : 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0]) ); ENDTRANSLATIONBLOCK TC BLOCK: 03660061 SCID_SCS_SHUTDOWN_POWEROFF TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[0] == 0, TRANSLATE('Request made via user agent (SCMI)') ); CONDITIONAL(

teb.u.data.ltei.lter.termination_event.params.param[0] == 1, TRANSLATE('Request made via OCP') ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[0] == 2, TRANSLATE('Request made via TBM') ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[0] == 3, TRANSLATE('Request made via controller button') ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[0] == 4, TRANSLATE('Request made internally') ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[0] > 4, TRANSLATE('Unknown requester : 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0]) ); ENDTRANSLATIONBLOCK TC BLOCK: 03670000 SCID_SCS_CRASH_RESTART TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 03680040 SCID_SCS_CRASH_NORESTART TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 03690080 SCID_SCS_CRASH_RESTART_COUPLED TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 036a00c0 SCID_SCS_CRASH_NORESTART_COUPLED TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 036c01c8 SCID_SCS_NOTIFY_DEV TRANSLATIONBLOCK TRANSLATE('Generic parameter 0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Generic parameter 1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('Generic parameter 2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Generic parameter 3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('Generic parameter 4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('Generic parameter 5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] TRANSLATE('Generic parameter 6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] TRANSLATE('Generic parameter 7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ENDTRANSLATIONBLOCK TC BLOCK: 036f0061 SCID_SCS_SHUTDOWN_LOCATE_NORESTART TRANSLATIONBLOCK

); ); ); ); ); ); ); );

CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[0] == 0, TRANSLATE('Request made via user agent (SCMI)') ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[0] == 1, TRANSLATE('Request made via OCP') ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[0] == 2, TRANSLATE('Request made via TBM') ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[0] == 3, TRANSLATE('Request made via controller button') ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[0] == 4, TRANSLATE('Request made internally') ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[0] > 4, TRANSLATE('Unknown requester : 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0]) ); ENDTRANSLATIONBLOCK TC BLOCK: 03700022 SCID_SCS_FAST_FAILOVER_RECOVERY TRANSLATIONBLOCK TRANSLATE('Calling PC : 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0]); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[1] == 1, TRANSLATE('Request was made in an exiting inoperative Disk Group state in dual c ontroller mode') ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[1] == 2, TRANSLATE('Request was made to allow failover to clear cache data lost') ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[1] == 3, TRANSLATE('Request was made to present unit with bad batteries on slave : crash slave') ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[1] == 4, TRANSLATE('Request was made to allow slave to join so units can clear cache data lost: crash master') ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[1] == 5, TRANSLATE('Thawed units are in fast failover: crash slave') ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[1] == 6, TRANSLATE('Request was made to present unit with no cache on master: crash maste r') ); CONDITIONAL(

teb.u.data.ltei.lter.termination_event.params.param[1] == 7, TRANSLATE('Request was made to present unit with no cache on slave: crash slave' ) ); ENDTRANSLATIONBLOCK TC BLOCK: 03780101 SCID_SCS_CANT_REALIZE_XXXDB TRANSLATIONBLOCK TRANSLATE('Status: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 03790020 SCID_SCS_CODE_LOAD_RESTART TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0400011f SCID_FM_DEF_EXCEPTION TRANSLATIONBLOCK TRANSLATE('Ecde [llistppcec]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]);

TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0401011f SCID_FM_MACHINE_CHECK TRANSLATIONBLOCK TRANSLATE('Glue chip interrupt bits [31:0]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Glue chip interrupt bits [63:32]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]);

TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0402011f SCID_FM_DEBUG TRANSLATIONBLOCK TRANSLATE('Pointer to DEBUG purpose string: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]);

TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0403047f SCID_FM_RECURSIVE_TE TRANSLATIONBLOCK TRANSLATE('Recursive event termination location: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Recursive event termination code: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('Recursive event termination parameter 0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Recursive event termination parameter 1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Recursive event termination parameter 2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('Recursive event termination parameter 3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]); TRANSLATE('Recursive event termination parameter 4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6]); TRANSLATE('Recursive event termination parameter 5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7]); TRANSLATE('Recursive event termination parameter 6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8]); TRANSLATE('Recursive event termination parameter 7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9]); TRANSLATE('Recursive event termination parameter 8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('Recursive event termination parameter 9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]);

TRANSLATE('Recursive event termination parameter 10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('Recursive event termination parameter 11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('Recursive event termination parameter 12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('Recursive event termination parameter 13: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('Recursive event termination parameter 14: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('Recursive event termination parameter 15: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('Recursive event termination parameter 16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('Recursive event termination parameter 17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('Recursive event termination parameter 18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('Recursive event termination parameter 19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('Recursive event termination parameter 20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('Recursive event termination parameter 21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('Recursive event termination parameter 22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('Recursive event termination parameter 23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('Recursive event termination parameter 24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('Recursive event termination parameter 25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('Recursive event termination parameter 26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('Recursive event termination parameter 27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('Recursive event termination parameter 28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 04050101 SCID_FM_UPDSCELABAE_EDBN_BAD TRANSLATIONBLOCK TRANSLATE('Event data block index: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0]); ENDTRANSLATIONBLOCK TC BLOCK: 0406017f SCID_FM_LTE_RESET TRANSLATIONBLOCK TRANSLATE('In progress event termination location: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE('In progress event termination code: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE('In progress event termination parameter 0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE('In progress event termination parameter 1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('In progress event termination parameter 2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('In progress event termination parameter 3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]);

TRANSLATE('In progress event termination parameter 4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6]); TRANSLATE('In progress event termination parameter 5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7]); TRANSLATE('In progress event termination parameter 6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8]); TRANSLATE('In progress event termination parameter 7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9]); TRANSLATE('In progress event termination parameter 8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('In progress event termination parameter 9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('In progress event termination parameter 10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('In progress event termination parameter 11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('In progress event termination parameter 12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('In progress event termination parameter 13: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('In progress event termination parameter 14: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('In progress event termination parameter 15: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('In progress event termination parameter 16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('In progress event termination parameter 17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('In progress event termination parameter 18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('In progress event termination parameter 19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('In progress event termination parameter 20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('In progress event termination parameter 21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('In progress event termination parameter 22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('In progress event termination parameter 23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('In progress event termination parameter 24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('In progress event termination parameter 25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('In progress event termination parameter 26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('In progress event termination parameter 27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('In progress event termination parameter 28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0407016a SCID_FM_PREMATURE_TERM TRANSLATIONBLOCK TRANSLATE('Trap type: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE('TC [llisttcc]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2]);

TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('CR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('XER: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]); TRANSLATE('CTR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6]); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7]); TRANSLATE('Exception code: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8]); TRANSLATE('Exception count: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9]); ENDTRANSLATIONBLOCK TC BLOCK: 04080582 SCID_FM_COUPLED_CRASH_DR TRANSLATIONBLOCK TRANSLATE('Other controller termination location: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE('Other controller termination code: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1]); ENDTRANSLATIONBLOCK TC BLOCK: 040905a2 SCID_FM_COUPLED_CRASH_NDR TRANSLATIONBLOCK TRANSLATE('Other controller termination location: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE('Other controller termination code: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1]); ENDTRANSLATIONBLOCK TC BLOCK: 040a05c2 SCID_FM_COUPLED_CRASH_DNR TRANSLATIONBLOCK TRANSLATE('Other controller termination location: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE('Other controller termination code: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1]); ENDTRANSLATIONBLOCK TC BLOCK: 040b05e2 SCID_FM_COUPLED_CRASH_NDNR TRANSLATIONBLOCK TRANSLATE('Other controller termination location: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE('Other controller termination code: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1]); ENDTRANSLATIONBLOCK TC BLOCK: 040c0582 SCID_FM_COUPLED_CRASH_BADDRCC TRANSLATIONBLOCK TRANSLATE('Other controller termination location: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE('Other controller termination code: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1]); ENDTRANSLATIONBLOCK TC BLOCK: 040d0101 SCID_FM_UNRECOG_UPDSCELABAE_OP TRANSLATIONBLOCK TRANSLATE('Unrecognized value: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0]);

ENDTRANSLATIONBLOCK TC BLOCK: 040e0100 SCID_FM_NOT_MASTER TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 040f0100 SCID_FM_IS_MASTER TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 04100182 SCID_FM_SCEL_NOT_ACTIVE TRANSLATIONBLOCK TRANSLATE('Local control flags: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE('Master control flags: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1]); ENDTRANSLATIONBLOCK TC BLOCK: 04110181 SCID_FM_CSLD_SCXEL_INACC TRANSLATIONBLOCK TRANSLATE('Status: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0]); ENDTRANSLATIONBLOCK TC BLOCK: 04120123 SCID_FM_ALL_LTE_RESET TRANSLATIONBLOCK TRANSLATE('Unexpected event type: %d. (%[fm_ue])', teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE('Index: %d.', teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE('Good entries: %d.', teb.u.data.ltei.lter.termination_event.params.param[2]); ENDTRANSLATIONBLOCK TC BLOCK: 04130107 SCID_FM_INVALID_STRUCT_TYPE TRANSLATIONBLOCK TRANSLATE('Unexpected value: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE('Allowed value 1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE('Allowed value 2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE('Allowed value 3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('Allowed value 4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('Allowed value 5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]); TRANSLATE('Allowed value 6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6]); ENDTRANSLATIONBLOCK TC BLOCK: 04140104 SCID_FM_EIP_OUT_OF_RANGE TRANSLATIONBLOCK TRANSLATE('Event code: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE('Out-of-range EIP type: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE('Minimum allowed EIP type: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE('Maximum allowed EIP type: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3]); ENDTRANSLATIONBLOCK TC BLOCK: 04150104 SCID_FM_EIP_TOO_BIG TRANSLATIONBLOCK TRANSLATE('Event code: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE('EIP type: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE('EIP size: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE('Maximum allowed EIP size: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3]); ENDTRANSLATIONBLOCK TC BLOCK: 04160103 SCID_FM_EIP_NOT_MULTLW TRANSLATIONBLOCK TRANSLATE('Event code: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE('EIP type: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE('EIP size: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2]); ENDTRANSLATIONBLOCK TC BLOCK: 04170107 SCID_FM_CSIO_REQUEST_INVALID TRANSLATIONBLOCK TRANSLATE('Status: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE('I/O operation: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE('NOID: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE('Block address: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('Number of blocks: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[5] == 0, TRANSLATE('Buffer address supplied to CS: 0x00000000 (erase)'), TRANSLATE('Buffer address supplied to CS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]) ); TRANSLATE('PC of call to Container Services: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6]); ENDTRANSLATIONBLOCK TC BLOCK: 04180107 SCID_FM_CSIO_UNRECOG_STATUS TRANSLATIONBLOCK TRANSLATE('Status: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE('I/O operation: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE('NOID: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE('Block address: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('Number of blocks: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[4]); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[5] == 0, TRANSLATE('Buffer address supplied to CS: 0x00000000 (erase)'), TRANSLATE('Buffer address supplied to CS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]) ); TRANSLATE('PC of call to Container Services: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6]); ENDTRANSLATIONBLOCK TC BLOCK: 04190100 SCID_FM_RESTARTDEBUG TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 041a0100 SCID_FM_UNEXP_ACTIVEQ_EMPTY TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 041b0105 SCID_FM_CORRECT_EDBN_NOT_CACHED TRANSLATIONBLOCK TRANSLATE('Event data block number: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE('Current event pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE('Event entry check status: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE('Current event sequence number: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('Expected event sequence number: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); ENDTRANSLATIONBLOCK TC BLOCK: 041c0100 SCID_FM_NOT_SCMI_ETC TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 041d0100 SCID_FM_NOT_SCMI TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 041e0102 SCID_FM_TEISP_BAD TRANSLATIONBLOCK TRANSLATE('Unexpected value: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE('Expected value: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1]); ENDTRANSLATIONBLOCK TC BLOCK: 041f0a1f SCID_FM_LOW_MEM_ACC_V TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE('Undefined: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK

TC BLOCK: 0420011f SCID_FM_WATCHDOG_TIMEOUT TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 04210107 SCID_FM_CSIO_DRIVE_BROKEN_STATUS TRANSLATIONBLOCK TRANSLATE('Status: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE('I/O operation: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE('NOID: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE('Block address: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('Number of blocks: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[5] == 0, TRANSLATE('Buffer address supplied to CS: 0x00000000 (erase)'), TRANSLATE('Buffer address supplied to CS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]) ); TRANSLATE('PC of call to Container Services: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6]); ENDTRANSLATIONBLOCK TC BLOCK: 04220102 SCID_FM_EC_ILLEGAL_SCID TRANSLATIONBLOCK TRANSLATE('Event code: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE('Illegal software component: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1]); ENDTRANSLATIONBLOCK TC BLOCK: 04240960 SCID_FM_POWER_LOSS TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 043f011f SCID_FM_PPC_EXCEPTION_0000 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] TRANSLATE('R28: 0x%08x',

); ); ); ); ); ); ); );

teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0440011f SCID_FM_PPC_EXCEPTION_0100 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('R31: 0x%08x',

); ); ); ); );

teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0441011f SCID_FM_PPC_EXCEPTION_0200 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0442011f SCID_FM_PPC_EXCEPTION_0300

TRANSLATIONBLOCK TRANSLATE('DSISR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('DAR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('DABR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0443011f SCID_FM_PPC_EXCEPTION_0400 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0444011f SCID_FM_PPC_EXCEPTION_0500 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0445011f SCID_FM_PPC_EXCEPTION_0600 TRANSLATIONBLOCK TRANSLATE('DSISR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('DAR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0446011f SCID_FM_PPC_EXCEPTION_0700 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0447011f SCID_FM_PPC_EXCEPTION_0800 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0448011f SCID_FM_PPC_EXCEPTION_0900 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0449011f SCID_FM_PPC_EXCEPTION_0A00 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] TRANSLATE('R28: 0x%08x',

); ); ); ); ); ); ); );

teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 044a011f SCID_FM_PPC_EXCEPTION_0B00 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('R31: 0x%08x',

); ); ); ); );

teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 044b011f SCID_FM_PPC_EXCEPTION_0C00 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 044c011f SCID_FM_PPC_EXCEPTION_0D00

TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 044d011f SCID_FM_PPC_EXCEPTION_0E00 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 044e011f SCID_FM_PPC_EXCEPTION_0F00 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 044f011f SCID_FM_PPC_EXCEPTION_1000 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0450011f SCID_FM_PPC_EXCEPTION_1100 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0451011f SCID_FM_PPC_EXCEPTION_1200 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0452011f SCID_FM_PPC_EXCEPTION_1300 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0453011f SCID_FM_PPC_EXCEPTION_1400 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] TRANSLATE('R28: 0x%08x',

); ); ); ); ); ); ); );

teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 04540101 SCID_FM_BAD_EDBN_COUNT TRANSLATIONBLOCK TRANSLATE('Event data block count: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 04550101 SCID_FM_BAD_REI_STATUS TRANSLATIONBLOCK TRANSLATE('Unexpected status: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 04560102 SCID_FM_ACTIVEQ_EVENT_NA

TRANSLATIONBLOCK TRANSLATE('Sequence number requested: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Number events reported valid for retrieval: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 04570105 SCID_FM_DIRECT_TERM_CALL TRANSLATIONBLOCK TRANSLATE('PC of direct call: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Stack pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('Trap type parameter: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('TC parameter: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('Save area parameter: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ENDTRANSLATIONBLOCK

); ); ); ); );

TC BLOCK: 0458011f SCID_FM_PPC_EXCEPTION_1500 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0459011f SCID_FM_PPC_EXCEPTION_1600 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 045a011f SCID_FM_PPC_EXCEPTION_1700 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 045b011f SCID_FM_PPC_EXCEPTION_1800 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] TRANSLATE('R27: 0x%08x',

); ); ); ); ); ); ); ); );

teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 045c011f SCID_FM_PPC_EXCEPTION_1900 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] TRANSLATE('R30: 0x%08x',

); ); ); ); ); );

teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 045d011f SCID_FM_PPC_EXCEPTION_1A00 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 045e011f SCID_FM_PPC_EXCEPTION_1B00 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 045f011f SCID_FM_PPC_EXCEPTION_1C00 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0460011f SCID_FM_PPC_EXCEPTION_1D00 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0461011f SCID_FM_PPC_EXCEPTION_1E00 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0462011f SCID_FM_PPC_EXCEPTION_1F00 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0463011f SCID_FM_PPC_EXCEPTION_2000 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0464011f SCID_FM_PPC_EXCEPTION_2100 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0465011f SCID_FM_PPC_EXCEPTION_2200 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] TRANSLATE('R27: 0x%08x',

); ); ); ); ); ); ); ); );

teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0466011f SCID_FM_PPC_EXCEPTION_2300 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] TRANSLATE('R30: 0x%08x',

); ); ); ); ); );

teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0467011f SCID_FM_PPC_EXCEPTION_2400 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0468011f SCID_FM_PPC_EXCEPTION_2500 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0469011f SCID_FM_PPC_EXCEPTION_2600 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 046a011f SCID_FM_PPC_EXCEPTION_2700 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 046b011f SCID_FM_PPC_EXCEPTION_2800 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 046c011f SCID_FM_PPC_EXCEPTION_2900 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 046d011f SCID_FM_PPC_EXCEPTION_2A00 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 046e011f SCID_FM_PPC_EXCEPTION_2B00 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 046f011f SCID_FM_PPC_EXCEPTION_2C00 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] TRANSLATE('R27: 0x%08x',

); ); ); ); ); ); ); ); );

teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0470011f SCID_FM_PPC_EXCEPTION_2D00 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] TRANSLATE('R30: 0x%08x',

); ); ); ); ); );

teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0471011f SCID_FM_PPC_EXCEPTION_2E00 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0472011f SCID_FM_PPC_EXCEPTION_2F00 TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 04730167 SCID_FM_BUILD_ADDRESS_MAP_ERROR TRANSLATIONBLOCK TRANSLATE('ADDRESS_MAP index: %d.', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Parameter 1: %d. (0x%08x)', teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('Parameter 2: %d. (0x%08x)', teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Parameter 3: %d. (0x%08x)', teb.u.data.ltei.lter.termination_event.params.param[3], teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Parameter 4: %d. (0x%08x)', teb.u.data.ltei.lter.termination_event.params.param[4], teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('Parameter 5: %d. (0x%08x)', teb.u.data.ltei.lter.termination_event.params.param[5], teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('Parameter 6: %d. (0x%08x)', teb.u.data.ltei.lter.termination_event.params.param[6], teb.u.data.ltei.lter.termination_event.params.param[6] ); ENDTRANSLATIONBLOCK TC BLOCK: 04740160 SCID_FM_ELPMA_NOTALLOC TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0476013f SCID_FM_LTE_RESET_CMPLT TRANSLATIONBLOCK TRANSLATE('In progress event termination location: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE('In progress event termination code: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE('In progress event termination parameter 0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE('In progress event termination parameter 1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('In progress event termination parameter 2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('In progress event termination parameter 3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]); TRANSLATE('In progress event termination parameter 4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6]); TRANSLATE('In progress event termination parameter 5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7]); TRANSLATE('In progress event termination parameter 6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8]); TRANSLATE('In progress event termination parameter 7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9]); TRANSLATE('In progress event termination parameter 8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('In progress event termination parameter 9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('In progress event termination parameter 10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('In progress event termination parameter 11: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('In progress event termination parameter 12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('In progress event termination parameter 13: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('In progress event termination parameter 14: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('In progress event termination parameter 15: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('In progress event termination parameter 16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('In progress event termination parameter 17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('In progress event termination parameter 18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('In progress event termination parameter 19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('In progress event termination parameter 20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('In progress event termination parameter 21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('In progress event termination parameter 22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('In progress event termination parameter 23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('In progress event termination parameter 24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('In progress event termination parameter 25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('In progress event termination parameter 26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('In progress event termination parameter 27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('In progress event termination parameter 28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0477013f SCID_FM_LTE_RESET_INTD TRANSLATIONBLOCK TRANSLATE('In progress event termination location: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE('In progress event termination code: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE('In progress event termination parameter 0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE('In progress event termination parameter 1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('In progress event termination parameter 2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('In progress event termination parameter 3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]); TRANSLATE('In progress event termination parameter 4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6]); TRANSLATE('In progress event termination parameter 5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7]); TRANSLATE('In progress event termination parameter 6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8]); TRANSLATE('In progress event termination parameter 7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9]); TRANSLATE('In progress event termination parameter 8: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('In progress event termination parameter 9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('In progress event termination parameter 10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('In progress event termination parameter 11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('In progress event termination parameter 12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('In progress event termination parameter 13: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('In progress event termination parameter 14: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('In progress event termination parameter 15: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('In progress event termination parameter 16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('In progress event termination parameter 17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('In progress event termination parameter 18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('In progress event termination parameter 19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('In progress event termination parameter 20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('In progress event termination parameter 21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('In progress event termination parameter 22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('In progress event termination parameter 23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('In progress event termination parameter 24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('In progress event termination parameter 25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('In progress event termination parameter 26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('In progress event termination parameter 27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('In progress event termination parameter 28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 0478393f SCID_FM_LTE_RESET_SPPC_RESET TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE('Reserved: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE('Reserved: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2]); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[3] != 0,

TRANSLATE( 'Previous termination event code[-1]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[4] != 0, TRANSLATE( 'Previous termination event code[-2]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[5] != 0, TRANSLATE( 'Previous termination event code[-3]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[6] != 0, TRANSLATE( 'Previous termination event code[-4]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[7] != 0, TRANSLATE( 'Previous termination event code[-5]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[8] != 0, TRANSLATE( 'Previous termination event code[-6]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[9] != 0, TRANSLATE( 'Previous termination event code[-7]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[10] != 0, TRANSLATE( 'Previous termination event code[-9]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10] )

); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[11] != 0, TRANSLATE( 'Previous termination event code[-10]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[12] != 0, TRANSLATE( 'Previous termination event code[-11]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[13] != 0, TRANSLATE( 'Previous termination event code[-12]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[14] != 0, TRANSLATE( 'Previous termination event code[-13]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[15] != 0, TRANSLATE( 'Previous termination event code[-14]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[16] != 0, TRANSLATE( 'Previous termination event code[-15]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[17] != 0, TRANSLATE( 'Previous termination event code[-16]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[18] != 0,

TRANSLATE( 'Previous termination event code[-17]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[19] != 0, TRANSLATE( 'Previous termination event code[-18]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[20] != 0, TRANSLATE( 'Previous termination event code[-19]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[21] != 0, TRANSLATE( 'Previous termination event code[-20]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[22] != 0, TRANSLATE( 'Previous termination event code[-21]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[23] != 0, TRANSLATE( 'Previous termination event code[-22]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[25] != 0, TRANSLATE( 'Previous termination event code[-23]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[26] != 0, TRANSLATE( 'Previous termination event code[-24]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26] )

); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[27] != 0, TRANSLATE( 'Previous termination event code[-25]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[28] != 0, TRANSLATE( 'Previous termination event code[-26]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[29] != 0, TRANSLATE( 'Previous termination event code[-27]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29] ) ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[30] != 0, TRANSLATE( 'Previous termination event code[-28]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30] ) ); ENDTRANSLATIONBLOCK TC BLOCK: 04790020 SCID_FM_LTE_RESET_MMTSTEXECD TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 047a013f SCID_FM_LTE_RESET_UNEXP TRANSLATIONBLOCK TRANSLATE('Termination processing state value: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE('Reserved: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE('In progress event termination location: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE('In progress event termination code: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('In progress event termination parameter 0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('In progress event termination parameter 1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]); TRANSLATE('In progress event termination parameter 2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6]); TRANSLATE('In progress event termination parameter 3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7]); TRANSLATE('In progress event termination parameter 4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8]); TRANSLATE('In progress event termination parameter 5: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[9]); TRANSLATE('In progress event termination parameter 6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('In progress event termination parameter 7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('In progress event termination parameter 8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('In progress event termination parameter 9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('In progress event termination parameter 10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('In progress event termination parameter 11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('In progress event termination parameter 12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('In progress event termination parameter 13: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('In progress event termination parameter 14: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('In progress event termination parameter 15: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('In progress event termination parameter 16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('In progress event termination parameter 17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('In progress event termination parameter 18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('In progress event termination parameter 19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('In progress event termination parameter 20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('In progress event termination parameter 21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('In progress event termination parameter 22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('In progress event termination parameter 23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('In progress event termination parameter 24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('In progress event termination parameter 25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('In progress event termination parameter 26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 047b0025 SCID_FM_SCRUB_REQUESTED TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[0] == 15, TRANSLATE('SCRUB resync was requested via OCP') ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[0] == 56, TRANSLATE('SCRUB resync was requested via OCP') ); CONDITIONAL( teb.u.data.ltei.lter.termination_event.params.param[0] == 99, TRANSLATE('SCRUB resync was requested via SCMI') ); CONDITIONAL(

teb.u.data.ltei.lter.termination_event.params.param[0] == 100, TRANSLATE('SCRUB resync was requested via the Console') ); TRANSLATE('Scrub resync calling PC: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE('Scrub Requestor Program Counter: %08x', teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE('Requestor Scrub Type: %d (%[scs_scrub_types])', teb.u.data.ltei.lter.termination_event.params.param[3], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('DebugFlags: %08X', teb.u.data.ltei.lter.termination_event.params.param[4]); ENDTRANSLATIONBLOCK TC BLOCK: 04810111 SCID_FM_XL_WATCHDOG_TIMEOUT TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('GLUE_RESET_DIS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('GLUE_RESET_IN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('GLUE_SELF_RESET: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); ENDTRANSLATIONBLOCK TC BLOCK: 04822070 SCID_FM_CACHE_VTT_FAIL TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) );

TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('ATLANTIS_CPU_ERROR_CAUSE: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); ENDTRANSLATIONBLOCK TC BLOCK: 04832070 SCID_FM_DIMM_012_DC_NOT_OK TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8]

); ); ); ); ); ); ); ); );

TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('ATLANTIS_CPU_ERROR_CAUSE: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); ENDTRANSLATIONBLOCK TC BLOCK: 04842070 SCID_FM_DIMM_3_DC_NOT_OK TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('ATLANTIS_CPU_ERROR_CAUSE: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); ENDTRANSLATIONBLOCK TC BLOCK: 04852010 SCID_FM_60X_DPE TRANSLATIONBLOCK

CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('ATLANTIS_CPU_ERROR_CAUSE: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); ENDTRANSLATIONBLOCK TC BLOCK: 04862011 SCID_FM_60X_APE TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]

); ); ); ); ); );

TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('ATLANTIS_CPU_ERROR_CAUSE: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); ENDTRANSLATIONBLOCK TC BLOCK: 0487390f SCID_FM_PPC_L1_ICACHE_ERROR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]);

TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); ENDTRANSLATIONBLOCK TC BLOCK: 0488390f SCID_FM_PPC_L1_DCACHE_ERROR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); ENDTRANSLATIONBLOCK TC BLOCK: 0489390f SCID_FM_PPC_L2_CACHE_TAG_OR_DPE TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3]

); ); ); );

TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); ENDTRANSLATIONBLOCK TC BLOCK: 048a2016 SCID_FM_60X_TIMEOUT_ERROR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]);

TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('GLUE_TIMER_CTRL: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('GLUE_PPC_SV (pre-Sprite3 only): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('GLUE_PPC_CT (pre-Sprite3 only): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('SPRITE_PC_ADDR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('SPRITE_PC_REV (Sprite3 only): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('SPRITE_PC_WTT (Sprite3 only): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('SPRITE_PC_TT: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); ENDTRANSLATIONBLOCK TC BLOCK: 048b0031 SCID_FM_KILLED_BY_OTHER TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('GLUE_RESET_DIS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('GLUE_RESET_IN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('GLUE_SELF_RESET: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); ENDTRANSLATIONBLOCK TC BLOCK: 048c0026 SCID_FM_RESET_BY_SELF TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] );

TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('GLUE_RESET_DIS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('GLUE_RESET_IN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('GLUE_SELF_RESET: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ENDTRANSLATIONBLOCK TC BLOCK: 048d0026 SCID_FM_RESET_BY_BUTTON TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('GLUE_RESET_DIS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('GLUE_RESET_IN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('GLUE_SELF_RESET: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ENDTRANSLATIONBLOCK

); ); ); ); );

); ); ); ); ); );

TC BLOCK: 048e0115 SCID_FM_ATLANTIS_60X_BAD_ADDR TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('ATLANTIS_CPU_ERROR_CAUSE: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]);

TRANSLATE('ATLANTIS_CPU0_ERROR_MASK: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('ATLANTIS_CPU_ERROR_ADDRESS_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('ATLANTIS_CPU_ERROR_ADDRESS_HIGH: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('ATLANTIS_CPU_ERROR_DATA_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('ATLANTIS_CPU_ERROR_DATA_HIGH: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('ATLANTIS_CPU_ERROR_PARITY: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); ENDTRANSLATIONBLOCK TC BLOCK: 048f2016 SCID_FM_ATLANTIS_60X_TT_IV_BIRV TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('ATLANTIS_CPU_ERROR_CAUSE: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('ATLANTIS_CPU0_ERROR_MASK: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('ATLANTIS_CPU_ERROR_ADDRESS_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('ATLANTIS_CPU_ERROR_ADDRESS_HIGH: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]);

TRANSLATE('ATLANTIS_CPU_ERROR_DATA_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('ATLANTIS_CPU_ERROR_DATA_HIGH: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('ATLANTIS_CPU_ERROR_PARITY: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); ENDTRANSLATIONBLOCK TC BLOCK: 04900115 SCID_FM_ATLANTIS_PROTECTION_ERR TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('ATLANTIS_CPU_ERROR_CAUSE: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('ATLANTIS_CPU0_ERROR_MASK: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('ATLANTIS_CPU_ERROR_ADDRESS_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('ATLANTIS_CPU_ERROR_ADDRESS_HIGH: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('ATLANTIS_CPU_ERROR_DATA_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('ATLANTIS_CPU_ERROR_DATA_HIGH: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('ATLANTIS_CPU_ERROR_PARITY: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); ENDTRANSLATIONBLOCK TC BLOCK: 04913916 SCID_FM_ATLANTIS_ISRAM_PERR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller'

) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('ATLANTIS_SRAM_CONFIGURATION: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('ATLANTIS_SRAM_ERROR_CAUSE: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('ATLANTIS_SRAM_ERROR_ADDRESS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('ATLANTIS_SRAM_ERROR_ADDRESS_HIGH: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('ATLANTIS_SRAM_ERROR_DATA_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('ATLANTIS_SRAM_ERROR_DATA_HIGH: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('ATLANTIS_SRAM_ERROR_PARITY: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); ENDTRANSLATIONBLOCK TC BLOCK: 04922016 SCID_FM_ATLANTIS_PM_ECC_ERROR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] );

TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('ATLANTIS_SDRAM_ERROR_ADDRESS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('ATLANTIS_SDRAM_ERROR_DATA_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('ATLANTIS_SDRAM_ERROR_DATA_HIGH: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('ATLANTIS_SDRAM_RECEIVED_ECC: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('ATLANTIS_SDRAM_CALCULATED_ECC: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('ATLANTIS_SDRAM_ECC_COUNTER: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('ATLANTIS_SDRAM_ECC_CONTROL: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); ENDTRANSLATIONBLOCK TC BLOCK: 04930113 SCID_FM_ATLANTIS_DEV_BURST_ERROR TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7]

); ); ); ); ); ); ); );

TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('ATLANTIS_DEVICE_INTERRUPT_CAUSE: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('ATLANTIS_DEVICE_INTERRUPT_MASK: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('ATLANTIS_DEVICE_ERROR_ADDRESS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('ATLANTIS_DEVICE_ERROR_DATA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('ATLANTIS_DEVICE_ERROR_PARITY: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); ENDTRANSLATIONBLOCK TC BLOCK: 04942014 SCID_FM_ATLANTIS_DEV_RDY_TIMEOUT TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]);

TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('ATLANTIS_DEVICE_INTERRUPT_CAUSE: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('ATLANTIS_DEVICE_INTERRUPT_MASK: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('ATLANTIS_DEVICE_ERROR_ADDRESS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('ATLANTIS_DEVICE_ERROR_DATA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('ATLANTIS_DEVICE_ERROR_PARITY: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); ENDTRANSLATIONBLOCK TC BLOCK: 04952014 SCID_FM_ATLANTIS_DEV_PERR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('ATLANTIS_DEVICE_INTERRUPT_CAUSE: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('ATLANTIS_DEVICE_INTERRUPT_MASK: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('ATLANTIS_DEVICE_ERROR_ADDRESS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('ATLANTIS_DEVICE_ERROR_DATA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]);

TRANSLATE('ATLANTIS_DEVICE_ERROR_PARITY: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); ENDTRANSLATIONBLOCK TC BLOCK: 04960113 SCID_FM_ATLANTIS_DMA_BAD_ADDR TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('ATLANTIS_IDMA_INTERRUPT_CAUSE: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('ATLANTIS_IDMA_INTERRUPT_MASK: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('ATLANTIS_IDMA_ERROR_ADDRESS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('ATLANTIS_IDMA_CROSSBAR_TIMEOUT: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('ATLANTIS_IDMA_ERROR_SELECT: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); ENDTRANSLATIONBLOCK TC BLOCK: 04970113 SCID_FM_ATLANTIS_DMA_ACCESS_PROT TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]

); ); ); ); ); );

TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('ATLANTIS_IDMA_INTERRUPT_CAUSE: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('ATLANTIS_IDMA_INTERRUPT_MASK: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('ATLANTIS_IDMA_ERROR_ADDRESS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('ATLANTIS_IDMA_CROSSBAR_TIMEOUT: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('ATLANTIS_IDMA_ERROR_SELECT: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); ENDTRANSLATIONBLOCK TC BLOCK: 04980113 SCID_FM_ATLANTIS_DMA_WRT_PRO_ERR TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('ATLANTIS_IDMA_INTERRUPT_CAUSE: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]);

TRANSLATE('ATLANTIS_IDMA_INTERRUPT_MASK: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('ATLANTIS_IDMA_ERROR_ADDRESS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('ATLANTIS_IDMA_CROSSBAR_TIMEOUT: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('ATLANTIS_IDMA_ERROR_SELECT: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); ENDTRANSLATIONBLOCK TC BLOCK: 04990113 SCID_FM_ATLANTIS_DMA_DSCRPT_ACC TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('ATLANTIS_IDMA_INTERRUPT_CAUSE: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('ATLANTIS_IDMA_INTERRUPT_MASK: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('ATLANTIS_IDMA_ERROR_ADDRESS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('ATLANTIS_IDMA_CROSSBAR_TIMEOUT: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('ATLANTIS_IDMA_ERROR_SELECT: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); ENDTRANSLATIONBLOCK TC BLOCK: 049a0110 SCID_FM_SPRITE_60X_TIMEOUT_PCIX TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] );

TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('SPRITE_PC_ERR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('SPRITE_PC_ADDR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); ENDTRANSLATIONBLOCK TC BLOCK: 049b2011 SCID_FM_SPRITE_LAST_ENTRY_ERROR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]);

TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('SPRITE_PC_ERR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('SPRITE_PC_ADDR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); ENDTRANSLATIONBLOCK TC BLOCK: 049c2011 SCID_FM_SPRITE_60X_ALIGNMENT_ERR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('SPRITE_PC_ERR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('SPRITE_PC_ADDR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); ENDTRANSLATIONBLOCK TC BLOCK: 049d3911 SCID_FM_SPRITE_QUEUE_RD_DPE TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1,

TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('SPRITE_PC_ERR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('SPRITE_PC_ADDR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); ENDTRANSLATIONBLOCK TC BLOCK: 049e0110 SCID_FM_SPRITE_PCIX_ACCESS_ERROR TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8]

); ); ); ); ); ); ); ); );

TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('SPRITE_PC_ERR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('SPRITE_PC_ADDR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); ENDTRANSLATIONBLOCK TC BLOCK: 049f2012 SCID_FM_SPRITE_QUEUE_INVAL_DEST TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('SPRITE_PC_ERR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('SPRITE_PC_ADDR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('SPRITE_Q_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]);

ENDTRANSLATIONBLOCK TC BLOCK: 04a0011c SCID_FM_SPRITE_XORDMA_TIMEOUT TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('SPRITE_PC_ERR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('SPRITE_X_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('SPRITE_X_TMO: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('SPRITE_X_CB: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('SPRITE_X_PI: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('SPRITE_X_CI: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('SPRITE_X_CC: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('SPRITE_X_USA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('SPRITE_X_SA0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('SPRITE_X_SA1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('SPRITE_X_SA2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('SPRITE_X_SA3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('SPRITE_X_UDA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('SPRITE_X_DA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]);

ENDTRANSLATIONBLOCK TC BLOCK: 04a1011c SCID_FM_SPRITE_XORDMA_SFRAME_ERR TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('SPRITE_PC_ERR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('SPRITE_X_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('SPRITE_X_TMO: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('SPRITE_X_CB: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('SPRITE_X_PI: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('SPRITE_X_CI: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('SPRITE_X_CC: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('SPRITE_X_USA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('SPRITE_X_SA0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('SPRITE_X_SA1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('SPRITE_X_SA2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('SPRITE_X_SA3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('SPRITE_X_UDA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('SPRITE_X_DA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]);

ENDTRANSLATIONBLOCK TC BLOCK: 04a2011c SCID_FM_SPRITE_XORDMA_EFRAME_ERR TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('SPRITE_PC_ERR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('SPRITE_X_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('SPRITE_X_TMO: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('SPRITE_X_CB: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('SPRITE_X_PI: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('SPRITE_X_CI: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('SPRITE_X_CC: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('SPRITE_X_USA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('SPRITE_X_SA0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('SPRITE_X_SA1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('SPRITE_X_SA2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('SPRITE_X_SA3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('SPRITE_X_UDA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('SPRITE_X_DA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]);

ENDTRANSLATIONBLOCK TC BLOCK: 04a3391d SCID_FM_SPRITE_XORDMA_PERR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('SPRITE_PC_ERR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('SPRITE_X_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('SPRITE_X_TMO: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('SPRITE_X_CB: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('SPRITE_X_PI: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('SPRITE_X_CI: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('SPRITE_X_CC: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('SPRITE_X_USA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('SPRITE_X_SA0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('SPRITE_X_SA1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]);

TRANSLATE('SPRITE_X_SA2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('SPRITE_X_SA3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('SPRITE_X_UDA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('SPRITE_X_DA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); ENDTRANSLATIONBLOCK TC BLOCK: 04a4011c SCID_FM_SPRITE_XORDMA_INVAL_OP TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('SPRITE_PC_ERR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('SPRITE_X_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('SPRITE_X_TMO: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('SPRITE_X_CB: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('SPRITE_X_PI: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('SPRITE_X_CI: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('SPRITE_X_CC: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('SPRITE_X_USA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('SPRITE_X_SA0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('SPRITE_X_SA1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]);

TRANSLATE('SPRITE_X_SA2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('SPRITE_X_SA3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('SPRITE_X_UDA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('SPRITE_X_DA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); ENDTRANSLATIONBLOCK TC BLOCK: 04a5011c SCID_FM_SPRITE_XORDMA_CNT_ERROR TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('SPRITE_PC_ERR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('SPRITE_X_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('SPRITE_X_TMO: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('SPRITE_X_CB: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('SPRITE_X_PI: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('SPRITE_X_CI: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('SPRITE_X_CC: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('SPRITE_X_USA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('SPRITE_X_SA0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('SPRITE_X_SA1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]);

TRANSLATE('SPRITE_X_SA2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('SPRITE_X_SA3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('SPRITE_X_UDA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('SPRITE_X_DA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); ENDTRANSLATIONBLOCK TC BLOCK: 04a62012 SCID_FM_SPRITE_BAD_WRT_DATA_ERR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('SPRITE_PC_ERR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('SPRITE_PC_ADDR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('SPRITE_M_ES: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); ENDTRANSLATIONBLOCK TC BLOCK: 04a73912 SCID_FM_SPRITE_CMD_OR_DATA_PERR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1,

TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('SPRITE_PC_ERR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('SPRITE_PC_ADDR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('SPRITE_M_ES: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); ENDTRANSLATIONBLOCK TC BLOCK: 04a82012 SCID_FM_SPRITE_NEW_CMD_BAD_ERR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]

); ); ); ); );

TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('SPRITE_PC_ERR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('SPRITE_PC_ADDR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('SPRITE_M_ES: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); ENDTRANSLATIONBLOCK TC BLOCK: 04a92017 SCID_FM_SPRITE_CM_ECC_ERROR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]);

TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('SPRITE_PC_ERR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('SPRITE_PC_ADDR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('SPRITE_M_ES: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('SPRITE_M_ESE: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('SPRITE_M_ESO: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('SPRITE_M_EAE: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('SPRITE_M_EAO: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('SPRITE_M_ESC: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); ENDTRANSLATIONBLOCK TC BLOCK: 04aa2013 SCID_FM_PCIX_NO_BOF_INVAL_DEST TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]);

TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('SPRITE_PCIX_BUS_0_or_1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('SPRITE_Pn_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('SPRITE_Pn_CSR2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('SPRITE_Pn_EDR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); ENDTRANSLATIONBLOCK TC BLOCK: 04ab2013 SCID_FM_PCIX_XACTN_LEN_MISMATCH TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('SPRITE_PCIX_BUS_0_or_1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('SPRITE_Pn_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('SPRITE_Pn_CSR2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('SPRITE_Pn_EDR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); ENDTRANSLATIONBLOCK

TC BLOCK: 04ac3913 SCID_FM_PCIX_XACTN_ENTRY_RPERR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('SPRITE_PCIX_BUS_0_or_1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('SPRITE_Pn_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('SPRITE_Pn_CSR2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('SPRITE_Pn_EDR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); ENDTRANSLATIONBLOCK TC BLOCK: 04ad0112 SCID_FM_PCIX_BITE_COUNT_MISMATCH TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]

); ); ); ); );

TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('SPRITE_PCIX_BUS_0_or_1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('SPRITE_Pn_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('SPRITE_Pn_CSR2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('SPRITE_Pn_EDR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); ENDTRANSLATIONBLOCK TC BLOCK: 04ae0112 SCID_FM_PCIX_TARGT_RCNT_EXCEEDED TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('SPRITE_PCIX_BUS_0_or_1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]);

TRANSLATE('SPRITE_Pn_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('SPRITE_Pn_CSR2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('SPRITE_Pn_EDR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); ENDTRANSLATIONBLOCK TC BLOCK: 04af0112 SCID_FM_PCIX_INITR_RCNT_EXCEEDED TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('SPRITE_PCIX_BUS_0_or_1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('SPRITE_Pn_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('SPRITE_Pn_CSR2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('SPRITE_Pn_EDR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); ENDTRANSLATIONBLOCK TC BLOCK: 04b00112 SCID_FM_PCIX_SC_COUNT_EXCEEDED TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]

); ); ); ); );

TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('SPRITE_PCIX_BUS_0_or_1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('SPRITE_Pn_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('SPRITE_Pn_CSR2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('SPRITE_Pn_EDR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); ENDTRANSLATIONBLOCK TC BLOCK: 04b10112 SCID_FM_PCIX_SC_ERR_MSG_RCVD TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('SPRITE_PCIX_BUS_0_or_1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]);

TRANSLATE('SPRITE_Pn_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('SPRITE_Pn_CSR2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('SPRITE_Pn_EDR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); ENDTRANSLATIONBLOCK TC BLOCK: 04b20112 SCID_FM_PCIX_UNEXPECTED_SC TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('SPRITE_PCIX_BUS_0_or_1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('SPRITE_Pn_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('SPRITE_Pn_CSR2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('SPRITE_Pn_EDR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); ENDTRANSLATIONBLOCK TC BLOCK: 04b30112 SCID_FM_PCIX_SC_INVAL_TERMINATN TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]

); ); ); ); );

TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('SPRITE_PCIX_BUS_0_or_1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('SPRITE_Pn_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('SPRITE_Pn_CSR2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('SPRITE_Pn_EDR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); ENDTRANSLATIONBLOCK TC BLOCK: 04b40112 SCID_FM_PCIX_SC_WO_PREV_SR TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('SPRITE_PCIX_BUS_0_or_1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]);

TRANSLATE('SPRITE_Pn_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('SPRITE_Pn_CSR2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('SPRITE_Pn_EDR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); ENDTRANSLATIONBLOCK TC BLOCK: 04b52013 SCID_FM_PCIX_PERR_ASSERTED TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('SPRITE_PCIX_BUS_0_or_1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('SPRITE_Pn_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('SPRITE_Pn_CSR2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('SPRITE_Pn_EDR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); ENDTRANSLATIONBLOCK TC BLOCK: 04b60113 SCID_FM_PCIX_BAD_ADDR TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] );

TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('SPRITE_PCIX_BUS_0_or_1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('SPRITE_Pn_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('SPRITE_Pn_CSR2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('SPRITE_Pn_EDR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('SPRITE_PC_ADDR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); ENDTRANSLATIONBLOCK TC BLOCK: 04b72013 SCID_FM_PCIX_RCVD_TARG_ABORT TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6]

); ); ); ); ); ); );

TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('SPRITE_PCIX_BUS_0_or_1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('SPRITE_Pn_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('SPRITE_Pn_CSR2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('SPRITE_Pn_EDR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); ENDTRANSLATIONBLOCK TC BLOCK: 04b82014 SCID_FM_PCIX_SERR_ASSERTED TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]);

TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('SPRITE_PCIX_BUS_0_or_1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('SPRITE_Pn_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('SPRITE_Pn_CSR2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('SPRITE_Pn_EDR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); ENDTRANSLATIONBLOCK TC BLOCK: 04b92013 SCID_FM_PCIX_SERR_DETECTED TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('SPRITE_PCIX_BUS_0_or_1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('SPRITE_Pn_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('SPRITE_Pn_CSR2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]);

TRANSLATE('SPRITE_Pn_EDR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); ENDTRANSLATIONBLOCK TC BLOCK: 04ba011c SCID_FM_TACH_UNSUP_BYTE_ENA_ERR TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('REAL_PORT_NUMBER: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('TACHn_PCI_REG_1FC: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('SPRITE_PC_ADDR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('TACHn_TACH_CONTROL: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('TACHn_FM_STATUSS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('TACHn_FM_LINK_STAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('TACHn_FM_LINK_STAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('TACHn_FM_LINK_STAT3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('TACHn_FM_CONFIG1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('TACHn_FM_CONFIG2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('TACHn_FM_CONFIG3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('TACHn_INBOUND_RSTAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('TACHn_INBOUND_RSTAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]);

TRANSLATE('TACHn_FM_RCVD_AL_PA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); ENDTRANSLATIONBLOCK TC BLOCK: 04bb391c SCID_FM_TACH_OUTBOUND_PERR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('REAL_PORT_NUMBER: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('TACHn_TACH_STATUS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('TACHn_TACH_CONTROL: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('TACHn_FM_STATUSS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('TACHn_FM_LINK_STAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('TACHn_FM_LINK_STAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('TACHn_FM_LINK_STAT3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('TACHn_FM_CONFIG1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('TACHn_FM_CONFIG2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]);

TRANSLATE('TACHn_FM_CONFIG3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('TACHn_INBOUND_RSTAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('TACHn_INBOUND_RSTAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('TACHn_FM_RCVD_AL_PA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); ENDTRANSLATIONBLOCK TC BLOCK: 04bc391c SCID_FM_TACH_INBOUND_PERR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('REAL_PORT_NUMBER: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('TACHn_TACH_STATUS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('TACHn_TACH_CONTROL: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('TACHn_FM_STATUSS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('TACHn_FM_LINK_STAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('TACHn_FM_LINK_STAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]);

TRANSLATE('TACHn_FM_LINK_STAT3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('TACHn_FM_CONFIG1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('TACHn_FM_CONFIG2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('TACHn_FM_CONFIG3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('TACHn_INBOUND_RSTAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('TACHn_INBOUND_RSTAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('TACHn_FM_RCVD_AL_PA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); ENDTRANSLATIONBLOCK TC BLOCK: 04bd201d SCID_FM_TACH_DETECTED_PERR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('REAL_PORT_NUMBER: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('TACHn_PCICFG_REG_04: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('SPRITE_PC_ADDR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]);

TRANSLATE('TACHn_TACH_CONTROL: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('TACHn_FM_STATUSS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('TACHn_FM_LINK_STAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('TACHn_FM_LINK_STAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('TACHn_FM_LINK_STAT3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('TACHn_FM_CONFIG1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('TACHn_FM_CONFIG2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('TACHn_FM_CONFIG3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('TACHn_INBOUND_RSTAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('TACHn_INBOUND_RSTAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('TACHn_FM_RCVD_AL_PA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); ENDTRANSLATIONBLOCK TC BLOCK: 04be201d SCID_FM_TACH_SIGNALED_SERR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]);

TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('REAL_PORT_NUMBER: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('TACHn_PCICFG_REG_04: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('SPRITE_PC_ADDR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('TACHn_TACH_CONTROL: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('TACHn_FM_STATUSS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('TACHn_FM_LINK_STAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('TACHn_FM_LINK_STAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('TACHn_FM_LINK_STAT3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('TACHn_FM_CONFIG1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('TACHn_FM_CONFIG2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('TACHn_FM_CONFIG3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('TACHn_INBOUND_RSTAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('TACHn_INBOUND_RSTAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('TACHn_FM_RCVD_AL_PA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); ENDTRANSLATIONBLOCK TC BLOCK: 04bf011c SCID_FM_TACH_RECEIVED_MABORT TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]);

TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('REAL_PORT_NUMBER: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('TACHn_PCICFG_REG_04: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('SPRITE_PC_ADDR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('TACHn_TACH_CONTROL: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('TACHn_FM_STATUSS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('TACHn_FM_LINK_STAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('TACHn_FM_LINK_STAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('TACHn_FM_LINK_STAT3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('TACHn_FM_CONFIG1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('TACHn_FM_CONFIG2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('TACHn_FM_CONFIG3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('TACHn_INBOUND_RSTAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('TACHn_INBOUND_RSTAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('TACHn_FM_RCVD_AL_PA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); ENDTRANSLATIONBLOCK TC BLOCK: 04c0201d SCID_FM_TACH_RECEIVED_TABORT TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9]

); ); ); ); ); ); ); ); ); );

TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('REAL_PORT_NUMBER: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('TACHn_PCICFG_REG_04: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('SPRITE_PC_ADDR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('TACHn_TACH_CONTROL: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('TACHn_FM_STATUSS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('TACHn_FM_LINK_STAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('TACHn_FM_LINK_STAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('TACHn_FM_LINK_STAT3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('TACHn_FM_CONFIG1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('TACHn_FM_CONFIG2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('TACHn_FM_CONFIG3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('TACHn_INBOUND_RSTAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('TACHn_INBOUND_RSTAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('TACHn_FM_RCVD_AL_PA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); ENDTRANSLATIONBLOCK TC BLOCK: 04c1201d SCID_FM_TACH_SIGNALED_TABORT TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]

); ); ); ); ); );

TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('REAL_PORT_NUMBER: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('TACHn_PCICFG_REG_04: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('SPRITE_PC_ADDR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('TACHn_TACH_CONTROL: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('TACHn_FM_STATUSS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('TACHn_FM_LINK_STAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('TACHn_FM_LINK_STAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('TACHn_FM_LINK_STAT3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('TACHn_FM_CONFIG1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('TACHn_FM_CONFIG2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('TACHn_FM_CONFIG3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('TACHn_INBOUND_RSTAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('TACHn_INBOUND_RSTAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('TACHn_FM_RCVD_AL_PA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); ENDTRANSLATIONBLOCK TC BLOCK: 04c2201d SCID_FM_TACH_MASTER_DATA_PERR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] );

TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('REAL_PORT_NUMBER: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('TACHn_PCICFG_REG_04: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('SPRITE_PC_ADDR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('TACHn_TACH_CONTROL: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('TACHn_FM_STATUSS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('TACHn_FM_LINK_STAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('TACHn_FM_LINK_STAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('TACHn_FM_LINK_STAT3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('TACHn_FM_CONFIG1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('TACHn_FM_CONFIG2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('TACHn_FM_CONFIG3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('TACHn_INBOUND_RSTAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('TACHn_INBOUND_RSTAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('TACHn_FM_RCVD_AL_PA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); ENDTRANSLATIONBLOCK TC BLOCK: 04c3011c SCID_FM_TACH_UNEXP_SC_ERROR TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] );

TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('REAL_PORT_NUMBER: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('TACHn_PCI_X_S: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('TACHn_ESCR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('TACHn_TACH_CONTROL: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('TACHn_FM_STATUSS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('TACHn_FM_LINK_STAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('TACHn_FM_LINK_STAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('TACHn_FM_LINK_STAT3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('TACHn_FM_CONFIG1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('TACHn_FM_CONFIG2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('TACHn_FM_CONFIG3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('TACHn_INBOUND_RSTAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('TACHn_INBOUND_RSTAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('TACHn_FM_RCVD_AL_PA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); ENDTRANSLATIONBLOCK TC BLOCK: 04c4011c SCID_FM_TACH_SC_DISCARDED_ERROR TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] );

TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('REAL_PORT_NUMBER: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('TACHn_PCI_X_S: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('TACHn_ESCR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('TACHn_TACH_CONTROL: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('TACHn_FM_STATUSS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('TACHn_FM_LINK_STAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('TACHn_FM_LINK_STAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('TACHn_FM_LINK_STAT3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('TACHn_FM_CONFIG1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('TACHn_FM_CONFIG2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('TACHn_FM_CONFIG3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('TACHn_INBOUND_RSTAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('TACHn_INBOUND_RSTAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('TACHn_FM_RCVD_AL_PA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); ENDTRANSLATIONBLOCK TC BLOCK: 04c5391d SCID_FM_TACH_PERR_ON_SC_XACTION TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1,

TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('REAL_PORT_NUMBER: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('TACHn_FSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('TACHn_ESCR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('TACHn_TACH_CONTROL: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('TACHn_FM_STATUSS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('TACHn_FM_LINK_STAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('TACHn_FM_LINK_STAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('TACHn_FM_LINK_STAT3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('TACHn_FM_CONFIG1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('TACHn_FM_CONFIG2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('TACHn_FM_CONFIG3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('TACHn_INBOUND_RSTAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('TACHn_INBOUND_RSTAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]);

TRANSLATE('TACHn_FM_RCVD_AL_PA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); ENDTRANSLATIONBLOCK TC BLOCK: 04c6391d SCID_FM_TACH_PERR_ON_IN_DATA TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('REAL_PORT_NUMBER: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('TACHn_FSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('TACHn_ESCR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('TACHn_TACH_CONTROL: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('TACHn_FM_STATUSS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('TACHn_FM_LINK_STAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('TACHn_FM_LINK_STAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('TACHn_FM_LINK_STAT3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('TACHn_FM_CONFIG1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]);

TRANSLATE('TACHn_FM_CONFIG2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('TACHn_FM_CONFIG3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('TACHn_INBOUND_RSTAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('TACHn_INBOUND_RSTAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('TACHn_FM_RCVD_AL_PA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); ENDTRANSLATIONBLOCK TC BLOCK: 04c7391d SCID_FM_TACH_PERR_ON_OUT_DATA TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('REAL_PORT_NUMBER: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('TACHn_FSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('TACHn_ESCR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('TACHn_TACH_CONTROL: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('TACHn_FM_STATUSS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]);

TRANSLATE('TACHn_FM_LINK_STAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('TACHn_FM_LINK_STAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('TACHn_FM_LINK_STAT3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('TACHn_FM_CONFIG1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('TACHn_FM_CONFIG2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('TACHn_FM_CONFIG3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('TACHn_INBOUND_RSTAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('TACHn_INBOUND_RSTAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('TACHn_FM_RCVD_AL_PA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); ENDTRANSLATIONBLOCK TC BLOCK: 04c8201d SCID_FM_TACH_ATTRIBUTE_PERR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('REAL_PORT_NUMBER: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]);

TRANSLATE('TACHn_FSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('TACHn_ESCR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('TACHn_TACH_CONTROL: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('TACHn_FM_STATUSS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('TACHn_FM_LINK_STAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('TACHn_FM_LINK_STAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('TACHn_FM_LINK_STAT3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('TACHn_FM_CONFIG1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('TACHn_FM_CONFIG2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('TACHn_FM_CONFIG3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('TACHn_INBOUND_RSTAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('TACHn_INBOUND_RSTAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('TACHn_FM_RCVD_AL_PA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); ENDTRANSLATIONBLOCK TC BLOCK: 04c9011c SCID_FM_TACH_SC_BYTE_CNT_EXCESS TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('REAL_PORT_NUMBER: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]);

TRANSLATE('TACHn_FSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('TACHn_ESCR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('TACHn_TACH_CONTROL: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('TACHn_FM_STATUSS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('TACHn_FM_LINK_STAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('TACHn_FM_LINK_STAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('TACHn_FM_LINK_STAT3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('TACHn_FM_CONFIG1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('TACHn_FM_CONFIG2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('TACHn_FM_CONFIG3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('TACHn_INBOUND_RSTAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('TACHn_INBOUND_RSTAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('TACHn_FM_RCVD_AL_PA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); ENDTRANSLATIONBLOCK TC BLOCK: 04ca011c SCID_FM_TACH_RD_BYTE_CNT_EXCESS TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('REAL_PORT_NUMBER: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]);

TRANSLATE('TACHn_FSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('TACHn_ESCR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('TACHn_TACH_CONTROL: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('TACHn_FM_STATUSS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('TACHn_FM_LINK_STAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('TACHn_FM_LINK_STAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('TACHn_FM_LINK_STAT3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('TACHn_FM_CONFIG1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('TACHn_FM_CONFIG2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('TACHn_FM_CONFIG3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('TACHn_INBOUND_RSTAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('TACHn_INBOUND_RSTAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('TACHn_FM_RCVD_AL_PA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); ENDTRANSLATIONBLOCK TC BLOCK: 04cb011c SCID_FM_TACH_READ_FIFO_PERR TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('REAL_PORT_NUMBER: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]);

TRANSLATE('TACHn_FSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('TACHn_ESCR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('TACHn_TACH_CONTROL: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('TACHn_FM_STATUSS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('TACHn_FM_LINK_STAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('TACHn_FM_LINK_STAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('TACHn_FM_LINK_STAT3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('TACHn_FM_CONFIG1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('TACHn_FM_CONFIG2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('TACHn_FM_CONFIG3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('TACHn_INBOUND_RSTAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('TACHn_INBOUND_RSTAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('TACHn_FM_RCVD_AL_PA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); ENDTRANSLATIONBLOCK TC BLOCK: 04cc011c SCID_FM_TACH_WRITE_FIFO_PERR TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('REAL_PORT_NUMBER: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]);

TRANSLATE('TACHn_FSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('TACHn_ESCR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('TACHn_TACH_CONTROL: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('TACHn_FM_STATUSS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('TACHn_FM_LINK_STAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('TACHn_FM_LINK_STAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('TACHn_FM_LINK_STAT3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('TACHn_FM_CONFIG1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('TACHn_FM_CONFIG2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('TACHn_FM_CONFIG3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('TACHn_INBOUND_RSTAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('TACHn_INBOUND_RSTAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('TACHn_FM_RCVD_AL_PA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); ENDTRANSLATIONBLOCK TC BLOCK: 04cd011c SCID_FM_TACH_RSVD_REGION_ACCESS TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('REAL_PORT_NUMBER: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]);

TRANSLATE('TACHn_GSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('SPRITE_PC_ADDR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('TACHn_TACH_CONTROL: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('TACHn_FM_STATUSS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('TACHn_FM_LINK_STAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('TACHn_FM_LINK_STAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('TACHn_FM_LINK_STAT3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('TACHn_FM_CONFIG1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('TACHn_FM_CONFIG2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('TACHn_FM_CONFIG3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('TACHn_INBOUND_RSTAT1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('TACHn_INBOUND_RSTAT2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('TACHn_FM_RCVD_AL_PA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); ENDTRANSLATIONBLOCK TC BLOCK: 04ce010e SCID_FM_TACH_PERR_ON_SC TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); ENDTRANSLATIONBLOCK

TC BLOCK: 04cf011b SCID_FM_XL_UNDECODED_MC TRANSLATIONBLOCK TRANSLATE('SRR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SRR1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('MSSSR0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('GLUE_MCP_31_0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('GLUE_MCP_47_32: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('SPRITE_PC_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('TACH01_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('TACH23_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('TACH45_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TACH67_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TACH89_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TACH1011_CINTPEND: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('ATLANTIS_CPU_ERROR_CAUSE: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('ATLANTIS_CPU0_ERROR_MASK: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('ATLANTIS_CPU_ERROR_ADDRESS_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('ATLANTIS_CPU_ERROR_ADDRESS_HIGH: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('ATLANTIS_CPU_ERROR_DATA_LOW: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('ATLANTIS_CPU_ERROR_DATA_HIGH: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('ATLANTIS_CPU_ERROR_PARITY: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('SPRITE_P0_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('SPRITE_P0_CSR2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('SPRITE_P0_EDR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('SPRITE_P1_CSR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('SPRITE_P1_CSR2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('SPRITE_P1_EDR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); ENDTRANSLATIONBLOCK TC BLOCK: 04d00180 SCID_FM_MEALCP_INUSE TRANSLATIONBLOCK

ENDTRANSLATIONBLOCK TC BLOCK: 04e2096a SCID_FM_OFFLOAD_POWER_LOSS TRANSLATIONBLOCK TRANSLATE('Offload Event Code: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Offload Event Time: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('Generic Data Byte 0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Generic Data Byte 1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('Generic Data Byte 2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('Generic Data Byte 3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] TRANSLATE('Generic Data Byte 4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] TRANSLATE('Generic Data Byte 5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] TRANSLATE('Generic Data Byte 6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] TRANSLATE('Generic Data Byte 7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ENDTRANSLATIONBLOCK TC BLOCK: 04e3096a SCID_FM_OFFLOAD_CONTROLLER_REMOVED TRANSLATIONBLOCK TRANSLATE('Offload Event Code: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Offload Event Time: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('Generic Data Byte 0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Generic Data Byte 1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('Generic Data Byte 2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('Generic Data Byte 3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] TRANSLATE('Generic Data Byte 4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] TRANSLATE('Generic Data Byte 5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] TRANSLATE('Generic Data Byte 6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] TRANSLATE('Generic Data Byte 7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ENDTRANSLATIONBLOCK TC BLOCK: 04e4096a SCID_FM_OFFLOAD_WATCHDOG_EXPIRED TRANSLATIONBLOCK TRANSLATE('Offload Event Code: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Offload Event Time: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('Generic Data Byte 0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Generic Data Byte 1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3]

); ); ); ); ); ); ); ); ); );

); ); ); ); ); ); ); ); ); );

); ); ); );

TRANSLATE('Generic Data Byte 2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('Generic Data Byte 3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] TRANSLATE('Generic Data Byte 4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] TRANSLATE('Generic Data Byte 5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] TRANSLATE('Generic Data Byte 6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] TRANSLATE('Generic Data Byte 7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ENDTRANSLATIONBLOCK TC BLOCK: 04e5096a SCID_FM_OFFLOAD_UNEXPECTED_EVENT TRANSLATIONBLOCK TRANSLATE('Offload Event Code: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Offload Event Time: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('Generic Data Byte 0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Generic Data Byte 1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('Generic Data Byte 2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('Generic Data Byte 3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] TRANSLATE('Generic Data Byte 4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] TRANSLATE('Generic Data Byte 5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] TRANSLATE('Generic Data Byte 6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] TRANSLATE('Generic Data Byte 7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ENDTRANSLATIONBLOCK TC BLOCK: 04e80100 SCID_FM_SPRITE_CHECKSUM_FAILURE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK

); ); ); ); ); );

); ); ); ); ); ); ); ); ); );

TC BLOCK: 04f6013f SCID_FM_USERAPNDR_TEST TRANSLATIONBLOCK TRANSLATE('TP[0]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE('TP[1]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE('TP[2]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE('TP[3]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('TP[4]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('TP[5]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]); TRANSLATE('TP[6]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6]); TRANSLATE('TP[7]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7]);

TRANSLATE('TP[8]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8]); TRANSLATE('TP[9]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9]); TRANSLATE('TP[10]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TP[11]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TP[12]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TP[13]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TP[14]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('TP[15]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('TP[16]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('TP[17]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('TP[18]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('TP[19]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('TP[20]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('TP[21]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('TP[22]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('TP[23]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('TP[24]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('TP[25]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('TP[26]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('TP[27]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('TP[28]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('TP[29]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('TP[30]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 04f70000 SCID_FM_CTRL_Z_NOCC TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 04f9017f SCID_FM_POFF_TEST TRANSLATIONBLOCK TRANSLATE('TP[0]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE('TP[1]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE('TP[2]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2]);

TRANSLATE('TP[3]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('TP[4]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('TP[5]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]); TRANSLATE('TP[6]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6]); TRANSLATE('TP[7]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7]); TRANSLATE('TP[8]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8]); TRANSLATE('TP[9]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9]); TRANSLATE('TP[10]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TP[11]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TP[12]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TP[13]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TP[14]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('TP[15]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('TP[16]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('TP[17]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('TP[18]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('TP[19]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('TP[20]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('TP[21]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('TP[22]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('TP[23]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('TP[24]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('TP[25]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('TP[26]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('TP[27]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('TP[28]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('TP[29]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('TP[30]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 04fa0100 SCID_FM_USERNP_TEST TRANSLATIONBLOCK

ENDTRANSLATIONBLOCK TC BLOCK: 04fb011f SCID_FM_USERAP_TEST TRANSLATIONBLOCK TRANSLATE('TP[0]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE('TP[1]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE('TP[2]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE('TP[3]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('TP[4]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('TP[5]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]); TRANSLATE('TP[6]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6]); TRANSLATE('TP[7]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7]); TRANSLATE('TP[8]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8]); TRANSLATE('TP[9]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9]); TRANSLATE('TP[10]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TP[11]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TP[12]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TP[13]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TP[14]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('TP[15]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('TP[16]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('TP[17]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('TP[18]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('TP[19]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('TP[20]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('TP[21]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('TP[22]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('TP[23]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('TP[24]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('TP[25]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('TP[26]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('TP[27]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]);

TRANSLATE('TP[28]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('TP[29]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('TP[30]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 04fc0100 SCID_FM_ISRNP_TEST TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 04fd011f SCID_FM_ISRAP_TEST TRANSLATIONBLOCK TRANSLATE('TP[0]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE('TP[1]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE('TP[2]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE('TP[3]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('TP[4]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('TP[5]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]); TRANSLATE('TP[6]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6]); TRANSLATE('TP[7]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7]); TRANSLATE('TP[8]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8]); TRANSLATE('TP[9]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9]); TRANSLATE('TP[10]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('TP[11]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('TP[12]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('TP[13]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('TP[14]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('TP[15]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('TP[16]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('TP[17]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('TP[18]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('TP[19]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('TP[20]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('TP[21]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('TP[22]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]);

TRANSLATE('TP[23]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('TP[24]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('TP[25]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('TP[26]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('TP[27]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('TP[28]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('TP[29]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('TP[30]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 04fe0100 SCID_FM_NYI TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 04ff011f SCID_FM_OLD_STYLE_BUGCHECK TRANSLATIONBLOCK TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Undefined: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SRR1 (machine state): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Link Register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Stack Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('R31: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('R30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('R29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('R28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('R27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('R26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('R25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('R24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('R23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('R22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('R21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('R20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('R19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]);

TRANSLATE('R18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('R17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('R16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('R12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('R11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('R10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('R9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('R8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('R7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('R6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('R5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('R4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('R3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 06040100 SCID_FCS_INIT_MEM_SFQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 06150100 SCID_FCS_INIT_FCS_DUMP TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 061c0100 SCID_FCS_INIT_MEM_IBQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 06280100 SCID_FCS_INVAL_PORT_EVENT_TYPE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 06290100 SCID_FCS_UNKNOWN_FED_TYPE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 062a0100 SCID_FCS_UNKNOWN_LDN_FED TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 062b0100 SCID_FCS_START_TIMER_FAIL TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 062c0100 SCID_FCS_UNKNOWN_TIMER_STATE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK

TC BLOCK: 062f0100 SCID_FCS_UNKNOWN_EXCH_TYPE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 06320100 SCID_FCS_PORT_OFFLINE_FAIL TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 06330100 SCID_FCS_OUT_RESERVED_FEDS TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 06340100 SCID_FCS_UNSUPPORTED_ELS TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 06360100 SCID_FCS_UNSUPPORTED_DRIVE_INIT TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 063c0100 SCID_FCS_LBA_RANGE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 06480100 SCID_FCS_INIT_MEM_ENC_MGT_REQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 065a010e SCID_FCS_TSDK_ASSERT TRANSLATIONBLOCK TRANSLATE('tsdk_nport_id[0]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('link_state[0]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('tsdk_state[0]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('tsdk_port_state[0]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('tsdk_discover_state[0]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('tsdk_discover_count[0]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('fm_statuss[0]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('tsdk_nport_id[1]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('link_state[1]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('tsdk_state[1]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('tsdk_port_state[1]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('tsdk_discover_state[1]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('tsdk_discover_count[1]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('fm_statuss[1]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); ENDTRANSLATIONBLOCK

TC BLOCK: 07000100 SCID_CS_INSUFF_MEM TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07010100 SCID_CS_LMAP_ALLOC_FAIL TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07020100 SCID_CS_LMAP_ALLOC_FAIL_2 TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07030100 SCID_CS_INVALID_RAID_TYPE_INIT TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07070100 SCID_CS_QS_READ_FAIL_1 TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 070a0100 SCID_CS_RSD_ALLOC_FAIL TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 070b0100 SCID_CS_BAD_REF_COUNT TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 070c0100 SCID_CS_INVALID_OBJECT_FOR_IO TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 070d0100 SCID_CS_INVALID_IO_RANGE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07130100 SCID_CS_INVALID_RS_RAID_TYPE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07150100 SCID_CS_INVALID_STRUCT_LDSBZQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07160100 SCID_CS_INVALID_STRUCT_ODWORKQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07170100 SCID_CS_PBUFF_LEAK TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07190100 SCID_CS_NOT_IMPLEMENTED TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 071a0102 SCID_CS_WRONG_LDSB TRANSLATIONBLOCK TRANSLATE('Expected NOID : 0x%04x', teb.u.data.ltei.lter.termination_event.params.param[0]);

TRANSLATE('Received NOID : 0x%04x', teb.u.data.ltei.lter.termination_event.params.param[1]); ENDTRANSLATIONBLOCK TC BLOCK: 071b0100 SCID_CS_WRONG_LDAD_LABORT TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 071c0100 SCID_CS_INVALID_RM_MAP_TYPE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 071d0100 SCID_CS_RM_CACHE_HIT TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 071e0100 SCID_CS_INVALID_PSEG_USAGE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 071f0100 SCID_CS_BAD_OBJ_CLASS_REG_REP TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07200100 SCID_CS_NO_CMAPS TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07220100 SCID_CS_INVALID_CS_REQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07240100 SCID_CS_NO_REQS TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07260100 SCID_CS_BAD_VOLNOID TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 072a0100 SCID_CS_TRANS_RECOV_FAIL TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 072b0100 SCID_CS_RECOV_INVALID_TRANS_TYPE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 072d0100 SCID_CS_NO_TRANS_DETECTED TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 072f0100 SCID_CS_ZERO_BAD_MEM_STATE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07300100 SCID_CS_REGENS_NOT_COMPLETE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK

TC BLOCK: 07340100 SCID_CS_BAD_OBJ_HANDLE_REQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07350100 SCID_CS_INVALID_OP_REQ_HANDLER1 TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07370100 SCID_CS_BAD_VOLNOID_SPARING TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07380100 SCID_CS_NO_XDS TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07390100 SCID_CS_INVALID_RTYPE_REGREASS TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 073b0100 SCID_CS_UNKNOWN_TRANS_TYPE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 073c0100 SCID_CS_TRANS_INCONSISTENCY TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 073e0100 SCID_CS_INVALID_STRUCT_LEVELLDQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 073f0100 SCID_CS_INVALID_STRUCT_SPARERSQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07400100 SCID_CS_INVALID_STRUCT_CSREQQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07410100 SCID_CS_INVALID_STRUCT_PLDMCQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07420100 SCID_CS_NO_RLBS TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07430100 SCID_CS_BAD_RLB_LIST TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07440100 SCID_CS_BAD_RLB_STATE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07450100 SCID_CS_INVALID_STRUCT_CSLDQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK

TC BLOCK: 07460100 SCID_CS_INVALID_STRUCT_CSEBITQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07480100 SCID_CS_NONMASTER_QSIO TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07490100 SCID_CS_NONMASTER_CSLDIO TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 074a0100 SCID_CS_INVALID_STRUCT_ACBWQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 074b0100 SCID_CS_INVALID_ACBW_OPCODE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 074c0100 SCID_CS_INVALID_STRUCT_MAINUNSHQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 074f0100 SCID_CS_INVALID_STRUCT_MIGRATE_WORKQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07500100 SCID_CS_INVALID_STRUCT_MIGRATE_RSQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07510100 SCID_CS_BAD_MEM_STATE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07520100 SCID_CS_INOPERATIVE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07530100 SCID_CS_INVALID_STRUCT_ALB_LIST TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07540114 SCID_CS_RSTORE_NOT_UTILIZED_IN_MAP TRANSLATIONBLOCK TRANSLATE('NOID : 0x%04x', teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE('PLDMC: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE('OP : 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE('rsdm offset : 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('pseg 0 : 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('orig pseg 0 : 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]); TRANSLATE('pseg 1 : 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6]);

TRANSLATE('orig pseg 1 : 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7]); TRANSLATE('pseg 2 : 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8]); TRANSLATE('orig pseg 2 : 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9]); TRANSLATE('pseg 3 : 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('orig pseg 3 : 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('pseg 4 : 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('orig pseg 4 : 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('pseg 5 : 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('orig pseg 5 : 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('pseg 6 : 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('orig pseg 6 : 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('pseg 7 : 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('orig pseg 7 : 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); ENDTRANSLATIONBLOCK TC BLOCK: 07550100 SCID_CS_INVALID_STRUCT_ALLOC_WQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07570100 SCID_CS_REALIZE_FAILED TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07580100 SCID_CS_UNREALIZE_FAILED TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 075a0100 SCID_CS_TEST_CRASH TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 075b0104 SCID_CS_IO_FAILURE TRANSLATIONBLOCK TRANSLATE('NOID : 0x%04x', teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE('Base LBA: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE('ID/LBA : 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE('Status : 0x%02x', teb.u.data.ltei.lter.termination_event.params.param[3]); ENDTRANSLATIONBLOCK TC BLOCK: 075d0100 SCID_CS_INVALID_STRUCT_CSCBITQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK

TC BLOCK: 075e0100 SCID_CS_INVALID_STRUCT_MAINODBGALOCQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 075f0100 SCID_CS_BAD_DUB_RSS TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07600100 SCID_CS_INVALID_LD_TYPE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07610100 SCID_CS_BAD_DIP_STATE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07620100 SCID_CS_DEALLOC_PSEG_FAILURE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07630100 SCID_CS_RESERVED_CAPACITY_FAILURE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07640100 SCID_CS_INVALID_STRUCT_REBUILD_PARITY TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07650100 SCID_CS_INVALID_STATUS TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07680100 SCID_CS_MEMBER_REMOVED_FROM_RSS TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07690102 SCID_CS_BAD_MEMBER_MANAGER_STATE TRANSLATIONBLOCK TRANSLATE('Volume NOID: 0x%04x', teb.u.data.ltei.lter.termination_event.params.param[0] ); CONDITIONAL(teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('MM Op: IDLE') ); CONDITIONAL(teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('MM Op: REGEN S') ); CONDITIONAL(teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('MM Op: REGEN D') ); CONDITIONAL(teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('MM Op: REPLACE S') ); CONDITIONAL(teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('MM Op: REPLACE D') ); CONDITIONAL(teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('MM Op: RESTORE S') ); CONDITIONAL(teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('MM Op: REVERT')

== 0, == 1, == 2, == 3, == 4, == 5, == 6,

); CONDITIONAL(teb.u.data.ltei.lter.termination_event.params.param[1] == 7, TRANSLATE('MM Op: INIT') ); ENDTRANSLATIONBLOCK TC BLOCK: 076a0100 SCID_CS_NO_QUORUM_DISKS TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 076b0100 SCID_CS_INVALID_PSEG_ALLOC_TYPE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 076c0100 SCID_CS_XMFC_FAILURE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 076d0100 SCID_CS_INVALID_XMFC_OPERATION TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07700105 SCID_CS_CHKDSK_FAILED TRANSLATIONBLOCK TRANSLATE('Status: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Op Code: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('Error Count: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Error Bits[0]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('Error Bits[1]: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ENDTRANSLATIONBLOCK TC BLOCK: 07710100 SCID_CS_INVALID_STRUCT_MAINRESYNCQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07720100 SCID_CS_RESYNC_CONTROL_NOT_FOUND TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 07730100 SCID_CS_UNEXPECTED_RSD TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0775011a SCID_CS_UNEXPECTED_REALIZE TRANSLATIONBLOCK TRANSLATE('ld noid: 0x%04x', teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE('ref count: %d', teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE('sref count: %d', teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE('vd noid: 0x%04x', teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('pred noid: 0x%04x', teb.u.data.ltei.lter.termination_event.params.param[4]);

); ); ); ); );

TRANSLATE('succ noid: 0x%04x', teb.u.data.ltei.lter.termination_event.params.param[5]); TRANSLATE('vd scmi cond: %d', teb.u.data.ltei.lter.termination_event.params.param[6]); TRANSLATE('vd scmi type: %d', teb.u.data.ltei.lter.termination_event.params.param[7]); TRANSLATE('scvd cond: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8]); TRANSLATE('vdsb flags: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9]); TRANSLATE('vflags: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('data lost: 0x%04x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('ldad noid: 0x%04x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('pref nsc: %d', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('ult succ vd noid: 0x%04x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('ult succ ld noid: 0x%04x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('ult succ ref count: %d', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('ult succ pref count: %d', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('ult succ tref count: %d', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('ult succ uref count: %d', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('ult succ sref count: %d', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('ult succ pref nsc: %d', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('ult succ dr group ptr: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('ult succ duck: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('ult succ group noid: 0x%04x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('ult succ group mode: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); ENDTRANSLATIONBLOCK TC BLOCK: 07760120 SCID_CS_TEST_CRASH_NO_DUMP TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 08010100 SCID_RS_BAD_EBIT_STATUS TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 08020100 SCID_RS_BAD_MEMBER_STATE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 08030100 SCID_RS_BAD_RAID_TYPE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK

TC BLOCK: 08040100 SCID_RS_REWRITE_UNSUPPORTED TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 08070100 SCID_RS_CANT_ALLOCATE_MEM TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 08080100 SCID_RS_UNSUPPORTED_STRUCT TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 08110120 SCID_RS_TEST_CRASH_NO_DUMP TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 09010100 SCID_SCMI_BQ_NO_MEM TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 09040100 SCID_SCMI_INTERNAL_ERROR TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 09060100 SCID_SCMI_RES_BUF_NO_MEM TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 09080100 SCID_SCMI_CMDLCK_NO_MEM TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 09090100 SCID_SCMI_CMDLCK_INIT_FAIL TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0b000100 SCID_SYS_BAD_XMFC_RESPONSE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0b010100 SCID_SYS_BAD_MFC_VECTOR TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0b020100 SCID_SYS_BAD_SACB_STATE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0b040100 SCID_SYS_BAD_UTIL_STATE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0b052001 SCID_SYS_EEPROM_FAILURE TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) );

TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 0b062001 SCID_SYS_UUID_RANGE_OVERFLOW TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 0b080100 SCID_SYS_RESYNC_NOT_ALLOWED TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0b092003 SCID_SYS_LCD_FAILURE TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Failure status: %d', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('Message code: %d', teb.u.data.ltei.lter.termination_event.params.param[2] ); ENDTRANSLATIONBLOCK TC BLOCK: 0b0a0100 SCID_SYS_BAD_XMFC_STATE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0b0f0122 SCID_SYS_FILE_TOO_BIG TRANSLATIONBLOCK TRANSLATE('File size: %d.', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Code load buffer size: %d.', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 0b100021 SCID_SYS_GLUE_CODE_RELOAD TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK

TC BLOCK: 0b110020 SCID_SYS_RESYNC_NOW TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0b130021 SCID_SYS_SPRITE_CODE_RELOAD TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 0b140021 SCID_SYS_GLUE_SPRITE_CODE_RELOAD TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 0b150020 SCID_SYS_ALLOW_PART_RELOAD TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0b16f060 SCID_SYS_CODE_LOAD_DENIED_1GB TRANSLATIONBLOCK TRANSLATE( 'Master controllers code is incompatible with this hardware.' ); TRANSLATE( 'Upgrade the master controller before restarting this controller.' ); ENDTRANSLATIONBLOCK TC BLOCK: 0c010102 SCID_DRM_INVALID_DDS TRANSLATIONBLOCK TRANSLATE('MFC Status: %d', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('DDS State: %d', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c03010e SCID_DRM_INVALID_GSB_DELETE_STATE TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %08x %08x %08x %08x', teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('Group state (should be 0): %d', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('EETBs held to acknowledge (should be 0): %d',

teb.u.data.ltei.lter.termination_event.params.param[5]); TRANSLATE('EETBs Held To Receive (should be 0): %d', teb.u.data.ltei.lter.termination_event.params.param[6]); TRANSLATE('Member List (should be 0): %d', teb.u.data.ltei.lter.termination_event.params.param[7]); TRANSLATE('Member Count (should be 0): %d', teb.u.data.ltei.lter.termination_event.params.param[8]); TRANSLATE('Control Waiter (should be 0): %d', teb.u.data.ltei.lter.termination_event.params.param[9]); TRANSLATE('Control Wait List empty (should be 1): %d', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('Copy In Progress (should be 0): %d', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('Held write response (should be 0): %d', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('Held MNODESs (should be 0): %d', teb.u.data.ltei.lter.termination_event.params.param[13]); ENDTRANSLATIONBLOCK TC BLOCK: 0c040101 SCID_DRM_RECOVERY_WRITE_DUPLICATE TRANSLATIONBLOCK TRANSLATE('Group Sequence Number: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0]); ENDTRANSLATIONBLOCK TC BLOCK: 0c050106 SCID_DRM_RECOVERY_WRITE_NOT_CACHED TRANSLATIONBLOCK TRANSLATE('LDSB: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE('Group Sequence Number: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE('Block Address: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE('Blocks: %d', teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('Cache Node: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('Status: %d', teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0c060106 SCID_DRM_RECOVERY_WRITE_NOT_DIRTY TRANSLATIONBLOCK TRANSLATE('LDSB: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE('Group Sequence Number: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE('Block Address: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE('Blocks: %d', teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('Cache Node: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('Cache Node State: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0c070106 SCID_DRM_RECOVERY_WRITE_LOST_GNODE TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %08x %08x %08x %08x',

teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('GSN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('State: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0c080106 SCID_DRM_INVALID_SCRAG_MIRROR_RIE TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %08x %08x %08x %08x', teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('RIE Address: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('RIE State Field: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0c090106 SCID_DRM_INVALID_SCRAG_MIRROR_MEMBERS TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %08x %08x %08x %08x', teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('Online count: %d', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('GCA Entry Address: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0c0a0106 SCID_DRM_INVALID_SCRAG_PRIMARY_RIE TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %08x %08x %08x %08x', teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('RIE Address: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('RIE State (should be 0): %d', teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0c0b0106 SCID_DRM_INVALID_SCRAG_PRIMARY_MEMBERS TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %08x %08x %08x %08x', teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('Online count: %d', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('GCA Entry Address: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]);

ENDTRANSLATIONBLOCK TC BLOCK: 0c0c0104 SCID_DRM_INVALID_GSB_DELETE_IO TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %08x %08x %08x %08x', teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); ENDTRANSLATIONBLOCK TC BLOCK: 0c0d0104 SCID_DRM_INVALID_GSB_INSERT TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %08x %08x %08x %08x', teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); ENDTRANSLATIONBLOCK TC BLOCK: 0c0e0106 SCID_DRM_GSN_OUT_OF_SEQUENCE_1 TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %08x %08x %08x %08x', teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('GSN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('Expected GSN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0c0f0105 SCID_DRM_WRITE_LONG_E_SET_FAILED TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %08x %08x %08x %08x', teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('GSN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); ENDTRANSLATIONBLOCK TC BLOCK: 0c110105 SCID_DRM_LOST_GNODE TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %08x %08x %08x %08x', teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('GSN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); ENDTRANSLATIONBLOCK TC BLOCK: 0c130105 SCID_DRM_IO_FAILURE TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %08x %08x %08x %08x', teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1],

teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('Lock State: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); ENDTRANSLATIONBLOCK TC BLOCK: 0c140106 SCID_DRM_GSN_OUT_OF_SEQUENCE_2 TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %08x %08x %08x %08x', teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('GSN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('Expected GSN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0c150106 SCID_DRM_GSN_OUT_OF_SEQUENCE_3 TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %08x %08x %08x %08x', teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('GSN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('Expected GSN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0c160106 SCID_DRM_GSN_OUT_OF_SEQUENCE_4 TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %08x %08x %08x %08x', teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('GSN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('Expected GSN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0c170106 SCID_DRM_GSN_OUT_OF_SEQUENCE_5 TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %08x %08x %08x %08x', teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('GSN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('Expected GSN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0c180106 SCID_DRM_GSN_OUT_OF_SEQUENCE_6 TRANSLATIONBLOCK

TRANSLATE('Data Replication Group: %08x %08x %08x %08x', teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('GSN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('Expected GSN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0c190106 SCID_DRM_GSN_OUT_OF_SEQUENCE_7 TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %08x %08x %08x %08x', teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('GSN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('Expected GSN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0c1a0106 SCID_DRM_GSN_OUT_OF_SEQUENCE_8 TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %08x %08x %08x %08x', teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('GSN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('Expected GSN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0c1b0106 SCID_DRM_GSN_OUT_OF_SEQUENCE_9 TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %08x %08x %08x %08x', teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('GSN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('Expected GSN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0c1c0107 SCID_DRM_GSN_OUT_OF_SEQUENCE_10 TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %08x %08x %08x %08x', teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('GSN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('Expected GSN: 0x%08x',

teb.u.data.ltei.lter.termination_event.params.param[5]); TRANSLATE('RIE State (should be 0): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6]); ENDTRANSLATIONBLOCK TC BLOCK: 0c200106 SCID_DRM_GSN_OUT_OF_SEQUENCE_11 TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %08x %08x %08x %08x', teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('GSN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('Expected GSN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0c210113 SCID_DRM_GSN_OUT_OF_SEQUENCE_12 TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %08x %08x %08x %08x', teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('Group Online GSN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('GSN to use + Write Resources Per Bundle: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]); TRANSLATE('LOG Reset GSN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6]); TRANSLATE('GSN Received: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7]); TRANSLATE('GSN Receive: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8]); TRANSLATE('GSN Sent: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9]); TRANSLATE('First Member: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('Operation: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('LOG Flags 1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('LOG Flags 2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('LOG Flags 3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('Member GSN Sent: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('Log vdoi Reset GSN flag: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('DRM Req Data Reset GSN flag: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('Reset GSN reason: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); ENDTRANSLATIONBLOCK TC BLOCK: 0c220108 SCID_DRM_GSN_OUT_OF_SEQUENCE_13 TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %08x %08x %08x %08x',

teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('Group Online GSN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('Expected GSN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]); TRANSLATE('Group Mode: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6]); TRANSLATE('Log Flags: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7]); ENDTRANSLATIONBLOCK TC BLOCK: 0c230108 SCID_DRM_UNEXPECTED_UNIT_CACHE_STATE TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %08x %08x %08x %08x', teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('VDSB Presented state: %08x', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('VDSB Inoperative: %08x', teb.u.data.ltei.lter.termination_event.params.param[5]); TRANSLATE('Is vdoi online: %08x', teb.u.data.ltei.lter.termination_event.params.param[6]); TRANSLATE('Battery Cache Policy %08x', teb.u.data.ltei.lter.termination_event.params.param[7]); ENDTRANSLATIONBLOCK TC BLOCK: 0c240107 SCID_DRM_INVALID_SIDE TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %08x %08x %08x %08x', teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('GSN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('Requested Side: %d', teb.u.data.ltei.lter.termination_event.params.param[5]); TRANSLATE('Actual Side: %d', teb.u.data.ltei.lter.termination_event.params.param[6]); ENDTRANSLATIONBLOCK TC BLOCK: 0c270106 SCID_DRM_GSN_OUT_OF_SEQUENCE_14 TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %08x %08x %08x %08x', teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('GSN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('Expected GSN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0c280106 SCID_DRM_GSN_OUT_OF_SEQUENCE_15

TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %08x %08x %08x %08x', teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('GSN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('Expected GSN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0c290105 SCID_DRM_INVALID_DDS_ADD_MEMBER TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %08x %08x %08x %08x', teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('DDS State: %d', teb.u.data.ltei.lter.termination_event.params.param[4] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c2a0106 SCID_DRM_INVALID_DDS_ACK_DAS TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %08x %08x %08x %08x', teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('MFC Status: %d', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('DDS State: %d', teb.u.data.ltei.lter.termination_event.params.param[5] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c2b0102 SCID_DRM_INVALID_DDS_ACK_WAIT TRANSLATIONBLOCK TRANSLATE('MFC Status: %d', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('DDS State: %d', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c2c0102 SCID_DRM_INVALID_DDS_WAIT_DONE TRANSLATIONBLOCK TRANSLATE('MFC Status: %d', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('DDS State: %d', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c2d0105 SCID_DRM_INVALID_DDS_DAS_BUILD TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %08x %08x %08x %08x', teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('DDS State: %d',

teb.u.data.ltei.lter.termination_event.params.param[4] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c2e0105 SCID_DRM_INVALID_DDS_DSF_BUILD TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %08x %08x %08x %08x', teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('DDS State: %d', teb.u.data.ltei.lter.termination_event.params.param[4] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c2f0106 SCID_DRM_INVALID_DDS_DRRW_ACK TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %08x %08x %08x %08x', teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('MFC Status: %d', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('DDS State: %d', teb.u.data.ltei.lter.termination_event.params.param[5] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c300105 SCID_DRM_INVALID_DDS_DRRW_BUILD TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %08x %08x %08x %08x', teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('DDS State: %d', teb.u.data.ltei.lter.termination_event.params.param[4] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c310105 SCID_DRM_INVALID_DDS_GOB_BUILD TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %08x %08x %08x %08x', teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('DDS State: %d', teb.u.data.ltei.lter.termination_event.params.param[4] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c320101 SCID_DRM_INVALID_DDS_MAIN TRANSLATIONBLOCK TRANSLATE('DDS State: %d', teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c330103 SCID_DRM_INVALID_DDS_MANAGE TRANSLATIONBLOCK TRANSLATE('MFC function: %d', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('DDS Expected State: %d',

teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('DDS State: %d', teb.u.data.ltei.lter.termination_event.params.param[2] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c360102 SCID_DRM_INVALID_DDS_SIMPLE TRANSLATIONBLOCK TRANSLATE('DDS Expected State: %d', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('DDS State: %d', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c370102 SCID_DRM_INVALID_DDS_SIMPLE_WAIT TRANSLATIONBLOCK TRANSLATE('DDS Expected State: %d', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('DDS State: %d', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c380102 SCID_DRM_INVALID_DDS_SIMPLE_BUILD TRANSLATIONBLOCK TRANSLATE('DDS Expected State: %d', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('DDS State: %d', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c390102 SCID_DRM_INVALID_DDS_SOB_BUILD TRANSLATIONBLOCK TRANSLATE('DDS Expected State: %d', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('DDS State: %d', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c3a0102 SCID_DRM_INVALID_DDS_LDSB_ACK_WAIT TRANSLATIONBLOCK TRANSLATE('MFC Status: %d', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('DDS State: %d', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c3b0102 SCID_DRM_INVALID_DDS_LDSB_ACK_WAIT_RESP TRANSLATIONBLOCK TRANSLATE('MFC Status: %d', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('DDS State: %d', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c410102 SCID_DRM_INVALID_DDS_SITE_FAILOVER TRANSLATIONBLOCK TRANSLATE('DDS Expected State: %d', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('DDS State: %d', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK

TC BLOCK: 0c420102 SCID_DRM_INVALID_DDS_SYNCH_BUFFS_ACK TRANSLATIONBLOCK TRANSLATE('MFC Status: %d', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('DDS State: %d', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c430102 SCID_DRM_INVALID_DDS_UPDATE_MDW_ACK TRANSLATIONBLOCK TRANSLATE('MFC Status: %d', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('DDS State: %d', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c450100 SCID_DRM_INVALID_CODE_PATH TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0c460103 SCID_DRM_CORRUPT_MFC_FRAME TRANSLATIONBLOCK TRANSLATE('FRAME_SIZE: %d', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('SLOT_INDEX: %d', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('FRAME_INDEX: %d', teb.u.data.ltei.lter.termination_event.params.param[2] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c480100 SCID_DRM_INIT_FAIL_DDCB_ALLOC TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0c490100 SCID_DRM_INIT_FAIL_RNSB_ALLOC TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0c4b0100 SCID_DRM_INIT_FAIL_GIDFT_ALLOC TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0c4c0100 SCID_DRM_BAD_MFC_VECTOR TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0c4d0100 SCID_DRM_BAD_RXMFC_RESPONSE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0c4e0106 SCID_DRM_BAD_RNSB_DDCB TRANSLATIONBLOCK TRANSLATE('RNSB address: %x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('RNSB->DDCB: %x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('Node WWN (high): %x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Node WWN (low): %x',

teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('DDCB address: %x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('DDCB->RNSB: %x', teb.u.data.ltei.lter.termination_event.params.param[5] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c4f0101 SCID_DRM_FCP_INIT_MEM TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 0c500106 SCID_DRM_GSN_OUT_OF_SEQUENCE_16 TRANSLATIONBLOCK TRANSLATE('Data Replication Group: %08x %08x %08x %08x', teb.u.data.ltei.lter.termination_event.params.param[0], teb.u.data.ltei.lter.termination_event.params.param[1], teb.u.data.ltei.lter.termination_event.params.param[2], teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('GSN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('Expected GSN: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]); ENDTRANSLATIONBLOCK TC BLOCK: 0e000020 SCID_SDC_INVALID_BATT_SYS_STATE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0e010020 SCID_SDC_INVALID_HOLDUP_TIME TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0e020020 SCID_SDC_INVALID_BRICK_NUMBER TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0e030020 SCID_SDC_INVALID_BRICK_STATE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0e050020 SCID_SDC_INVALID_BLOWER_NUMBER TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0e060020 SCID_SDC_INVALID_BLOWER_STATE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0e080020 SCID_SDC_INVALID_TEMPERATURE_STATE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0e090020 SCID_SDC_INVALID_PWR_SUPPLY_NUMBER TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0e0a0020 SCID_SDC_INVALID_PWR_SUPPLY_STATE TRANSLATIONBLOCK

ENDTRANSLATIONBLOCK TC BLOCK: 0e0b0020 SCID_SDC_COMMAND_SEND_COLLISION TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0f000100 SCID_MIRROR_EMPTY_DMA_CONTEXT_Q TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0f010101 SCID_MIRROR_OUTOFSYNC_DMA_CONTEXT_Q TRANSLATIONBLOCK TRANSLATE('XD Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 0f020100 SCID_MIRROR_FULL_DMA_CONTEXT_Q TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0f100100 SCID_MIRROR_UNEXPECTED_CODE_PATH TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0f110100 SCID_MIRROR_MEMORY_ALLOCATION_FAILED TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0f150102 SCID_MIRROR_TREHDRADDR_ER TRANSLATIONBLOCK TRANSLATE('Target Read Entry Address: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Header Address: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 0f160101 SCID_MIRROR_UNKNOWN_FED_TYPE TRANSLATIONBLOCK TRANSLATE('FED type: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 0f170100 SCID_MIRROR_START_TIMER_FAIL TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0f18011f SCID_MIRROR_MFC_PROC_ACK_DSI_TRAP TRANSLATIONBLOCK TRANSLATE('MFC Port Status: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('rcvd_pcb_ptr: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('rcvd_d_id: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('out_credits: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('next_sn: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('last_rcvd_ack: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]

); ); ); ); ); );

TRANSLATE('delivered_sn: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('last_xferred_ack: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('flags: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('acked_sn: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('process_sn: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10] ); TRANSLATE('ack_cnt: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11] ); TRANSLATE('tunnel_idx: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12] ); TRANSLATE('in-tunnel 0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13] ); TRANSLATE('in-tunnel 1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14] ); TRANSLATE('in-tunnel 2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15] ); TRANSLATE('in-tunnel 3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16] ); TRANSLATE('in-tunnel 4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17] ); TRANSLATE('in-tunnel 5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18] ); TRANSLATE('in-tunnel 6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19] ); TRANSLATE('in-tunnel 7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20] ); TRANSLATE('in-tunnel 8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21] ); TRANSLATE('out-tunnel 0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22] ); TRANSLATE('out-tunnel 1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23] ); TRANSLATE('out-tunnel 2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24] ); TRANSLATE('out-tunnel 3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25] ); TRANSLATE('out-tunnel 4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26] ); TRANSLATE('out-tunnel 5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27] ); TRANSLATE('out-tunnel 6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28] ); TRANSLATE('out-tunnel 7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29] ); TRANSLATE('out-tunnel 8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30] ); ENDTRANSLATIONBLOCK TC BLOCK: 0f190100 SCID_MIRROR_INIT_MEM_MFC_COP_BUF TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0f1a0100 SCID_MIRROR_INIT_MEM_SFQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK

TC BLOCK: 0f1b0100 SCID_MIRROR_INIT_MEM_ELSDS TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0f1e0100 SCID_MIRROR_INIT_MEM_IBQ TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0f1f0101 SCID_MIRROR_INVAL_PORT_EVENT_TYPE TRANSLATIONBLOCK TRANSLATE('Type: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 0f200100 SCID_MIRROR_OUT_RESERVED_FEDS TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0f210100 SCID_MIRROR_INVAL_COMPL_MSG TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0f220100 SCID_MIRROR_SEST_PROGM_ERROR TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0f230100 SCID_MIRROR_CLASS2_OUTB_FAILURE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0f24011f SCID_MIRROR_HOST_PROGRAMMING_ERROR TRANSLATIONBLOCK TRANSLATE('Callback: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Byte Count: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('SEST Byte Count: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('CDB10B Opcode: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Loc: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('SGL ptr: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('SGL Byte Count: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('SGL ptr: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SGL Byte Count: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('SGL ptr: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('SGL Byte Count: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10] ); TRANSLATE('SGL ptr: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11] ); TRANSLATE('SGL Byte Count: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12] ); TRANSLATE('SGL ptr: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13] );

TRANSLATE('SGL Byte Count: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14] TRANSLATE('SGL ptr: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15] TRANSLATE('SGL Byte Count: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16] TRANSLATE('SGL ptr: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17] TRANSLATE('SGL Byte Count: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18] TRANSLATE('SGL ptr: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19] TRANSLATE('SGL Byte Count: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20] TRANSLATE('SGL ptr: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21] TRANSLATE('SGL Byte Count: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22] TRANSLATE('SGL ptr: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23] TRANSLATE('SGL Byte Count: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24] TRANSLATE('SGL ptr: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25] TRANSLATE('SGL Byte Count: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26] TRANSLATE('SGL ptr: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27] TRANSLATE('SGL Byte Count: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28] TRANSLATE('SGL ptr: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29] TRANSLATE('SGL Byte Count: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30] ENDTRANSLATIONBLOCK TC BLOCK: 0f250080 SCID_MIRROR_REMOTE_COUPLE_CRASH TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0f260100 SCID_MIRROR_UNSUPPORTED_ELS TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0f270100 SCID_MIRROR_UNHANDLED_ERROR TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0f280100 SCID_MIRROR_SCDBS_CORRUPTED TRANSLATIONBLOCK ENDTRANSLATIONBLOCK

); ); ); ); ); ); ); ); ); ); ); ); ); ); ); ); );

TC BLOCK: 0f290101 SCID_MIRROR_UNKNOWN_LDN_FED TRANSLATIONBLOCK TRANSLATE('FED type: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 0f2b0100 SCID_MIRROR_UNKNOWN_LOOP_STATE TRANSLATIONBLOCK

ENDTRANSLATIONBLOCK TC BLOCK: 0f2c0100 SCID_MIRROR_UNKNOWN_EXCH_TYPE TRANSLATIONBLOCK ENDTRANSLATIONBLOCK TC BLOCK: 0f2d0106 SCID_MIRROR_BAD_RP_LOGIN_STATE TRANSLATIONBLOCK TRANSLATE('Invocation instance: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Port login state: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('Local port: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Port id value: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('Port name (low): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('Port name (high): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ENDTRANSLATIONBLOCK

); ); ); ); ); );

TC BLOCK: 0f2e0105 SCID_MIRROR_BAD_RP_LOGGEDIN_TMR_EXP TRANSLATIONBLOCK TRANSLATE('Port login state: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Local port: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('Port id value: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Port name (low): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Port name (high): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); ENDTRANSLATIONBLOCK TC BLOCK: 0f2f0dc6 SCID_MIRROR_CONTROLLER_MISMATCH TRANSLATIONBLOCK TRANSLATE('THIS Cache config: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('THIS Cache size: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('THIS Policy size: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('OTHER Cache config: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('OTHER Cache size: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('OTHER Policy size: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ENDTRANSLATIONBLOCK

); ); ); ); ); );

TC BLOCK: 42000101 SCID_HP_INIT_FAIL_MEM_ALLOC TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 42050103 SCID_HP_UNEXPECTED_CACHE_LOCK TRANSLATIONBLOCK

TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); ENDTRANSLATIONBLOCK TC BLOCK: 42060105 SCID_HP_UNEXPECTED_SCSI_COMMAND TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ENDTRANSLATIONBLOCK

); ); ); ); );

TC BLOCK: 42070123 SCID_HP_DROP_DEAD_CNDR TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); ENDTRANSLATIONBLOCK TC BLOCK: 420801a3 SCID_HP_DROP_DEAD_CCNDR TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); ENDTRANSLATIONBLOCK TC BLOCK: 420901c3 SCID_HP_DROP_DEAD_DC TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); ENDTRANSLATIONBLOCK TC BLOCK: 420c0184 SCID_HP_UNKNOWN_RSCSI_BUILD_CONTEXT TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] );

TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); ENDTRANSLATIONBLOCK TC BLOCK: 420d0182 SCID_HP_UNKNOWN_RSCSI_RECEIVE_CONTEXT TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 420e0181 SCID_HP_ICOPS_OUT_OF_MEMORY TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 420f0182 SCID_HP_ICOPS_UNKNOWN_BUILD_CONTEXT TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 42100182 SCID_HP_ICOPS_UNKNOWN_RECIEVE_CONTEXT TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 42120104 SCID_HP_ILLEGAL_INPROCQ TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ENDTRANSLATIONBLOCK

); ); ); );

TC BLOCK: 42130101 SCID_HP_NO_CMD_HTBS TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 42140102 SCID_HP_INVALID_RCV_DATA_CTX TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK

TC BLOCK: 42150102 SCID_HP_CHMOD_NO_ACB TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 42160102 SCID_HP_PRESENT_LUN_NO_ACB TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 42190104 SCID_HP_INVALID_CCB_STATE TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ENDTRANSLATIONBLOCK

); ); ); );

TC BLOCK: 421a0183 SCID_HP_INVALID_HTB_FLOW TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); ENDTRANSLATIONBLOCK TC BLOCK: 421b0102 SCID_HP_INVALID_WORK_REQ_TYPE TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 421c0101 SCID_HP_NO_WORK_REQUESTS TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 421e0102 SCID_HP_CMD_HTB_IN_USE TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK

TC BLOCK: 42230102 SCID_HP_UNPLUN_NO_ACB TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 42250104 SCID_HP_BAD_ACB_DEL TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ENDTRANSLATIONBLOCK TC BLOCK: 42260104 SCID_HP_NO_UA_TABLE TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ENDTRANSLATIONBLOCK TC BLOCK: 42270108 SCID_HP_UNKNOWN_PORT_EVENT TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ENDTRANSLATIONBLOCK

); ); ); );

); ); ); );

); ); ); ); ); ); ); );

TC BLOCK: 42280102 SCID_HP_UNKNOWN_CM TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK

TC BLOCK: 42290103 SCID_HP_ILLEGAL_SEST_ID TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); ENDTRANSLATIONBLOCK TC BLOCK: 422c0003 SCID_HP_TACHYON_ERROR TRANSLATIONBLOCK TRANSLATE('Unique identifier 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Bad port number (zero-based): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('PCI interrupt status register: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); ENDTRANSLATIONBLOCK TC BLOCK: 422d010a SCID_HP_UNKNOWN_IO_ERROR TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ENDTRANSLATIONBLOCK TC BLOCK: 422e0104 SCID_HP_ILLEGAL_LUN_ACCESS TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ENDTRANSLATIONBLOCK

); ); ); ); ); ); ); ); ); );

); ); ); );

TC BLOCK: 422f0103 SCID_HP_UNKNOWN_INBOUND_STATUS TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] );

TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); ENDTRANSLATIONBLOCK TC BLOCK: 42300103 SCID_HP_ILLEGAL_SCRIPT_RSP TRANSLATIONBLOCK TRANSLATE('Unique identifier 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Function that returned bad response: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('Bad response: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); ENDTRANSLATIONBLOCK TC BLOCK: 42310102 SCID_HP_BAD_SCRIPT_ERROR_STATUS TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 42320104 SCID_HP_DUPLICATE_LUN TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ENDTRANSLATIONBLOCK TC BLOCK: 4233010a SCID_HP_INVALID_IMMEDIATE_ERROR TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ENDTRANSLATIONBLOCK

); ); ); );

); ); ); ); ); ); ); ); ); );

TC BLOCK: 42340104 SCID_HP_INVALID_HTBX_STATE TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ENDTRANSLATIONBLOCK TC BLOCK: 42350104 SCID_HP_INVALID_UNQUIESCE TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ENDTRANSLATIONBLOCK

); ); ); );

); ); ); );

TC BLOCK: 42360102 SCID_HP_INVALID_CSEL_STATE TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 42370183 SCID_HP_EVENT_NOTIFY_GAP TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); ENDTRANSLATIONBLOCK TC BLOCK: 4238011f SCID_HP_CSM_HANG TRANSLATIONBLOCK TRANSLATE('CSM stack 0: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('CSM stack 1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('CSM stack 2: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('CSM stack 3: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('CSM stack 4: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('CSM stack 5: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] TRANSLATE('CSM stack 6: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] TRANSLATE('CSM stack 7: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7]

); ); ); ); ); ); ); );

TRANSLATE('CSM stack 8: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('CSM stack 9: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('CSM stack 10: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('CSM stack 11: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('CSM stack 12: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('CSM stack 13: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('CSM stack 14: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('CSM stack 15: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('CSM stack 16: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('CSM stack 17: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('CSM stack 18: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('CSM stack 19: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('CSM stack 20: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('CSM stack 21: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('CSM stack 22: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('CSM stack 23: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('CSM stack 24: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); TRANSLATE('CSM stack 25: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[25]); TRANSLATE('CSM stack 26: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[26]); TRANSLATE('CSM stack 27: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[27]); TRANSLATE('CSM stack 28: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[28]); TRANSLATE('CSM stack 29: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[29]); TRANSLATE('CSM stack 30: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[30]); ENDTRANSLATIONBLOCK TC BLOCK: 42390184 SCID_HP_PROXY_BAD_STATE TRANSLATIONBLOCK TRANSLATE('Bad Proxy IO MFC State: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('State value: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('Expected state: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('HTB Pointer: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ENDTRANSLATIONBLOCK

); ); ); );

TC BLOCK: 423a0102 SCID_HP_TACHERR_BOGUS_PORT TRANSLATIONBLOCK TRANSLATE('Bogus port number (zero-based): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Bogus port number (zero-based): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 423b0102 SCID_HP_TACH_NOT_RESPONDING TRANSLATIONBLOCK TRANSLATE('Bad port number (zero-based): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Bad port number (zero-based): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); ENDTRANSLATIONBLOCK TC BLOCK: 423e0107 SCID_HP_INVALID_HTB_STATE TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('HTB: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('HTB flags: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Flow function: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('Port: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('SFQ index: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] TRANSLATE('FC header address: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ENDTRANSLATIONBLOCK

); ); ); ); ); ); );

TC BLOCK: 423f010c SCID_HP_INVALID_HTB_DISCARD TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('HTB: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('HTB type: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('HTB flags: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('HTB Flow function: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('HTB Callback function 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('Port: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('CCB address: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('HTB hdr flink: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('HTB hdr blink: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('HTB l.fc flink: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10] ); TRANSLATE('HTB l.fc blink: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11] );

ENDTRANSLATIONBLOCK TC BLOCK: 42400104 SCID_HP_PRESENT_NO_VDSB TRANSLATIONBLOCK TRANSLATE('Unique termination identifier 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Lun 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('Lut Index 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Adapter 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ENDTRANSLATIONBLOCK TC BLOCK: 42410106 SCID_HP_QUEUE_ERROR TRANSLATIONBLOCK TRANSLATE('Unique termination identifier 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('HTB 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('HTB Status 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('HTB Opcode 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('Param 1 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] TRANSLATE('Param 2 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ENDTRANSLATIONBLOCK TC BLOCK: 42420105 SCID_HP_ILLEGAL_CCBPENDQ TRANSLATIONBLOCK TRANSLATE('Parameter to assist in analysis 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[0] TRANSLATE('Item address 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] TRANSLATE('Type 0x%x', teb.u.data.ltei.lter.termination_event.params.param[2] TRANSLATE('Port %d', teb.u.data.ltei.lter.termination_event.params.param[3] TRANSLATE('CCB address 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ENDTRANSLATIONBLOCK

); ); ); );

); ); ); ); ); );

); ); ); ); );

TC BLOCK: 83002061 SCID_DOG_CANNOT_BRANCH_ERR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); ENDTRANSLATIONBLOCK TC BLOCK: 83012079 SCID_DOG_UNEXPECTED_VECTOR_ERR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1,

TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Pointer to ASCII error message: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('TE number: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Test number: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Error code: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('Address of BUD: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('Exception type: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('SRR0 at interrupt: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('SRR1/MSR at interrupt: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('LR: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('UIC status: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('UIC mask: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); TRANSLATE('UIC critical: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[12]); TRANSLATE('GLUE IS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[13]); TRANSLATE('GLUE MCPE: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[14]); TRANSLATE('GLUE NPIS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[15]); TRANSLATE('GLUE NPIE: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[16]); TRANSLATE('GLUE ACNS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[17]); TRANSLATE('GLUE APNS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[18]); TRANSLATE('GLUE FPIS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[19]); TRANSLATE('GLUE FPIE: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[20]); TRANSLATE('GLUE ACFS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[21]); TRANSLATE('GLUE APFS: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[22]); TRANSLATE('QSR ERRDET1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[23]); TRANSLATE('QSR ERREN1: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[24]); ENDTRANSLATIONBLOCK TC BLOCK: 8302206c SCID_DOG_HARD_ERR TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1,

TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0] ); TRANSLATE('Pointer to ASCII error message: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[1] ); TRANSLATE('TE number: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2] ); TRANSLATE('Test number: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3] ); TRANSLATE('Error code: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4] ); TRANSLATE('Address of BUD: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5] ); TRANSLATE('Address of error (hi): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6] ); TRANSLATE('Address of error (lo): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7] ); TRANSLATE('Expected data (hi): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8] ); TRANSLATE('Expected data (lo): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[9] ); TRANSLATE('Actual data (hi): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[10]); TRANSLATE('Actual data (lo): 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[11]); ENDTRANSLATIONBLOCK TC BLOCK: 84032069 SCID_DRS_XL_EXCESSIVE_CM_CDES TRANSLATIONBLOCK CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE('Cache memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE('Current number of detected errors: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE('Previous number of detected errors: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('Number of seconds over which errors occurred: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); TRANSLATE('Sprite's m_ese, even ECC status, register value: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[5]); TRANSLATE('Sprite's m_eso, odd ECC status, register value: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[6]); TRANSLATE('Sprite's m_eae, even ECC address, register value: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[7]); TRANSLATE('Sprite's m_eae, odd ECC address, register value: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[8]); ENDTRANSLATIONBLOCK TC BLOCK: 84042065 SCID_DRS_XL_EXCESSIVE_PM_CDES TRANSLATIONBLOCK

CONDITIONAL( teb.u.data.ltei.lteihd.flags.spsctrlr == 1, TRANSLATE( 'Single Power Supply HSV450 Controller' ) ); TRANSLATE('Policy memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[0]); TRANSLATE('Cache memory size: %d MB', teb.u.data.ltei.lter.termination_event.params.param[1]); TRANSLATE('Current number of detected errors: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[2]); TRANSLATE('Previous number of detected errors: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[3]); TRANSLATE('Number of seconds over which errors occurred: 0x%08x', teb.u.data.ltei.lter.termination_event.params.param[4]); ENDTRANSLATIONBLOCK DEFINITIONS: %[scmi_nsc_restart_option] 0 = None -- no restart 1 = Regular -- full restart, host system connectivity is lost until the controll er returns to normal operation 2 = Fast -- resynchronization, restart of the controller in a manner that has li ttle or no impact on host system connectivity %[scmi_nsc_battery_present_condition] 0 = Not present 1 = Present %[scmi_group_auto_suspend_state] 1 = Connection between the Data Replication Source and Data Replication Destinat ion is active. 2 = Connection between the Data Replication Source and Data Replication Destinat ion is inactive. %[scmi_nsc_fc_port_condition] 0 = Unknown 1 = Normal 2 = Failed %[scmi_scvd_snap_attach_type] 0 = Snapshot 1 = SnapClone 2 = Mirror Clone %[scmi_read_disk_cache_policy_type] 1 = Read cache on 2 = Read cache off %[scmi_fan_status] 1 = Normal 2 = Elevated 3 = High 4 = Bad 5 = Unknown 6 = Not Present %[scmi_rundown_flag]

0 = Flag is off, log is NOT in rundown mode, normal operation 1 = Flag is on, log is in rundown mode %[scmi_nsc_shutdown_other_option] 0 = Remain operational 1 = Coupled shutdown %[scmi_object_function_code] 1001 = *** 1001 not used *** 1002 = *** 1002 not used *** 1003 = *** 1003 not used *** 1004 = *** 1004 not used *** 1005 = *** 1005 not used *** 1006 = *** 1006 not used *** 1007 = *** 1007 not used *** 1008 = *** 1008 not used *** 1009 = *** 1009 not used *** 1010 = *** 1010 not used *** 1011 = *** 1011 not used *** 2001 = *** 2001 not used *** 2002 = *** 2002 not used *** 2003 = *** 2003 not used *** 2004 = *** 2004 not used *** 2005 = *** 2005 not used *** 2006 = *** 2006 not used *** 2007 = *** 2007 not used *** 2008 = *** 2008 not used *** 2009 = *** 2009 not used *** 2010 = *** 2010 not used *** 2011 = *** 2011 not used *** 2012 = *** 2012 not used *** 2013 = *** 2013 not used *** 2014 = *** 2014 not used *** 2015 = *** 2015 not used *** 2016 = *** 2016 not used *** 2017 = *** 2017 not used *** 2018 = *** 2018 not used *** 2019 = *** 2019 not used *** 2020 = *** 2020 not used *** 2021 = *** 2021 not used *** 2022 = *** 2022 not used *** 2023 = *** 2023 not used *** 2024 = *** 2024 not used *** 2025 = *** 2025 not used *** 2026 = *** 2026 not used *** 2027 = *** 2027 not used *** 2028 = *** 2028 not used *** 2029 = *** 2029 not used *** 2030 = *** 2030 not used *** 2031 = *** 2031 not used *** 2032 = *** 2032 not used *** 2033 = *** 2033 not used *** 2034 = *** 2034 not used *** 2035 = *** 2035 not used *** 2036 = *** 2036 not used *** 2037 = *** 2037 not used *** 2038 = *** 2038 not used *** 2039 = *** 2039 not used *** 3001 = Disk Group Create 3002 = Disk Group Discard

3003 3004 3005 3006 3007 3008 3009 3010 3011 3012 3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023 3024 3025 3026 3027 3028 3029 3030 3031 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012 4013 4014 4015 4016 4017 4018 4019 4020 4021 4022 4023 4024 4025 4026 4027 4028 4029 4030 4031

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

Disk Group Get Capacity *** 3004 not used *** Disk Size Disk Group Get Occupancy Disk Group Get Occupancy Highwater Disk Group Get Volumes Disk Group Get Volumes Count Disk Group Set Occupancy Highwater Disk Group Get Management Logical Disk Size Disk Group Read Management Logical Disk Disk Group Write Management Logical Disk Disk Group Get Spares Current Disk Group Get Spares Goal Disk Group Set Spares Goal Disk Group Get Condition Disk Group Resolve Condition Disk Group Locate Disk Group Create New Disk Group Add Volumes Disk Group Write Management Logical Disk Blocks Disk Group Get Leveling Info Disk Group Get SRC Mode Disk Group Locate RSS Disk Group Get Volumes Info Disk Group Set Requested SRC Mode *** 3027 not used *** info Disk Group Get Drive Type *** 3029 not used *** nyi, implemented in LargeLuns branch Disk Group Set UDOD Controller Crash Controller Generate Id *** 4003 not used *** *** 4004 not used *** Controller Get Cache Capacity Controller Get Cache Condition Controller Get Condition Controller Get Default SCM EP Id Controller Get Fibre Channel Context Id Controller Get Firmware Version *** 4011 not used *** Controller Get Identity *** 4013 not used *** *** 4014 not used *** *** 4015 not used *** Controller Get Loop Port Node Id Controller Get Loop Port Node Type Controller Get Loop Port Position *** 4019 not used *** *** 4020 not used *** *** 4021 not used *** *** 4022 not used *** Controller Get Controllers Controller Get Controllers Count Controller Get Participation Controller Get Storage System Controller Get Supported Class Versions Controller Maintenance Invoke Routine Controller Maintenance Read Memory Controller Read Dump Controller Read ILF Log

4032 4033 4034 4035 4036 4037 4038 4039 4040 4041 4042 4043 4044 4045 4046 4047 4048 4049 4050 4051 4052 4053 4054 4055 4056 4057 4058 4059 4060 4061 4062 4063 4064 4065 4066 4067 4068 4069 4070 4071 4072 4073 4074 4075 4076 4077 4078 4079 4080 4081 4082 4083 4084 4085 4086 4087 4088 4089 4090 4091

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

Controller Set Default SCM EP Id Controller Set ILF Log Mask Controller Set Participation Controller Shutdown Controller Get Physical Stores Controller Get Physical Stores Count *** 4038 not used *** Controller Get Unassigned Host Ports Controller Get Unassigned Host Ports Count Controller Get Enclosure Status Controller Set Enclosure Fan High Speed Mode Controller Set Enclosure Temp Trip Point Controller Get Hardware Info Controller Get Fibre Channel Node Id Controller Get Fibre Channel Port Address Controller Get Fibre Channel Port Condition Controller Get Fibre Channel Port Id Controller Get Fibre Channel Port Type Controller Get ILF Component Mask Controller Get ILF Component Class Mask Controller Get ILF Disk Slot Controller Set ILF Component Mask Controller Set ILF Component Class Mask Controller Set ILF Disk Slot Controller Get Battery System Capacity Controller Get Battery System Condition Controller Get Battery Hardware Status Controller Get UPS Condition Controller Login Controller Logout Controller Save Firmware Controller Use Firmware Controller Locate Controller Login Step1 Controller Login Step2 Controller Get Disk Enclosures Controller Get Disk Enclosures Count Controller Get Disk Enclosures Status Controller Get Disk Enclosure Page Controller Locate Disk Enclosure Controller Set Disk Enclosure Audible Alarm Controller Get Host Port Info Controller Get Drive Code Load Info Controller Get Loop Port Node Info Controller Get Fibre Channel Port Info Controller Get Physical Stores Info Controller Read Termination Events Controller Read Events Activeq Controller Open Events Activeq Controller Close Events Activeq Controller Get Crash Dump Info Controller Open Crash Dump Controller Read Crash Dump Controller Close Crash Dump Controller Open ILF Memory Controller Read ILF Memory Controller Close ILF Memory Controller Enable Loop Port Controller Get Loop Port Node Error Controller Clear Loop Port Node Error

4092 4093 4094 4095 4096 4097 4098 4099 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 4120 4121 4122 4123 4124 4125 4126 4127 4128 4129 4130 4131 4132 5001 5002 5003 5004 6001 6002 6003 6004 6005 6006 6007 6008 6009 6010 6011 6012 6013 6014 6015

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

Controller Start DILX Controller Stop DILX Controller Get DILX Summary Controller Get Controller Info Controller Get Memory Size Controller Free Unassigned Host Ports Get EPBC Error Counts Controller Read Checkpoint Memory Controller Close Checkpoint Memory Controller Open Checkpoint Memory Controller Request Log Size Controller Set Host Port Topology Controller Get Controller Info 2 Controller Get Controller Enclosure Info Controller Get Disk Enclosure Info Controller Get Management Module Info Controller Set Management Module Info Controller Is Password Set Controller Set Password Controller Clear Password Controller Unbypass All Loops Controller Set Loop Recovery Controller get Loop Recovery Controller Callisto Send Command Controller Set WWN Controller Get ELMO Error Counters Controller Get ELMO Event Logs Controller Get Management Module Hardware Info Controller Locate Controller Enclosure Controller Get Controller Locate State Controller Get Controller Enclosure Locate State Place custom event on event queue Controller Set UDOD Controller Set Controller Enclosure UDOD Controller Set Disk Enclosure UDOD Controller Get Controller Enclosure UDOD Controller Discard Disk Enclosure Controller Get Disk Enclosures Handles Controller Set UDOD Controller Get Supported Host Modes Controller Get Disk Enclosure UDOD *** 5001 not used *** *** 5002 not used *** *** 5003 not used *** *** 5004 not used *** Physical Store Clear Failed Physical Store Erase Volume Physical Store Get Capacity Physical Store Get Condition Physical Store Get LUN Physical Store Get Maintenance Mode Physical Store Get Physical Device Physical Store Get Volume Physical Store Is Failed Physical Store Is Failure Predicted Physical Store Is Media Inaccessible Physical Store Read Inquiry Strings *** 6013 not used *** Physical Store Read Volume Is Quorum Disk Physical Store Read Volume Disk Group Id

6016 6017 6018 6019 6020 6021 6022 6023 6024 7001 7002 7003 7004 7005 7006 7007 7008 7009 7010 7011 8001 8002 8003 8004 8005 8006 8007 8008 8009 8010 8011 8012 8013 8014 8015 8016 8017 8018 8019 8020 8021 8022 8023 8024 8025 8026 8027 8028 8029 8030 8031 8032 8033 8034 8035 8036 8037 8038 8039 8040

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

Physical Store Read Volume Storage System Id Physical Store Read Volume Storage System Name Physical Store Send Command Physical Store Set Maintenance Mode Physical Store Read Node Id Physical Store Locate Physical Store Get Drive Type Physical Store Get Download Condition Physical Store Get Info Presented Unit Create Presented Unit Discard *** 7003 not used *** Presented Unit Get LUN Presented Unit Get Storage System Client Presented Unit Set LUN *** 7007 not used *** *** 7008 not used *** Presented Unit Get Reservation Type Presented Unit Get SCVD Presented Unit Get State Storage System Create Storage System Discard Storage System Get Context Id *** 8004 not used *** Storage System Get Device Addition Policy *** 8006 not used *** Storage System Get Events *** 8008 not used *** *** 8009 not used *** Storage System Get Master Controller *** 8011 not used *** Storage System Get Name *** 8013 not used *** *** 8014 not used *** Storage System Get Supported Class Versions Storage System Get Time Storage System Get Volume Replacement Delay Storage System Lookup Object Storage System Lookup Object Count *** 8020 not used *** *** 8021 not used *** Storage System Set Device Addition Policy *** 8023 not used *** Storage System Set Name *** 8025 not used *** Storage System Set Time Storage System Set Volume Replacement Delay Storage System Translate Id To Handle *** 8029 not used *** Storage System Free Command Lock Storage System Get Command Lock Description Storage System Get Command Lock Status Storage System Set Default Lock Timeout Storage System Set Override Lock Timeout Storage System Take Command Lock Storage System Get SACD Settable Id Storage System Set SACD Settable Id Storage System Read Controller Termination Events Storage System Sync Reset *** 8040 not used ***

8041 = Storage System Get Ups Mode 8042 = Storage System Set Ups Mode 8043 = Storage System Resolve Condition 8044 = Storage System Get Connection Status 8045 = Storage System Get Performance Geometry 8046 = Storage System Get Performance Data 8047 = Storage System Create New 8048 = *** 8048 not used *** 8049 = Storage System Get Groups Info 8050 = *** 8050 not used *** 8051 = Storage System Get Object Class Status 8052 = Storage System Update Object Class Status 8053 = Storage System Get 8054 = Storage System Set 8055 = Storage System Set 8056 = Storage System Get 9001 = *** 9001 not used *** 9002 = Storage System Client Create 9003 = Storage System Client Discard 9004 = Storage System Client Get Client Connections 9005 = Storage System Client Get Client Connections Count 9006 = *** 9006 not used *** 9007 = *** 9007 not used *** 9008 = *** 9008 not used *** 9009 = Storage System Client Add Port WWN 9010 = Storage System Client Get Port WWNs 9011 = Storage System Client Get Port WWNs Count 9012 = Storage System Client Remove Port WWN 9013 = Storage System Client Get Client Mode 9014 = Storage System Client Set Client Mode 9015 = Storage System Client Get Client Mode New 9016 = Storage System Client Set Client Mode New 9017 = *** 9017 not used *** Get Name 9018 = *** 9018 not used *** Set Name 9019 = Storage System Set Udod 9020 = Storage System Set Udod 10001 = *** 10001 not used *** 10002 = Storage System Virtual Disk Disable 10003 = *** 10003 not used *** 10004 = Storage System Virtual Disk Enable 10005 = *** 10005 not used *** 10006 = *** 10006 not used *** 10007 = *** 10007 not used *** 10008 = *** 10008 not used *** 10009 = *** 10009 not used *** 10010 = *** 10010 not used *** 10011 = *** 10011 not used *** 10012 = *** 10012 not used *** 10013 = Storage System Virtual Disk Set Capacity 10014 = *** 10014 not used *** 10015 = *** 10015 not used *** 10016 = *** 10016 not used *** 10017 = *** 10017 not used *** 10018 = *** 10018 not used *** 10019 = Storage System Virtual Disk Set Group 10020 = Storage System Virtual Disk Set Group None 10021 = *** 10021 not used *** 10022 = Storage System Virtual Disk Set Disk Cache Policy 10023 = Storage System Virtual Disk Get Remote Storage System Virtual Disk Count 10024 = Storage System Virtual Disk Get Remote Storage System Virtual Disks

10025 10026 10027 10028 10029 10030 10031 10032 10033 10034 10035 10036 10037 10038 10039 10040 10041 10042 10043 10044 11001 11002 11003 11004 11005 11006 11007 11008 11009 11010 11011 11012 11013 11014 11015 11016 12001 12002 12003 12004 12005 12006 12007 12008 12009 12010 12011 12012 12013 12014 12015 12016 12017 12018 12019 12020 12021 12022 12023 12024

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

*** 10025 not used *** Storage System Virtual Disk Create Vdisk Storage System Virtual Disk Discard Vdisk Storage System Virtual Disk Get Info Storage System Virtual Disk Get Presented Units Storage System Virtual Disk Get Presented Units Count Storage System Virtual Disk Attach Snaps Storage System Virtual Disk Clear Container Storage System Virtual Disk Clear Data Lost Storage System Virtual Disk Mirror Clone Storage System Virtual Disk Restore Storage System Virtual Disk Set Lun WWID Storage System Virtual Disk Set Preferred NSC Storage System Virtual Disk Snapclone Storage System Virtual Disk Snapshot Storage System Virtual Disk Set Settable Id Storage System Virtual Disk Set Write Protected Storage System Virtual Disk Get Condition Storage System Virtual Disk Set Udod Storage System Virtual Disk Get Udod Volume Clear Failure Predicted Volume Create Volume Data Security Erase Volume Fail Missing Blocks Volume Get Capacity Volume Get Condition Volume Get Disk Group Volume Get Occupancy Volume Get Physical Store Volume Get Requested Usage Volume Get Usage Volume Is Failure Predicted Volume Is Insufficient Resources Volume Is Quorum Disk Volume Set Requested Usage Volume Get RSS Info Group Create Group Discard Group Get DRM Log State Group Get Failsafe Group Get Failsafe Locked Group Get Log Storage System Virtual Disk Handle Group Get Member Count Group Get Members Group Get Mode Group Get Operation Group Get Remote Storage System Count Group Get Remote Storage Systems Group Get Suspend Group Set Site Failover Group Set Mode Group Set Failsafe Group Set Operation Group Set Suspend Group Get Generation Group Get Group Name Group Get Read Only Group Set Read Only *** 12023 not used *** *** 12024 not used ***

12025 12026 12027 12028 12029 12030 12031 12032 12033 12034 12035 12036 12037 12038 12039 13001 13002 13003 13004 13005 14001

= = = = = = = = = = = = = = = = = = = = =

Group Get Comment Group Get User Name Group Set Comment Group Set User Name Group Get Capacity For Logging Group Get Member Condition ***12031 not used Group Invalidate Log Group Set Max Log Size Group Set Destination Presentation Group Set Auto Suspend V4 and later style Group Create Group Get Info Group Set Defer Copy Group Set Split Brain Protect Remote Node Discard Remote Node Get Info Remote Node Purge Remote Node Reset DRM Port Pref Remote Node Set DRM Port Preferences Management Module Maintenance Invoke

%[scmi_nsc_shutdown_poweroff_option] 0 = Remain in the power on state 1 = Power itself off %[scmi_temp_system_state] 1 = Normal 2 = Critical 3 = Over Temperature 4 = Unknown %[scmi_nsc_condition] 0 = Unknown 1 = Normal 2 = *** 2 not used *** 3 = Failed 4 = Degraded %[scs_confirmation_message] 0 = Multiple Storagecells detected 1 = Metadata unprotected 2 = Storage Cell lost 3 = Bad single controller configuration 4 = Must always be last %[scmi_volume_usage] 1 = Disk Group 2 = Reserved 3 = *** 3 no longer used *** 4 = Temporarily reserved for drive code load 5 = Temporarily reserved for drive code load 6 = Temporarily reserved for drive code load 7 = Temporarily reserved for drive code load 8 = Temporarily reserved for drive code load 9 = Temporarily reserved for drive code load 10 = Temporarily reserved for drive code load 11 = Temporarily reserved for drive code load 12 = Temporarily reserved for drive code load 13 = Temporarily reserved for drive code load

14 15 16 17 18 19 20

= = = = = = =

Temporarily Temporarily Temporarily Temporarily Temporarily Temporarily Temporarily

reserved reserved reserved reserved reserved reserved reserved

for for for for for for for

drive drive drive drive drive drive drive

code code code code code code code

load load load load load load load

%[scmi_volume_condition] 1 = Normal - Volume is present and operating normally 2 = Migrating - Data from this volume is being moved to other storage in this Di sk Group 3 = Missing - Volume is inaccessible 4 = Reconstructing - Volume is inaccessible; redundant data is being regenerated and moved to other storage in this Disk Group 5 = Completing - This previously inaccessible volume has become accessible; data migration is being completed 6 = Reverting - This previously inaccessible volume has become accessible; data is being regenerated 7 = Failed - Volume is not being used in the Disk Group; disk errors are prevent ing normal usage %[scmi_storagecell_device_addition_policy] 1 = Manual (Extrinsic) 2 = Automatic (Intrinsic) %[scmi_scvd_type] 1 = Original Disk 2 = Space Efficient Snapshot 3 = Space Inefficient Snapshot 4 = Snapclone 5 = Unknown 6 = Empty Container 7 = Mirror Clone %[scmi_write_disk_cache_policy_type] 1 = Writethrough 2 = Writeback %[scmi_shutdown] 1 = Success 2 = Failure 3 = Not Applicable %[scmi_power_supply_state] 1 = Good 2 = Bad 3 = Unknown 4 = Not Present %[scs_scrub_types] 0 = undefined 1 = SCMI (SCell discard) 2 = PFG (prompt for go) 3 = MM (aka TBM) 4 = maintenance command 5 = OCP 6 = lab-only scrub mechanism (MINDY, SCS debug) %[scmi_battery_brick_status_code]

0 = Unknown 16 = Too Old 32 = Charger Fault 48 = Faulted 64 = Temperature Fault 80 = Charging 96 = Charged 112 = Under Load Test 128 = Code Load 144 = Bad Charger %[scmi_scvd_condition] 1 = Normal 2 = Obsolete 3 = Obsolete 4 = Obsolete 5 = Failed 6 = Creation in progress 7 = Snapshot is inoperative due to lack of snapshot space 8 = Deletion in progress 9 = Capacity expand in progress progress 10 = Inoperative due to data lost 11 = Capacity reservation in progress 12 = Capacity unreservation in progress 13 = Snap deletion in progress 14 = Attaching empty container as snapclone in progress 15 = Attaching empty container as snapshot in progress 16 = Clearing container in progress 17 = Attaching empty container as mirror clone in progress 18 = Resyncing mirror clone in progress 19 = Detaching mirror clone in progress 20 = Fracture mirror clone in progress 21 = Mirror clone fractured 22 = Invalidated 23 = Source of instant restore 24 = Target of instant restore 25 = Instant restore taking place in tree 26 = Capacity shrink in progress %[scmi_nsc_fanps_present_condition] 0 = Not present 1 = Present %[scmi_group_operation_type] 1 = Synchronous 2 = Asynchronous %[sys_inop_failure_codes] 1 = 0 2 = Quorum disks from >4 cells 3 = LDAD Metadata Inoperative 4 = Non-uniform device connectivity 5 = >120/240/324 disks 6 = <4 disks 7 = Quorum disks from >1 cell (value must not be 1) 8 = User refused multi-quorum boot 9 = Only one quorum disk ( value must not be 1) 10 = User refused single-quorum boot 11 = >2 HSVs connected (value must not be 1) 12 = All Quorum disks have been lost

13 14 15 16 17 18 19 20 21 22 23 24 25

= = = = = = = = = = = = =

User refused lost quorum boot Dual nscs not seeing same disks >10 shelves on a port ports connected backwards firmware does not support SCSDB version Cannot tell if other nsc is there or not Cannot tell if other nsc is there or not, user does not want to run The cache manager has too much frozen data to bring a unit online no backend ports are operative backend is misconfigured Mirror bus not functioning User must select quorum from multiple cells Must be last one.

%[scmi_nsc_battery_use_condition] 0 = Not in use 1 = In use %[scmi_physical_store_condition] 1 = Normal 2 = Degraded 3 = Failed 4 = Not present 5 = Single port on Fibre %[scmi_nsc_shutdown_encl_poweroff_option] 0 = Remain in the power on state 1 = Powered off %[scmi_scvd_write_protect_condition] 0 = Write protect off 1 = Write protect on %[scmi_group_drm_ld_state] 1 = Operative 2 = Inoperative %[scmi_group_suspend_state] 1 = Connection between the Data Replication Source and Data Replication Destinat ion is active. 2 = Connection between the Data Replication Source and Data Replication Destinat ion is inactive. %[scmi_ldad_condition] 1 = Normal 2 = Disk Group with no redundancy is inoperative 3 = Disk Group with parity redundancy is inoperative 4 = Disk Group with mirrored redundancy is inoperative 5 = Disk Group with no redundancy is inoperative, marked for re-use 6 = Disk Group with parity redundancy is inoperative, marked for re-use 7 = Disk Group with mirrored redundancy is inoperative, marked for re-use 8 = Disk Group with RAID6 redundancy is inoperative 9 = Disk Group with RAID6 redundancy is inoperative, marked for re-use %[scmi_volume_resource_availability_condition] 0 = Sufficient resources available 1 = Insufficient resources available %[scmi_scvd_operation] 1 = Cache Fast Failover

2 = Create 4 = Delete 8 = Restore 16 = MC Detach 32 = MC Fracture 64 = MC Resync 128 = Clear Container 256 = Unshare 512 = Prepare Delete 1024 = Set Capacity 2048 = Flush %[scmi_group_readonly_type] 0 = Data Replication Destination Storage System Virtual Disk disabled for read a ccess. 1 = Data Replication Destination Storage System Virtual Disk enabled for read ac cess. %[scmi_group_drm_mode] 0 = Normal Active Source 1 = Normal Active Destination 2 = Active/Active (Master) 3 = Active/Active (Slave) %[scmi_nsc_shutdown_battass_failure_mode] 0 = No failure indicated. 1 = Failed only on this controller 2 = Failed only on the other controller of the pair. 3 = Failed on both controllers. %[scmi_battery_brick_state] 1 = Good 2 = Bad 3 = Unknown 4 = Not Present %[scmi_mirror_disk_cache_policy_type] 1 = Mirror 2 = No mirror %[scmi_volume_quorum_disk_condition] 0 = Not quorum disk 1 = Quorum disk %[scmi_scvd_redundancy_type] 0 = Unknown vd redundancy type 1 = Vraid0 2 = Vraid1 3 = Vraid5 4 = Vraid6 %[scmi_nsc_fan_present_condition] 0 = Not present 1 = Present %[scmi_group_dest_present_state] 0 = Data Replication Destination Storage System Virtual Disk disabled for destin ation presentation. 1 = Data Replication Destination Storage System Virtual Disk enabled for destina tion presentation.

%[scmi_group_split_brain_allow_state] 1 = Connection between the Data Replication Source and Data Replication Destinat ion is active. 2 = Connection between the Data Replication Source and Data Replication Destinat ion is inactive. %[scmi_nsc_shutdown_requester] 0 = via user agent (SCMI) 1 = via OCP 2 = via TBM 3 = via controller button 4 = internally 99 = test simulation for removal %[scmi_state] 1 = Disabled 2 = Enabled %[scmi_client_mode] 0 = Unknown 1 = User defined 2 = *** 2 not used *** 3 = WINNT with SecurePath 4 = VMS 5 = TRU64 UNIX 6 = Sun UNIX 7 = NetWare 8 = HP 9 = IBM 10 = LINUX 11 = SCO UNIX 12 = VMWARE 13 = Windows 'Longhorn' Server 14 = Apple Mac OS X %[scmi_scvd_quiescent_condition] 0 = Not quiescent 1 = Quiescent %[scmi_nsc_battery_system_condition] 1 = Good 2 = *** 2 not used *** 3 = Low 4 = *** 4 not used *** 5 = Bad 6 = Unkown %[scmi_group_defer_copy_state] 1 = Connection between the Data Replication Source and Data Replication Destinat ion is active. 2 = Connection between the Data Replication Source and Data Replication Destinat ion is inactive. %[scmi_nsc_shutdown_battass_option] 0 = Enabled 1 = Disabled %[scmi_scvd_data_availability_condition] 0 = Data Available

1 = Data Lost %[scmi_response_status_value] 0 = 0x00 Success 1 = 0x01 Already Exists 2 = 0x02 Buffer Too Small 3 = 0x03 Id Already Assigned 4 = 0x04 Insufficient Data Storage Available 5 = 0x05 Internal Error 6 = 0x06 Invalid Storage System State Logical Disk 7 = 0x07 Invalid Class 8 = 0x08 Invalid Function 9 = 0x09 Invalid Logical Disk Block State 10 = 0x0A Invalid Loop Configuration 11 = 0x0B Invalid Parameter 12 = 0x0C Invalid Parameter Handle 13 = 0x0D Invalid Parameter Id 14 = 0x0E Invalid Quorum Configuration 15 = 0x0F Invalid Target Handle 16 = 0x10 Invalid Target Id 17 = 0x11 Invalid Time 18 = 0x12 Media Inaccessible 19 = 0x13 No Fibre Channel Port 20 = 0x14 No Image 21 = 0x15 No Permission 22 = 0x16 No Storage System 23 = 0x17 Not Loop Port 24 = 0x18 Not Participating 25 = 0x19 Object In Use 26 = 0x1A Parameter Object Does Not Exist 27 = 0x1B Target Object Does Not Exist 28 = 0x1C Timeout 29 = 0x1D Unknown Id 30 = 0x1E Unknown Parameter Handle 31 = 0x1F Unrecoverable Media Error 32 = 0x20 Invalid State 33 = 0x21 Transport Error 34 = 0x22 Volume Missing 35 = 0x23 Invalid Cursor 36 = 0x24 Invalid Target Logical Disk 37 = 0x25 No More Events 38 = 0x26 Lock Busy 39 = 0x27 Time Not Set 40 = 0x28 Not Supported Version 41 = 0x29 No Logical Disk For Storage System Virtual Disk 42 = 0x2A SCVD Presented 43 = 0x2B Denied On Slave 44 = 0x2C Not DRM Licensed 45 = 0x2D Not DRM Member 46 = 0x2E Invalid DRM Mode 47 = 0x2F Is Copying 48 = 0x30 Login Needed 49 = 0x31 Login Failed 50 = 0x32 Already Logged In 51 = 0x33 Storage Cell Connection Down 52 = 0x34 Group Empty 53 = 0x35 Incompatible Attribute 54 = 0x36 Is DRM Member 55 = 0x37 Is Log Unit 56 = 0x38 Not Online

57 = 0x39 Not Presented 58 = 0x3A Other Controller Failed 59 = 0x3B Maximum Objects 60 = 0x3C Maximum Size 61 = 0x3D Password Mismatch 62 = 0x3E Is Merging 63 = 0x3F Is Logging 64 = 0x40 Is Suspended 65 = 0x41 Bad Image Header 66 = 0x42 Bad Image 67 = 0x43 Image Too Large 68 = 0x44 EMU Not Available 69 = 0x45 EMU Indefinite Delay 70 = 0x46 Image Incompatible 71 = 0x47 Bad Image Segment 72 = 0x48 Image Already Loaded 73 = 0x49 Image Write Error 74 = 0x4A SCVD Sharing 75 = 0x4B Bad Image Size 76 = 0x4C Image Load Busy 77 = 0x4D Volume Failure Predicted 78 = 0x4E Invalid Object Condition 79 = 0x4F Invalid Pred Logical Disk Condition 80 = 0x50 Invalid Volume Usage 81 = 0x51 Minimum Volumes In Disk Group 82 = 0x52 Shutdown In Progress 83 = 0x53 Not Ready 84 = 0x54 Is Snapshot 85 = 0x55 Incompatible Mirror Policy 86 = 0x56 Inoperative 87 = 0x57 Disk Group Inoperative 88 = 0x58 Storage System Inoperative 89 = 0x59 Failsafe Locked 90 = 0x5A Data Flush Incomplete 91 = 0x5B Redundancy Mirrored Inoperative 92 = 0x5C Duplicate LUN 93 = 0x5D Other Remote Controller Failed 94 = 0x5E Unknown Remote Unit 95 = 0x5F Unknown Remote Group 96 = 0x60 PLDMC Failed 97 = 0x61 Storage System Management Interface Lock Failed 98 = 0x62 Remote SCS Error 99 = 0x63 Storage System Connection Up 100 = 0x64 Login Needed Pwd Changed 101 = 0x65 Maximum Logins 102 = 0x66 Invalid Cookie 103 = 0x67 Login Timedout 104 = 0x68 Maximum Snapshot Depth 105 = 0x69 Attribute Mismatch 106 = 0x6A Password Not Set 107 = 0x6B Not Host Port 108 = 0x6C Duplicate LUN WWID 109 = 0x6D System Inoperative 110 = 0x6E Snapclone Active 111 = 0x6F EMU Load Busy 112 = 0x70 Duplicate User Name 113 = 0x71 Drive Reserved For Code Load 114 = 0x72 Already Presented 115 = 0x73 Invalid Remote Storage System 116 = 0x74 No Storage System Management Interface Lock

117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0

Maximum Members Maximum Destinations Empty User Name Storage System Exists Already Open Session Not Open Not Marked Inoperative Media Not Available Battery System Failed Member Is Cache Data Lost Internal Lock Collision OCP error Mirror temporarily offline Failsafe Mode enabled Drive FW load abort due to Vraid0 Vdisk FC Ports Unavailable Only two remote relations are allowed The requested SRC mode is not possible Src group discarded, but dest group NOT discarded Invalid DRM Group Tunnel specified Specified DRM Log size is too small Invalid DRM Log LDAD specified DRM Group is already read-only DRM Group is already active-active DILX is already running DILX is not running invalid user defined log size Invalid second handle parameter passed to scmi DRM Group already Auto Suspended. Specified option is not implemented yet DRM Group is already present_only The PU NOID is invalid SCS Internal Error Invalid SCS Function Code Unsupported SCS Function Code Init PS Failed Target BAD NOID PStore Is Volume Bad Volume Usage Bad LDAD_Usage No LDAD Handle Bad Quorum Flag SCS U_T_TAG Invalid SCS U_T_TAG Bad UUID Too Many PS Tags Bad Routine No Tag for NOID Bad Loop Num Too Many Port WWNS Port WWN Not Found No DU For PU No SCCL For PU Unsupported SCS Operation Failed Has Members Incompatible Preferred Mask Too Few Vol Tag ILF Debug Flag Not Set Invalid POID Too Few Drives

177 = 0xB1 178 = 0xB2 179 = 0xB3 180 = 0xB4 181 = 0xB5 182 = 0xB6 183 = 0xB7 184 = 0xB8 185 = 0xB9 186 = 0xBA 187 = 0xBB 188 = 0xBC 189 = 0xBD 190 = 0xBE 191 = 0xBF 192 = 0xC0 193 = 0xC1 194 = 0xC2 195 = 0xC3 196 = 0xC4 197 = 0xC5 198 = 0xC6 199 = 0xC7 200 = 0xC8 201 = 0xC9 202 = 0xCA 203 = 0xCB 204 = 0xCC 205 = 0xCD 206 = 0xCE tree). 207 = 0xCF 208 = 0xD0 209 = 0xD1 210 = 0xD2 211 = 0xD3 212 = 0xD4 213 = 0xD5 214 = 0xD6 215 = 0xD7 216 = 0xD8 217 = 0xD9 218 = 0xDA 219 = 0xDB 220 = 0xDC 221 = 0xDD 222 = 0xDE 223 = 0xDF 224 = 0xE0 225 = 0xE1 226 = 0xE2 227 = 0xE3 228 = 0xE4 229 = 0xE5 230 = 0xE6 231 = 0xE7 232 = 0xE8 233 = 0xE9 234 = 0xEA 235 = 0xEB

Too Few PS Tags Unexpected SCS Error Unsupported Capacity One or both controllers do not have the required 512MB of memory. Insuffcient drives of required type to create LDAD LDAD contains mixed drive types. Operation already in on state Operation already in off state cs_ld_get_vdisk_info failed. No Derived Unit For Storage System Virtual Disk Invalid on mixed DRM configuration Invalid Port number spefified DRM group does not exist Target Object is inoperative A read16 command requested that is unknown. The controller requested is not A or B A get special page scsi cmd requested an unknown page. Cannot set failsafe because async enabled The Logical Disk is not an empty container/not a mirror clone The source LD and empty container are in different LDAD's This operation is not allowed on an empty container This operation is not allowed in AA mode The redundancy specified for snap is not allowed The redundancy in a snapshot tree must be the consistent No path was found to DR destination Nonexistent group for operation Invalid async log size Generic async log size failure going to async Is not in syncronous mode An instant restore operation is in progress on this LD (or others in The logical disk is a mirror clone The mirror clone is resyncing The logical disk has a mirror clone. Unknown Remote Node Instant Restore mode incompatible. The DRM group is not suspended. The Logical Disks are not in the same snapshot tree The operation is not allowed on an original Logical Disk. Recontructing or reverting is in progress in LDAD. Not enough quorum disks for redundancy to do drive codeload. The requested operation has already been done. A drive is in maintenance mode. Invalid snapshots are being deleted. Temp Sync Set Maximum instant restores - wait for one to finish. SCELL Not Locked SCELL Lock Busy DRM Group already set to Defer Copy. Related operation in set of operations has failed A Log Shrink is currently in progress A Log Dealloc is currently in progress Resereved WWN LD not compatible with LDAD type Cannot clear additional drive INOPs without resync Group is performing an ASYNC add/remove/shrink Member Removed due to LOG FULL DRM groups exist Can't resolve a RAID6 INOP condition DRM Destination can't support the source requested Raid Type

236 = 0xEC 237 = 0xED ioned 238 = 0xEE 239 = 0xEF state 240 = 0xF0 241 = 0xF1 242 = 0xF2

An operation on the object is not supported because it is a large lun An operation on the object is not supported because it is thin provis SCSI-3 Check Condition Error. Autosense data returned This operation failed because the target SCVD is in the TP OVERCOMMIT MC and VD with same LDAD and RAID Drives are in Exception proccessing or the BE is unstable CS set capacity failed on expand/shrink operation

%[fcs_fail] 1 = Excessive exchange timeouts on loop 2 = Excessive link errors on loop 3 = Exhausted Link Down retries on loop with signal 4 = Exhausted Link Down retries on loop with loss of signal 5 = Excessive link inits on loop without completing device 6 = Unsupported SFP speed rating 7 = Purposely failed for elmo codeload****************************************** *************************************************************** %[mirror_fcs_fail] 65 = Excessive link errors on loop 66 = Exhausted Link Down retries on loop with signal 67 = Exhausted Link Down retries on loop with loss of signal 68 = Excessive link inits on loop without completing device 69 = Unsupported SFP speed rating 70 = Freezing Fibre Channel port in order to abort 71 = Restart to process bogus bad AL_PA Outbound Completion Message 72 = Forced link fail following detection of Frame Time Out 73 = Forced link fail due to maximum number of Link Down link init retries excee ded 74 = Forced link fail due to Port Event Queue full %[scsi_asc_ascq] 0x0000 = No additional sense information 0x0001 = Filemark detected 0x0002 = End-of-partition/medium detected 0x0003 = Setmark detected 0x0004 = Beginning-of-partition/medium detected 0x0005 = End-of-data detected 0x0006 = I/O process terminated 0x0011 = Audio play operation in progress 0x0012 = Audio play operation paused 0x0013 = Audio play operation successfully completed 0x0014 = Audio play operation stopped due to error 0x0015 = No current audio status to return 0x0100 = No index/sector signal 0x0200 = No seek complete 0x0300 = Peripheral device write fault 0x0301 = No write current 0x0302 = Excessive write errors 0x0386 = Write error - recommend reassignment 0x0400 = Logical unit not ready, cause not reportable 0x0401 = Logical unit is in process of becoming ready 0x0402 = Logical unit not ready, initializing command required 0x0403 = Logical unit not ready, manual intervention required 0x0404 = Logical unit not ready, format in progress 0x0600 = No reference position found 0x0700 = Multiple peripheral devices selected 0x0800 = Logical unit communication failure

0x0801 0x0802 0x0900 0x0901 0x0902 0x0903 0x0904 0x0A00 0x0B01 0x0C00 0x0C01 0x0C02 0x0C03 0x0E03 0x1000 0x1100 0x1101 0x1102 0x1103 0x1104 0x1105 0x1106 0x1107 0x1108 0x1109 0x110A 0x110B 0x110C 0x1200 0x1300 0x1400 0x1401 0x1402 0x1403 0x1404 0x1500 0x1501 0x1502 0x1503 0x1600 0x1700 0x1701 0x1702 0x1703 0x1704 0x1705 0x1706 0x1707 0x1708 0x1800 0x1801 0x1802 0x1803 0x1804 0x1805 0x1806 0x1807 0x1900 0x1901 0x1902

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

Logical unit communication time-out Logical unit communication parity error Track following error Tracking servo failure Focus servo failure Spindle servo failure Head Select Fault Error log overflow Temperature exceeded Write error Recovered data - data auto-reallocated Write error - auto reallocation failed Write error - recommend reassignment Invalid Field in Command Information Unit Id crc or ecc error Unrecovered read error Read retries exhausted Error too long to correct Multiple read errors Unrecovered read error - auto reallocate failed L-ec uncorrectable error Circ unrecovered error Data resynchronization error Incomplete block read No gap found Miscorrected error Unrecovered read error - recommend reassignment Unrecovered read error - recommend rewrite the data Address mark not found for id field Address mark not found for data field Recorded entity not found Record not found Filemark or setmark not found End-of-data not found Block sequence error Random positioning error Mechanical positioning error Positioning error detected by read of medium End of user area encountered on this track Data synchronization mark error Recovered data with no error correction applied Recovered data with retries Recovered data with positive head offset Recovered data with negative head offset Recovered data with retries and/or circ applied Recovered data using previous sector id Recovered data without ecc - data auto-reallocated Recovered data without ecc - recommend reassignment Recovered data without ecc - recommend rewrite Recovered data with error correction applied Recovered data with error correction & retries applied Recovered data - data auto-reallocated Recovered data with circ Recovered data with lec Recovered data - recommend reassignment Recovered data - recommend rewrite Recovered data - data rewritten Defect list error Defect list not available Defect list error in primary list

0x1903 0x190E 0x1A00 0x1B00 0x1C00 0x1C01 0x1C02 0x1D00 0x1E00 0x1F00 0x2000 0x2100 0x2101 0x2200 0x2200 0x2400 0x2500 0x2600 0x2601 0x2602 0x2603 0x2604 0x2697 0x2698 0x2699 0x2700 0x2800 0x2801 0x2900 0x2901 0x2902 0x2903 0x2904 0x2A00 0x2A01 0x2A02 0x2A03 0x2A04 0x2A05 0x2A06 0x2A07 0x2A09 0x2B00 0x2C00 0x2C01 0x2C02 0x2D00 0x2F00 0x3000 0x3001 0x3002 0x3003 0x3100 0x3101 0x3191 0x3200 0x3201 0x3300 0x3500 0x3501

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

Defect list error in grown list Defect list error -- fewer than 50% defect list copies Parameter list length error Synchronous data transfer error Defect list not found Primary defect list not found Grown defect list not found Miscompare during verify operation Recovered id with ecc correction Read Defect command allocated space overflow Invalid command operation code Logical block address out of range Invalid element address Illegal function Present Only Read Violation Invalid field in cdb Logical unit not supported Invalid field in parameter list Parameter not supported Parameter value invalid Threshold parameters not supported Invalid release of persistent reservation Invalid field parameter -- TMS firmware tag Invalid field parameter -- check sum Invalid field parameter -- firmware tag Write protected Not ready to ready transition, medium may have changed Import or export element accessed Power on, reset, or bus device reset occurred Power on occurred SCSI bus reset occurred Bus device reset occurred Internal reset Parameters changed Mode parameters changed Log parameters changed Reservations Preempted Reservations Released Registrations preempted Asymmetric access state changed Asymmetric access state transition failed Capacity data changed Copy cannot execute since host cannot disconnect Command sequence error Too many windows specified Invalid combination of windows specified Overwrite error on update in place Commands cleared by another initiator Incompatible medium installed Cannot read medium - unknown format Cannot read medium - incompatible format Cleaning cartridge installed Medium format corrupted Format command failed Format corrupted World Wide Name invalid No defect spare location available Defect list update failure Tape length error Unspecified enclosure services failure Unsupported enclosure function

0x3502 0x3503 0x3504 0x3600 0x3700 0x3900 0x3A00 0x3B00 0x3B01 0x3B02 0x3B03 0x3B04 0x3B05 0x3B06 0x3B07 0x3B08 0x3B09 0x3B0A 0x3B0B 0x3B0C 0x3B0D 0x3B0E 0x3D00 0x3E00 0x3F00 0x3F01 0x3F02 0x3F03 0x3F05 0x3F0E 0x3F80 0x3F90 he ETF 0x3F91 0x3f05 0x4000 0x4001 0x4002 0x4100 0x4200 0x4300 0x4400 0x4500 0x4600 0x4700 0x4780 0x4800 0x4900 0x4A00 0x4B00 0x4C00 0x4E00 0x5000 0x5001 0x5002 0x5100 0x5200 0x5300 0x5301 0x5302

= Enclosure services unavailable = Enclosure transfer failure = Enclosure transfer refused = Ribbon, ink, or toner failure = Rounded parameter = Saving parameters not supported = Medium not present = Sequential positioning error = Tape position error at beginning-of-medium = Tape position error at end-of-medium = Tape or electronic vertical forms unit not ready = Slew failure = Paper jam = Failed to sense top-of-form = Failed to sense bottom-of-form = Reposition error = Read past end of medium = Read past beginning of medium = Position past end of medium = Position past beginning of medium = Medium destination element full = Medium source element empty = Invalid bits in identify message = Logical unit has not self-configured yet = Target operating conditions have changed = Microcode has been changed = Changed operating definition = Inquiry data has changed = Device identifier changed = Reported LUNs data has changed = Read after write buffer contents changed = Invalid CAP block -- servo Flash SAP HDA serial number does not match t SAP HDA serial number = World Wide Name mismatch = Device identifier has changed = Ram failure = DRAM parity error = DRAM parity error = Data path failure = Power-on or self-test failure = Message error = Internal target failure = Select or reselect failure = Unsuccessful soft reset = SCSI parity error = Fibre Channel Sequence Error -- frame not received by E_D_TOV = Initiator detected error message received = Invalid message error = Command phase error = Data phase error = Logical unit failed self-configuration = Overlapped commands attempted = Write append error = Write append position error = Position error related to timing = Erase failure = Cartridge fault = Media load or eject failed = Unload tape failure = Medium removal prevented

0x5400 0x5500 0x5501 0x5700 0x5800 0x5900 0x5A00 0x5A01 0x5A02 0x5A03 0x5B00 0x5B01 0x5B02 0x5B03 0x5C00 0x5C01 0x5C02 0x5D00 0x5D04 0x5D05 0x5D06 0x5D31 0x5D32 0x5D37 0x5D38 0x5D41 0x5D43 0x5D45 0x5D5B 0x5DEE 0x5DFF 0x6000 0x6100 0x6101 0x6102 0x6200 0x6300 0x6400 0x6500 0x8000 0x8080 0x8081 0x8082 0x8083 0x8084 0x8085 0x8086 0x8087 0x8100

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

SCSI to host system interface failure System resource failure XOR cache not available Unable to recover table-of-contents Generation does not exist Updated block read Operator request or state change input Operator medium removal request Operator selected write protect Operator selected write permit Log exception Threshold condition met Log counter at maximum Log list codes exhausted Rpl status change Spindles synchronized Spindles not synchronized Failure prediction threshold exceeded exceeded -- disk reassign DST table exceeded -- disk reassign AST table exceeded -- disk reassign DDT table Failure prediction threshold exceeded -- head failure Failure prediction threshold exceeded -- recovered data error rate Failure prediction threshold exceeded -- recovered TA Failure prediction threshold exceeded -- hard TA event Failure prediction threshold exceeded -- SSE DPF smoothing Failure prediction threshold exceeded -- seek DPF smoothing Failure prediction threshold exceeded -- track following errors Failure prediction threshold exceeded -- spinup DFP smoothing Failure prediction threshold exceeded -- no control table on disk False failure prediction threshold exceeded Lamp failure Video acquisition error Unable to acquire video Out of focus Scan head positioning error End of user area encountered on this track Illegal mode for this track Voltage fault Vendor specific. FC FIFO error during read transfer FC FIFO error during write transfer DISC FIFO error during read transfer DISC FIFO error during write transfer LBA seeded LRC error on read LBA seeded LRC error on write IOEDC error on read IOEDC error on write Reassign power fail recovery failed

%[scsi_sensekey] 0x0 = NO SENSE 0x1 = RECOVERED ERROR 0x2 = NOT READY 0x3 = MEDIUM ERROR 0x4 = HARDWARE ERROR 0x5 = ILLEGAL REQUEST 0x6 = UNIT ATTENTION 0x7 = DATA PROTECT 0x8 = BLANK CHECK

0x9 0xA 0xB 0xC 0xD 0xE 0xF

= = = = = = =

Vendor Specific COPY ABORTED ABORTED COMMAND EQUAL VOLUME OVERFLOW MISCOMPARE RESERVED

%[scsi_cmds] 0x00 = TEST UNIT READY 0x01 = REZERO UNIT 0x03 = REQUEST SENSE 0x04 = FORMAT UNIT 0x07 = REASSIGN BLOCKS 0x08 = READ (6 byte) 0x0A = WRITE (6 byte) 0x0B = SEEK (6 byte) 0x12 = INQUIRY 0x14 = RECOVER BUFFERED DATA 0x15 = MODE SELECT (6 byte) 0x16 = RESERVE UNIT 0x17 = RELEASE UNIT 0x18 = COPY 0x1A = MODE SENSE (6 byte) 0x1B = START STOP UNIT 0x1C = RECEIVE DIAGNOSTIC RESULTS 0x1D = SEND DIAGNOSTIC 0x1E = PREVENT-ALLOW MEDIUM REMOVAL 0x25 = READ CAPACITY 0x28 = READ (10 byte) 0x2A = WRITE (10 byte) 0x2B = SEEK (10 byte) 0x2E = WRITE AND VERIFY (10 byte) 0x2F = VERIFY (10 byte) 0x30 = SEARCH DATA HIGH (10 byte) 0x31 = SEARCH DATA EQUAL (10 byte) 0x32 = SEARCH DATA LOW (10 byte) 0x33 = SET LIMITS (10 byte) 0x34 = PRE-FETCH 0x35 = SYNCHRONIZE CACHE 0x36 = LOCK-UNLOCK CACHE 0x37 = READ DEFECT DATA (10 byte) 0x38 = MEDIUM SCAN 0x39 = COMPARE 0x3A = COPY AND VERIFY 0x3B = WRITE BUFFER 0x3C = READ BUFFER 0x3E = READ LONG 0x3F = WRITE LONG (10 byte) 0x40 = CHANGE DEFINITION 0x41 = WRITE SAME (10 byte) 0x4C = LOG SELECT 0x4D = LOG SENSE 0x50 = XDWRITE (10 bytes) 0x51 = XPWRITE (10 bytes) 0x52 = XDREAD (10 bytes) 0x55 = MODE SELECT (10 byte) 0x56 = SCSI-3 SPC p.70 0x57 = SCSI-3 SPC p.88 0x5A = MODE SENSE (10 byte)

0x5E 0x5F 0x81 0x82 0x88 0x8A 0x8E 0x8F 0x91 0x9E 0x9E 0x9E 0x9F 0x9F 0xA0 0xA3 0xA4 0xA8 0xAA 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xEB 0xEC

= = = = = = = = = = = = = = = = = = = = = = = = = = =

PERSISTENT RESERVE IN PERSISTENT RESERVE OUT REBUILD REGENERATE READ (16 byte) WRITE (16 byte) WRITE AND VERIFY (16 byte) VERIFY (16 byte) SYNCHRONIZE CACHE (16 bytes) READ CAPACITY (Jumbo Version) SERVICE ACTION IN (16 bytes) READ LONG (16 bytes) WRITE LONG (16 byte) SERVICE ACTION OUT (16 bytes) REPORT LUNS Report Timestamp Set Timestamp READ (12 byte) WRITE (12 byte) WRITE AND VERIFY (12 byte) VERIFY (12 byte) SEARCH DATA HIGH (12 byte) SEARCH DATA EQUAL (12 byte) SEARCH DATA LOW (12 byte) SET LIMITS (12 byte) WRITE ID REPORT ID

%[els_codes] 0x01 = Link service reject 0x02 = Accept 0x03 = N_Port login 0x04 = F_port login 0x05 = Logout 0x06 = Abort exchange 0x07 = Read connection status 0x08 = Read exchange status block 0x09 = Read sequence status block 0x0A = Read sequence initiative 0x0B = Establish streaming 0x0C = Estimate credit 0x0D = Advise credit 0x0E = Read timeout value 0x0F = Read link status 0x10 = Echo 0x11 = Test 0x12 = Reinstate recovery qualifier 0x13 = Read Exchange Concise 0x20 = Process login 0x21 = Process logout 0x22 = State change notification 0x23 = Test process login state 0x24 = Third party process logout 0x25 = Login Control List Management 0x30 = Get alias id 0x31 = Fabric activate alias id 0x32 = Fabric deactivate alias id 0x33 = N_Port activate alias id 0x34 = N_Port deactivate alias id 0x40 = Quality of service request

0x41 0x50 0x51 0x52 0x53 0x56 0x57 0x58 0x59 0x60 0x61 0x62 0x63 0x68 0x69 0x70 0x71 0x72 0x77 0x78 0x79 0x7A 0xF0

= = = = = = = = = = = = = = = = = = = = = = =

Read virtual circuit status Discover N_Port service parms Discover F_Port service parms Discover address Report Node Capabilites Read Port Status Block Read Port List Bandwidth Allocation Bandwidth DeAllocation Fabric Address Notification Registered State Change Notification State Change Registration Report Node FC-4 Types Clock Sync Request Clock Sync Update Loop Initialize Loop Port Control Loop Status Request Topology Information Request Node Identification Information Registered Link Incident Record Link Incident Record Registration Vendor Unique - SCS message

%[fm_terminate_routines] 0 = FM_TERMINATE_START 1 = FM_TERMINATE_PREP1 2 = FM_TERMINATE_LOAD_LTE_GLUE_REGS 3 = FM_TERMINATE_PREP2 4 = FM_TERMINATE_LOAD_LTE_INFO 5 = FM_TERMINATE_LOAD_LTE_POLMEMCTRLR_REGS 6 = FM_TERMINATE_LOAD_LTE_CACMEMCTRLR_REGS 7 = FM_TERMINATE_LOAD_LTE_TACHYON0_REGS 8 = FM_TERMINATE_LOAD_LTE_TACHYON1_REGS 9 = FM_TERMINATE_LOAD_LTE_TACHYON2_REGS 10 = FM_TERMINATE_LOAD_LTE_TACHYON3_REGS 11 = FM_TERMINATE_LOAD_LTE_TACHYON4_REGS 12 = FM_TERMINATE_LOAD_LTE_TACHYON5_REGS 13 = FM_TERMINATE_LOAD_LTE_TACHYON6_REGS 14 = FM_TERMINATE_LOAD_LTE_TACHYON7_REGS 15 = FM_TERMINATE_LOAD_LTE_TACHYON8_REGS 16 = FM_TERMINATE_LOAD_LTE_TACHYON9_REGS 17 = FM_TERMINATE_LOAD_LTE_TOY_REGS 18 = FM_TERMINATE_LOAD_LTE_UART1_REGS 19 = FM_TERMINATE_LOAD_LTE_UART2_REGS 20 = FM_TERMINATE_LOAD_LTE_UART3_REGS 21 = FM_TERMINATE_LOAD_LTE_UART4_REGS 22 = FM_TERMINATE_DECODER_REGS 23 = FM_TERMINATE_LOAD_LTE_TACHYON10_REGS 24 = FM_TERMINATE_LOAD_LTE_TACHYON11_REGS 25 = FM_TERMINATE_EXPANSION8 26 = FM_TERMINATE_CBIC_TALK_OFF 27 = FM_TERMINATE_DECODE_MACHINE_CHECK 28 = FM_TERMINATE_PRESERVE_EVENTS 29 = FM_TERMINATE_SEND_LAST_GASP 30 = FM_TERMINATE_CRASH_DUMP_PREP 31 = FM_TERMINATE_CRASH_DUMP 32 = FM_TERMINATE_COMPUTE_LTE_EDC 33 = FM_TERMINATE_RESTART_INIT 34 = FM_TERMINATE_RESTART_ACTION

35 = FM_TERMINATE_END %[fm_ue] 0 = Unrecognized Unexpected Event code 1 = Power failure before initialization could complete 2 = Recursive termination before initialization could complete 3 = Terminated during the first part post-termination preparation 4 = Terminated during the load of the G3 Glue registers 5 = Terminated during the second part post-termination preparation 6 = Terminated during event report block load 7 = Terminated during initialization of all hardware components and software dat a structures in preparation for restart 8 = Terminated during execution of an unrecognized post-termination operation (p remature) 9 = Power failure during execution of a post-termination operation 10 = No good entries found in Termination Event Array. (Note that this condition is expected following the first boot of a newly manufactured HSV450 controller. In that case this event can be safely ignored; no action is necessary.) 11 = The edc of one or more Last Termination Event Array entries is bad 12 = Last Termination Event Array entry control block revision is different 13 = Last Termination Event Array entry information block revision is different 14 = Last Termination Event Array entry up time value is greater than the system 's up time value 15 = Last Termination Event Array entry up time value is less than the previous entry's up time value 16 = Last Termination Event Array entry sequence number value is less than the p revious entry's sequence number value 17 = Detected an unrecognized dump/restart control code 18 = Failed to terminate the entity dump loop 19 = Unexpected dump entity size 20 = Unexpected elp processing stage code 21 = Number of Termination Parameters supplied not equal to maximum allowed as r equired 22 = Detected an unexpected address map companion block control code 23 = Original TP[0] value replaced by DIMM size load 24 = Unexpected meal commit stage code %[fm_mpvfc] 0 = Success 1 = Cookie value is not as expected 2 = Event data overflows the buffer 3 = Event data size is not a multiple of 4 bytes, is less than the minimum, or i s greater than the maximum 4 = Event Information Packet type is greater than the maximum 5 = Event information size is not a multiple of 4 bytes, is less than the minimu m, is greater than the maximum, doesn't match the eip type size, or when combine d with the entry header size doesn't equal the entry size 6 = Event code is zero 7 = Event is out of sequence (0) 8 = Dead space area at the end of a partially packed buffer contains a nonzero v alue 9 = An event data block containing a nonzero value was found after end of event data was detected 10 = Sequence number reset flag not set as expected 11 = The event log contains no entries 12 = Event data block read failed during maintenance verification 13 = Event data block read failed during maintenance completion 14 = Event data block erase failed during maintenance completion 15 = Control block read failed during maintenance verification 16 = Control block write failed during maintenance verification

17 = Event data block write failed during maintenance update 18 = Control block write failed during maintenance completion 19 = Storage System Termination Event Log related send was unsuccessful or the m aster found that the Storage System Termination Event Log is inaccessible 20 = Control block read failed during maintenance verification by the other HSV4 50 controller 21 = Control block read failed during update retrieval 22 = Event data block read failed during retrieval request 23 = Log has been prepared for re-initialization 24 = Event is out of sequence (1) 25 = Event is out of sequence (2) 26 = Event is out of sequence (3) %[fm_quiesce] 0 = Make FM quiescent on both controllers 1 = Make FM quiescent on slave controller only %[rcse] 0 = Requested by Storage System Management Interface use image 1 = Requested by CTRL_F 2 = Requested by Storage System Management Interface, shutdown #define RCSE_DFW_ UPGRADE 3 obsolete #define RCSE_DFW_UPGRADED 4 obsolete 5 = Attempt to check new device for System WWN 6 = Existing cell lost quorum 7 = Quorum disks have changed in existing cell 8 = An active cell has lost its quorum 9 = WWN has been found on new quorum 10 = ID has changed on a physical store 11 = System has been scrubbed 12 = Logged in port for ILF cannot be found 13 = The ILF disk is no longer logged in 14 = The ILF id block failed to write 15 = Scrub requested from OCP 16 = The system Disk Group changed 17 = An attempt to realize a logical disk failed 18 = The master crashed during a resync recovery window 19 = The master crashed during a resync window with no cell 20 = The slave failed before returning status of an unshare 21 = An operation to get a cmap failed 22 = A CVMDB access failed #define RCSE_METADATA_FAIL 23 obsolete 24 = An initiate logical disk expand failed 25 = An attempt to take a logical disk online failed 26 = A flush unit operation failed on the slave 27 = Recovery to handle too much frozen data 28 = An attempt to take a logical disk offline failed 29 = An attempt to unrealize a logical disk failed 30 = An attempt to update the RSSM on media failed 31 = Container Services failed to initiate a merge operation 32 = A new WWN was entered on the OCP 33 = Deadlock avoidance for drive code load 34 = A drive appeared while the system was inoperative 35 = A drive has failed a BBR check 36 = A drive has appeared which may fix a multi disk failure #define RCSE_HIERAR CHY_FAIL 37 obsolete 38 = A virtual disk could not be presented 39 = Quorum disk could not be found after a failover 40 = An attempt to realize the csld failed 41 = A storage cell went undetected during realization 42 = Quorum was lost during cell realization 43 = A drive disappeared during cell realization

44 = Cell realization failed but device discovery will not complete 45 = An attempt to realize the scscb failed 46 = A snapshot or snapclone tree was split across the master and slave 47 = A reduced quorum set was reconstructed 48 = A migration operation initiation failed 49 = An attempt to delete a logical disk failed 50 = An attempt to take a logical disk offline other failed 51 = An attempt to synch the mirror for a logical disk failed 52 = Container Services failed to initiate a split operation 53 = A virtual disk could not be unpresented 54 = An attempt to take a unit operative failed 55 = Debug flags are being committed 56 = Requested by the OCP 57 = DRM went offline 58 = DRM went offline with writes in progress 59 = A memory allocation failed 60 = A loop initiator disruptor drive was bypassed 61 = ID blocks on a drive were erased 62 = An attempt to realize the PLDMC failed 63 = A logical disk in an inoperative Disk Group was expected to be inoperative but was not 64 = An unshare operation failed 65 = An rss member failed during cell realization 66 = A Disk Group has become metadata inoperative for all use RAID types 67 = Requested by maintenance or SCS debug command 68 = A confirmation was refused on the OCP 69 = A confirmation was approved on the OCP 70 = An attempt to unmirror a logical disk failed 71 = An attempt to quiesce a unit failed 72 = Container Services failed to add a Disk Group 73 = Container Services failed to delete a Disk Group 74 = Print flags have changed 75 = Debug flags have changed 76 = The master failed while trying to get information from it 77 = An attempt to erase quorum failed 78 = An attempt to copy psars failed 79 = Container Services failed to initiate a marry operation 80 = An attempt to update or init rss meta failed so an attempt was made to faul t a drive 81 = A system inoperative controller was activated by the master indicating that inoperative condition was fixed 82 = A drive has unexpectedly changed its worldwide name 83 = A drive has unexpectedly changed its worldwide name 84 = PRLI handler detected other controller reboot 85 = host port topology change detected 86 = Slave failed during staggered code load, so reboot now 87 = The configuration changed while the system was inoperative 88 = I/O commited, log inop so no place to put it, so reboot now 89 = About to write an ID block, but drive pointer changed 90 = Enter safe mode 91 = The slave failed before returning status of a mirrorclone resync 92 = Starting a mirror clone resync failed 93 = Couldn't clear the ldrm to finish fracture 94 = Starting a mirror clone fracture failed 95 = The slave failed before returning status of an instant restore 96 = Completing a LD restore failed 97 = Couldn't clear the ldrm to finish detach 98 = Starting a mirror clone detach failed 99 = Scrub requested from SCMI 100 = Scrub requested from CONSOLE

101 102 103 104 105 106 107 108 109 256 257 258

= = = = = = = = = = = =

Starting a lun shrink failed Forcing resync to clear ALL drive inop's Transaction present during preserving resync Preserved image validity check fail Preserved anchor not able to be restored Other controller down when trying to check allocation for vdisk create Other controller went down while creating lds for vdisk Remapping the TLB to be 1GB aligned Rewrote a drive's ID blocks because because of cached mismatch Active/Active write collision Trying to close tunnel with outstanding qsce operation Used for drm_flt_125, cause resync while destroying a group

%[drv_inop] 0x0 = Unknown 0x001 = Container Services I/O failure 0x002 = Scrubber I/O failure 0x003 = Attempt to set CBIT on normal drive 0x004 = Attempt to set CBIT on reverting drive 0x100 = Target Discovery Service Descriptor retry count exceeded 0x101 = Inoperable for Bad Block Replacement 0x102 = Soft error count exceeded */ /* DCD: UNREACHABLE? 0x103 = Exchange timeout count exceeded 0x104 = UNUSED 0x105 = Command retries exceeded 0x106 = Medium/Hardware Errors encountered on this device 0x107 = UNUSED 0x108 = Transport error count threshold exceeded 0x109 = Unsupported DSL operation 0x10A = Uncorrected SCSI error 0x200 = Smart event from a physical disk drive not in Storage System 0x201 = Smart event from a physical disk drive not a Volume 0x202 = Smart event from a physical disk drive not a Redundant Storage Set 0x203 = Failure predicted from physical disk drive 0x204 = Cannot read from physical disk drive from the poll 0x205 = Failure predicted from physical disk drive while deleting Disk Group 0x206 = physical disk drive forced inoperative from maintenence command for temp orary POID 0x207 = physical disk drive forced inoperative from maintenence command for POID 0x208 = Bad block recovery failed or cannot read FPAB 0x209 = Failure to remove volume from Storage System 0x20a = Failure to update metadata 0x20b = Failure to update metadata - physical disk drive is missing - will NOT b e marked inoperable 0x210 = About to write ID block 0 to wrong physical disk drive 0x211 = About to write ID blocks to wrong physical disk drive 0x212 = About to write ID block 2 to wrong physical disk drive 0x213 = About to write ID blocks after retry to wrong physical disk drive %[fcs_mtl] 1 = The physical disk drive left itself bypassed 2 = The Drive Enclosure Environmental Monitoring Unit bypassed the drive bay %[cac_mnemonic] 0x00 = CAC_NO_ACTION 0x01 = CAC_NOTIFY_FUSION_DEV 0x02 = CAC_NOTIFY_OPSYS 0x03 = CAC_SEE_TC 0x04 = CAC_TC_RECURSED 0x05 = CAC_SEE_OTC

0x06 0x07 0x08 0x09 0x0a 0x0d 0x20 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x36 0x37 0x38 0x39 0x3a 0x3b 0x40 0x41 0x42 0x44 0x46 0x47 0x48 0x49 0x4a 0x4c 0x4d 0x4e 0x4f 0x50 0x51 0x52 0x5f 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6a 0x6b 0x80 0x81 0x82

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

CAC_SEE_ASSOC_TEVENT CAC_ADVISEW_FUSION_DEV CAC_ADVISEI_FUSION_DEV CAC_DETERMINE_PFC CAC_LOW_MEM_ACC_ADVICE CAC_USER_INTERVENTION CAC_REPLACE_CB CAC_REPLACE_BATTA CAC_REPLACE_BATTB CAC_REPLACE_BLOWERA CAC_REPLACE_BLOWERB CAC_REPLACE_BLOWERPSA CAC_REPLACE_BLOWERPSB CAC_REP_REMOVED_BATTA CAC_REP_REMOVED_BATTB CAC_REP_REMOVED_BLWRA CAC_REP_REMOVED_BLWRB CAC_REP_REMOVED_BLWRPSA CAC_REP_REMOVED_BLWRPSB CAC_REDUCE_AMBIENT CAC_CHECK_BATTS CAC_GBIC_CHECK_FAILURE CAC_OVER_TEMP CAC_TEMP_UNDETERMINED CAC_REPLACE_BATTCAUTION CAC_RECUR_REPLACE_CB CAC_GBIC_NOT_PRESENT CAC_SRAM_TEST_ERROR CAC_REPLACE_DRIVE CAC_REP_REMOVED_DRIVE CAC_REMOVE_REPLACE_DRIVE CAC_PORT_FAILURE CAC_REPLACE_DRIVE_PORT CAC_FRAME_TIMEOUT CAC_UNEXPECTED_WORK CAC_BAD_ALPA CAC_LINK_FAILURE CAC_SPOF_DRIVE CAC_UPDATE_DRIVE_FW CAC_SPOF_SHELF CAC_REMOVE_DRIVE CAC_DEL_SNAP_SCVD CAC_EVAL_SCVD CAC_IR_DEL_SCVD CAC_CHECK_CONN CAC_CHECK_SRC_UNIT CAC_CHECK_DEST_UNIT CAC_CHECK_LOG CAC_CHECK_SITE_VERSIONS CAC_DRM_CHECK_REM_BACKEND CAC_DRM_RESTART_REM CAC_DRM_RESTART_LOCAL CAC_DRM_CHECK_ISL CAC_DRM_CHECK_RMTNODES CAC_DRM_CHECK_ISL_SWITCH CAC_CHECK_SITE_SETTINGS CAC_DRM_CHECK_CONFIG CAC_REMOVE_REPLACE_DEPS CAC_REPLACE_DEPS CAC_REMOVE_REPLACE_DEBLWR

0x83 0x85 0x86 0x87 0x89 0x90 0x93 0x95 0x99 0x9a 0xb4 0xb5 0xb6 0xb9 0xba 0xbf 0xc3 0xc4 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef 0xf0 0xf1 0xf2 0xf3 0xf4

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

CAC_REPLACE_DEBLWR CAC_DE_CTRLR_SHUTDN CAC_CORRECT_TEMP CAC_CORRECT_TEMP_IMM CAC_REPLACE_DEEMU CAC_DE_CHECK_XCVR CAC_REPLACE_DEIOM CAC_RESET_DEIOM CAC_CHECK_DEIOM_CABLE CAC_CHECK_RACK_PDU CAC_CHANGE_OCCUPANCY CAC_CHANGE_LDAD_CONFIG CAC_RESTORE_SPOFRC CAC_EVAL_OTHER_NSC CAC_EVAL_PWR_OTHER_NSC CAC_EVAL_VOL CAC_EVAL_PORT CAC_NEW_DRIVE_FW CAC_REPLACE_BATT0 CAC_REPLACE_BATT1 CAC_REPLACE_BATT2 CAC_REPLACE_BATT3 CAC_REP_REMOVED_BATT0 CAC_REP_REMOVED_BATT1 CAC_REP_REMOVED_BATT2 CAC_REP_REMOVED_BATT3 CAC_CHECK_BATTS_XL CAC_REPLACE_BATTCAUTION_XL CAC_REPLACE_BLOWER0 CAC_REPLACE_BLOWER1 CAC_REP_REMOVED_BLWR0 CAC_REP_REMOVED_BLWR1 CAC_CHECK_REPLACE_PS0 CAC_CHECK_REPLACE_PS1 CAC_REP_REMOVED_PS0 CAC_REP_REMOVED_PS1 CAC_CHECK_BATT_COMM_XL CAC_MISMATCH_CODE CAC_REMOVE_ENCLOSURE CAC_RESTART_CONTROLLER CAC_RESTORE_REDUNDANCY CAC_CHECK_REPLACE_ENC_PS

%[storage_usage] 0 = Unallocated 1 = Quorum Space 2 = CSLD Logical Data 3 = Primary Logical Disk 4 = Primary LD Metadata 5 = LD Base RSD (LDDIR) 6 = Physical Metadata 7 = DRM LOG OD storage 8 = Supported USAGE Types %[exec_tod] 1 = TOY clock unavailable, 2 = TOY clock time is less eset to default 3 = Bad EDC for previously 4 = TOY clock not running, this controller's time reset to default than previously stored time, this controller's time r stored time, this controller's time reset to default this controller's time reset to default

5 = TOY clock is accurate, this controller's time set to TOY clock time value 6 = This controller's time was set from policy memory metadata following a contr oller resynchronization operation 7 = This controller's time was set to the current time value 8 = Following Storage System time synchronization the primary controller request ed that the secondary controller set its TOY clock to the current time value 9 = The secondary controller set its TOY clock to the current time value as requ ested by the primary controller 10 = This controller's TOY clock was set to the current time value STRUCTURE REVISION LEVELS: eip01: 4. eip02: 3. eip03: 5. eip04: 7. eip05: 4. eip06: 5. eip07: 1. eip08: 5. eip09: 7. eip0A: 3. eip0B: 5. eip0C: 5. eip0D: 1. eip0E: 3. eip0F: 2. eip10: 0. eip11: 4. eip12: 2. eip13: 7. eip14: 2. eip15: 0. eip16: 0. eip17: 1. eip18: 0. eip19: 11. eip1A: 0. eip1B: 4. eip1C: 1. eip1D: 0. eip1E: 1. eip1F: 0. eip20: 0. eip21: 0. eip23: 1. eip24: 1. eip26: 1. eip27: 1. eip28: 0. eip2A: 0. elp_event: 3. lte_control_block: 1. lte_info_block: 249. MAPPING INFORMATION: 00001a60 00000004 a07ed9acb22b54a0cec9e6d9bfc49902a078f3cc3ed0496478389489930763 d5 00001a64 00000098 af73cfbbb22d5cbed6efd0cca2 00001afc 00000140 af73cfbbb23c58aac3c5d5cb8fc5a508907de2cb36d95e49 00001c3c 00000244 af73cfbbb23c54bfd2d1cddcb8e9b50ca6

00001e80 000000d4 00001f54 0000022c 00002180 00000088 00002208 00000504 0000270c 00000074 00002780 00000274 000029f4 00000068 00002a5c 00000060 00002abc 00000040 00002afc 00000020 00002b1c 00000004 00002b20 00000004 00002b24 00000004 d5 00002b28 00000008 000038ac 00000004 d5 000038b0 00000010 000038c0 000001fc 00003abc 00000098 00003b54 000000a4 00003bf8 000000b4 00003cac 000000e4 df9415c7 00003d90 0000021c 00003fac 0000039c 00004348 00000120 00004468 000002d0 00004738 00000114 0000484c 000000cc 00004918 00000044 0000495c 00000ec8 00006128 00000004 d5 0000612c 00000004 00006130 0000006c 0000619c 00000088 00006224 00000114 00006338 000003f0 00006728 0000017c 000068a4 000001cc 00006a70 00000210 00006c80 000003fc 0000707c 00000354 000073d0 00000168 00007538 0000025c c3871fda7445 00007794 000000ac 00007840 000001bc 000079fc 0000027c 00007d04 00000004 d5 00007d08 00000478 00008180 00000060 000081e0 000000bc 0000829c 00000174 00008410 0000026c 0000867c 00000294 00008910 0000012c 00008a3c 000000dc

af73cfbbb22b50a5fdd3cbdea3de9909ae7be7c937c7 af73cfbbb2305ca2c6dcdce0bdd7a509a67be6fa31dd5e5864 8f53ef9bb2305ca2c6dcdce0b5ceb204bd7be2c90ddc554f6a2b94928a1d 8f53ef9bb23b4fadd1d8e6dbb9c4a302bb7af1 af73cfbbb23c58aac3c5d5cb8fd3be15aa67edc43eea52557b3c94958f1970 af73cfbbb2305ca2c6dcdce0a0c4a906bd74ee 8f53ef9bb2284fa3c1d5cacc8fd3be02aa65f7cc3ddb af73cfbbb2355ebcfdd3cbdea3de9909ae7be7c937c7 af73cfbbb22b4dbecbc4dce0bdd5b63ea774edc13ed049 8f53ef9bb2284fa9d2d1cbda8fd0a9139067e6d62bdb58 8f53ef9bb23c54bfc3d2d5da8fdbaf13bd7af1 8f53ef9bb22a58bfc7c4d8d3bce9b308ac4aebc43cd1575e7d2a 8f53ef9bb22a58bfc7c4d8d3bce9a319ac70f3d13bda556467388883960c76 8f53ef9bb22f5cbecfefcbdaa3d3b23ebf76eac00dd654496a a07ed9acb22b54a0cec9e6d9bfc49902a078f3cc3ed0496478389489930763 8f53ef9bb2284fa5ccc4e6cdb5d1b5 8f53ef9bb22a58adc6efd4debec3a03eaa70f3d73dd8645f6e2d87 a964c4ab82345893d0d5d8db8fc6b408a161dcc33ed45c48 a964c4ab82345893d0d5d8db8fd2a303ba72dcc33ed45c48 a964c4ab82345893d0d5d8db8fdfa810bf7ce7 a964c4ab82345893d0d5d8db8ff096199071e6c333c0574f502989958e3670 a964c4ab82345893d0d5d8db8fc1b10f a964c4ab82345893d3c5dccda9 8f53ef9bb22b55a3d5efdbdea4c5 ad6ede87822849a5cddeca ba79c3b699075fa0fdd9d7d9bf a87ec3b4890751a3c1d1d5e0a0d9a90d a87ec3b489074dbec7c3dccda6d3a23ebf7aecc9 8f53ef9bb23153a5d6efc9cfb3 a07ed9acb22b54a0cec9e6d9bfc49902a078f3cc3ed0496478389489930763 af73cfbbb22b44a2c1d8e6d9a5d8a53eae76e8fa31d457576d38858c 8f53ef9bb22c54a1c7efcac6bed59908a17cf7 8f53ef9bb23153a5d6efcdd0a9e9a50da076e8 8f53ef9bb23b52a2d4d5cbcb8fc2a93ebf65e0fa26dc565e 8f53ef9bb23b52a2d4d5cbcb8fd7b502a67cdcd13dea5952612d8f8a 8f53ef9bb22a58adc6efcdd0a9e9a50da076e8 8f53ef9bb23b52a2d4d5cbcb8fd0b40ea24af3d531ea4f52623c 8f53ef9bb23b52a2d4d5cbcb8fd4af0fbb7ceefa26da645a7c3a8f8e 8f53ef9bb22d4da8c3c4dce0a4d9bf3eac79ecc639 8f53ef9bb22b58b8fdc4d0d2b5 8f53ef9bb22c54a1c7efcac6bed5ae3ea960edc6 8f53ef9bb23b52a2d4d5cbcb8fd4af0fbb7ceefa26da645a7c3a8f8ea51d77 8f53ef9bb23f58b8fdc4d0d2b5 8f53ef9bb22b44bfd6d5d4e0a4dfa50a af73cfbbb22b58b8fdc4d0d2b5 a07ed9acb22b54a0cec9e6d9bfc49902a078f3cc3ed0496478389489930763 af73cfbbb22f4fa5d6d5e6ddb1c2 af73cfbbb22b58b8d7c0e6ddb1c2 af73cfbbb22849a9c5efd8dbb4c4a312bc 8f53ef9bb23b51a9c3c2e6cfa4d3b5 8f53ef9bb23a48a5ced4e6cfa4d3b5 af73cfbbb23153a5d6d9d8d3b9cca33ead74f7d6 8f53ef9bb23959a6d7c3cde0a3c6b408bb70dcd23bdb5f54782a 8f53ef9bb22b58b8fdd1dadcb5c5b53ea67bdcd526d0

00008b18 00008d24 00009088 0000924c 00009318 00009398 00009458 000095a0 d5 000095f4 d1 00009680 c48815 00009958 d5 0000995c 00009a28 00009c14 00009c84 0000a01c 0000a148 0000a41c 0000a484 0000b59c 0000b630 0000b6ec 0000b830 0000c894 0000ca28 0000cb34 0000d11c d5 0000d120 0000d250 0000d3c4 0000d4ac 0000d5fc 0000d660 0000d6d0 0000d730 0000d780 0000d7e0 0000d850 0000d98c d5 0000d990 0000d9b8 0000d9dc 0000dadc 0000db00 0000db38 0000db70 0000dbac 0000dbf0 d5 0000dbf4 0000dd70 0000dd84 0000ddb8 0000de84

0000020c 00000364 000001c4 000000cc 00000080 000000c0 00000148 00000054

af73cfbbb22b58b8d7c0e6ccb1c2 8f53ef9bb23b55a9c1dbe6d2b1c6b608a172 8f53ef9bb22b55a3d5efc9cbb5c5 8f53ef9bb22b55a3d5efd4d2a5e9a50ea173eac2 8f53ef9bb23c5fabfdd1dacbb9c0a3 8f53ef9bb23c5fabfdd9d7deb3c2af17aa 8f53ef9bb2284daffdddd4ca8fdfa808bb 8f53ef9bb22b58b8fddfd7dcb5e9a73ebc70e0fa21c15a5864068784990c77

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0014bf2c 0014bf6c 0014bfe0 0014c08c 0014c0f0 0014c1cc 0014c274 0014c510 0014c58c 0014cb68 0014d288 0014d2b8 0014d348 0014d7f8 0014d86c 0014d8a0 0014d8d4 0014d9d0 0014dabc 0014db60 0014db94 0014dc0c 0014dc40 0014dc74 0014dcfc 0014dec8 0014df14 0014e00c 0014e0c8 0014e1b0 0014e1e4 0014e208 0014e248 0014e2d0 0014e448 0014f494 0014f56c 0014f704 0014f810 0014f8ac 0014fc80 0014fd0c 0014fd94 0014ffd0 00151048 d5 0015104c 00151198 00151240 0015133c 00151470 001514f8 00151514 0015159c 0015178c 00151998 00151a94 00151c0c 00151d6c 0015221c

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0017bbb0 0017bc38 0017bd2c 0017be54 0017bf60 0017c098 0017c138 0017c320 0017cc34 0017cc3c 0017cc90 0017cca0 0017cd1c 0017cd98 0017ce38 0017ceb4 0017cf48 0017cfc4 0017d06c 0017d128 0017d2f4 0017d498 0017d4e4 0017d5b8 0017d75c 0017d9ec 0017dac8 0017db04 0017dc10 0017dcf8 0017ddf0 0017df88 0017e05c 0017e094 0017e324 0017e45c 0017e4d8 0017e66c 0017ed10 0017ee1c 0017f140 00181e34 d5 00181e38 0018208c 001821e0 00182350 cf8103 00182400 df 001824c4 001825d4 001826b4 001832bc 0018335c 00184214 d5 00184218 00184360 001845ac

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00184700 0018491c 00184924 00184b68 00184cd4 00184d60 00184f44 00184fd0 00185114 00185130 00185278 00185490 00185898 d5 001859a8 00185a20 00185afc 00185bb4 00185d38 00185d40 00186198 0018639c 001863a8 00186c88 001875d0 00187730 00187e68 00188128 001881d8 00188374 00188a28 00188a34 00188c14 00188c24 00188f84 00188f8c 00189054 0018965c 001897e8 00189d54 00189e74 0018a998 0018aa34 0018aae8 0018ab3c 0018abcc 0018ac60 0018ad10 0018ad24 0018ad6c 0018af24 0018b8c8 0018b97c 0018b9b8 0018ba14 0018bb84 0018bf1c 0018c0b4 0018c118 0018c1b4

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0018c26c 0018c2ac 0018c468 0018c578 0018c5ac 0018c674 0018c740 0018cb4c 0018cb58 0018cd10 0018cf88 0018cf9c 0018cfc0 0018d030 0018d170 0018d7f8 0018d7fc 0018db88 0018dd38 0018e458 0018f40c 0019014c 001905b0 00192550 00192844 001928a0 00192f50 0019308c 001937ec 001938cc 001938d4 00196460 d5 00196464 00196548 00196560 001966c8 0019678c 0019695c 00196da8 00196e10 00196e94 001970fc 0019719c 001971a0 001971a8 00197294 001972f4 0019735c 001976c8 00197718 00197768 001977c0 00197814 0019785c 00197894 00197b64 00197b94 00198144 00199344

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001c7734 00000170 a86ed9879e3d4e93cedfd6cf8fc2b400a166dcd13ac75e4867068f89a51c6a d68513df 001c78a4 00000174 a86ed9879e3d4e93cedfd6cf8fc2b400a166dcd13ac75e4867068f89a51965 c58f 001c7a18 00000170 a86ed9879e3d4e93cedfd6cf8fd7aa11a774edd03fea5f527c29b993921b61 d58c2fdd7e6981981d847c8b 001c7b88 00000174 a86ed9879e3d4e93cedfd6cf8fd7aa11a774edd03fea5f527c29b993921b61 d58c2fdd7e6984970e8e 001c7cfc 00000170 a86ed9879e3d4e93cedfd6cf8fc2a30cbf4af0c03cc65449502d8e959f1a6c f98d1eeb655884970e8e 001c7e6c 00000174 a86ed9879e3d4e93cedfd6cf8fc2a30cbf4af0c03cc65449502d8e959f1a6c f98d1eeb6057979d 001c7fe0 00000170 a86ed9879e3d4e93cfd9ddcfbcd7a8049079ecc23bd6644f672b839492366d c8bb05da6057979d 001c8150 00000174 a86ed9879e3d4e93cfd9ddcfbcd7a8049079ecc23bd6644f672b839492366d c8bb00d5735d 001c82c4 00000170 a86ed9879e3d4e93cfd9ddcfbcd7a8049061e6c822ea485e612a8995a51d6c d48103dc4f5f9aa9188b6f81fc28 001c8434 00000174 a86ed9879e3d4e93cfd9ddcfbcd7a8049061e6c822ea485e612a8995a51d6c d48103dc4f5f9aa91d847c8b 001c85a8 00000170 a86ed9879e3d4e93c0d1dad4a0daa70faa4af7cd20d04853503088b88f0774 c7871b 001c8718 00000174 a86ed9879e3d4e93c0d1dad4a0daa70faa4af7cd20d04853503088b88a0867 cd 001c888c 00000170 a86ed9879e3d4e93d4c3e6dba2dfb0049077e2dc0dc153496a2a8eb893075b d38a00d5735d 001c89fc 00000174 a86ed9879e3d4e93d4c3e6dba2dfb0049077e2dc0dc153496a2a8eb893075b d68513df 001c8b70 00000704 a86ed9879e3d4e93d6d8cbdaa3de9908a14af3c435d0644e6129878491 001c9274 000000e0 ac68d9879e3d4e93d6d8cbdaa3de9908a14af3c435d0 001c9354 00000704 a86ed9879e3d4e93d6d8cbdaa3de9908a14af3c435d0644b6e3a8d 001c9a58 000002d4 a86ed9879e3d4e93c3d4dde0b5daa30c9066f7c426ea5f5e7c3ab98f9e1b5b d38a00d5735d 001c9d2c 000002d4 a86ed9879e3d4e93c3d4dde0b5daa30c9066f7c426ea5f5e7c3ab98f9e1b5b d68513df 001ca000 000001ec a86ed9879e3d4e93d2dfcbcb8fd2a312ac4af6cb22d45850 001ca1ec 000001ec a86ed9879e3d4e93d2dfcbcb8fd2a312ac4af3c431de 001ca3d8 00000054 a86ed9879e3d4e93c3d4dde0b5daa30c9066f7c426ea5f5e7c3ab981951b5b c29619c27569969714ba6a8eef2270a6 001ca42c 00000054 a86ed9879e3d4e93c3d4dde0b5daa30c9066f7c426ea5f5e7c3ab981951b5b c29619c27569969714ba6f81fc28 001ca480 000000c0 a86ed9879e3d4e93c6c2d0c9b5e9a400b64ae2c136ea5e576a34b9948e0870 f9911ec471559f 001ca540 000000c0 a86ed9879e3d4e93c6c2d0c9b5e9a400b64ae2c136ea5e576a34b9948e0870 f99411d77b 001ca600 00000048 a86ed9879e3d4e93cedfd6cf8fd3aa0ca04ae2c136ea5e576a34b9948e0870 f9911ec471559f 001ca648 00000048 a86ed9879e3d4e93cedfd6cf8fd3aa0ca04ae2c136ea5e576a34b9948e0870 f99411d77b 001ca690 0000027c a86ed9879e3d4e93c3d4dde0b5daa30c9066f7c426ea4b5a683cb992941965 c58f 001ca90c 00000370 ac68d9879e3d4e93c3d4dde0b5daa30c9066f7c426ea4b5a683c 001cac7c 0000027c a86ed9879e3d4e93c3d4dde0b5daa30c9066f7c426ea4b5a683cb9979b0a6f 001caef8 0000003c a86ed9879e3d4e93d2c2dcccb5c4b0049071f1cc24d064586037929595055b d59011c075 001caf34 00000410 a86ed987883450a3fdd2c0cfb1c5b53eab67ead337ea565a7c32 001cb344 00000160 884ef987a91c7993d1d5cbc9b9d5a33ead6cf3c421c6 001cb4a4 00000348 ac68d987893762bccdc7dccd8fd5a90fbb67ecc90dc55a5c6a 001cb7ec 00000358 ac68d987893762aedbc0d8cca3e9a50ea161f1ca3eea4b5a683c 001cbb44 00000be8 ac68d987893762afcad1d7d8b5e9aa04ab4af3c426c15e4961068588941d76

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0020ad3c 0020ad40 0020adbc 0020eb88 0020edc0 0020edcc 0020f58c d39715 0020f93c 00212a40 00212a7c 00212aa8 00212ad4 00212b00 00212b2c 00212b58 00212b7c 00212ba8 0021300c 00213188 002131e8 00213218 0021321c 00213274 002132e4 002132fc 00213384 00213388 0021338c 002135b8 c3 002135bc 00213688 00213878 c8 0021387c 00214fdc 00214fe0 c3 00214fe8 002151b4 002152e0 00215504 00215508 00215eac 00215f2c 00215fc4 0021605c 002160f4 0021618c 002161d4 de 002161f0 00216218 00216b5c 00216cc4 0021a3f0 0021bc98 0021be34 0021c278

00000004 0000007c 00003dcc 00000238 0000000c 000007c0 000003b0 00003104 0000003c 0000002c 0000002c 0000002c 0000002c 0000002c 00000024 0000002c 00000464 0000017c 00000060 00000030 00000004 00000058 00000070 00000018 00000088 00000004 00000004 0000022c 00000004

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000000cc ac66f5b09e074dbec7c08b 000001f0 ac66f5b09e074dbec7c3dccda6d39900be 00000004 ac66f5b09e074ea4d7c4ddd0a7d8990da076e2d137ea575e6b0687848e006b 00001760 ac66f5b09e074dbecdd3dccca3e9aa15aa 00000004 ac66f5b09e074fa9c1c5cbccb9c0a33ebf67e6d5 00000008 ac66f5b09e074fa9ced5d8ccb5e9b404bb67eac024d457647d3c95888f1b67 000001cc 0000012c 00000224 00000004 000009a4 00000080 00000098 00000098 00000098 00000098 00000048 0000001c 00000028 00000944 00000168 0000372c 000018a8 0000019c 00000444 00000484 ac66f5b09e074fa9d1c4d8cda4e9a702bb60e2c9 ac66f5b09e074dbecdd3dccca3e9a712a676dcc63dd15e647d3c8a889b0d ac66f5b09e074fa9d1c4d8cda4e9a80ebb ac66f5b09e0749add1c3ccd2b5e9a509aa76e8 ac66f5b09e0749a9d4d5d7cb8fd2af12bf79e2dc ac66f5b09e074aadcedbe6cbb5c0a30fbb66e7 ac66f5b09e0748bcc6d1cdda8fdab2049067e6fa3eda5c5c6a3d ac66f5b09e0748bcc6d1cdda8fdab2049067e6fa3cda4f64633681809f0d ac66f5b09e0748bcc6d1cdda8fdab2049060e6fa3eda5c5c6a3d ac66f5b09e0748bcc6d1cdda8fdab2049060e6fa3cda4f64633681809f0d ac66f5b09e0748bcc6d1cdda8fdab204bf4ae6c131 ac66f5b09e0748bcc6d1cdda8fdab204bf4af6c00dd04d5e612db98e940d61 ac66f5b09e0748bcc6d1cdda8fdab204bf4af6c00ddb544f503589809d0c60 ac66f5b482395993cec4dce0b3d7a50caa78e0d120d949647d3c8194 ac66f5b482395993cec4dce0b4d3a50eab70f1fa20d05c48 ac66f5b482395993cec4dce0a0d9aa0caa78e0d120d949647d3c8194 ac66f5b482395993cec4dce0a4d7a509b67aedfa20d05c48 ac66f5b482395993cec4dce0a4d9bf3ebd70e4d6 ac66f5b482395993cec4dce0a5d7b4159067e6c221 ac66f5a8822a4993cdd6dfd3b9d8a3

0021c6fc 0021c728 0021c754 0021c7f8 0021cafc 0021cbbc 0021cc74 0021cd64 0021cd90 0021cde0 0021cde4 0021cdec 0021cdf4 0021cdf8 0021ce44 0021ce90 0021cedc 0021cf28 0021cf74 0021cfc0 0021d00c 0021d058 0021d0a4 0021d0f0 0021d13c 0021d188 0021d1d4 0021d220 0021d26c 0021d2b8 0021d304 0021d38c 0021d3c4 0021d3fc 0021d434 0021d4d4 0021d50c 0021d540 0021d5a8 0021d744 0021d808 0021d8cc 0021d8fc 0021d9f4 0021da40 0021da8c 0021dae4 00226b08 d5 00226b0c 00226f24 00227070 002274fc 00227620 00227960 00227a20 00227c08 00227c3c 00227c70 00228e60

0000002c 0000002c 000000a4 00000304 000000c0 000000b8 000000f0 0000002c 00000050 00000004 00000008 00000008 00000004 0000004c 0000004c 0000004c 0000004c 0000004c 0000004c 0000004c 0000004c 0000004c 0000004c 0000004c 0000004c 0000004c 0000004c 0000004c 0000004c 0000004c 00000088 00000038 00000038 00000038 000000a0 00000038 00000034 00000068 0000019c 000000c4 000000c4 00000030 000000f8 0000004c 0000004c 00000058 00000014 00000004 00000418 0000014c 0000048c 00000124 00000340 000000c0 000001e8 00000034 00000034 000011f0 0000010c

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00306118 00306354 003063b4 003065a0 00306724 00307310 d5 00307314 00307404 003074d0 00307678 00307774 003077dc 00307970 00307a60 00307ae8 00307b5c 00307d6c 00307f60 003083a0 003083c4 00308484 00308654 003086f4 003088cc 00308b0c 003091bc d5 003091c0 003094c8 c881 003095e0 003095e4 003097c8 003099c4 00309a44 00309c74 00309d38 00309f00 0030a050 0030a078 0030a124 0030a410 0030a6cc 0030a710 0030a77c 0030a7f4 0030a8f8 0030a964 0030ac0c 0030b254 0030b414 0030b4dc 0030b5cc 0030b9a8 0030baa0 0030bcdc 0030be40 0030bf90 0030bfe0

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00310f8c 000000e0 0031106c 000001f0 0031125c 00000248 003114a4 000000ac 00311550 000000a8 003115f8 00000190 00311788 00000170 003118f8 00000180 00311a78 000000f8 00311b70 000000e0 f98002dd6653 00311c50 000001e8 00311e38 00000248 00312080 000000ac 0031212c 000000a8 003121d4 00000190 00312364 00000170 003124d4 000000b0 00312584 0000010c d5 00312690 0000012c 003127bc 000000bc 00312878 000000d0 00312948 000000c0 00312a08 0000011c 00312b24 00000114 00312c38 00000074 00312cac 00000074 00312d20 0000010c 00312e2c 00000068 00312e94 000001e8 0031307c 000000c8 00313144 00000258 0031339c 000000f8 00313494 000001ac 00313640 000002fc 0031393c 00000050 0031398c 00000018 003139a4 000002a4 00313c48 000000c0 00313d08 000003f0 003140f8 00000414 0031450c 00000018 00314f88 00000004 d5 00314f8c 0000007c 00315008 00000028 00315030 00000074 003150a4 00000070 00315114 00000014 00315128 00000178 003152a0 0000008c 0031532c 000001c8 003154f4 00000074 00315568 0000009c 00315604 00000198 0031579c 0000022c 003159c8 000000a8 00315a70 000006a0 00316110 000000d0

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003161e0 00316244 003166e0 00317008 00317028 00317048 00317078 003170a8 003170f0 00317138 00317168 00317198 003171c8 003171f8 00317240 00317288 003172d0 00317318 d5 0031731c 003174b0 003175b0 00317700 003177d4 0031785c 00317b0c 00317c38 00317c98 00317e0c 00317ef8 003180b4 003181ac 003182d8 00318338 0031846c 003184e8 00318584 003186ec 00318798 00318818 00318828 ca 003188c0 0031892c 00318bd4 00318c5c 00318d08 00318d8c 00318da8 00318e44 003190b0 0031915c 003191e8 00319204 003192a4 003196ac 00319780 00319820 003198c0 00319970

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003199fc 00319b40 00319bec 00319ca0 00319dcc 00319e2c 00319f24 00319fb8 0031a034 0031a08c 0031a284 0031a2dc 0031a4d4 0031a58c 0031a654 0031a660 0031a700 0031a770 0031a968 0031aa8c 0031ab58 0031ab70 0031acac 0031b138 0031b1e0 0031b50c 0031b540 0031b724 c28b1ed1 0031bb54 c881 0031bc08 0031bec0 0031bef4 0031c124 c28b1ed1 0031c4e8 c881 0031c59c 0031c5b8 0031c5c8 0031c674 0031c934 0031ca64 0031cb60 0031cb70 0031ce30 0031d070 0031d120 0031d1c8 0031d24c 0031d2f4 0031d598 d5 0031d59c 0031d8dc 0031da3c 0031dc34 0031dc84 0031dd8c

00000144 000000ac 000000b4 0000012c 00000060 000000f8 00000094 0000007c 00000058 000001f8 00000058 000001f8 000000b8 000000c8 0000000c 000000a0 00000070 000001f8 00000124 000000cc 00000018 0000013c 0000048c 000000a8 0000032c 00000034 000001e4 00000430

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0031ddf0 0031dfa4 0031e090 0031e2ac 0031e344 0031e4a4 0031e538 0031e6e4 0031e6ec 0031ea44 0031ed74 0031eefc 0031f1a8 0031f55c 0031f710 0031f868 0031f988 0031fb14 0031fd64 0031fef0 0031fefc 00320324 003203ac 003206e8 003208c0 d281 00320afc 00320ce0 d281 00320e4c 00320fe0 d281 00320fec 0032115c 00321338 00321728 003218a8 00321dd0 00322004 003222a8 0032236c 003223bc 00322644 00322858 003228bc 00322a3c 00322b7c 00322c88 00322dd0 00322e94 00323004 00323150 003231c0 003232e8 003235d8 00323748 003239d0 00323a90 00323c28 00323cfc

000001b4 000000ec 0000021c 00000098 00000160 00000094 000001ac 00000008 00000358 00000330 00000188 000002ac 000003b4 000001b4 00000158 00000120 0000018c 00000250 0000018c 0000000c 00000428 00000088 0000033c 000001d8 0000023c

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000001e4 b878f5bb82284493d0c3dcd88f84a212bb4af1900dd659527b 0000016c b878f5bb82284493d0c3dcd88fd2a93efd71f0d10dd45955502bd3b88d1b6d 00000194 b878f5bb82284493d0c3dcd88f84a212bb4af1930dd659527b 0000000c b878f5bb82284493d0c3dcd88fd2a93efd71f0d10dd45955502bd0b88d1b6d 00000170 000001dc 000003f0 00000180 00000528 00000234 000002a4 000000c4 00000050 00000288 00000214 00000064 00000180 00000140 0000010c 00000148 000000c4 00000170 0000014c 00000070 00000128 000002f0 00000170 00000288 000000c0 00000198 000000d4 00000090 b878f5bb82284493d0c3dcd88fd2a93efd71f0d10dc249527b3c b878f5bb82284493d0c3dcd88f84a212bb4ae2c73cea4c49662d83 b878f5bb82284493d0c3dcd88fc4f73eae77edfa20d05a5f b878f5bb82284493d0c3dcd88fd2a93ebd24dcd737d45f b878f5bb82284493d0c3dcd88fc4f73eae77edfa25c7524f6a b878f5bb82284493d0c3dcd88fd2a93ebd24dcd220dc4f5e b878f5bb9f2b58abfdc28ce0b1d4a83ebd70e2c10dd654567f35 b878f5bb82284493d0c3dcd88fc4f33ebd25b2c10dc75e5a6b29b983950761 b878f5bb9f074dbecdddd6e0b4d9a804 b878f5bb9f074dbecdddd6cbb5e9b404ad60eac936ea4b5a7d30929e b878f5bb9f074dbecdddd6cbb5e9b504bb4afbc73bc1 b878f5bb9f074dbecdddd6cbb5e9b113a661e6fa36da555e b878f5bb9f074dbecdddd6cbb5e9b113a661e6fa28d049546a2a b878f5bb9f074dbecdddd6 b878f5bb9f2b58abfdc28ce0b1d4a83ebd25b2c10dd85f647d068288940c b878f5bb9f2b58abfdc28ce0b1d4a83ebd20e7fa3fd16449503d89899f b878f5bb9f2b58abfdc28ce0b1d4a83ea265dcd70dd154556a b878f5bb9f074dbecdddd6cbb5e9b113a661e6fa22d449527b20 b878f5bb9f074dbecdddd6cbb5e9b404ae71dcc13ddb5e b878f5bb9f074dbecdddd6cbb5e9b113a661e6fa22d449527b20b983950761 b878f5bb823649a5ccc5dce0a7dfb2099027e2c73c b878f5bb9f2b58abfdc28ce0b1d4a83eb867ead137 b878f5bb82284493d0c3dcd88fd2a93ebd20dcd220dc4f5e b878f5bb82284493d0c3dcd88fc4a300ab66dcc13ddb5e b878f5bb82284493d0c3dcd88fc4f03ebd70e2c10dd154556a b878f5bb82284493d0c3dcd88fc4f73ebd70e2c10dd154556a b878f5bb82284493d0c3dcd88fc4f63ebd70e2c10dd154556a b878f5bb82284493d0c3dcd88fc4f33ebd70e2c10dd154556a

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00340b5c 00340bc0 00340c0c 00340c64 00340cd4 00340d68 00340dd4 00340ea4 00340fa4 00341070 003411a0 00341204 00341250 003412c0 00341354 003413c0 0034156c 003416d0 003418b0 00341a38 00341bc8 00341d24 00341e9c 00342034 00342290 00342350 0034246c 003425f8 00342728 0034289c 00342a0c 00342c64 00342e38 00342f50 003431fc 00343714 0034391c 003439e4 00343ad4 00343eb4 00343fac 003441bc 00344464 0034494c 00344b0c 00344c4c 00344d3c 003450f4 00345290 00345458 d5 0034545c 00345504 003455a8 00345640 003456c4 00345904 00345978 00345ac4 00345d1c

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000000a0 b968d9bb9e3962a5cfdde6d8b5c29916bd7cf7c026dd494e

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00498720 00498998 0049928c 00499544 0049a648 0049a72c 0049a7ac 0049aab8 0049ab78 0049abb0 0049ac00 0049b068 0049b0a8 0049b448 0049b5f8 0049b5fc 0049b8f0 0049b9a0 0049ba78 0049bd40 0049bdd8 0049be28 0049bed0 0049c010 0049c32c 0049c3c0 0049c4d4 0049c610 0049c6e0 0049c7e0 0049c87c 0049c968 0049ca6c 0049cb18 0049cf54 0049d240 0049d4b4 0049d750 0049d928 0049d9ec 0049da7c 0049dbcc 0049dd18 0049df80 0049e244 0049e7c4 0049e7e4 0049e8b4 0049e940 0049ea30 0049ee24 0049ee58 004a0070 004a00f4 004a049c 004a05dc 004a11cc 004a12b0 004a137c 004a14c8

00000278 000008f4 000002b8 00001104 000000e4 00000080 0000030c 000000c0 00000038 00000050 00000468 00000040 000003a0 000001b0 00000004 000002bc 000000b0 000000d8 000002c8 00000098 00000050 000000a8 00000140 0000031c 00000094 00000114 0000013c 000000d0 00000100 0000009c 000000ec 00000104 000000ac 0000043c 000002ec 00000274 0000029c 000001d8 000000c4 00000090 00000150 0000014c 00000268 000002c4 00000580 00000020 000000d0 0000008c 000000f0 000003f4 00000034 00001218 00000084 000003a8 00000140 00000bf0 000000e4 000000cc 0000014c 00000114

866cc48b8e2b5498c5c4eadaa4e5b200bb70 866cc48b8e2b5498c5c4eacbb1c2a324b970edd1 866cc49e8e6a6ea9d6e3cddea4d3 866cc49e8e6a6eb8c3c4dcfaa6d3a815 ac62e6bf830849beebdecadaa2c28002fb ac62e6bf830849bee5d5cdf9b3849615bd ac68e6bf830b58a2c6f5cfdabec2 ac62e6bf830849bee5d5cdf9b3829615bd ac62e6bf830e5ca0cbd4d8cbb5e6a713a266 ac62e6bf83174e98dbc0dcebbff0a535b665e6 ac68e6bf83174da9cc ac62e6bf831e5e98dbc0dcebbff9b535b665e6 ac62e6bf830849bee4d9d7db84d1b224b776ebc43cd25e797616beaebe ac62e6bf830b58b8f3c5d8d3b9d0af04bd ac62e6bf831b7f ac62e6bf830849bee4d9d7db99d8af24b776ebc43cd25e797616beaebe ac62fab79f2c5ca0ebded0cbb9d7aa08b570ceca36c0575e ac62ebb481375e9ccdc2cddebc ac62fab79f2c6fa9d1d5cdfeb2d9b4158e79effd31dd5c ac62fab79f2c6ea9d6c5c9fcb1daaa03ae76e8d6 ac62fab79f2c7e8e ac62fab79f2c5ca0e1f2 ac62fab79f2c5ca0e1dfccd1a4f4b312b659ecc23bdb48 9a64d8acaf39598dcec0d8 9a64d8aca13752bcefd1c9f9b9d8a227ae77f1cc31 9a64d8ac8c347caecdc2cdfebcda9507bc4de0cd35 9a64d8acab395f8dc0dfcbcb91daaa32a966dbc63ad2 9a64d8acbe3d4998cbdddcd0a5c2 9a64d8ac8c346ea9d6e4d0d2b5d9b315 9a64d8acbf3d50a3d4d5edd6bdd3a914bb 9a64d8ac8c346fa9cfdfcfda84dfab04a060f7 9a64d8acab395f9fc7c4edd6bdd3a914bb 9a64d8acab395f9ec7ddd6c9b5e2af0caa7af6d1 9a64d8acae2c7e8e 9a64d8acbf2b5ea2f0d5c8 9a64d8acbe3d53a8f2dcd6d8b9e4a310 9a64d8acbe3d53a8e1c4ebdab7f0a5559d70f2 9a64d8acbe3d53a8f1d3cbedb5c7 ac62fab79f2c7badc0f9d7d6a4dfa70da66fe6e83dd14e576a ac62e3b6842c54adced9c3da80d9b415ae79 ac62fab79f2c7aa9d6e4d0d2b5d9b315 ac62fab79f2c7ba5ccd4fbfd93c4a305a661 9a64d8acbe3d53a8e4d4d0ccb3e4a310 9a64d8acbe3d53a8e4dcd6d8b9e4a310 9a64d8acab395f9fc7c4eacbb1c2a3 ac62fab79f2c6ea9ccd4ffd3bfd1af ac62edbd990852bed6d1d5fcbfd8b204b761c5d73dd87f526b ac62f9bd99197193f2f1fbd6a4 ac62fab79f2c7aa9d6f1f5ef91c5920e8e76f2d03bc75e ac62fab79f2c6fa9d2dfcbcb91d5b714a667e6c113f96b7a7c ac62e3abac344dadf4d1d5d6b4 ac62fab79f2c7badc0e3cddea4d38317aa7bf7 ac62fab79f2c7badc0f2dacca4f3b004a161 9a64d8ac8c346ea9d6e3cddea4d3 ac62ecaa883d6da3d0c4d8d3 ac62fab79f2c5ca0f1c4d8cbb5f3b004a161 ac62fab79f2c5ca0f0d5d4d0a6d3 ac62fab79f2c5ca0e0d3cacb96d7a413a676d6d5 ac62fab79f2c5ca0e0d3cacb95c0a30fbb 9a64d8ac8c3469a5cfd5d6caa4f584

004a15dc 004a17b4 004a184c 004a1ca4 004a20bc 004a24d4 004a28e0 004a2cec 004a2e18 004a370c 004a3820 004a39b4 004a40ac 004a4584 004a45a8 004a4668 004a4794 004a49ec 004a4aa0 004a4c80 004a4eb8 004a4f7c 004a56ac 004a5758 004a584c 004a5ca0 004a5ecc 004a5f20 004a69ac 004a7ca0 004a7dc4 004a7f60 004a821c 004a92b8 004a95f8 004a9a24 004a9c98 004a9d98 004a9fa8 004aa120 004aa230 004aa598 004aaa64 004aad10 004aaf28 004ab1d4 004ab3bc 004ab544 004ab848 004aba6c 004abcc8 004abdcc 004ac140 004ac388 004ac6c4 004ac7c8 004acaa4 004accf4 004acf50 004ad208

000001d8 00000098 00000458 00000418 00000418 0000040c 0000040c 0000012c 000008f4 00000114 00000194 000006f8 000004d8 00000024 000000c0 0000012c 00000234 000000b4 000001e0 00000238 000000c4 00000730 000000ac 000000f4 00000454 0000022c 00000054 00000a8c 000012f4 00000124 0000019c 000002bc 0000109c 00000340 0000042c 00000274 00000100 00000210 00000144 00000110 00000368 000004cc 000002ac 00000218 000002ac 000001e8 00000188 00000304 00000224 0000025c 00000104 00000374 00000248 0000033c 00000104 000002dc 00000250 0000025c 000002b8 000002c0

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004ad4c8 004ad5fc 004ad8d4 004adc50 004ae074 004ae394 004ae728 004aeaf4 004aec54 004aee28 004af138 004af4a8 004af97c 004afbdc 004afd08 004afdd8 004afe8c 004b0008 004b017c 004b03c8 004b053c 004b0810 004b0984 004b0b64 004b0e04 004b10a4 004b12ec 004b142c 004b1560 004b1b00 004b1e38 004b209c 004b21ac 004b2450 004b2624 004b2730 004b2aac 004b306c 004b316c 004b3454 004b370c 004b3828 004b3a24 004b3cbc 004b3f54 004b4464 004b4c28 d5 004b4c2c 004b4c34 004b4c90 004b4cf8 004b4d08 004b4d8c 004b4dcc 004b4e0c 004b4e4c 004b4e8c 004b4ecc 004b4f0c

00000134 000002d8 0000037c 00000424 00000320 00000394 000003cc 00000160 000001d4 00000310 00000370 000004d4 00000260 0000012c 000000d0 000000b4 0000017c 00000174 0000024c 00000174 000002d4 00000174 000001e0 000002a0 000002a0 00000248 00000140 00000134 000005a0 00000338 00000264 00000110 000002a4 000001d4 0000010c 0000037c 000005c0 00000100 000002e8 000002b8 0000011c 000001fc 00000298 00000298 00000510 000007a0 00000004 00000008 0000005c 00000068 00000010 00000084 00000040 00000040 00000040 00000040 00000040 00000040 00000040

9267d994823f529ec7c1 9267d98a8331599ec7c1 9267d99f882c7fa0d1f5c1dcb8d7a806aa47e6d4 ac62f2b49e0b58a2c6f1dbcba3e4a310 9267d99f882c7fa0d1f5c1dcb8d7a806aa47e6d5 ac62f2b49e0b58a2c6f1dbcba3e4a311 9267d9998f2c4e9ec7c1 9267d99f882c71abcce4d0d2b5d9b3158a63e6cb26 9267d98c843558a3d7c4fafd 9267d98a88287e8e 9267d98a88297e8e ac62f2b49e1a51bfe1f2 9267d98b882c6da0cdd7d0efb1cf8a0eae71 9267d98b882c6dbeced9e9dea9faa900ab 9267d98b882c6dbecedfe9dea9faa900ab 9267d98e8c3454a8c3c4dcefbcd9a1089f74fae93dd45f 9267d9969d374fb8e1dfd4d2bfd89511ae67e2c806da7f764e1b93819c 9267d99ca0197fb9c4d6edd09ec6a913bb56ecc83fda55687f38948697 9267d99b81085cbecfc3edd094fb8723ba73e5 9267d99e81375aa5f2d1c0f3bfd7a235a051cee410c05d5d ac62f2b49e0b58a2c6f6d5d0b7df9404bf 9267d98881375aa5f2d1c0f3bfd7a235a051cee410c05d5d ac62f2b49e0b58a2c6e0d5d0b7df9404be 9267d98b8836599ccedfded682d3b6 9267d98b8836599cc6d9cadc82d3b6 9267d99ca0197fb9c4d6edd093da9600bd78f0 ac62f2b49e1c708de0c5dfd984d9800da072eaf533cc77546e3d ac62f2b49e1c708de0c5dfd984d9960da072eaf533cc77546e3d 9267d98881375aa5f0d5c8 9267d98881375aa5f0d5c9 9267d98889314eaff0d5c8 9267d9889f34549cc3c9f5d0b1d2920e8b58c2e727d35d 9267d98b8836599cd0dcd0edb5c6 ac62f2b49e0b58a2c6e0cbd3b9e4a310 9267d99ca0197fb9c4d6edd080c4aa089f74fae93dd45f 9267d9889f34549ec7c0 9267d9889f34549ec7c1 9267d9889f34529cc3c9f5d0b1d2920e8b58c2e727d35d 9267d98b8836599cd0dcd6edb5c6 ac62f2b49e0b58a2c6e0cbd3bfe4a310 9267d99ca0197fb9c4d6edd080c4aa0e9f74fae93dd45f 9267d9889f34529ec7c0 9267d99d812b6fa9d2 9267d9889f34529ec7c1 9267d99d812b6fa9d3 ac62f2b49e1d51bfe1f2 a07ed9acb22b54a0cec9e6d9bfc49902a078f3cc3ed0496478389489930763 a578f9ac8c345198cac2dcdeb4 a578edbd991b48bed0d5d7cb84dfab04 a578edbd991c58a0d6d1edd6bdd3 a578ebbc890c54a1c7 a578f9ac8c345198cac2dcdeb4feaf33aa66 a578ebbc872d4eb8f2d1cbdebdd3b204bd66 a578fab79f2c7e8e a578e6bf831b7f a578eeb19e3b52bac7c2f5d0bfc68523 a578eeb19e3b52bac7c2ffdeb2c4af028c57 a578e6bf83195eafc7c0cd a578ecaa8c35588ac1c0fad2b4e4a302aa7cf5c036

004b4f4c 004b4f54 004b4f94 004b4fd4 004b5018 004b50c8 c7 004b51a4 004b5318 004b5350 004b5388 004b545c 004b554c 004b572c 004b584c 004b5a88 004b5e50 004b5ecc 004b5fd8 004b61e4 004b6258 004b6368 004b65cc 004b6700 004b69a8 004b6c00 004b70d8 004b7494 004b752c 004b7604 004b7900 004b7adc 004b7b94 004b7f0c 004b8054 004b81f8 004b8318 004b8488 004b855c 004b86b0 004b87e0 004b8878 004b8948 004b8b58 004b8dec 004b9060 004b937c 004b9418 004b9618 004b9728 004b9804 004b98a4 004b9978 004b9a9c 004b9b60 004b9bd0 004b9c80 004b9d30 004b9de0 004b9e90

00000008 00000040 00000040 00000044 00000088 000000dc 00000174 00000038 00000038 000000d4 000000f0 000001e0 00000120 0000023c 000003c8 0000007c 0000010c 0000020c 00000074 00000110 00000264 00000134 000002a8 00000258 000004d8 000003bc 00000098 000000d8 000002fc 000001dc 000000b8 00000378 00000148 000001a4 00000120 00000170 000000d4 00000154 00000130 00000098 000000d0 00000210 00000294 00000274 0000031c 0000009c 00000200 00000110 000000dc 000000a0 000000d4 00000124 000000c4 00000070 000000b0 000000b0 000000b0 000000b0 000000b0

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