Avinash Rajagiri 12.

1) Design, lay out, and simulate the operation of a CMOS AND gate with a VSP of approximately 500 mV. Use the standard-cell frame discussed in Ch. 4 for the layout.
A CMOS AND gate can be designed using a NAND gate with its output inverted. Therefore, we need a NAND and an Inverter circuit to layout our AND gate. The switching point of the AND gate will be dominated by the NAND circuit. Since, we are using short-channel process, the NMOS and PMOS can be considered as just resistors. Similar to example 11.3, we can write the switching point equation as:

Rn + Rn Vsp = VDD * ( Rn + Rn) + ( Rp // Rp ) . 34k 68k and Rp = , substituting them in the above equation, For short-channel, Rn = Wp Wn we get, Wn = 2 * Wp . Choosing the size of NMOS as 10/2 we have the PMOS size as 20/2.

Shown are the circuit Schematic and the Layout of 2-input AND gate using Electric

Avinash Rajagiri Simulations Result of Schematic:

Switching point is measured as 550mV.

Simulations Result of Layout:

Switching point if found to be 550mV from the above plot, which is comparable to the required 500mV switching-point.

Problem 12.2

Steve Bard

Design and simulate the operation of a CMOS AOI half adder circuit using static logic gates. Solution: A half adder circuit calculates a half sum (HS) and a carry out (CO). It takes two input bits, A and B. The logic equations for HS and CO are HS = A B CO = A B = ( A + B ) Figure 1 shows a circuit schematic of a half adders components. For clarity, the components are not wired together in the figure. The SPICE simulation and code appear on the next page.

VDD

VDD

Figure 1: Half adder components

*** Problem 12.2 *** .control destroy all run plot VA VB CO HS .endc .option scale=50n .tran 10p 2.2n Vdd VA VB Vdd VA VB 0 0 0 DC DC DC Vdd N3 Vdd N3 N2 0 N1 0 Vdd 0 Vdd 0 1 0 0 Vdd Vdd Vdd Vdd 0 0 0 0 Vdd 0 Vdd 0 Vdd Vdd 0 0 pulse 0 1 250p 50p 50p 0.5n 1n pulse 0 1 1.5n 50p 50p 0.5n 1n PMOS L=1 W=20 PMOS L=1 W=20 PMOS L=1 W=20 PMOS L=1 W=20 NMOS L=1 W=10 NMOS L=1 W=10 NMOS L=1 W=10 NMOS L=1 W=10 PMOS L=1 W=20 NMOS L=1 W=10 PMOS L=1 W=20 NMOS L=1 W=10 PMOS L=1 W=20 PMOS L=1 W=20 NMOS L=1 W=10 NMOS L=1 W=10

*XOR gate -- A XOR B = HS M12 N3 VB M11 HS B_ M10 M9 M8 M7 M6 M5 N3 HS HS N2 HS N1 VA A_ A_ B_ VA VB VA VA VB VB

*A inverter M2 A_ M1 A_ *B inverter M4 B_ M3 B_

*NOR gate -- A_ NOR B_ = AB = CO M16 N4 A_ Vdd M15 CO B_ N4 M14 CO B_ 0 M13 CO A_ 0 .MODEL NMOS NMOS LEVEL = 14 .MODEL PMOS PMOS LEVEL = 14 .end

12.3 Shambhu Roy Repeat Ex 12.3 for a three-input NOR gate (Use the effective resistances to estimate Vsp) Ex 12.3 Estimate the intrinsic propagation delays t PHL + t PLH , of a three input NAND gate made using 10/1 NMOS and 20/1 PMOS in a short channel process. Estimate and simulate the delay when the gate is driving a load capacitance of 50fF. Assume that inputs are tied together. Solution: For a 3 input NOR when it goes from high to low the load is charged through 3 NMOS is parallel and when output goes from low to high it has 3 PMOS resistances in series, So
C outp Rn (3.C outn + + C load ) 3 3 C outp t PLH = 0.7.3.R p (3.C outn + + C load ) + 0.35 R p C oxp .3 2 3 Using the values of resistances and capacitances for a short channel process from table 10.2 t PHL = 0.7

t PHL = 0.7 t PLH

3.4k 1.25 fF (3.0.625 fF + + 50 fF ) = 41.4 ps 3 3 1.25 fF = 0.7.3.3.4k (3.0.625 fF + + 50 fF ) + 0.35.3.4k .1.25 fF .3 2 = 386.7 ps 3

delay = 41.4+386.7=428.1ps Vsp can vary from

3.R p R 3.R p + n 3

to

3.R p 3.R p + Rn

ie 900mV to 750mV

*** Sol 12.3 *** .control destroy all run plot vin out ylimit 0 1 .endc .option scale=50n .tran 10p 2n 10p vdd Vin x1 vdd vin vin 0 0 vin DC DC vin 1 0 out pulse 0 1 200p 0 0 0.5n 4n vdd NOR_3

cl

out

50f A VDD n1 n2 0 0 0 B VDD VDD VDD 0 0 0 C out VDD PMOS L=1 W=20 PMOS L=1 W=20 PMOS L=1 W=20 NMOS L=1 W=10 NMOS L=1 W=10 NMOS L=1 W=10

.subckt NOR_3 M1 n1 A M2 n2 B M3 out C M4 out A M5 out B M6 out C .ends

Problem 12.4

Harish Reddy Singidi

Repeat Ex. 12.4 for a three-input NOR gate. (Use the effective resistances to estimate the VSP) Solution: tPHL = 0.7 (Rn)(Cload) tPHL = 0.7 (3.4K)(50fF) tPHL = 119ps tPLH = 0.7 (N)(Rn)(Cload) tPLH = 0.7 (3)(3.4K)(50fF) tPLH = 357ps

Simulations Results tPHL = 118ps (Which is equal to hand calculations) tPLH = 566ps ( Considerably longer Since single NMOS device is pulling the output high.

Rupa Balan 12.5 Sketch the schematic of an OR gate with 20 inputs. Comment on your design. OR gate with 20 inputs can be drawn with a 20 input NOR gate and inverter as shown

In this case there are 20 PMOS in series in the NOR gate. Hence low to high propagation delay of the NOR gate is high. (In case of equal sized NMOS and PMOS devices, Rp>Rn and here the PMOS are in series. Hence here tpLH of NOR gate is very high. Also here the delay tpLH of NOR gate increases as the square of N, where N is number of inputs which are 20.) Also 21 PMOS and 21 NMOS including the inverter for a total of 42 Mosfets are needed. Hence above schematic is hard to implement. So the following schematic can be used which again uses a 20 input NOR gate and an inverter.

Here also the low to high propagation delay of the NOR gate would be considerably high due to the large resistance of the long length pull up device and also due to the large output capacitance of the parallel NMOS. But here only 23 Mosfets are needed. In order to ensure that the output of the NOR gate gets pulled low enough (VOL=0), the resistance of the Long L PMOS has to be atleast four times the resistance of the NMOS in the NOR gate. For the simulation shown below, the size of all NMOS devices in the NOR gate has been taken as 10/1, the size of long L PMOS in the NOR gate has been taken as 20/10, the size of NMOS in the inverter is 10/1 and size of PMOS in the inverter is 20/1.

Thus by using a long value for L in the PMOS, the output vout1 of the NOR gate is pulled to zero as seen in the simulation.

PROBLEM 12.6 Indira . Estimate the worst Sketch the schematic of a static logic gate that implements case delay delay through the gate when driving a 50fF load capacitance? Solution:

PMOS=20/1 NMOS=10/1 COUT=2/3COXN + COXN + 3/5COXP + CLOAD COUT=2/3(0.625Ff) + 0.625Ff + 3/5(1.25Ff) + 50Ff COUT=51.78Ff Worst-case delay is when all the , and (PMOS) are ON. We will have three resistors in series. Therefore we get, 3Rp=3(68K/20) =10.2K tPLH =0.7*10.2K*51.78Ff tPLH =369.7ps

KRISHNAMRAJU KURRA
PROBLEM 12.7 Design and simulate the operation of a CVSL OR gate made with minimum size devices.

*** KRISHNAM Q:12.7 *** .control destroy all run plot vA VB+1 VC+2 vout+3 plot vAI vBI+1 VCI+2 VIN+3 .endc .option scale=50n .tran 110P 40n vdd vdd 0 DC 1 VA vA 0 DC 0 VB vB 0 DC 0 VC vC 0 DC 0 VAI vAI 0 DC 0 VBI vBI 0 DC 0 VCI vCI 0 DC 0 x1 vA vB vC vIN x2 vAI vBI vCI vout .subckt NOR_31 A B M4 vout1 A 0 0 M5 vout1 B 0 0 M6 vout1 C 0 0 .ends .subckt NOR_32 A B M1 vout2 A n1 0 M2 n1 B n2 0 M3 n2 C 0 0 .ends M7 vout vIN VDD VDD M8 vIN vOUT VDD VDD .model nmos nmos level = 14 .end

pulse 0 1 200p 0 0 5n 10n pulse 0 1 200p 0 0 10n 20n pulse 0 1 200p 0 0 15n 30n pulse 1 0 200p 0 0 5n 10n pulse 1 0 200p 0 0 10n 20n pulse 1 0 200p 0 0 15n 30n vdd NOR_31 vdd NOR_32 C vout1 VDD NMOS L=1 W=10 NMOS L=1 W=10 NMOS L=1 W=10 C vout2 VDD NMOS L=1 W=10 NMOS L=1 W=10 NMOS L=1 W=10 PMOS L=2 W=20 PMOS L=2 W=20

By using minimum size devices the output was being pulled by the PMOS devices to high before it reached zero. The out put can be pulled down to zero by increasing the strength of the NMOS(increase width of NMOS)or by decreasing the strength of the PMOS(increase length of PMOS).

Problem 12.8:

Surendranath C Eruvuru

Design and simulate the operation of a tri-state buffer that has propagation delays under 5ns when driving a 1 pF load. Assume that the maximum input capacitance of the buffer is 100fF.

In tri state buffer if enable is low, then the output will be high impedance state. If enable is high, then the output will have the same logic value as A. According to the question, input capacitance cant exceed 100fF. So, the total input capacitance can be written as follows: Cin = 3/2(Cox,n + Cox,p + Cox,n + Cox,p) = 100fF Inverter NAND

We know that Cox = .0625fF. So, 100fF > 3 (Cox (Wn Ln + Wp Lp )) To solve the above inequality, considering Wn = 2Wp & Ln = Lp, we can obtain a better result than any other assumption in short channel process. After solving, Wn Ln~178 & Wp Lp~ 356. Approximating above values in the following net list, a Tri-state buffer that has propagation delay under 5ns has been obtained.

Net list: .CONTROL DESTROY ALL RUN Plot V(A) V(out) .ENDC .option scale=50n .tran .1n 50n UIC *.IC V(BOUT)=1 VDD Vdd 0 VA A 0 VEn En 0 XNand XNor 3 XINV En M1 out M2 out C1 out A A 3 1 2 0 DC DC DC En Vdd Vdd Vdd 0 1p 1 0 1 Vdd 2 INV Vdd 0

PULSE 0 1 0 0.1n 0.1n 10n 20n

1 Nor

Nand

PMOS L=1 W=20 NMOS L=1 W=10

*****SUBCKT 1****** .SUBCKT INV in1 out1 Vdd M1 out1 in1 Vdd Vdd PMOS L=1 W=20 M2 out1 in1 0 0 NMOS L=1 W=10 .ENDS *****SUBCKT 2 ****** .SUBCKT Nand A M1 1 B 0 0 M2 out A 1 0 M3 out A Vdd Vdd B Vdd out NMOS L=5 W=40 NMOS L=5 W=40 PMOS L=5 W=80

M4

out

Vdd Vdd PMOS L=5 W=80

.ENDS *****SUBCKT 3 ****** .SUBCKT Nor A M1 out B 0 0 M2 out A 0 0 M3 1 A Vdd Vdd M4 out B 1 Vdd .ENDS .model nmos nmos Level=14 .model pmos pmos Level=14 B Vdd out NMOS L=5 W=40 NMOS L=5 W=40 PMOS L=5 W=80 PMOS L=5 W=80

Delay from simulation: TPHL = 2.1ns TPLH = 2.3ns

Problem 12.9 Sketch the schematic of a three-input XOR gate implemented in AOI logic.

Justin Wood

The truth table for the three-input XOR gate is as follows:

By applying Boolean math, an AOI logic function can be developed. (See Below.) _ _ _ _ _ _ Z=ABC=ABC+ BAC+ CAB _ _ _ _ Z= (A+B+C)(B+A+C)(C+A+B) ________________________ _ _ _ Z= (A+B+C)(B+A+C)(C+A+B) ______ ______ ______ _ _ _ Z= (A+B+C)+(B+A+C)+(C+A+B) The schematic can then be drawn as shown below.

Problem 12.10

By Vehid Suljic

The circuit shown in Fig. 12.27 is an edge detector. Discuss and simulate the operation of the circuit.

Xor gate gives us logic 1 out any time we have 2 different signals at the input of the gate (logic 1 and logic 0). Other logic combination inputs gives us output of logic 1. So if we have same inputs just one delayed then for the time of the delay inputs are going to be different whenever input signal changes for 0 to 1 (rising edge) or from 1 to 0 (falling edge). Basically, we generate pulse at each edge with the width of the delay at the input signals. Figure bellow shows simulation of the circuit in Fig. 12.27. Input signals was delayed with 8 stage buffers that gave about 200 psec delays. Simulation shows that we generated pulse at output at each edge of input signal with the width of about 200 psec.

.control destroy all run plot vin vout vin_delayed .endc .option scale=50n .tran 10p 4n 50p vdd Vin x1 vdd vin vin 0 0 DC DC 1 0 out pulse 0 1 0.2n 10p 10p 1n 2n vdd Xor_2

vin_delayed

X2 vin vin1 VDD X3 vin1 vin2 VDD X4 vin2 vin3 VDD X5 vin3 vin4 VDD X6 vin4 vin5 VDD X7 vin5 vin6 VDD X8 vin6 vin7 VDD X9 vin7 vin_delayed .subckt inverter in M1 out in 0 M2 out in VDD .ends .subckt Xor_2 xx1 A xx2 B M1 P3 M2 out M3 P4 M4 out M5 M6 M7 M8 .ends out p1 out p1 A notA notB B A notB notA B VDD VDD 0 p3 0 p3

inverter inverter inverter inverter inverter inverter inverter VDD inverter out VDD 0 NMOS L=1 W=10 VDD PMOS L=1 W=20 out vdd inverter inverter 0 NMOS L=1 W=10 p3 NMOS L=1 W=10 0 NMOS L=1 W=10 p3 NMOS L=1 W=10 p1 VDD p1 VDD PMOS L=1 W=20 PMOS L=1 W=20 PMOS L=1 W=20 PMOS L=1 W=20

notA p1 A vdd notB P1 B vdd