UCC27321, UCC27322 UCC37321, UCC37322

SLUS504C SEPTEMBER 2002 REVISED NOVEMBER 2004

SINGLE 9 A HIGH SPEED LOW-SIDE MOSFET DRIVER WITH ENABLE

FEATURES D Industry-Standard Pin-Out With Addition of D D D D D D D D D
Enable Funtion High-Peak Current Drive Capability of 9 A at the Miller Plateau Region Using TrueDrive Efficient Constant Current Sourcing Using a Unique BiPolar & CMOS Output Stage TTL/CMOS Compatible Inputs Independent of Supply Voltage 20-ns Typical Rise and Fall Times with 10-nF Load Typical Propagation Delay Times of 25 ns With Input Falling and 35 ns with Input Rising 4-V to 15-V Supply Voltage Available in Thermally Enhanced MSOP PowerPADTM Package With 4.7C/W jc Rated From 40C to 105C Pb-Free Finish (NiPdAu) on SOIC-8 and PDIP-8 Packages

APPLICATIONS D Switch Mode Power Supplies D DC/DC Converters D Motor Controllers D Class-D Switching Amplifiers D Line Drivers D Pulse Transformer Driver DESCRIPTION
The UCC37321/2 family of high-speed drivers deliver 9 A of peak drive current in an industry standard pinout. These drivers can drive the largest of MOSFETs for systems requiring extreme Miller current due to high dV/dt transitions. This eliminates additional external circuits and can replace multiple components to reduce space, design complexity and assembly cost. Two standard logic options are offered, inverting (UCC37321) and noninverting (UCC37322).

VDD

1 INVERTING

VDD

INPUT/OUTPUT TABLE ENBL 0 0 1 1 0 NON INVERTING UCC37322 0 1 1 IN 0 1 0 1 0 1 0 1 OUT 0 0 1 0 0 0 0 1

7 VDD IN 2 NON INVERTING RENBL 100 k 6

OUT

INVERTING UCC37321

OUT

ENBL AGND

3 4

PGND

UDG01112

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPADt is trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 2004, Texas Instruments Incorporated

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UCC27321, UCC27322 UCC37321, UCC37322

SLUS504C SEPTEMBER 2002 REVISED NOVEMBER 2004

description (continued)
Using a design that inherently minimizes shoot-through current, the outputs of these can provide high gate drive current where it is most needed at the Miller plateau region during the MOSFET switching transition. A unique hybrid output stage paralleling bipolar and MOSFET transistors (TrueDrive) allows efficient current delivery at low supply voltages. With this drive architecture, UCC37321/2/3 can be used in industry standard 6-A, 9-A and many 12-A driver applications. Latch up and ESD protection circuitries are also included. Finally, the UCC37321/2 provides an enable (ENBL) function to have better control of the operation of the driver applications. ENBL is implemented on pin 3 which was previously left unused in the industry standard pinout. It is internally pulled up to Vdd for active high logic and can be left open for standard operation. In addition to SOIC-8 (D) and PDIP-8 (P) package offerings, the UCC37321/2 also comes in the thermally enhanced but tiny 8-pin MSOP PowerPADt (DGN) package. The PowerPADt package drastically lowers the thermal resistance to extend the temperature operation range and improve the long-term reliability.

absolute maximum ratings over operating free-air temperature (unless otherwise noted)}
UCCx732x Supply voltage, VDD Output current (OUT) DC, IOUT_DC Input voltage (IN), VIN Enable voltage (ENBL) Power dissipation at TA = 25C D package DGN package P package Junction operating temperature, TJ Storage temperature, Tstg Lead temperature (soldering, 10 sec.) 650 3 350 55 to 150 65 to 150 300 mW W mW C C C 0.3 to 16 0.6 5 V to 6 V or VDD+0.3 (whichever is larger) 0.3 V to 6 V or VDD+0.3 (whichever is larger) V UNIT V A

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal.

ordering information
OUTPUT CONFIGURATION TEMPERATURE RANGE TA = TJ 40C to +105C Inverting NonInverting 0C to +70C 40C to +105C 0C to +70C PACKAGED DEVICES SOIC-8 (D) UCC27321D UCC37321D UCC27322D UCC37322D MSOP-8 PowerPAD (DGN) UCC27321DGN UCC37321DGN UCC27322DGN UCC37322DGN PDIP-8 (P) UCC27321P UCC37321P UCC27322P

UCC37322P D (SOIC8) and DGN (PowerPADMSOP) packages are available taped and reeled. Add R suffix to device type (e.g. UCC37321DR, UCC37322DGNR) to order quantities of 2,500 devices per reel.

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UCC27321, UCC27322 UCC37321, UCC37322

SLUS504C SEPTEMBER 2002 REVISED NOVEMBER 2004

electrical characteristics, VDD = 4.5 V to 15 V, TA = 40C to 105C for UCC2732x, TA = 0C to 70C for UCC3732x, TA = TJ, (unless otherwise noted) input (IN)
PARAMETER VIN_H, logic 1 input threshold VIN_L, logic 0 input threshold Input current 0 V VIN VDD 10 0 TEST CONDITION MIN 2 1 10 TYP MAX UNITS V V A

output (OUT)
PARAMETER Peak output current(1)(2) VOH, output high level VOL, output high level Output resistance high(3) Output resistance low(3) latchup protection(1) TEST CONDITION VDD = 14 V, VOH = VDD VOUT, IOUT = 10 mA IOUT = 10 mA IOUT = 10 mA, IOUT = 10 mA, VDD = 14 V VDD = 14 V 500 MIN TYP 9 150 11 15 1.1 300 25 25 2.5 MAX UNITS A mV mV mA

overall
PARAMETER IN = LO, EN = LO, UCC37321 UCC27321 IDD, static operating current UCC37322 UCC27322 IN = HI, IN = HI, IN = HI, IN = HI, EN = LO, EN = HI, EN = LO, EN = HI, IN = LO, EN = HI, IN = LO, EN = LO, IN = LO, EN = HI, TEST CONDITION VDD = 15 V VDD = 15 V VDD = 15 V VDD = 15 V VDD = 15 V VDD = 15 V VDD = 15 V VDD = 15 V MIN TYP 150 440 370 370 150 450 75 675 MAX 225 650 550 550 225 650 125 1000 A A UNITS

enable (ENBL)
PARAMETER VIN_H, high-level input voltage VIN_L, low-level input voltage Hysteresis RENBL, enable impedance tD3, propagation delay time(5) tD4, propagation delay time(5) VDD = 14 V, CLOAD = 10 nF CLOAD = 10 nF ENBL = GND LO to HI transition HI to LO transition TEST CONDITION MIN 1.7 1.1 0.25 75 TYP 2.2 1.6 0.55 100 60 60 MAX 2.7 2.0 0.90 135 90 90 ns V k UNITS V

NOTES: 1. Ensured by design. Not tested in production. 2. The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The peak output current rating is the combined current from the bipolar and MOSFET transistors. 3. The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the RDS(ON) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. 5. See Figure 2.

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SLUS504C SEPTEMBER 2002 REVISED NOVEMBER 2004

electrical characteristics, VDD = 4.5 V to 15 V, TA = 40C to 105C for UCC2732x, TA = 0C to 70C for UCC3732x, TA = TJ, (unless otherwise noted) (continued) switching time (4)
PARAMETER tR, rise time (OUT) tF, fall time (OUT) tD1, propagation delay, IN rising (IN to OUT) tD2, propagation delay, IN falling (IN to OUT) CLOAD = 10 nF CLOAD = 10 nF CLOAD = 10 nF CLOAD = 10 nF TEST CONDITION MIN TYP 20 20 25 35 MAX 70 30 70 70 ns UNITS

NOTES: 4. See Figure 1 for switching waveforms.

(a) 5V IN 0V VTH tD1 tF 80% OUT 20% 0V 80% tR OUT 80% VTH tD2 IN

(b)

VTH tD1

VTH tD2

VDD

80% tR 20% tF

Figure 1. Switching Waveforms for (a) Inverting Input to (b) Output Times(6)
5V ENBL 0V tD3 VDD 80% OUT tR 20% 0V 80% tF tD4 VIN_H VIN_L

Figure 2. Switching Waveform for Enable to Output(6)

NOTES: 6. The 20% and 80% thresholds depict the dynamics of the BiPolar output devices that dominate the power MOSFET transition through the Miller regions of operation.

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SLUS504C SEPTEMBER 2002 REVISED NOVEMBER 2004

pin configurations
PDIP (P) PACKAGE (TOP VIEW) SOIC (D) OR MSOP (DGN) PACKAGE (TOP VIEW)

VDD IN ENBL AGND

1 2 3 4

8 7 6 5

VDD OUT OUT PGND

VDD IN ENBL AGND

1 2 3 4

8 7 6 5

VDD OUT OUT PGND

power dissipation rating table

PACKAGE SOIC-8 PDIP-8 SUFFIX D P jc (5C/W) 42 49 ja (5C/W) 84 160 } 110 Power Rating (mW) TA = 705C 344655 } 500 Derating Factor Above 705C (mW/5C) 6.25 11.9 } 9

MSOP PowerPAD-8 DGN 4.7 5059 1370 17.1 125C operating junction temperature is used for power rating calculations The range of values indicates the effect of pcboard. These values are intended to give the system designer an indication of the best and worst case conditions. In general, the system designer should attempt to use larger traces on the pcboard where possible in order to spread the heat away form the device more effectively. For additional information on device temperature management, please refer to Packaging Information section of the Power Supply Control Products Data Book, (Ti Literature Number SLUD003).

terminal functions
TERMINAL NO. 4 NAME AGND I/O FUNCTION Common ground for input stage. This ground should be connected very closely to the source of the power MOSFET which the driver is driving. Grounds are separated to minimize ringing affects due to output switching di/dt which can affect the input threshold. Enable input for the driver with logic compatible threshold and hysteresis. The driver output can be enabled and disabled with this pin. It is internally pulled up to VDD with 100-k resistor for active high operation. The output state when the device is disabled will be low regardless of the input state. Input signal of the driver which has logic compatible threshold and hysteresis. Driver outputs that must be connected together externally. The output stage is capable of providing 9-A peak drive current to the gate of a power MOSFET. Common ground for output stage. This ground should be connected very closely to the source of the power MOSFET which the driver is driving. Grounds are separated to minimize ringing affects due to output switching di/dt which can affect the input threshold. Supply voltage and the power input connections for this device. Three pins must be connected together externally.

ENBL

2 6, 7

IN OUT

I O

PGND

1, 8

VDD

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UCC27321, UCC27322 UCC37321, UCC37322

SLUS504C SEPTEMBER 2002 REVISED NOVEMBER 2004

APPLICATION INFORMATION general information

The UCC37321 and UCC37322 drivers serve as an interface between low-power controllers and power MOSFETs. They can also be used as an interface between DSPs and power MOSFETs. High-frequency power supplies often require high-speed, high-current drivers such as the UCC37321/2 family. A leading application is the need to provide a high power buffer stage between the PWM output of the control device and the gates of the primary power MOSFET or IGBT switching devices. In other cases, the device drives the power device gates through a drive transformer. Synchronous rectification supplies also have the need to simultaneously drive multiple devices which can present an extremely large load to the control circuitry. The inverting driver (UCC37321) is useful for generating inverted gate drive signals from controllers that have only outputs of the opposite polarity. For example, this driver can provide a gate signal for ground referenced, N-channel synchronous rectifier MOSFETs in buck derived converters. This driver can also be used for generating a gate drive signal for a P-channel MOSFET from a controller that is designed for N-channel applications. MOSFET gate drivers are generally used when it is not feasible to have the primary PWM regulator device directly drive the switching devices for one or more reasons. The PWM device may not have the brute drive capability required for the intended switching MOSFET, limiting the switching performance in the application. In other cases there may be a desire to minimize the effect of high frequency switching noise by placing the high current driver physically close to the load. Also, newer devices that target the highest operating frequencies may not incorporate onboard gate drivers at all. Their PWM outputs are only intended to drive the high impedance input to a driver such as the UCC37321/2. Finally, the control device may be under thermal stress due to power dissipation, and an external driver can help by moving the heat from the controller to an external package.

input stage
The IN threshold has a 3.3-V logic sensitivity over the full range of VDD voltages; yet, it is equally compatible with 0 V to VDD signals. The inputs of UCC37321/2 family of drivers are designed to withstand 500-mA reverse current without either damage to the device or logic upset. In addition, the input threshold turn-off of the UCC37321/2 has been slightly raised for improved noise immunity. The input stage of each driver should be driven by a signal with a short rise or fall time. This condition is satisfied in typical power supply applications, where the input signals are provided by a PWM controller or logic gates with fast transition times (<200 ns). The IN input of the driver functions as a digital gate, and it is not intended for applications where a slow changing input voltage is used to generate a switching output when the logic threshold of the input section is reached. While this may not be harmful to the driver, the output of the driver may switch repeatedly at a high frequency. Users should not attempt to shape the input signals to the driver in an attempt to slow down (or delay) the signal at the output. If limiting the rise or fall times to the power device is desired, then an external resistance can be added between the output of the driver and the load device, which is generally a power MOSFET gate. The external resistor may also help remove power dissipation from the device package, as discussed in the section on Thermal Considerations.

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SLUS504C SEPTEMBER 2002 REVISED NOVEMBER 2004

APPLICATION INFORMATION output stage

The TrueDrive output stage is capable of supplying 9-A peak current pulses and swings to both VDD and GND and can encourage even the most stubborn MOSFETs to switch. The pull-up/pull-down circuits of the driver are constructed of bipolar and MOSFET transistors in parallel. The peak output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance is the RDS(ON) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. Each output stage also provides a very low impedance to overshoot and undershoot due to the body diode of the external MOSFET. This means that in many cases, external-schottky-clamp diodes are not required. This unique BiPolar and MOSFET hybrid output architecture (TrueDrive) allows efficient current sourcing at low supply voltages. The UCC37321/2 family delivers 9 A of gate drive where it is most needed during the MOSFET switching transition at the Miller plateau region providing improved efficiency gains.

source/sink capabilities during miller plateau

Large power MOSFETs present a significant load to the control circuitry. Proper drive is required for efficient, reliable operation. The UCC37321/2 drivers have been optimized to provide maximum drive to a power MOSFET during the Miller Plateau Region of the switching transition. This interval occurs while the drain voltage is swinging between the voltage levels dictated by the power topology, requiring the charging/discharging of the drain-gate capacitance with current supplied or removed by the driver device. [1] Two circuits are used to test the current capabilities of the UCC37321/2 driver. In each case external circuitry is added to clamp the output near 5 V while the device is sinking or sourcing current. An input pulse of 250 ns is applied at a frequency of 1 kHz in the proper polarity for the respective test. In each test there is a transient period where the current peaked up and then settled down to a steady-state value. The noted current measurements are made at a time of 200 ns after the input pulse is applied, after the initial transient. The circuit in Figure 3 is used to verify the current sink capability when the output of the driver is clamped around 5 V, a typical value of gate-source voltage during the Miller Plateau Region. The UCC37321 is found to sink 9 A at VDD = 15 V.
VDD

UCC37321 INPUT 1 VDD 2 IN VDD 8 OUT OUT DSCHOTTKY 7 6 C2 1 F C3 100 F + VSUPPLY 5.5 V 10

3 ENBL 4 AGND

PGND 5

VSNS 1 F CER 100 F AL EL RSNS 0.1

UDG01113

Figure 3. Sink Current Test Circuit

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SLUS504C SEPTEMBER 2002 REVISED NOVEMBER 2004

APPLICATION INFORMATION
The circuit in Figure 4 is utilized to test the current source capability with the output clamped to around 5 V with a string of Zener diodes. The UCC37321 is found to source 9 A at VDD = 15 V.
VDD

UCC37321 INPUT 1 VDD IN VDD 8 OUT DSCHOTTKY 7 C2 1 F C3 100 F 4.5 V DADJ

ENBL

OUT

AGND

PGND 5 RSNS 0.1

VSNS 1 F CER 100 F AL EL

UDG01114

Figure 4. Source Current Test Circuit It should be noted that the current sink capability is slightly stronger than the current source capability at lower VDD. This is due to the differences in the structure of the bipolar-MOSFET power output section, where the current source is a P-channel MOSFET and the current sink has an N-channel MOSFET. In a large majority of applications it is advantageous that the turn-off capability of a driver is stronger than the turn-on capability. This helps to ensure that the MOSFET is held OFF during common power supply transients which may turn the device back ON.

operational circuit layout

It can be a significant challenge to avoid the overshoot/undershoot and ringing issues that can arise from circuit layout. The low impedance of these drivers and their high di/dt can induce ringing between parasitic inductances and capacitances in the circuit. Utmost care must be used in the circuit layout. In general, position the driver physically as close to its load as possible. Place a 1-F bypass capacitor as close to the output side of the driver as possible, connecting it to pins 1 and 8. Connect a single trace between the two VDD pins (pin 1 and pin 8); connect a single trace between PGND and AGND (pin 5 and pin 4). If a ground plane is used, it may be connected to AGND; do not extend the plane beneath the output side of the package (pins 5 8). Connect the load to both OUT pins (pins 7 and 6) with a single trace on the adjacent layer to the component layer; route the return current path for the output on the component side, directly over the output path. Extreme conditions may require decoupling the input power and ground connections from the output power and ground connections. The UCCx7321/2 has a feature that allows the user to take these extreme measures, if necessary. There is a small amount of internal impedance of about 15 between the AGND and PGND pins; there is also a small amount of impedance (30 ) between the two VDD pins. In order to take advantage of this feature, connect a 1-F bypass capacitor between VDD and PGND (pins 5 and 8) and connect a 0.1-F bypass capacitor between VDD and AGND (pins 1 and 4). Further decoupling can be achieved by connecting between the two VDD pins with a jumper that passes through a 40-MHz ferrite bead and connect bias power only to pin 8. Even more decoupling can be achieved by connecting between AGND and PGND with a pair of anti-parallel diodes (anode connected to cathode and cathode connected to anode).

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SLUS504C SEPTEMBER 2002 REVISED NOVEMBER 2004

APPLICATION INFORMATION VDD

Although quiescent VDD current is very low, total supply current will be higher, depending on OUTA and OUTB current and the operating frequency. Total VDD current is the sum of quiescent VDD current and the average OUT current. Knowing the operating frequency and the MOSFET gate charge (Qg), average OUT current can be calculated from: IOUT = Qg x f, where f is frequency For the best high-speed circuit performance, two VDD bypass capacitors are recommended tp prevent noise problems. The use of surface mount components is highly recommended. A 0.1-F ceramic capacitor should be located closest to the VDD to ground connection. In addition, a larger capacitor (such as 1-F) with relatively low ESR should be connected in parallel, to help deliver the high current peaks to the load. The parallel combination of capacitors should present a low impedance characteristic for the expected current levels in the driver application.

drive current and power requirements

The UCC37321/2 family of drivers are capable of delivering 9-A of current to a MOSFET gate for a period of several hundred nanoseconds. High peak current is required to turn an N-channel device ON quickly. Then, to turn the device OFF, the driver is required to sink a similar amount of current to ground. This repeats at the operating frequency of the power device. An N-channel MOSFET is used in this discussion because it is the most common type of switching device used in high frequency power conversion equipment. References 1 and 2 contain detailed discussions of the drive current required to drive a power MOSFET and other capacitiveinput switching devices. Much information is provided in tabular form to give a range of the current required for various devices at various frequencies. The information pertinent to calculating gate drive current requirements will be summarized here; the original document is available from the TI website. When a driver device is tested with a discrete, capacitive load it is a fairly simple matter to calculate the power that is required from the bias supply. The energy that must be transferred from the bias supply to charge the capacitor is given by: E + 1 CV 2, where C is the load capacitor and V is the bias voltage feeding the driver. 2 There is an equal amount of energy transferred to ground when the capacitor is discharged. This leads to a power loss given by the following: P+2 1 CV 2f, where f is the switching frequency. 2

This power is dissipated in the resistive elements of the circuit. Thus, with no external resistor between the driver and gate, this power is dissipated inside the driver. Half of the total power is dissipated when the capacitor is charged, and the other half is dissipated when the capacitor is discharged. An actual example using the conditions of the previous gate drive waveform should help clarify this. With VDD = 12 V, CLOAD = 10 nF, and f = 300 kHz, the power loss can be calculated as: P = 10 nF x (12)2 x (300 kHz) = 0.432 W With a 12-V supply, this would equate to a current of: I + P + 0.432 W + 0.036 A V 12 V

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SLUS504C SEPTEMBER 2002 REVISED NOVEMBER 2004

APPLICATION INFORMATION drive current and power requirements (continued)

The switching load presented by a power MOSFET can be converted to an equivalent capacitance by examining the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus the added charge needed to swing the drain of the device between the ON and OFF states. Most manufacturers provide specifications that provide the typical and maximum gate charge, in nC, to switch the device under specified conditions. Using the gate charge Qg, one can determine the power that must be dissipated when charging a capacitor. This is done by using the equivalence Qg = CeffV to provide the following equation for power: P+C V2 f + Qg V f

This equation allows a power designer to calculate the bias power required to drive a specific MOSFET gate at a specific bias voltage.

enable
UCC37321/2 provides an Enable input for improved control of the driver operation. This input also incorporates logic compatible thresholds with hysteresis. It is internally pulled up to VDD with 100-k resistor for active high operation. When ENBL is high, the device is enabled and when ENBL is low, the device is disabled. The default state of the ENBL pin is to enable the device and therefore can be left open for standard operation. The output state when the device is disabled is low regardless of the input state. See the truth table below for the operation using enable logic. ENBL input is compatible with both logic signals and slow changing analog signals. It can be directly driven or a powerup delay can be programmed with a capacitor between ENBL and AGND. Table 1. Input/Ouput Table
ENBL 0 0 1 1 0 NON INVERTING UCC37322 0 1 1 IN 0 1 0 1 0 1 0 1 OUT 0 0 1 0 0 0 0 1

INVERTING UCC37321

10

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SLUS504C SEPTEMBER 2002 REVISED NOVEMBER 2004

THERMAL INFORMATION
The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal characteristics of the device package. In order for a power driver to be useful over a particular temperature range the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits. The UCC37321/2 family of drivers is available in three different packages to cover a range of application requirements. As shown in the power dissipation rating table, the SOIC-8 (D) and PDIP-8 (P) packages each have a power rating of around 0.5 W with TA = 70C. This limit is imposed in conjunction with the power derating factor also given in the table. Note that the power dissipation in our earlier example is 0.432 W with a 10-nF load, 12 VDD, switched at 300 kHz. Thus, only one load of this size could be driven using the D or P packag. The difficulties with heat removal limit the drive available in the D or P packages. The MSOP PowerPAD-8 (DGN) package significantly relieves this concern by offering an effective means of removing the heat from the semiconductor junction. As illustrated in Reference 3, the PowerPAD packages offer a leadframe die pad that is exposed at the base of the package. This pad is soldered to the copper on the PC board directly underneath the device package, reducing the jc down to 4.7C/W. Data is presented in Reference 3 to show that the power dissipation can be quadrupled in the PowerPAD configuration when compared to the standard packages. The PC board must be designed with thermal lands and thermal vias to complete the heat removal subsystem, as summarized in Reference 4. This allows a significant improvement in heatsinking over that available in the D or P packages, and is shown to more than double the power capability of the D and P packages. Note that the PowerPADt is not directly connected to any leads of the package. However, it is electrically and thermally connected to the substrate which is the ground of the device.

references
1. SEM-1400, Topic 2, A Design and Application Guide for High Speed Power MOSFET Gate Drive Circuits, TI Literature No. SLUP133 2. U137, Practical Considerations in High Performance MOSFET, IGBT and MCT Gate Drive Circuits, by Bill Andreycak, TI Literature No. SLUA105 3. Technical Brief, PowerPad Thermally Enhanced Package, TI Literature No. SLMA002 4. Application Brief, PowerPAD Made Easy, TI Literature No. SLMA004

related products
PRODUCT UCC37323/4/5 UCC27423/4/5 TPS2811/12/13 TPS2814/15 TPS2816/17/18/19 TPS2828/29 DESCRIPTION Dual 4-A Low-Side Drivers Dual 4-A Low-Side Drivers with Enable Dual 2-A Low-Side Drivers with Internal Regulator Dual 2-A Low-Side Drivers with Two Inputs per Channel Single 2-A Low-Side Driver with Internal Regulator Single 2-A Low-Side Driver PACKAGES MSOP8 PowerPAD, SOIC8, PDIP8 MSOP8 PowerPAD, SOIC8, PDIP8 TSSOP8, SOIC8, PDIP8 TSSOP8, SOIC8, PDIP8 5-Pin SOT23 5-Pin SOT23

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SLUS504C SEPTEMBER 2002 REVISED NOVEMBER 2004

TYPICAL CHARACTERISTICS
INPUT CURRENT IDLE vs SUPPLY VOLTAGE (UCCx7321)
700

700

INPUT CURRENT IDLE vs SUPPLY VOLTAGE (UCCx7322)

600 IDD Input Current Idle A ENBL = 0 V IN = 5 V IDD Input Current Idle A

600 ENBL = 0 V IN = 5 V

500 400

500 400 ENBL = 0 V IN = 0 V

ENBL = VDD IN = 5 V ENBL = 0 V IN = 0 V

300 200

300 200

ENBL = VDD IN = 5 V ENBL = VDD, IN = 0 V

100 0 0 2 4 ENBL = VDD, IN = 0 V 6 8 10 12 14 16

100 0 0 2 4 6 8 10 12 14 16 VDD Supply Voltage V

VDD Supply Voltage V

Figure 5
INPUT CURRENT IDLE vs TEMPERATURE (UCCx7321)
800 700 IDD Input Current Idle A IDD Input Current Idle A 600 ENBL = LO IN = HI 500 400 300 200 100 0 50 ENBL = LO IN = LO ENBL = HI IN = HI ENBL = HI IN = LO 800 700 600 500 400 300 200 100 0 50 ENBL = HI IN = HI

Figure 6
INPUT CURRENT IDLE vs TEMPERATURE (UCCx7322)

ENBL = LO IN = HI

ENBL = LO IN = LO

ENBL = HI IN = LO

25

0 25 50 75 TJ Temperature C

100

125

25

25 50 75 TJ Temperature C

100

125

Figure 7

Figure 8

12

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SLUS504C SEPTEMBER 2002 REVISED NOVEMBER 2004

TYPICAL CHARACTERISTICS
RISE TIME vs SUPPLY VOLTAGE
70 CLOAD = 10 nF 60 tA = 40C tF Fall Time ns 60 70

FALL TIME vs SUPPLY VOLTAGE

tR Rise Time ns

50 40

50 40

tA = 105C 30

tA = 25C

30

tA = 105C

tA = 25C

20

20 tA = 0C

10 0 4 6

10 0 4

tA = 0C

tA = 40C 8 10 12 VDD Supply Voltage V 14 16

10

12

14

16

VDD Supply Voltage V

Figure 9
RISE TIME vs LOAD CAPACITANCE

Figure 10
FALL TIME vs OUTPUT CAPACITANCE

40

200

VDD = 5 V 160 30 tF Fall Time ns tR Rise Time ns VDD = 10 V VDD = 15 V 20 120

VDD = 5 V VDD = 10 V VDD = 15 V

80

10

40

0 1 10 CLOAD Load Capacitance nF 100

0 1 10 CLOAD Load Capacitance nF 100

Figure 11

Figure 12

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SLUS504C SEPTEMBER 2002 REVISED NOVEMBER 2004

TYPICAL CHARACTERISTICS
tD1 DELAY TIME vs SUPPLY VOLTAGE
70 CLOAD = 10 nF 60 tA = 105C tD1 Delay Time ns 50 tA = 25C 40 tD2 Delay Time ns 50 tA = 25C 60 tA = 105C 70 CLOAD = 10 nF

tD2 DELAY TIME vs SUPPLY VOLTAGE

40

30 20 tA = 40C 10 0 4 6 8 10 12 14 16 VDD Supply Voltage V tA = 0C

30 tA = 0C 20 tA = 40C 10 0 4 6 8 10 12 14 16 VDD Supply Voltage V

Figure 13
tD1 DELAY TIME vs LOAD CAPACITANCE
70 70

Figure 14
tD2 DELAY TIME vs LOAD CAPACITANCE

60

VDD = 5 V 60

tD1 Delay Time ns

tD2 Delay Time ns

50 VDD = 5 V 40 30 VDD = 10 V

50

40 30 VDD = 15 V 20 10 VDD = 10 V

20 10

VDD = 15 V

0 1 10 CLOAD Load Capacitance nF 100

0 1 10 CLOAD Load Capacitance nF 100

Figure 15

Figure 16

14

www.ti.com

UCC27321, UCC27322 UCC37321, UCC37322

SLUS504C SEPTEMBER 2002 REVISED NOVEMBER 2004

TYPICAL CHARACTERISTICS
PROPAGATION TIMES vs PEAK INPUT VOLTAGE
VDD = 15 V CLOAD = 10 nF TA = 25C tRISE Propagation Time ns 35 30 25 20 15 10 5 0 0 10 VIN(peak) Peak Input Voltage V 5 15 tD1 tFALL

50 45 40

2.0 VON Input Threshold Voltage V 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 50 VDD = 10 V

INPUT THRESHOLD vs TEMPERATURE

tD2

VDD = 15 V

VDD = 4.5 V

25

25

50

75

100

125

TJ Temperature C

Figure 17
ENABLE THRESHOLD AND HYSTERESIS vs TEMPERATURE

Figure 18
ENABLE RESISTANCE vs TEMPERATURE
150 140 RENBL Enable Resistance 130 120 110 100 90 80 70 60 50 50

3.0

ENBL ON Enable threshold and hysteresis V 2.5

2.0

1.5

1.0 ENBL OFF 0.5 ENBL HYSTERESIS 0 50

25

0 25 50 75 TJ Temperature C

100

125

25

25

50

75

100

125

TJ Temperature C

Figure 19

Figure 20

www.ti.com

15

UCC27321, UCC27322 UCC37321, UCC37322

SLUS504C SEPTEMBER 2002 REVISED NOVEMBER 2004

TYPICAL CHARACTERISTICS
OUTPUT BEHAVIOR vs VDD (UCC37321)
IN = GND ENBL = VDD

OUTPUT BEHAVIOR vs VDD (UCC37321)

IN = GND ENBL = VDD

VDD Input Voltage V 1 V/div

VDD Input Voltage V 1 V/div

VDD OUT

OUT

0V

0V

VDD 10 nF Between Output and GND 50 s/div

10 nF Between Output and GND 50 s/div

Figure 21
OUTPUT BEHAVIOR vs VDD (INVERTING)

Figure 22
OUTPUT BEHAVIOR vs VDD (INVERTING)

IN = VDD ENBL = VDD VDD Supply Voltage V 1 V/div VDD Supply Voltage V 1 V/div

IN = VDD ENBL = VDD

VDD

VDD

OUT

OUT

0V

0V

10 nF Between Output and GND 50 s/div

10 nF Between Output and GND 50 s/div

Figure 23

Figure 24

16

www.ti.com

UCC27321, UCC27322 UCC37321, UCC37322

SLUS504C SEPTEMBER 2002 REVISED NOVEMBER 2004

TYPICAL CHARACTERISTICS
OUTPUT BEHAVIOR vs VDD (UCC37322)
IN = VDD ENBL = VDDIN = GND VDD Input Voltage V 1 V/div VDD Input Voltage V 1 V/div

OUTPUT BEHAVIOR vs VDD (UCC37322)

IN = VDD ENBL = VDDIN = GND

VDD OUT

VDD

OUT 0V

0V

10 nF Between Output and GND 50 s/div

10 nF Between Output and GND 50 s/div

Figure 25
OUTPUT BEHAVIOR vs VDD (NON-INVERTING)
IN = GND ENBL = VDD

Figure 26
OUTPUT BEHAVIOR vs VDD (NON-INVERTING)
IN = GND ENBL = VDD

VDD Supply Voltage V 1 V/div

VDD

VDD Supply Voltage V 1 V/div

VDD

OUT

OUT

0V

0V

10 nF Between Output and GND 50 s/div

10 nF Between Output and GND 50 s/div

Figure 27

Figure 28

www.ti.com

17

PACKAGE OPTION ADDENDUM

www.ti.com

27-Feb-2006

PACKAGING INFORMATION
Orderable Device UCC27321D UCC27321DGN Status (1) ACTIVE ACTIVE Package Type SOIC MSOPPower PAD MSOPPower PAD MSOPPower PAD MSOPPower PAD SOIC SOIC PDIP PDIP SOIC SOIC MSOPPower PAD MSOPPower PAD MSOPPower PAD MSOPPower PAD SOIC SOIC PDIP PDIP SOIC MSOPPower PAD Package Drawing D DGN Pins Package Eco Plan (2) Qty 8 8 75 80 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-1-260C-UNLIM Level-1-260C-UNLIM

UCC27321DGNG4

ACTIVE

DGN

80

CU NIPDAU

Level-1-260C-UNLIM

UCC27321DGNR

ACTIVE

DGN

2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 50 50 75 75 80 Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

UCC27321DGNRG4

ACTIVE

DGN

CU NIPDAU

Level-1-260C-UNLIM

UCC27321DR UCC27321DRG4 UCC27321P UCC27321PE4 UCC27322D UCC27322DG4 UCC27322DGN

ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE

D D P P D D DGN

8 8 8 8 8 8 8

CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU

Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM

UCC27322DGNG4

ACTIVE

DGN

80

CU NIPDAU

Level-1-260C-UNLIM

UCC27322DGNR

ACTIVE

DGN

2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 50 50 75 80 Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

UCC27322DGNRG4

ACTIVE

DGN

CU NIPDAU

Level-1-260C-UNLIM

UCC27322DR UCC27322DRG4 UCC27322P UCC27322PE4 UCC37321D UCC37321DGN

ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE

D D P P D DGN

8 8 8 8 8 8

CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU

Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type Level-1-260C-UNLIM Level-1-260C-UNLIM

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

27-Feb-2006

Orderable Device UCC37321DGNG4

Status (1) ACTIVE

Package Type MSOPPower PAD MSOPPower PAD MSOPPower PAD SOIC SOIC PDIP PDIP SOIC MSOPPower PAD MSOPPower PAD MSOPPower PAD MSOPPower PAD SOIC SOIC PDIP PDIP

Package Drawing DGN

Pins Package Eco Plan (2) Qty 8 80 Green (RoHS & no Sb/Br)

Lead/Ball Finish CU NIPDAU

MSL Peak Temp (3) Level-1-260C-UNLIM

UCC37321DGNR

ACTIVE

DGN

2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 50 50 75 80 Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

UCC37321DGNRG4

ACTIVE

DGN

CU NIPDAU

Level-1-260C-UNLIM

UCC37321DR UCC37321DRG4 UCC37321P UCC37321PE4 UCC37322D UCC37322DGN

ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE

D D P P D DGN

8 8 8 8 8 8

CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU

Level-1-260C-UNLIM Level-2-260C-1 YEAR N / A for Pkg Type N / A for Pkg Type Level-1-260C-UNLIM Level-1-260C-UNLIM

UCC37322DGNG4

ACTIVE

DGN

80

CU NIPDAU

Level-1-260C-UNLIM

UCC37322DGNR

ACTIVE

DGN

2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 50 50 Pb-Free (RoHS) Pb-Free (RoHS)

CU NIPDAU

Level-1-260C-UNLIM

UCC37322DGNRG4

ACTIVE

DGN

CU NIPDAU

Level-1-260C-UNLIM

UCC37322DR UCC37322DRG4 UCC37322P UCC37322PE4

(1)

ACTIVE ACTIVE ACTIVE ACTIVE

D D P P

8 8 8 8

CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU

Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type

The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

27-Feb-2006

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 3

MECHANICAL DATA
MPDI001A JANUARY 1995 REVISED JUNE 1999

P (R-PDIP-T8)
0.400 (10,60) 0.355 (9,02) 8 5

PLASTIC DUAL-IN-LINE

0.260 (6,60) 0.240 (6,10)

4 0.070 (1,78) MAX 0.325 (8,26) 0.300 (7,62) 0.015 (0,38) 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.010 (0,25) NOM Gage Plane

0.020 (0,51) MIN

0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M

0.430 (10,92) MAX

4040082/D 05/98 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001

For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

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