Networks-on-Chip

This paper investigates the benefits of a recently proposed communication approach, namely on-chip stochastic communication, and proposes an analytical model for computing its mean hitting time. Towards this end, we model the stochastic communication as a branching process taking place on a finite mesh and estimate the mean number of communication rounds.

The proposed system is based on analytical model of Router and queueing theory. This approach not only provides aggregate performance metrics such as average latency and throughput, but also feedback about the network characteristics such as buffer utilization, average latency per router and per flow at a fine-level of granularity. The proposed analytical model can predict the average packet latency faster than an accurate simulation

Reducing energy consumption in multiprocessor systems-on-chip (MPSoCs) where communication happens via the network-on-chip (NoC) approach calls for multiple voltage/frequency island (VFI)-based designs. In turn, such multi-VFI architectures need efficient, robust, and accurate runtime control mechanisms that can exploit the workload characteristics in order to save power. Despite being tractable, the linear control models for power management cannot capture some important workload characteristics (e.g., fractality, nonstationarity) observed in heterogeneous NoCs; if ignored, such characteristics lead to inefficient communication and resources allocation, as well as high power dissipation in MPSoCs. To mitigate such limitations, we propose a new paradigm shift from power optimization based on linear models to control approaches based on fractal-state equations. As such, our approach is the first to propose a controller for fractal workloads with precise constraints on state and control variables and specific time bounds. Our results show that significant power savings can be achieved at runtime while running a variety of benchmark applications.

As the end of Moores-law is on the horizon, power becomes a limiting factor to continuous increases in performance gains for single-core processors. Processor engineers have shifted to the multicore paradigm and many-core processors are a reality. Within the context of these multicore chips, three key metrics point themselves out as being of major importance, performance, fault-tolerance (including yield), and power consumption. A solution that optimizes all three of these metrics is challenging. As the number of cores increases the importance of the interconnection network-on-chip (NoC) grows as well, and chip designers should aim to optimize these three key metrics in the NoC context as well. In this paper we identify and discuss the main properties that a NoC must exhibit in order to enable such optimizations. In particular, we propose the use of virtualization techniques at the NoC level. As a major finding, we identify the implementation of unicast and broadcast routing algorithms to become a key design parameter in order to achieve an effective virtualization of the chip. The intention behind this paper is for it to serve as a position paper on the topic of virtualization for NoC and the challenges that should be met at the routing layer in order to optimize performance, fault-tolerance and power consumption in multicore chips.

Special issue on Communication Architectures for Scalable Systems We are delighted to introduce this Special Issue for Communication Architectures for Scalable Systems. High-speed communication is a critical component in every part of an HPC system. On-chip networks for emerging manycore processors, point-to-point interconnects, which have replaced the system bus for intra-node communication, and system-wide networks, which form the backbone of any large-scale parallel system, all contribute to the construction of the world's fastest computers. Numerous research groups in academia, industry, and government are currently investigating the issues involved in improving the speed, reliability, power consumption, and other characteristics of all of these types of interconnects and seeking new ways to advance the state of the art in cluster communication. This Special Issue focuses on these communication architectures and in particular on recent results from research performed at every level of the network hierarchy (on-chip, intra-node, and cross-cluster) to present the reader with insights and ideas that span what have traditionally been separate communities. A competitive selection process was set up, including two review stages, with an outcome of 12 high quality contributions out of 35 submissions, addressing a range of topics related to interconnects. The first set of four papers addresses some well-known issues of current interconnects: QoS, flow control, and routing. First, quality of service is addressed by Jae W. Lee et al. in Globally Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks. This paper proposes a lightweight QoS mechanism for Chip Multiprocessor Systems that provides minimum bandwidth and maximum delay bounds. Then, Lizhong Chen et al., in Efficient Implementation of Globally-aware Network Flow Control, present a flow control mechanism, Critical Bubble Scheme, for k-ary n-cube networks. Then, Eitan Zahavi proposes, in Fat-Tree Routing and Node Ordering Providing Contention Free Traffic for MPI Global Collectives, a routing method and node ordering to completely remove contention in fat-tree networks for MPI applications with collective communication. In A Scalable and Fault-Tolerant Network Routing Scheme for Many-Core and Multi-Chip Systems, by Wen-Chung Tsai et al., a fault-tolerant routing algorithm is presented for both chip multiprocessors and for multi-chip systems. In the next two papers, performance and application-specific designs are the target. Performance effects and power implications for 10GbE networks are explored in Analyzing Performance and Power Efficiency of Network Processing over 10GbE by Guangdeng Liao et al. Then, an application-driven design of communication architectures is proposed for MPSoC systems by Yahya Jan et al. in Scalable Communication Architectures for Massively Parallel Hardware Multi-Processors.

Interference from high priority tasks and messages in a hard real-time Networks-on-Chip (NoC) create computation and communication delays. As the delays increase in number, maintaining the system's schedulability become difficult. In order to overcome the problem, one way is to reduce interference in the NoC by changing task mapping and network routing. Some population-based heuristics evaluate the worst-case response times of tasks and messages based on the schedulability analysis, but requires a significant amount of optimization time to complete due to the complexity of the evaluation function. In this paper, we propose an optimization technique that explore both parameters simultaneously with the aim to meet the schedulability of the system, hence reducing the optimization time. One of the advantages from our approach is the unrepeated call to the evaluation function, which is unaddressed in the heuristics that configure design parameters in stages. The results show that a schedulable configuration can be found from the large design space.

Network-on-Chip technology is gaining wide popularity for the interconnection of an increasing number of processor cores on the same silicon die. However, growing process variations cause interconnect malfunction or prevent the network from working at the intended frequency, directly impacting yield and manufacturing cost. Topology agnostic routing algorithms have the potential to tolerate process variations without degrading performance. We propose a three step methodology for evaluating routing algorithms in their ability to deal with variability. Using yield enhancement and operation speed preservation as the criteria, we demonstrate how this methodology can be used to select the best design choice among several plausible combinations of routing algorithms and implementations. Also, we show how an efficient table-less routing implementation can be used to minimise the impact of variability on manufacturing and operating frequency.

As interconnect becomes an important component of modern Chip Multiprocessors (CMPs), significant work has gone into finding the best tradeoff between performance and energy efficiency for the Network-on-Chip (NoC). Increasing core counts lead to high bandwidth demands and tight power and area constraints. One recent line of work examines bufferless deflection routing, which eliminates buffers in the NoC and instead handles contention by deflecting (misrouting) traffic.

The network-on-chip (NoC) is a primary shared resource in a chip multiprocessor (CMP) system. As core counts continue to increase and applications become increasingly data-intensive, the network load will also increase, leading to more congestion in the network. This network congestion can degrade system performance if the network load is not appropriately controlled. Prior works have proposed sourcethrottling congestion control, which limits the rate at which new network traffic (packets) enters the NoC in order to reduce congestion and improve performance. These prior congestion control mechanisms have shortcomings that significantly limit their performance: either 1) they are not application-aware, but rather throttle all applications equally regardless of applications' sensitivity to latency, or 2) they are not network-loadaware, throttling according to application characteristics but sometimes under-or over-throttling the cores.

As interconnect becomes an important component of modern Chip Multiprocessors (CMPs), significant work has gone into finding the best tradeoff between performance and energy efficiency for the Network-on-Chip (NoC). Increasing core counts lead to high bandwidth demands and tight power and area constraints. One recent line of work examines bufferless deflection routing, which eliminates buffers in the NoC and instead handles contention by deflecting (misrouting) traffic.

Networks-on-chips (NoCs) is an advanced form of an interconnect network for a System-on-chip (SoC). This communication substrate is a promising solution for common issues like scalability, ?exibility etc. faced by a typical bus based SoC. However, load balancing is one issue faced by NoC that would eventually lead to congestion. Hence congestion avoidance has become a primary challenge. Congestion avoidance schemes explore various routing algorithms, designs of routers etc. Another strategy for congestion avoidance is ?ow control. Various source throttling techniques are used to achieve ?ow control. This work proposes a scheme where the applications are classi?ed into two major groups, network intensive and network non intensive. Further, network intensive group is throttled with a heterogeneous throttling rate that yields better performance by analysing the overall network. This work tries to impose varying throttling rates for network intensive applications and performcomparison with state-of-art method. This work is evaluated on different traf?cs and evaluations show a stable and consistent performance when compared to previous methods.

The proposed system is based on analytical model of Router and queueing theory. This approach not only provides aggregate performance metrics such as average latency and throughput, but also feedback about the network characteristics such as buffer utilization, average latency per router and per flow at a fine-level of granularity. The proposed analytical model can predict the average packet latency faster than an accurate simulation

Network-on-Chip technology is gaining wide popularity for the interconnection of an increasing number of processor cores on the same silicon die. However, growing process variations cause interconnect malfunction or prevent the network from working at the intended frequency, directly impacting yield and manufacturing cost. Topology agnostic routing algorithms have the potential to tolerate process variations without degrading performance. We propose a three step methodology for evaluating routing algorithms in their ability to deal with variability. Using yield enhancement and operation speed preservation as the criteria, we demonstrate how this methodology can be used to select the best design choice among several plausible combinations of routing algorithms and implementations. Also, we show how an efficient table-less routing implementation can be used to minimise the impact of variability on manufacturing and operating frequency.

Network-on-Chip technology is gaining wide popularity for the interconnection of an increasing number of processor cores on the same silicon die. However, growing process variations cause interconnect malfunction or prevent the network from working at the intended frequency, directly impacting yield and manufacturing cost. Topology agnostic routing algorithms have the potential to tolerate process variations without degrading performance. We propose a three step methodology for evaluating routing algorithms in their ability to deal with variability. Using yield enhancement and operation speed preservation as the criteria, we demonstrate how this methodology can be used to select the best design choice among several plausible combinations of routing algorithms and implementations. Also, we show how an efficient table-less routing implementation can be used to minimise the impact of variability on manufacturing and operating frequency.

Multi-core SoCs have been widely studied as the need for high speed computing increases. Networks-on-chip (NoCs) have been proposed as a viable solution to solving the communication problem in multicore systems. In this paradigm, mapping applications on various available resources leads to an extensive interaction and communication network. Therefore, a rigorous traffic analysis of the network becomes important so as to come up with an optimal network topology and mapping algorithms, apart from efficient resource management. Many of the traffic characteristics like self-similarity (fractal nature) and non-stationarity are not captured by the traditional Poisson and Queuing based approaches, and hence a new model that encompasses time and space dependent traffic behavior.

In a previous work we have introduced a multifractal traffic model based on so-called stochastic L-Systems, which were introduced by biologist A. Lindenmayer as a method to model plant growth. L-Systems are string rewriting techniques, characterized by an alphabet, an axiom (initial string) and a set of production rules. In this paper, we propose a novel traffic model, and an associated parameter fitting procedure, which describes jointly the packet arrival and the packet size processes. The packet arrival process is modeled through a L-System, where the alphabet elements are packet arrival rates. The packet size process is modeled through a set of discrete distributions (of packet sizes), one for each arrival rate. In this way the model is able to capture correlations between arrivals and sizes. We applied the model to measured traffic data: the well-known pOct Bellcore, a trace of aggregate WAN traffic and two traces of specific applications (Kazaa and Operation Flashing Point). We assess the multifractality of these traces using Linear Multiscale Diagrams. The suitability of the traffic model is evaluated by comparing the empirical and fitted probability mass and autocovariance functions; we also compare the packet loss ratio and average packet delay obtained with the measured traces and with traces generated from the fitted model. Our results show that our L-System based traffic model can achieve very good fitting performance in terms of first and second order statistics and queuing behavior.

Networks-on-chip (NoCs) have been proposed as a viable solution to solving the communication problem in multicore systems. In this new setup, mapping multiple applications on available computational resources leads to interaction and contention at various network resources. Consequently, taking into account the traffic characteristics becomes of crucial importance for performance analysis and optimization of the communication infrastructure, as well as proper resource management. Although queuing-based approaches have been traditionally used for performance analysis purposes, they cannot properly account for many of the traffic characteristics (e.g., non-stationarity, self-similarity) that are crucial for multicore platform design. To overcome these limitations, we propose a statistical physics inspired approach to capture the traffic dynamics in multicore systems. As shown later in this paper, this is of fundamental significance for re-thinking the very basis of multicore systems design; it also opens up new research directions into NoC optimization which require accurate models of time-dependent and space-dependent traffic behavior.

This paper identifies non-stationary effects in grid like Network-on-Chip (NoC) traffic and proposes QuaLe, a novel statistical physics-inspired model, that can account for non-stationarity observed in packet arrival processes. Using a wide set of real application traces, we demonstrate the need for a multi-fractal approach and analyze various packet arrival properties accordingly. As a case study, we show the benefits of our multifractal approach in estimating the probability of missing deadlines in packet scheduling for chip multiprocessors (CMPs).