Low Power Cmos Circuits

A method is presented in this paper for the design of a high frequency CMOS operational amplifier (Op-Amp) which operates at 3V power supply using tsmc 0.18 micron CMOS technology. The OPAMP designed is a two-stage CMOS OPAMP followed by an output buffer. This Operational Transconductance Amplifier (OTA) employs a Miller capacitor and is compensated with a current buffer compensation technique. The unique behaviour of the MOS transistors in saturation region not only allows a designer to work at a low voltage, but also at a high frequency. Designing of two-stage op-amps is a multi-dimensional-optimization problem where optimization of one or more parameters may easily result into degradation of others. The OPAMP is designed to exhibit a unity gain frequency of 2.02GHz and exhibits a gain of 49.02dB with a 60.5 0 phase margin. As compared to the conventional approach, the proposed compensation method results in a higher unity gain frequency under the same load condition. Design has been carried out in Tanner tools. Simulation results are verified using S-edit and W-edit.

In many applications there is a growing demand for the development of low voltage and low power
circuits and systems. Low power consumption is of great interest because it increases the battery
lifetime. One of the main building blocks in many applications is the analogue-to-digital converter
(ADC) which serves as an interface between the analogue world and the digital processing unit. In all
these designs the comparator of the ADC, which is one the most power hungry blocks, is always on.
In order to reduce the power consumption of the ADC it is possible to turn the comparator off when
the decision is made and the comparator is not needed until the next clock cycle.
Especially, this work focuses on the reduction of the power dissipation, which is showing an everincreasing
growth with the scaling down of the technologies. Various techniques at the different
levels of the design process have been implemented to reduce the power dissipation at the circuit,
architectural and system level. Conventional Dynamic Comparator are designed and then compared
with the stack Dynamic Comparator using 180nm technology on workstation installed with Mentor
Graphics and pyxis software.

A method is presented in this paper for the design of a high frequency CMOS operational amplifier (Op-Amp) which operates at 3V power supply using tsmc 0.18 micron CMOS technology. The OPAMP designed is a two-stage CMOS OPAMP followed by an output buffer. This Operational Transconductance Amplifier (OTA) employs a Miller capacitor and is compensated with a current buffer compensation technique. The unique behaviour of the MOS transistors in saturation region not only allows a designer to work at a low voltage, but also at a high frequency. Designing of two-stage op-amps is a multi-dimensional-optimization problem where optimization of one or more parameters may easily result into degradation of others. The OPAMP is designed to exhibit a unity gain frequency of 2.02GHz and exhibits a gain of 49.02dB with a 60.5 0 phase margin. As compared to the conventional approach, the proposed compensation method results in a higher unity gain frequency under the same load condition. Design has b...

In today’s VLSI field the exponentially increasing factor of integration takes the techniques of chip designing to be more cared about both switch level (eg. device, logic gate design, etc.) and chip level (eg. pad design, floorplanning, routing, etc.) as size of chip is continually decreasing and power consumption challenge is getting tougher. To design a complete & successful functional chip, pad frame design and floorplanning are also challenging. This study is an attempt to present a VLSI design of pad frame with less power consuming I/O architecture with an efficient way of floorplanning which includes block placement, global routing, detail routing. MAGIC is used as layout designing CAD tool to design the pad frame as it is the easiest and worldwide CAD tool for VLSI layout design, and for simulation purpose PSpice is used. This study presents details of the key research work, results, techniques and efficient way of pad frame design as well as floorplanning.

Two novel low power flip-flops are presented in the paper. Proposed flip-flops use new gating techniques that reduce power dissipation deactivating the clock signal. Presented circuits overcome the clock duty-cycle limitation of previously reported gated flip-flops.

In present work a new XNOR gate using three transistors has been presented, which shows power dissipation of 550.7272µW in 0.35µm technology with supply voltage of 3.3V. Minimum level for high output of 2.05V and maximum level for low output of 0.084V have been obtained. A single bit full adder using eight transistors has been designed using proposed XNOR cell, which shows power dissipation of 581.542µW. Minimum level for high output of 1.97V and maximum level for low output of 0.24V is obtained for sum output signal. For carry signal maximum level for low output of 0.32V and minimum level for high output of 3.2V have been achieved. Simulations have been performed by using SPICE based on TSMC 0.35µm CMOS technology. Power consumption of proposed XNOR gate and full adder has been compared with earlier reported circuits and proposed circuit's shows better performance in terms of power consumption and transistor count.

Page 1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.4, December 2011 DOI : 10.5121/vlsic.2011.2405 47 Single bit full adder design using 8 transistors with novel 3 transistors XNOR gate ...

Objective: To compare and analyse different FinFET full adder circuits by varying the temperature.
Method/Analysis: A
1-bit full adder is designed using various logic styles and the performance of these adders are compared over a range of
temperature values. 32nm FinFET Predictive Technology Model (PTM) is used for designing purpose. Various logic design
styles utilised are Complementary Metal-Oxide Semiconductor (CMOS) logic, Transmission Gate (TG) logic, Complementary
Pass-Transistor (CPTL) logic, Gate Diffusion Input (GDI) logic. Cadence Virtuoso and Spectre are used for designing and
simulation purpose, respectively.
Findings: The performance of these adders are analysed based on key circuit metrics
like static power, dynamic power, leakage power, delay and power delay product (PDP). On comparison, it is evident that
the GDI based adder consumes less leakage power. Also, the propagation delay and power delay product is very less in GDI
adder.
Novelty/Improvements: The simulation results prove that the GDI adder structure outperforms other structures in
sub nanometer technology. This advantage makes GDI technology suitable for realisation of combinational circuits. Future
research in digital circuits can be carried out by using GDI technology for designing low power and compact integrated
circuit design.

Device density in VLSI today enforces the process of chip designing much more complex; whereas MAGIC CAD tools made the IC design in this work, comparatively easier. Study on various amplifiers for sensor applications showed that their powers ranged from a few milliamperes to a few hundred milliamperes at the submicron fabrication processes by MOSIS, but within the affordable cost. Objectives of lowering the power at least by 1000 times in those fabrication processes engaged this research towards completing a new design, called the mirror-amplifier. This design is verified for precise functional behavior for the sensor and total power consumption, using MAGIC extractor and PSPICE electrical simulation tools. A compact model chip layout made silicon area more efficient for MOSIS tiny-chip fabrication in 0.6µm processes. To make even more economical, a multi-die placement technique was applied to the chip layout for this tiny-chip in silicon area of 1500µmX1500µm. MOSIS design rules for multi-die fabrication was verified for process scribe-lines and die packaging. This paper presents details of the key research works, results, completed chip layout and packaging of the chip.

This paper puts forward different low power adder cells using different XOR gate architectures. Adder plays an important role in arithmetic operation such as addition, subtraction, multiplication, division etc. The optimization and characterization of such low power adder designs will aid in comparison and choice of adder modules in system design. A comparative analysis is performed for the power, delay, and power delay product (PDP) optimization characteristic& deals with the design of five adder cells using transistors and schematic structure using CADENCE tool. 10 transistor adder circuits shows the least power consumption with others. Simulations are performed by using Cadence Design tools using 45nm CMOS technology. The four adder cell module proposed here demonstrates their advantages in comparison with Static Energy Recovery Full (SERF), including lower power consumption, smaller area, and higher speed at different frequencies. Keywords Low power, Static Energy Recovery Full Adder (SERF), 45 nm technology, power delay product (PDP).

Original scientific paper Radio frequency identification (RFID) is one of the most rapidly growing technologies to be utilized in almost every sector for storing and retrieving data wirelessly. Current advancements in CMOS technology help the scientists and technologists to reduce the size and improve the functionalities of the RFID circuits. In this paper, the design of an RF-CMOS power splitter circuit in 0,18 µm Silterra RF-CMOS technology is illustrated for a 2,45 GHz RFID reader. Wilkinson power divider is chosen for the proposed power splitter circuit with on-chip inductors and capacitors. The proposed power splitter achieves a maximum insertion loss of 10 dB. AWR Microwave Office® is used for the simulation of the circuit and for determination of its S-parameters. To design the inductors with accurate values in 2,45 GHz Sonnet® is used whereas Cadence® is used for capacitor and resistor layout.

In this paper, a compact branch-line coupler (BLC) for 60 GHz frequency band applications by using CMOS technology is presented. By use of meandered thin-film microstrip (TFMS) transmission line, miniaturized BLC can be obtained. To further decreasing of BLC dimension, capacitive loading technique (CLT) is used. It is shown that these two techniques results in 0.063 mm 2 occupied area, which is leading to a suitable structure for low cost and compact MMIC technology. The design procedure has advantage of the multilevel metallization processes offered in CMOS technology. The analysis is based on a full-wave commercial electromagnetic (EM) package, ADS Momentum. The simulation results provide wideband characteristics impedance over 57-64 GHz frequency band, as well as good transmission loss and isolation between ports.

— In this work, measurements of the two versions of the 12 nA Low Frequency Oscillator is presented. The circuit designed in a standard 0.6 µm MOS technology with most of the transistors operating in weak inversion, includes self-bias current and voltage references, and can be powered with a wide range supply voltage from 1.2 to 5.0 V. The oscillator is intended as part of the next generation of portable or autonomous devices, powered by microbatteries or energy harvesting systems.

Analog-to-digital converters (ADCs) are key design blocks and are currently adopted in many application fields to improve digital systems, which achieve superior performances with respect to analog solutions. Application such as wireless communication and digital audio and video have created the need for cost-effective data converters that will achieve higher speed and resolution. Widespread usage confers great importance to the design activities, which nowadays largely contributes to the production cost in integrated circuit devices (ICs). Various examples of ADC applications can be found in data acquisition systems, measurement systems and digital communication systems also imaging, instrumentation systems. Since the ADC has a continuous, infinite –valued signal as its input, the important analog points on the transfer curve x-axis for an ADC are the ones that corresponding to changes in the digital output word. These input transitions determine the amount of INL and DNL associated with the converter. Hence, we have to considered all the parameters and improving the associated performance may significantly reduce the industrial cost of an ADC manufacturing process and improved the resolution and design specially power consumption. The paper presents a design of 4 bit Pipeline ADC with low power dissipation implemented in <0.18µm.

Level shifter (LS) circuits are widely used as an interface for multiple voltage domains in modern ICs and System on Chips (SoCs). Low power dissipation is one of the main design considerations for high performance level shifters. This paper presents the design and performance of a low power dissipation and low input voltage range level shifter in CEDEC 0.18-µm CMOS process. Simulation results shows that the level shifter is able to perform voltage level shifting from low voltage level of 0.4 -0.7 V into high voltage level of 3 V. The obtained power dissipation is only 1.49 nW for 0.4 V and 1-kHz input pulse. This level shifter fulfills the needs of lower power systems and will be very useful for ICs and SoCs.

With the evolution of the semiconductor industry and the continuous growing demands for high performance VLSI circuit, the aggressive scaling in feature size and high integration density along with the high operating frequencies make power consumption and digital noise in modern analog and digital
devices one of the top concerns of Very Large Scale Integration (VLSI) circuit design. In this paper we delve into the design of n-fold flip-flops with output enable. A new n-fold flip-flop exploiting the clock gating technique for both outputs enabling and power saving is presented. To evaluate its performance, an
octal flip-flop was built according to the new proposed structure and compared to the main octal flip-flops used today. The different flip-flops were implemented in STMicroelectronics 65 nm process technology and simulated for the worst case condition where the switching activity is maximal. Post layout simulation showed that the new circuit provides the same functional performances as conventional solutions with
significantly less power consumption, area and digital noise.

Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. Apart from the basic addition adders also used in performing useful operations such as subtraction, multiplication, division, address calculation, etc. In most of these systems the adder lies in the critical path that determines the overall performance of the system. In this paper conventional complementary metal oxide semiconductor (CMOS) and adiabatic adder circuits are analyzed in terms of power and transistor count using 0.18UM technology.

This paper represents fixed body biased CMOS Tapered Buffer which is designed to minimize the PDP (Power Delay Product) of the circuit. CMOS Tapered Buffers are often used for driving large capacitive load at high speed. Since there are tradeoffs between performance parameters of Buffer for minimizing its PDP value and due to technology constraints on the threshold voltage of MOS; one can vary the Vth up to certain limit while keeping the VDD constant. The proposed work is helpful in designing power efficient CMOS Tapered Buffer. This is found that in proposed Buffer when Vth value for the first stage of inverter is taken between the range of (0.2VDD - 0.4 VDD), its performance gets improved in terms of power dissipation. This analysis is verified by simulating the 2-stage Tapered buffer using standard 180nm CMOS technology in Cadence environment. Analysis performed on the schematic shows that FBB (Fixed Body Bias) Tapered Buffer reduces the average power dissipation across capacitive load by 77 % and static power has been reduced to 18.3% at very less penalty in delay. Hence the proposed approach is suitable in the design of low power buffer for increasing the current capability of logic gate at optimal speed.