Logic Gate

The design of scalable and reliable interconnection net-works for System on Chips (SoCs) introduce new design constraints not present in current multicomputer systems. Although regular topologies are preferred for building NoCs, heterogeneous blocks, fabrication faults and reliabil-ity ...

In this paper, we develop a semianalytical model that predicts the geometric component in charge-pumping (CP) measurements for local oxidation of silicon (LOCOS) and lightly doped drain (LDD) transistors. It is not only based on thermal diffusion, drift field, and self-induced drift field but also on the contribution of the active CP area and the low-level voltage (V L) of the gate signal. By adding this model to constant-amplitude CP components, such as LOCOS, LDD, and effective channel regions, we will be able to compute I CP-V L characteristics of LDD-MOSFET devices with LOCOS structure. In addition, we compare the geometric component model against numerous experimental data obtained from transistors of different gate lengths and widths. The calculated I CP-V L characteristics with geometric component model are found in good correlation with the experimental I CP-V L data and are more accurate than the calculated CP without the geometric component. This modeling approach can be extended for MOSFET stress reliability evaluation such as negative bias temperature instability and radiation degradations. Index Terms-Active CP area, constant-amplitude charge pumping (CP), geometric component, LDD-MOSFET, LOCOS. I. INTRODUCTION N OWDAYS, charge-pumping (CP) technique is extensively used in modern MOSFET device reliability issues such as radiation [1]-[4], hot carrier [5], [6], and bias temperature instability (BTI) [7], [8]. More recently, some authors have proposed different CP-based methods [9]-[12], like oxide-trap CP (OTCP) for radiation-induced trap extraction [9], [10] and on-the-fly CP (OFIT) [11] and [12] to probe and understand BTI degradation. However, the accuracy of the standard CP measurements is affected by lightly doped drain (LDD) and field oxide regions and geometric component.

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The aim of this paper is to research the impact of physical parameters which characterize the MOSFET transistors structure on the threshold voltage values and its influence on critical voltage values which characterize digital circuits that contain the MOSFET transistors. The results obtained emphasize the impact of each single physical parameter on the total value of the threshold voltage. By adjusting the values of MOSFET physical parameters the accepted threshold voltage can be achieved. Since the threshold voltage will have influence on critical voltage values which characterise MOS inverters and delay times during transfer logic states between stages, it must be taken into consideration during design phase of logic gates that contain the MOSFET transistors.

This work is concerned with Carbon Nanotube diameter variations and the resulting uncertainties on the behavior of logic gates made from Single Walled Carbon Nanotubes (SWCNTs). Monte Carlo simulations were performed for the logic gates based on CNTs of different mean diameters using the Stanford CNFET model, developed in HSPICE. Delay characteristics of basic logic gates (NOT, NAND and NOR) are studied. This work reveals that logic gates employing SWCNTs with mean diameters greater than about 1.2 nm, show less variation in their timing characteristics, provided that a CNT diameter standard deviation of less than 0.1nm can be guaranteed by a technology process.

In this paper, we focus on broadband wireless mesh networks like 3GPP LTE-Advanced. This technology is a key enabler for next generation cellular networks which are about to increase by an order of magnitude the capacity provided to users. Such an objective needs a significative densification of cells which requires an efficient backhauling infrastructure. In many urban areas as well as under-developed countries, wireless mesh networking is the only available solution. Besides, economical and environmental concerns require that the energy expenditure of such infrastructure is optimized.

Degradation of p-channel poly-Si thin-film transistors under dynamic negative bias temperature (NBT) stress has been studied. A two-stage degradation behavior is observed under the dynamic NBT stress. Device threshold voltage (V th ) shifts toward positive values in the first stage to more negative values in the second stage. The capacitance-voltage characteristic indicates a negative-charge generation in the gate oxide during the dynamic NBT stress, which is responsible for the positive V th shift, while the well-known dc NBT instability effect causes the negative V th shift. The dynamic effect is more significant under dynamic NBT stress with shorter pulse falling time and/or higher pulse amplitude. A degradation mechanism is proposed to explain the negative-charge generation under the dynamic NBT stress.

This paper presents the design and implementation of a Mobile Trusted Module (MTM) which should satisfy small area and low-power condition. Unlike the general Trusted Platform Module (TPM) for PCs, the MTM, that is to be employed in mobile devices, has very stringent limitations with respect to available power, circuit area and so on. Therefore, a MTM needs the spatially-optimized architecture and design method. We introduce the requirements for a MTM design and then implement a compact and power efficient MTM chip based-on the introduced requirements. The designed MTM can support all the necessary functions for trusted mobile platforms. The MTM chip covers 400K logic gates and consumes at most 10mA. 1

Gate-first (GF) high-k metal gate (HKMG) for LSTP/LOP logic and DRAM periphery applications requires an efficient and low-cost effective work function (eWF) solution. We demonstrated TiAlN for pFET eWF tuning without appreciable EOT, Jg, and interface degradation. Hence TiAlN is shown to be a key enabler to realize process-friendly and cost-effective GF HKMG implementation.

Design of power-efficient and highspeed data path logic systems are one of the most substantial areas of research in VLSI system design. In digital adders, the speed of addition is limited by the time required to propagate a carry through the adder. The sum for each bit position in an elementary adder is generated sequentially only after the previous bit position has been summed and a carry propagated into the next position. The CSLA is used in many computational systems to alleviate the problem of carry propagation delay by independently generating multiple carries and then select a carry to generate the sum. However, the CSLA is not area efficient because it uses multiple pairs of Ripple Carry Adders (RCA) to generate partial sum and carry by considering carry input, then the final sum and carry are selected by the multiplexers (mux). The basic idea of this work is to use Binary to Excess-1 Converter (BEC) instead of RCA in the regular CSLA to achieve high speed and low power consumption.

This paper presents FROSTY, a computer program for automatically extracting the high-level structural representation of a large-scale digital CMOS circuit from its transistor-level netlist and a library of subcircuit descriptions. To handle the complexity and diversity of industrial circuits, FROSTY combines traditional structural recognition and pattern matching methods into a two-step extraction process. First, logic structures based on channel-connected-components are recognized from a circuit netlist and from all library subcircuits, and are condensed into ''macro devices'' or called logic gates. This leads to hybrid netlists that contain the recognized logic gates and remaining transistors. Then annotated graphs representing the connectivity and properties of logic gates and remaining transistors are constructed. Compared to transistor-level netlists, these hybrid graphs are much smaller in size, more distinguishable in structure, and are thus more suitable for labeling-based pattern matching. An efficient pattern matching algorithm is then applied to extract the high-level structural representation from these condensed circuit graphs. FROSTY has demonstrated to be orders of magnitude faster than the pattern matching-based extraction program SubGemini, and can extract entire industrial designs with several hundreds of

In mobile ad hoc networks (MANET), routing protocol plays the most important role. For more than one decade, Ad hoc On-demand Distance Vector (AODV) routing protocol becomes attention and research focus on MANET widely. A lot of protocols proposed to improve and optimize AODV performance. Yet, many of those do not consider the needs of node accessing Internet via infrastructure network. In this paper, we proposed a new variant of routing protocol AODV by combining two protocols, R-AODV [9] and AODV+ [10], we called it R-AODV+, so it will be able to be implemented in hybrid ad hoc networks. The reason of proposed R-AODV+ protocol to be achieved is the best performance and reliable. Nodes that attain a connection to the Internet will be able to have access with a gateway node support. In this work, we performed a simulation using NS-2 and measured the performance of the proposed protocol by measuring the routing overhead, end-to-end delay and packet delivery ratio. The result of the simulation shows that our proposed protocol outperformed AODV+.

This paper presents a concurrent error detection(CED) technique for a bit-slice of a full-adder. The proposed method involves computing the sum and carry bits in two alternative ways so that transient faults will be detected by comparing the results (Sum and Carry out) obtained from the two computing paths. This technique attempts to reduce the amount of extra hardware and cost of the circuit. In order to avoid the problem of extra time we will propagate the result when the first computation is finished so that dependent computation can commence execution as soon as possible. To prove the efficiency of the proposed method, the circuit is simulated in standard CMOS 32nm technology and some transient faults are voluntary injected in the Layout of the circuit. The proposed design involves 12.12% saving in transistor count compared to DMR (Dual Modular Redundancy) style design.

An analytical threshold-voltage model of short-channel undoped symmetrical double-gate metal-oxide-semiconductor field-effect transistors including positive or negative interface charges near the drain is presented. The threshold-voltage model is derived based on an analytical solution for the potential distribution along the channel in the subthreshold region. Both potential and threshold-voltage models are compared with the Atlas simulation results, with variables being the device dimensions, the interface-charge region length and the interface-charge density. A good agreement between the model and simulation results has been observed by calibrating as a constant parameter the gate voltage included in the position of the minimum potential and the carrier charge-sheet density at the potential minimum that is adequate to achieve the turn-on condition.

FPGA based Fault injection and Fault tolerance techniques are used to evaluate and validate the reliability of VLSI circuits. This approach combines the efficiency of hardware based techniques and the flexibility of simulation based techniques. The system efficiency and robustness increases as the reconfiguration of FPGA is not needed for each fault experiment. Fault injection is performed using commercial VHDL simulation tools such as static and dynamic methods. Instrumented 2 bit multiplier circuits were employed to evaluate the fault injection technique. The power analysis results provided for fault free, stuck-at-0 and stuck-at-1 faults in digital circuits validate the point that faulty circuits dissipate more and hence draw more power.

Quantum logic gates provide fundamental examples of conditional quantum dynamics. They could form the building blocks of general quantum information processing systems which have recently been shown to have many interesting non-classical properties. We describe a simple quantum logic gate, the quantum controlled-NOT, and analyse some of its applications. We discuss two possible physical realisations of the gate; one based on Ramsey atomic interferometry and the other on the selective driving of optical resonances of two subsystems undergoing a dipole-dipole interaction.

Emerging semiconductor VLSI requires improved device density on a single chip solution that many parameters are becoming vital concern for cost reduction by lowering the chip area, lowering power dissipation, reducing operating voltage, increasing speed etc. A previously designed precision sensor application mirror-amplifier was considered for optimizing in chip area consumption and improves sensing to make it ultra-precise, also this work has reduced the IC to a subcompact die sizes. MAGIC is used as two-dimensional CAD layout tool. Also PSPICE is used for electrical simulation purposes employed by extraction tool. Feature size is taken from mSCN3M_SUBM.30 process for 0.6µm layout and 0.5µm enhanced fabrication process. The improved design has area of 101λX48λ (minimized from 126λX59λ) or 30.3µmX15µm (minimized from 37.8µmX17.7µm) in 0.6µm CMOS design process. For multi-die placement, two sets of chip are designed those are placed on the four sub-dies in a single MOSIS tinychip die. For one set of chip coincidence detector is designed to make the mirror-amplifier ultra precise, buffer stage is designed for another set of chip to drive large load. This paper presents details of the key research works, results, completed chip layout and packaging of the chip.

Abstmct-At low temperatures, a mean free path of electrons in semiconductors may exceed device dimensions. Current-voltage characteristics, potentials, electrical field, and carrier distributions are calculated for a two-terminal device under such conditions when the electron transport is ballistic. Current-voltage characteristics of a "ballistic" FET are analyzed using an approach similar to the Shockley model. It is shown that very high drift velocities can be obtained at low voltages leading to high speed and low power consumption in possible applications in logic circuits. For example, GaAs logic devices with characteristic dimensions about a micrometer or less at 77 K will be comparable with or better than Josephson tunneling logic gates.

The Sagnac all-optical fiber logic gate functions as a two-input AND gate, a two-input AND gate with one inverting input, or both. The fiber logic gate is pipelined and has a fixed latency. This latency has no effect on feed-forward combinatoric circuits. The latency can be used to time multiplex circuits or to time multiplex gates to emulate a circuit. Possible applications such as a bit-jitter-tolerant communications system, an asynchronous communications system, a bit-interleaved self-routing switching system, an exchange/bypass permutation unit, and a folded universal state machine are discussed.

Analysis and design of on-chip power grids are complex problems. A typical grid consists of hundreds of millions of transistors that act as current consumers. Typical algorithms for power grid analysis or power grid automatic design, model the current consumers, namely the CMOS logic gates, as ideal current sources. In this study we offer a new methodology for modeling the power-consuming gates on the grid. Our approach is based on the analysis of the total dissipated power by these consumers. We propose a new model for the current consumers, based on effective impedance. In this model, only passive elements are employed. It relies on a calculation of the effective capacitance and effective resistance of the logic gates. Since during each clock period the dissipated power and the stored energy are exactly represented, total energy and power are exactly modeled. Methods from statistical/computational physics can be adopted to represent clusters of consumers on each subgrid as "macro-circuits". The interaction between the power grid and the current consumers is taken into account in this model and an example for it is presented.

Logic functions implemented using CMOS transmission gates provide a moderate improvement in area and speed over logic gate implementations. Several techniques for the implementation of pass transistor logic are presented. These techniques use only nMOS transistors in the ...

We propose a semiempirical graphene field effect transistor (G-FET) model for analysis and design of G-FET based circuits. The model describes the current-voltage characteristic for a G-FET over a wide range of operating conditions. The gate bias dependence of the output power spectrum is studied and compared with simulated values. A good agreement between the simulated and the experimental power spectrum up to the 3rd harmonic is demonstrated which confirms the model validity. Moreover, S-parameter measurements essentially coincide with the results obtained from the simulation. The model contains a small set of fitting parameters which can straightforwardly be extracted from S-parameters and DC measurements. The developed extraction method gives a more accurate estimation of the drain and source contact resistances compared to other approaches. As a design example, we use a harmonic-balance load-pull approach to extract optimum embedding impedances for a subharmonic G-FET mixer.

We propose a novel multi-stream framework for continuous conversational speech recognition which employs bidirectional Long Short-Term Memory (BLSTM) networks for phoneme prediction. The BLSTM architecture allows recurrent neural nets to model longrange context, which led to improved ASR performance when combined with conventional triphone modeling in a Tandem system. In this paper, we extend the principle of joint BLSTM and triphone modeling to a multi-stream system which uses MFCC features and BLSTM predictions as observations originating from two independent data streams. Using the COSINE database, we show that this technique prevails over a recently proposed single-stream Tandem system as well as over a conventional HMM recognizer.

We discuss our recent efforts to develop high performance carbon nanotube field effect transistors (CNTFETs) and logic circuits. By improving the metal nanotube contacts the characteristics of the CNTFETs are greatly enhanced. Analysis shows that the performance of p-type CNTFETs is already competitive to that of silicon p-MOSFETs. In addition to the p-CNTFETs, we present techniques by which ambipolar and pure n-type CNTFETs can be fabricated. A particulary simple process involving the annealing in vacuum of a p-CNTFET is shown to convert it to an n-CNTFET. This conversion is reversible, and re-exposure to oxygen leads to a p-CNTFET. Evidence is found that the key effect of oxygen involves modification of the contact barriers. Having complementary CNTFETs (i.e. p-and ntype) allows us to build the first integrated circuits. We present results on a NOT logic gate. Both an inter-molecular gate involving two separate CNTFETs, and an intra-molecular gate where the logic function is encoded along the length of a single tube are demonstrated. r

In sensor network applications, data gathering mechanisms, which are based on multi-hop forwarding, can be expensive in terms of energy. This limitation challenges the use of sensor networks for applications that demand a predefined operational-lifetime. To avoid this problem, using of mobile element (ME) as a mechanical data carrier has emerged as a promising approach. However, practical considerations such as the ME speed and route planning, sensor buffer size and data frequency generation constraints impose limits ...

In this paper we report the monolithic integration of two single grain silicon layers for SRAM and image sensor applications. A 12 × 28 silicon lateral photodiode array with a 25_µm pixel size prepared on top of a three transistor readout circuit with individual outputs for every pixel is demonstrated. 6T SRAM cells with two layers of stacked transistors were prepared to compare the performance and area of each cell in different configurations.

An ultra low voltage rail-to-rail DTMOS voltage follower is presented. The circuit is developed based on a complementary source follower with a commonsource output stage. The circuit is designed using a 0.13 μm CMOS technology and SPICE is used to verify the circuit performance. The voltage follower can drive ± 0.25 V to the 500 Ω with the total harmonic distortion (THD) of 0.4% at the operating frequency of 1 MHz. The bandwidth and power dissipation are 288 MHz and 103 μW, respectively.

Carry Look-Ahead Adder (CLA) is considered as one of the most widely used adder topologies which are used in high performance computing systems. In this research, an improved version of 4-bit CLA adder has been proposed. Performance improvement of 4-bit CLA adder has been made by using hybrid AND and XOR gates in the input side for generating carry propagate and carry generate terms. The CLA circuits are kept exactly the same as the conventional one. Performance of the proposed modified 4-bit CLA adder has been evaluated and compared with the conventional design using Cadence tools in 90 nm technology node. Performance has been evaluated and compared in terms of average power, propagation delay and power delay product. The proposed modified design exhibited significant improvement in performance while compared with the conventional one. Enhancement done by the proposed 4-bit CLA adder design in average power, propagation delay and PDP were 14.96%, 11.76% and 25.32% respectively. In ...

We present a monitoring system for the field test of photovoltaic modules. The system is designed for the monitoring of individual modules under maximum power point (MPP) conditions that allow the extraction of the energy yield of different modules under optimum conditions. It can also be used to monitor the performance and long-term stability of modules under realistic field conditions. The monitoring system consists of an individual MPP tracker attached to each module under test. The measurement data are transmitted to a central multichannel data logger by means of analog voltages proportional to the current at MPP, i.e., I m p , and voltage at MPP, i.e., V m p , of the modules.

Abstract—Leakage current in a metal-oxide–semiconductor (MOS) transistor can be a significant contributor to heat dissi-pation, resulting in higher power consumption. Leakage current can also be the cause of failure by some mechanisms such as latch-up or breakdown. In ...

Our strategy for automatic generation of functional vectors is based on exercising selected paths in the given hardware description language (HDL) model. The HDL model describes interconnections of arithmetic, logic, and memory modules. Given a path in the HDL model, the search for input stimuli that exercise the path can be converted into a standard satisfiability (SAT) checking problem by expanding the arithmetic modules into logic gates. However, this approach is not very efficient. We present a new HDL-SAT checking algorithm that works directly on the HDL model. The primary feature of our algorithm is a seamless integration of linear-programming techniques for feasibility checking of arithmetic equations that govern the behavior of data-path modules and SAT checking for logic equations that govern the behavior of control modules. This feature is critically important to efficiency, since it avoids module expansion and allows us to work with logic and arithmetic equations whose cardinality tracks the size of the HDL model. We describe the details of the HDL-SAT checking algorithm in this paper. Experimental results that show significant speedups over state-of-the-art gate-level SAT checking methods are included.

Recent trends in CMOS technology and scaling of devices clearly indicate that leakage power in digital circuits would be crucial and largely depend on the sub-threshold currents. Minimizing leakage, by power gating logic circuits using sleep transistors gives considerable power savings. However, this technique cannot be used in sequential circuits and memory cells, as it would result in loss of

Transistor mismatch data and analysis from poly/ SiON and high-k/metal-gate (HKMG) bulk CMOS technologies are presented. It is found that the traditional mismatch figure of merit from the Pelgrom plot (A VT ) continuously scales down as technology advances. Furthermore, the A VT values for both nFET and pFET in the HKMG technology are significantly reduced from poly/SiON technologies. By normalizing the mismatch data against electrical oxide thickness (T INV ), threshold voltage (V TH ), and effective work function, a direct comparison of the mismatch data from various technologies is made. The differences in nFET and pFET mismatch behaviors in both poly/SiON and HKMG technologies are discussed in detail. Correlation between transistor V TH mismatch and flicker noise variation is observed in both poly/SiON and HKMG technologies. Finally, it is quantitatively demonstrated that effective work function variation does not generate significant V TH variability in the present HKMG technology. Index Terms-Bulk CMOS technology, effective work function, flicker noise variation, high-k/metal gate (HKMG), Pelgrom mismatch slope (A VT ), poly/SiON, random dopant fluctuation (RDF), Takeuchi normalization method, threshold voltage (V TH ) variability.

The floating-body effect and impact ionization generate excess holes that are amplified by the parasitic bipolar junction transistor (BJT) in silicon-on-insulator lateral doublediffused MOSFETs (SOI-LDMOS) that degrade the transistor performance. In this paper, a novel silicon germanium (SiGe) window LDMOS on SOI (SW-SOI) is reported where the buried oxide under the channel region becomes thinner and a SiGe window has been replaced in order to reduce the hole concentration in the channel and control the BJT effect significantly. The novel features of an SW-SOI are simulated and compared with a conventional LDMOS on SOI (C-SOI). In addition, reduced self-heating effects and higher breakdown voltage have been achieved as compared with the C-SOI. Hence, this paper illustrates the benefits of the high performance SW-SOI device over a conventional one and expands the application of SOI MOSFETs to high temperature.

A novel expandable five-input majority gate for quantum-dot cellular automata and a new full-adder cell are presented. Quantum-dot cellular automata (QCA) is an emerging technology and a possible alternative for semiconductor transistor based technologies. A novel QCA majority-logic gate is proposed. This component is suitable for designing QCA circuits. The gate is simple in structure and powerful in terms of implementing digital functions. By applying these kinds of gates, the hardware requirement for a QCA design can be reduced and circuits can be simpler in level, gate counts and clock phases. In order to verify the functionality of the proposed device, some physical proofs are provided. The proper functionality of the FA is checked by means of computer simulations using QCADesigner tool. Both simulation results and physical relations confirm our claims and its usefulness in designing every digital circuit.

This paper introduces a new algorithm of extracting MFCC for speech recognition. The new algorithm reduces the computation power by 53% compared to the conventional algorithm. Simulation results indicate the new algorithm has a recognition accuracy of 92.93%. There is only a 1.5% reduction in recognition accuracy compared to the conventional MFCC extraction algorithm, which has an accuracy of 94.43%. However, the number of logic gates required to implement the new algorithm is about half of the MFCC algorithm, which makes the new algorithm very efficient for hardware implementation.

A study of the negative and positive bias temperature instability (N/PBTI) reliability of FinFETs with different TiN metal gates deposited by either atomic layer deposition (ALD) or physical vapor deposition (PVD) on HfO 2 dielectrics found that the nonuniformity of the interfacial oxide layer is closely related to reliability characteristics. FinFETs with an ALD TiN gate exhibit better NBTI and PBTI lifetimes than those with a PVD TiN gate. In addition, the dependence of fin width on NBTI reliability appeared to be worse with narrower fins, whereas PBTI reliability improves.