Data Flow Graph

In this paper, a novel algorithm is proposed for assigning supply voltages to serially executing functional units (FUs) in a digital system such that the overall dynamic energy consumption is minimized for a given timing constraint. Novel closed form expressions for optimum supply voltage values are presented. The computation time of the algorithm is O(N) for N FUs in series. An extension of the O(N) algorithm is proposed for optimizing the acyclic data flow graph associated with any given task. Given the number of FUs available for the task, the operations required for the task are scheduled on the FUs. Voltages are then assigned to the FUs on each path of the flow graph using the O(N) algorithm. Energy savings of 10-60% are achieved on DSP filter designs using the proposed high-level optimization methodology over single supply voltage designs.

This paper presents a high-level language for expressing image processing algorithms, and an optimizing compiler that targets FPGAs. The language is called SA-C, and this paper focuses on the language features that 1) support image processing, and 2) enable efficient compilation to FPGAs. It then describes the compilation process, in which SA-C algorithms are translated into non-recursive data flow graphs, which in turn are translated into VHDL. Finally, it presents performance numbers for some wellknown image processing routines, written in SA-C and automatically compiled to an Annapolis Microsystems WildForce board with Xilinx 4036XL FPGAs.

This paper presents a short description of the high level and logic synthesis stages in the digital design automation system DIADES. High level design, namely data path synthesis and control unit synthesis start han a peralkl program-graph, the form of descriplon that includes both the control-flow and the data-flow graph. While the data path is allocated and scheduled, the control unit is designed to be composed of either a microprogrammed units or Finite State Machines. The FSMs are minimized in two dimensions (states and inputs), assigned and realized in logic. Several logic synthesis procedures, respective to various design styles and methodologies, can be used to design combinational pans of state machines, microprogrammed units and data path logic. rurtiicr imvrmarivn can ~e mraineu morn ut-. w. hennern JenKins.

In this study, a cam-crank signal generator developed using Simulink and NXP Model Based Design Toolbox. Developed models compiled and flashed into NXP MPC5744P microcontroller. Generated cam and crank signals were measured using an oscilloscope for verification. Algorithm and Simulink models are describes in detail such that students and researchers can replicate and use in their studies using NXP or different microcontroller targets.

Data-flow is a natural approach to parallelism. However, describing dependencies and control between finegrained data-flow tasks can be complex and present unwanted overheads. TALM (TALM is an Architecture and Language for Multi-threading) introduces a user-defined coarse-grained parallel data-flow model, where programmers identify code blocks, called superinstructions, to be run in parallel and connect them in a data-flow graph. TALM has been implemented as a hybrid Von Neumann/data-flow execution system: the Trebuchet. We have observed that TALM's usefulness largely depends on how programmers specify and connect super-instructions. Thus, we present Couillard, a full compiler that creates, based on an annotated C-program, a data-flow graph and C-code corresponding to each super-instruction. We show that our toolchain allows one to benefit from data-flow execution and explore sophisticated parallel programming techniques, with small effort. To evaluate our system we have executed a set of real applications on a large multi-core machine. Comparison with popular parallel programming methods shows competitive speedups, while providing an easier parallel programing approach.

We describe GGI, a visual system that allows the user to execute an automatically generated data flow graph containing code modules that perform natural language processing tasks. These code modules operate on text documents. GGI has a suite of text visualisation tools that allows the user useful views of the annotation data that is produced by the modules in the executable graph. GGI forms part of the GATE natural language engineering system.

This paper introduces the FlowVR suite, a set of softwares targeted at high perfomrance interactive computing, in particular virtual re-ality applications, to be executed on clusters. The FlowVR middle-ware supports coupling of heterogeneous parallel codes and is com- ...

A large-scale reconfigurable data-path (LSRDP) processor based on single-flux quantum circuits is designed to overcome the issues originating from the CMOS technology. The LSRDP micro-architecture design procedure and its outcome will be presented in this paper.

Customization of processor architectures through Instruction Set Extensions (ISEs) is an effective way to meet the growing performance demands of embedded applications. A high-quality ISE generation approach needs to obtain results close to those achieved by experienced designers, particularly for complex applications that exhibit regularity: expert designers are able to exploit manually such regularity in the data flow graphs to generate high-quality ISEs. In this report, we present ISEGEN, an approach that identifies high-quality ISEs by iterative improvement following the basic principles of the well-known Kernighan-Lin (K-L) min-cut heuristic. Experimental results on a number of MediaBench, EEMBC and cryptographic applications show that our approach matches the quality of the optimal solution obtained by exhaustive search. We also show that our ISEGEN technique is on average ¾¼¢ faster than a genetic formulation that generates equivalent solutions. Furthermore, the ISEs identified by our technique exhibit ¿ ± more speedup than the genetic solution on a large cryptographic application (AES) by effectively exploiting its regular structure.

By incorporating reconfigurable hardware in embedded system architectures it has become easier to satisfy the performance constraints of demanding applications while lowering system cost. In order to evaluate the performance of a candidate architecture, the nodes (tasks) of the data flow graphs that describe an application must be assigned to the computing resources of the architecture: programmable processors and reconfigurable FPGAs, whose run-time reconfiguration capabilities must be exploited. In this paper we present a novel design exploration tool-based on a local search algorithm with global convergence properties-which simultaneously explores choices for computing resources, assignments of nodes to these resources, task schedules on the programmable processors and context definitions for the reconfigurable circuits. The tool finds a solution that minimizes system cost while meeting the performance constraints; more precisely it lets the designer select the quality of the optimization (hence its computing time) and finds accordingly a solution with close-to-minimal cost.

Recently, the Desktop-Grid ADaptive Application in Java (DG-ADAJ) project has been unveiled. Its goal is to provide an environment which facilitates adaptive control of distributed applications written in Java for the Grid or the Desktop Grid. However, in its current state it can be used only in closed environments (e.g. within a single laboratory), as it lacks features that would make it ready for an "open Grid." The aim of this paper is to show how the DG-ADAJ can be augmented by usage of software agents and ontologies to make it more robust.

This paper presents pre-optimization methods for distributed Java applications on Java Virtual Machines (JVMs), which reduce program execution time. On the basis of an analysis the byte code compiled for a program, an extended macro data flow graph is generated. To this graph clustering and scheduling algorithms are applied based on modified DSC heuristics. The algorithms define distribution of clusterized nodes and objects on JVMs, so as to reduce the total execution time of programs. The nodes of the macro data flow graph are distributed to different JVMs as dynamic threads of distributed objects by modification of the program byte code without modifications of Java virtual machines.

Synchronous Data Flow Graphs (SDFGs) are a useful tool for modeling and analyzing embedded data flow applications, both in a single processor and a multiprocessing context or for application mapping on platforms. Throughput analysis of these SDFGs is an important step for verifying throughput requirements of concurrent real-time applications, for instance within design-space exploration activities. Analysis of SDFGs can be hard, since the worst-case complexity of analysis algorithms is often high. This is also true for throughput analysis. In particular, many algorithms involve a conversion to another kind of data flow graph, the size of which can be exponentially larger than the size of the original graph. In this paper, we present a method for throughput analysis of SDFGs, based on explicit state-space exploration and we show that the method, despite its worst-case complexity, works well in practice, while existing methods often fail. We demonstrate this by comparing the method with state-ofthe-art cycle mean computation algorithms. Moreover, since the state-space exploration method is essentially the same as simulation of the graph, the results of this paper can be easily obtained as a byproduct in existing simulation tools.

Customization of processor architectures through Instruction Set Extensions (ISEs) is an effective way to meet the growing performance demands of embedded applications. A high-quality ISE generation approach needs to obtain results close to those achieved by experienced designers, particularly for complex applications that exhibit regularity: expert designers are able to exploit manually such regularity in the data flow graphs to generate high-quality ISEs. In this paper, we present ISEGEN, an approach that identifies high-quality ISEs by iterative improvement following the basic principles of the well-known Kernighan-Lin (K-L) min-cut heuristic. Experimental results on a number of MediaBench, EEMBC and cryptographic applications show that our approach matches the quality of the optimal solution obtained by exhaustive search. We also show that our ISEGEN technique is on average ¾¼¢ faster than a genetic formulation that generates equivalent solutions. Furthermore, the ISEs identified by our technique exhibit ¿ ± more speedup than the genetic solution on a large cryptographic application (AES) by effectively exploiting its regular structure.

strained problems where early pruning decisions exclude candidates leading to superior solutions. ILP schedulers (i.e. [3][6]) exactly solve scheduling but have difficulties with time complexity and complex control constraint formulation. Symbolic methods (i.e. [2][4][7][8][11]) are often effective in finding exact solutions in highly constrained problem formulations but may suffer from representation explosion. The technique described in this paper falls in the symbolic methods category. The most closely related previous work is found in [2][11] where system timing and synchronization requirements are encapsulated in finite-state machine (FSM) descriptions. Our work differs in two ways. First, we introduce non-determinism as a preferred representation for protocols. The work described in [9] supports this decision. Second, and more importantly, our formulation is hierarchical and amenable to abstraction. We believe hierarchy and abstraction are key components in making symbolic techniques manageable.

Optimization of hardware resources for conditional data-flow graph behavior is particularly important when conditional behavior occurs in cyclic loops and maximization of throughput is desired. In this paper, an exact and efficient conditional resource sharing analysis using a guardbased control representation is presented. The analysis is transparent to a scheduler implementation. The proposed technique systematically handles complex conditional resource sharing for cases when folded (software pipelined) loops include conditional behavior within the loop body.

This paper presents a heuristic scheduling algorithm for heterogeneous specifications, those formed by operations of different types and widths. The algorithm extracts the common operative kernel of the operations, and binds afterwards operations to cycles with the aim of distributing uniformly the number of bits calculated per cycle. In consequence, operations may be fragmented and executed during a set of non-necessarily consecutive cycles, and over a set of several linked simple hardware resources. The proposed algorithm, in combination with allocation algorithms able to guarantee bit-level reuse of hardware resources, obtains considerably smaller datapaths than the ones proposed by conventional synthesis algorithms. In the datapaths produced the type, number, and width of the hardware resources are independent of the type, number, and width of the specification operations and variables.

This paper presents a new algorithm for the stable computation of sample partial correlation coefficients. We start by generalizing Bareiss' algorithm for the solution of linear systems of equations with (non-symmetric) Toeplitz coefficient matrix to matrices that are not Toeplitz, and show that it computes their LU and UL factorizations. For symmetric positive-definite matrices B, the normalized version of Bareiss' algorithm is the Hyperbolic Cholesky algorithm, which computes the upper and lower triangular Cholesky factors U and L of B by means of 2X2 hyperbolic rotations. If B is a covariance matrix, certain partial correlation coefficients may be obtained as the geometric means of the multiplier pairs in Bareiss' algorithm or as the hyperbolic tangents of the hyperbolic rotations. The partial correlation coefficients for a given data matrix A may suffer from serious loss of numerical accuracy when computed from the covariance matrix B = ATA. While the data flow graph of Bareiss' algorithm suggests a method, due to Cybenko, for computing partial correlation coefficients directly from the columns of A, the graph of Hyperbolic Cholesky suggests an alternative that requires fewer operations and exhibits a higher degree of parallelism. In that method one computes the QR decomposition A = QU of the data matrix and applies orthogonal rotations to transform U to L; the sines of the rotation angles constitute a set of partial correlation coefficients. We extend this approach to determine arbitrary partial correlation coefficients at little extra computational cost.

This paper introduces the FlowVR suite, a set of softwares targeted at high perfomrance interactive computing, in particular virtual re-ality applications, to be executed on clusters. The FlowVR middle-ware supports coupling of heterogeneous parallel codes and is com-ponent oriented to favor code reuse. After introducing the FlowVR main concepts, we details the different tools associated and several applications. 1

A new control flow checking scheme, based on assigned-signature checking by a watchdog processor, is presented. This scheme is suitable for a multitasking, multiprocessor environment. The hardware overhead is comparatively low because of three reasons: first, hierarchically structured, the scheme uses only a single watchdog processor to monitor multiple processes or processors. Second, as an assigned-signature scheme it does not require monitoring the instruction bus of the processors. Third, the run-time and reference signatures are embedded into the checked program; thus, in the watchdog processor neither a reference database nor a time-consuming search and compare engine is required.

Data-flow is a natural approach to parallelism. However, describing dependencies and control between finegrained data-flow tasks can be complex and present unwanted overheads. TALM (TALM is an Architecture and Language for Multi-threading) introduces a user-defined coarse-grained parallel data-flow model, where programmers identify code blocks, called superinstructions, to be run in parallel and connect them in a data-flow graph. TALM has been implemented as a hybrid Von Neumann/data-flow execution system: the Trebuchet. We have observed that TALM's usefulness largely depends on how programmers specify and connect super-instructions. Thus, we present Couillard, a full compiler that creates, based on an annotated C-program, a data-flow graph and C-code corresponding to each super-instruction. We show that our toolchain allows one to benefit from data-flow execution and explore sophisticated parallel programming techniques, with small effort. To evaluate our system we have executed a set of real applications on a large multi-core machine. Comparison with popular parallel programming methods shows competitive speedups, while providing an easier parallel programing approach.

We extend the LLVM intermediate representation (IR) to make it a parallel IR (LLVM PIR), which is a necessary step for introducing simple and generic parallel code optimization into LLVM. LLVM is a modular compiler that can be efficiently and easily used for static analysis, static and dynamic compilation, optimization, and code generation. Being increasingly used to address high-performance computing abstractions and hardware, LLVM will benefit from the ability to handle parallel constructs at the IR level. We use SPIRE, an incremental methodology for designing the intermediate representations of compilers that target parallel programming languages, to design LLVM PIR. Languages and libraries based on the Partitioned Global Address Space (PGAS) programming model have emerged in recent years with a focus on addressing the programming challenges for scalable parallel systems. Among these, OpenSHMEM is a library that is the culmination of a standardization effort among many implementers and users of SHMEM; it provides a means to develop lightweight , portable, scalable applications based on the PGAS programming model. As a use case for validating our LLVM PIR proposal, we show how OpenSHMEM one-sided communications can be optimized via our implementation of PIR into the LLVM compiler; we illustrate two important optimizations for such operations using loop tiling and communication vectorization.

Stream processing is a well-suited application pattern for embedded computing. This holds true even more so when it comes to multi-core systems where concurrency plays an important role. With the latest trend towards more dynamic and heterogeneous systems there seems to be a shift from purely synchronous systems towards more asynchronous ones. The downside of this shift is an increase in programming complexity due to the more subtile concurrency issues. Several special purpose streaming languages have been ...

There are few processes which display cyclically changing but predefined behavior. These processes can be represented using cyclo static data flow graphs (CSDFG). This capability results in a higher degree of parallelism. In this paper we present the iteration bound for a CSDFG which is used to find the integral static schedule and determine whether a csdf is live or not based on some calculation. We also present an algorithm that schedules cyclo static data flow graphs without converting to their equivalent homogeneous graphs (EHG's) and demonstrate it with a suitable example.

One of the major differences in partitioning for codesign is in the way the communication cost is evaluated. Generally the size of the edge cut-set is used. When communication between components is through buffered channels, the size of the edge cut-set is not adequate to estimate the buffer size. A second important factor to measure the quality of partitioning is the system delay. Most partitioning approaches use the number of nodes/functions in each partition as constraints and attempt to minimize the communication cost. The data dependencies among nodes/functions, and their delays are not considered. In this paper we present partitioning with two objectives: (1) buffer size, which is estimated by analyzing the data flow patterns of the CDFG, and solved as a clique partitioning problem, and (2) the system delay that is estimated using List Scheduling. We pose the problem as a combinatorial optimization and use an efficient non-deterministic search algorithm called Problem-Space Genetic Algorithm to search for the optimum. Experimental results indicate that, according to a proposed quality metric, our approach can attain an average 87% of the optimum for two-way partitioning.

In this paper, we propose a fault-tolerant scheduling approach that achieves low energy consumption and high reliability efficiency. Our scheduling solution is dedicated to multi-bus heterogeneous architectures, which take as input a given system description and a given fault hypothesis. It is based on active redundancy to mask a fixed number k of failures supported in the system, so that there is no need for detecting and handling such failures. In order to maximize the system's reliability, the replicas of each operation are scheduled on different reliable processors. Our solution can maximize reliability and reduce energy consumption when using active redundancy.

We consider a dynamic application running on a multiprocessor network-on-chip as a set of independent jobs, each job possibly running on multiple processors. To provide guaranteed quality and performance, the scheduling of jobs, jobs themselves and the hardware must be amenable to timing analysis. For a certain class of applications and multiprocessor architectures, we propose exact timing models that effectively co-model both the computation and communication of a job. The models are based on interprocessor communication (IPC) graphs [4]. Our main contribution is a precise model of network-on-chip communication, including buffer models. We use a JPEG-decoder job as an example to demonstrate that our models can be used in practice to derive upper bounds on the job execution time and to reason about optimal buffer sizes.

Multimodal applications require the acquisition and processing of massive amounts of information from multiple sensors. Because this process is beyond the capabilities of a single machine, we developed a sensor network data transport system that can employ the numerous computing devices required to perform the task. The computational and data acquisition processes are thus allocated to components spread across a network of systems. We present the NIST Smart Data Flow System II, which is a middleware layer that represents applications as data flow graphs, and transports information streams between the different computational components of the application.

The Internet of Vehicle (IoV) is an extension of Vehicle-to-Vehicle (V2V) communication that can improve vehicles' fully autonomous driving capabilities. However, these communications are vulnerable to many attacks. Therefore, it is critical to provide run-time mechanisms to detect malware and stop the attackers before they manage to gain a foothold in the system. Anomaly-based detection techniques are convenient and capable of detecting off-nominal behavior by the component caused by zero-day attacks. One significant critical aspect when using anomaly-based techniques is ensuring the correct definition of the observed component's normal behavior. In this paper, we propose using the task's temporal specification as a baseline to define its normal behavior and identify temporal thresholds that give the system the ability to predict malicious tasks. By applying our solution on one use-case, we got temporal thresholds 20-40% less than the one usually used to alarm the system about security violations. Using our boundaries ensures the early detection of off-nominal temporal behavior and provides the system with a sufficient amount of time to initiate recovery actions.

While parallelism and multi-cores are receiving much attention as a major scalability path, customization is another, orthogonal and complementary, scalability path which can target not easily parallelizable programs or program sections. The key assets of customization are cost and power efficiency. The key limitation of customization is flexibility. However, we argue that there is no perfect balance between efficiency and flexibility, each system vendor may want to strike a different such balance. In this article, we present a method for achieving any desired balance between flexibility and efficiency by automatically combining any set of individual customization circuits into a larger compound circuit. This circuit is significantly more cost efficient than the simple union of all target circuits, and is configurable to behave as any of the target circuits, while avoiding the routing and configuration cost overhead of FP-GAs. The more individual circuits are included, the larger the number of applications which can potentially benefit from this compound customization circuit, realizing flexibility at a minimal cost. Moreover, we observe that the compound circuit cost does not increase in proportion to the number of target applications, due to the wide range of common data-flow and control-flow patterns in programs. Currently, the target individual circuits correspond to loops, like most accelerators in embedded systems, but the aggregation method can accommodate circuits of any size. Using the UTDSP benchmarks and accelerators coupled with an embedded PowerPC405 processor, we show that this approach can yield an average performance improvement of 2.97, while the corresponding synthesized aggregate accelerator is 3 time smaller than the sum of individual accelerators for each target benchmark.

A variety of applications have arisen where it is worthwhile to apply code optimizations directly to the machine code (or assembly code) produced by a compiler. These include link-time whole-program analysis and optimization, code compression, binary-to-binary translation, and bit-transition reduction (for power). Many, if not most, optimizations assume the presence of a control-flow graph (cfg). Compiled, scheduled code has properties that can make cfg construction more complex than it is inside a typical compiler. In particular, branch-to-register operations can introduce spurious edges into the cfg. If branch delay slots contain other branches, the classic algorithms for building a cfg produce incorrect results. This paper uses two simple examples to explain the problem. It presents an algorithm for building correct cfgs from scheduled assembly code that includes branches in branch delay slots. The algorithm works by building an approximate cfg and then refining it to reflect the actions of delayed branches. If all branches have explicit targets, the complexity of the refining step is linear with respect to the number of branches in the code.

In this study, parallel computation of blood flow in a 1-D model of human arterial network has been carried out employing a Taylor Galerkin Finite Element Method. Message passing interface libraries have been used on Origin 2000 SGI machine. A Greedy strategy for load-distribution has been devised and data-flow graphs necessary for parallelization have been generated. The performance of parallel implementation measured in terms of speedup and efficiency factors is found to be good. Further, the parallel code is used in simulating the propagation of pressure and velocity waveforms in our 1-D arterial model for two different inflow pressure pulses. Also, the influence of consideration of terminal resistance on pressure and velocity waveforms have been analyzed.

Stream processing is a well-suited model for parallel programming, as it allows the programmer to design parallel algorithms intuitively by arranging computational tasks into a data-flow graph and consecutively constructing a streaming network from it. However, a network that was designed with a specific workload in mind will not work optimally if anticipated parameters, as for example data rates or computational costs per data item, change over time. To nonetheless achieve optimal performance, a restructuring of the network and re-implementation of computational components is inevitable. As the deployment of a revised network usually causes service disruption, we present a system that supports reconfiguration of streaming networks at runtime. The reconfiguration of networks can either be triggered externally, i.e. initiated by the user, or from within the network itself (self-adaptation) by, for example, monitoring certain runtime parameters. Our system is based on S-Net, a coordination language for asynchronous stream processing systems. S-Net supports the simultaneous use of computational components implemented in a range of programming languages and it offers network combinators to construct streaming networks from these components. We will introduce S-Net and extensions of the language that allow for reconfiguration and self-adaptation of networks at runtime. The extensions are designed as network combinators and integrate seamlessly into the existing language.

Ahetract-Computer architects have been constantly looking for new approaches to design high-performance machines. Data flow and VLSI offer two mutually supportive approaches towards a promising design for future super-computers. When very high speed computations are needed, data flow machines may be relied upon as an adequate solution in which extremely parallel processing is achieved. This paper presents a formal analysis for data flow machines. Moreover, the following three machines are considered: (1) MIT static data flow machine; (2) TI's DDP static data flow machine; (3) LAU data flow machine. These machines are investigated by making use of a reference model. The contributions of this paper include: (1) Developing a Data Flow Random Access Machine model (DFRAM), for first time, to serve as a formal modeling tool. Also, by making use of this model one can calculate the time cost of various static data machines, as well as the performance of these machines. (2) Constructing a practical Data Flow Simulator (DFS) on the basis of the DFRAM model. Such DFS is modular and portable and can be implemented with less sophistication. The DFS is used not only to study the performance of the underlying data flow machines but also to verify the DFRAM model.

Most embedded systems rely on batteries as their source of energy, and hence, low power consumption is inherently essential for them. In processor-based embedded systems, a large portion of power is consumed for accessing instruction memories (including ...

The performance of computation intensive digital signal processing applications running on parallel systems is highly dependent on communication delays imposed by the parallel architecture. In order to obtain a more compact task/processor assignment, a scheduling algorithm considering the communication time between processors needs to be investigated. Such applications usually contain iterative or recursive segments that are modeled as communication sensitive data ow graphs (CS-DFGs) where nodes represent computational tasks and edges represent dependencies between them. Based on the theorems derived, this paper presents a novel e cient technique called cyclo-compaction scheduling which is applied to a CS-DFG to obtain a better schedule. This new method takes into account the data transmission time, loop carried dependencies and the target architecture. It implicitly uses the retiming technique (loop pipelining) and a task re-mapping procedure to allocate processors and to iteratively improve the parallelism while handling the underlying communication and resource constraints. Experimental results on di erent architectures demonstrate that this algorithm yields signi cant improvement over existing methods. For some applications, the nal schedule length is less than one half of its initial length.

In this paper, a temporal partitioning algorithm is presented which partitions data flow graphs in a realtime domain. Timing constraint is a critical factor in temporal partitioning of real-time reconfigurable design. An incremental algorithm is presented to partition data flow graphs while meeting the timing constraints by obtaining the target number of partitions. In addition, the proposed algorithm attempts to minimize the logic resources used for implementing the real-time application. In this algorithm, selecting the appropriate nodes and moving them between subsequent partitions results in more area balanced partitions and less number of partitions.

The walk distances in graphs are defined as the result of appropriate transformations of the ∞ k=0 (tA) k proximity measures, where A is the weighted adjacency matrix of a graph and t is a sufficiently small positive parameter. The walk distances are graph-geodetic; moreover, they converge to the shortest path distance and to the so-called long walk distance as the parameter t approaches its limiting values. Furthermore, the logarithmic forest distances which are known to generalize the resistance distance and the shortest path distance are a specific subclass of walk distances. On the other hand, the long walk distance is equal to the resistance distance in a transformed graph.

The High-Level Synthesis (HLS) tools aid in simplified and faster design development without familiarity with Hardware Description Language (HDL) and Register Transfer Logic (RTL) design flow. However, it is not straight forward to associate every line of source code to a clock-cycle of synthesized hardware design. On the other hand, the traditional RTL-based design development flow provides the fine-grained performance profile through waveforms. With the same level of visibility in HLS designs, the designers can identify the performance-bottlenecks and obtain the target performance by iteratively fine-tuning the source code. Although, the HLS development tools provide the low-level waveforms, interpreting them in terms of source code variables is a challenging and tedious task. Addressing this gap, we propose an automated profiler tool, HLS_Profiler, that provides performance profile of source code in a cycle-accurate manner. The HLS_Profiler tool is non-intrusive and collectively uses the ⟨static analysis, dynamic trace⟩ of the source code to present the performance profile report to attribute latent clock cycles to each line of source code. Additionally, we developed a set of associative rules to maintain correctness in performance profile of the HLS design. To verify correctness, we demonstrate the HLS_Profiler tool on MachSuite Benchmarks and an industry-grade recommendation application. The proposed HLS_Profiler framework provides visibility into the cycle-by-cycle hardware execution of source-code and aids the designer in making performance-centric decisions. CCS CONCEPTS • Hardware → Software tools for EDA; Board-and systemlevel test; • Computing methodologies → Model verification and validation; • General and reference → Evaluation.

Customization of processor architectures through instruction set extensions (ISEs) is an effective way to meet the growing performance demands of embedded applications. A high-quality ISE generation approach needs to obtain results close to those achieved by experienced designers, particularly for complex applications that exhibit regularity: expert designers are able to exploit manually such regularity in the data flow graphs to generate high-quality ISEs. In this paper, we present ISEGEN, an approach that identifies high-quality ISEs by iterative improvement following the basic principles of the well-known Kernighan-Lin min-cut heuristic. Experimental results on a number of MediaBench, EEMBC, and cryptographic applications show that our approach matches the quality of the optimal solution obtained by exhaustive search. We also show that our ISEGEN technique is on average 20 faster than a genetic formulation that generates equivalent solutions. Furthermore, the ISEs identified by our technique exhibit 35% more speedup than the genetic solution on a large cryptographic application by effectively exploiting its regular structure.

Customization of processor architectures through Instruction Set Extensions (ISEs) is an effective way to meet the growing performance demands of embedded applications. A high-quality ISE generation approach needs to obtain results close to those achieved by experienced designers, particularly for complex applications that exhibit regularity: expert designers are able to exploit manually such regularity in the data flow graphs to generate high-quality ISEs. In this paper, we present ISEGEN, an approach that identifies high-quality ISEs by iterative improvement following the basic principles of the well-known Kernighan-Lin (K-L) min-cut heuristic. Experimental results on a number of MediaBench, EEMBC and cryptographic applications show that our approach matches the quality of the optimal solution obtained by exhaustive search. We also show that our ISEGEN technique is on average ¾¼¢ faster than a genetic formulation that generates equivalent solutions. Furthermore, the ISEs identified by our technique exhibit ¿ ± more speedup than the genetic solution on a large cryptographic application (AES) by effectively exploiting its regular structure.

For the development of CORBA applications, an IDL compiler is needed that generates code for communication stubs, helper classes and implementation skeletons. For each IDL language mapping, for every version of a particular language mapping, and for every CORBA implementation, the generated code has to be different. Traditionally the code generation is hard-wired into a compiler, thus many different compilers have to be programmed. IDLflex is a generic IDL compiler which is able to generate arbitrary code for arbitrary languages. Only a mapping program written in an XML-based mapping language and a language-specific utility class have to be provided. Thus, IDLflex can be adapted to another target programming language, to another mapping or to another ORB implementation in a very fast way. Furthermore, IDLflex allows to easily integrate additional functionality into a CORBA-based system, as it was done within the AspectIX middleware project. 1. This ORB is no longer supported by its developers. However the JavaORB technology migrated to OpenORB, also an open source project.

Dynamic Partially Reconfiguration (DPR) on FPGA has attracted significant research interest in recent years since it provides benefits such as reduced area and flexible functionality. However, due to the lack of supporting synthesis tools in the current DPR design flow, leveraging benefits from DPR requires specific design expertise with laborious manual design effort. Considering the complicated concurrency relations among various functions, it is challenging to select appropriate Partial Reconfiguration Modules (PR Modules) and cluster them into proper groups with a proper reconfiguration schedule so that the hardware modules can be swapped in and out correctly during the run time. Furthermore, the design of PR Modules also impacts reconfiguration latency and resource utilization greatly. In this paper, we propose a Maximum-Weight Independent Set model to formulate the PR Module selection and clustering problem so that the original manual exploration can be solved efficiently and ...