Data Flow Graph

Reconfigurable systems have been shown to achieve significant performance speedup through architectures that map the most time-consuming application kernel modules or inner loops to a reconfigurable datapath. As each portion of the application starts to execute, the system partially reconfigures the datapath so as to perform the corresponding computation. The reconfigurable datapath should have as few and simple hardware blocks and interconnections as possible, in order to reduce its cost, area, and reconfiguration overhead. To achieve that, hardware blocks and interconnections should be reused as much as possible across the application. We represent each piece of the application as a data-flow graph (DFG). The DFG merging process identifies similarities among the DFGs, and produces a single datapath that can be dynamically reconfigured and has a minimum area cost, when considering both hardware blocks and interconnections. In this paper we present a novel technique for the DFG merge problem, and we evaluate it using programs from the MediaBench benchmark. Our algorithm execution time approaches the fastest previous solution to this problem and produces datapaths with an average area reduction of 20%. When compared to the best known area solution, our approach produces datapaths with area costs equivalent to (and in many cases better than) it, while achieving impressive speedups. Index Terms-High-level synthesis, reconfigurable computing, resource sharing.

This work presents a Model Driven Engineering (MDE) approach to the generation of a MOF-based internal design representation for an embedded application described using UML class and sequence diagrams. Differently from other similar MDE-based approaches for embedded system design, which translate UML models to some specific internal format, our internal design representation, as a MOF-based metamodel, can take advantage of the concept of transformation between models to implement cosynthesis tools. Our internal design representation captures the specified system as a set of hierarchical modules, interconnected by ports, and processes, which communicate through send/receive operations using channels or through shared variables. The execution flow of the application is also captured by means of a control/data flow graph, which is used as input to a co-synthesis framework for embedded systems design. The paper describes the defined transformations between models and illustrates them with a case study to show the effectiveness of the approach.

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In this paper, we consider the problem of verifying thread-state properties of multithreaded programs in which the number of active threads cannot be statically bounded. Our approach is based on decomposing the task into two modules, where one reasons about data and the other reasons about control. The data module computes thread-state invariants (e.g., linear constraints over global variables and local variables of one thread) using the thread interference information computed by the control module. The control module computes a representation of thread interference, as an incrementally constructed data flow graph, using the data invariants provided by the data module. These invariants are used to rule out patterns of thread interference that can not occur in a real program execution. The two modules are incorporated into a feedback loop, so that the abstractions of data and interference are iteratively coarsened as the algorithm progresses (that is, they become weaker) until a fixed point is reached. Our approach is sound and terminating, and applicable to programs with infinite state (e.g., unbounded integers) and unboundedly many threads. The verification method presented in this paper has been implemented into a tool, called DUET. We demonstrate the effectiveness of our technique by verifying properties of a selection of Linux device drivers using DUET, and also compare DUET with previous work on verification of parameterized Boolean program using the Boolean abstractions of these drivers.

This work discusses CHARM, a Composable Heterogeneous Accelerator-Rich Microprocessor design that provides scalability, flexibility, and design reuse in the space of accelerator-rich CMPs. CHARM features a hardware structure called the accelerator block composer (ABC), which can dynamically compose a set of accelerator building blocks (ABBs) into a loosely coupled accelerator (LCA) to provide orders of magnitude improvement in performance and power efficiency. Our software infrastructure provides a data flow graph to describe the composition, and our hardware components dynamically map available resources to the data flow graph to compose the accelerator from components that may be physically distributed across the CMP. Our ABC is also capable of providing load balancing among available compute resources to increase accelerator utilization. Running medical imaging benchmarks, our experimental results show an average speedup of 2.1X (best case 3.7X) compared to approaches that use LCAs together with a hardware resource manager. We also gain in terms of energy consumption (average 2.4X; best case 4.7X).

Tangible interaction shows promise to significantly enhance computer-mediated support for activities such as learning, problem solving, and design. However, tangible user interfaces are currently considered challenging to design and build. Designers and developers of these interfaces encounter several conceptual, methodological and technical difficulties. Among others, these challenges include: the lack of appropriate interaction abstractions, the shortcomings of current user interface software tools to address continuous and parallel interactions, as well as the excessive effort required to integrate novel input and output technologies. To address these challenges, we propose a specification paradigm for designing and implementing Tangible User Interfaces (TUIs), that enables TUI developers to specify the structure and behavior of a tangible user interface using high-level constructs, which abstract away implementation details. An important benefit of this approach, which is based on User Interface Description Language (UIDL) research, is that these specifications could be automatically or semi-automatically converted into concrete TUI implementations. In addition, such specifications could serve as a common ground for investigating both design and implementation concerns by TUI developers from different disciplines.

In this paper, we present a novel temporal partitioning algorithm that temporally partitions a data flow graph on reconfigurable system. Our algorithm can be used to resolve the temporal partitioning problem at the behaviour level. Our algorithm optimizes the whole latency of the design; this aim can be reached by minimizing the latency of the graph and the number of partitions at the same time. Consequently, our algorithm starts by the lowest possible number of partitions; and next it uses the eigenvectors of the graph to find the best schedule of nodes that minimizes the latency of the graph. The proposed methodology was tested on several examples on reconfigurable architecture based on Xilinx Vertex-II XC2V1000 FPGA device. The results show significant reduction in the design latency compared to famous related algorithms used in this field.

Implementing real-time video processing systems put high requirements on computation and memory performance. FPGAs have proven to be effective implementation architecture for these systems. However, the hardware based design flow for FPGAs make the implementation task complex. The system synthesis tool presented in this paper reduces this design complexity. The synthesis is done from a SystemC based coarse grain data flow graph that captures the video processing system. The data flow graph is optimized and mapped onto an FPGA. The results from real-life video processing systems clearly show that the presented tool produces effective implementations.

In this paper we consider two software-based control-flow error recovery methods with a rollback recovery mechanism for using in multithreaded architectures. Disregarding to thread interactions between different threads by previous CFE recovery techniques caused these methods not be suitable in multithreaded architectures. Furthermore, the high memory and performance overheads of these techniques may be problematic for real-time embedded systems which have tight memory and performance budget. Therefore, regarding to the importance of handling the CFE, unsuitability of the conventional related techniques to be utilized in the modern processors and high memory and performance overheads of previous CFE recovery techniques, two low-cost control-flow error recovery techniques, CFE Recovery using Data-flow graph Consideration (CRDC) and CFE Recovery using Macro block-level Check pointing (CRMC), are presented in this paper. The proposed recovery techniques are composed of two phases of control-flow error detection and control-flow error recovery. These phases are achieved through inserting additional instructions into program at compile time regarding to dependency graph. This graph is extracted to model control-flow and data dependencies among basic blocks and thread interactions between different threads of a program. In order to evaluate the proposed techniques, five multithreaded benchmarks Quick Sort, Matrix Multiplication, Bubble Sort, Linked List and Fast Fourier Transform utilized to run on a multi-core processor, and a total of 5000 transient faults has been injected into several executable points of each program. Fault injection experiments show that tolerable performance and memory overheads with noticeable error recovery coverage can be achieved via proposed techniques.

Presents a data flow graph exchange standard, agreed upon and used by the partners in the ESPRIT research project, ASCIS. These data flow graphs are generated from known user interface languages such as Silage, VHDL, and C, and are used to drive architectural synthesis packages and formal verification. The graph semantics are defined to offer a unique degree of freedom for time and area optimizations in synthesis, by giving a maximal parallel representation and combining control and data flow in a consistent way. The graph textual exchange format was developed to allow site and application dependent extensions, without disturbing tools who do not know about these

In this paper we consider two software-based control-flow error recovery methods with a rollback recovery mechanism for using in multithreaded architectures. Disregarding to thread interactions between different threads by previous CFE recovery techniques caused these methods not be suitable in multithreaded architectures. Furthermore, the high memory and performance overheads of these techniques may be problematic for real-time embedded systems which have tight memory and performance budget. Therefore, regarding to the importance of handling the CFE, unsuitability of the conventional related techniques to be utilized in the modern processors and high memory and performance overheads of previous CFE recovery techniques, two low-cost control-flow error recovery techniques, CFE Recovery using Data-flow graph Consideration (CRDC) and CFE Recovery using Macro block-level Check pointing (CRMC), are presented in this paper. The proposed recovery techniques are composed of two phases of control-flow error detection and control-flow error recovery. These phases are achieved through inserting additional instructions into program at compile time regarding to dependency graph. This graph is extracted to model control-flow and data dependencies among basic blocks and thread interactions between different threads of a program. In order to evaluate the proposed techniques, five multithreaded benchmarks Quick Sort, Matrix Multiplication, Bubble Sort, Linked List and Fast Fourier Transform utilized to run on a multi-core processor, and a total of 5000 transient faults has been injected into several executable points of each program. Fault injection experiments show that tolerable performance and memory overheads with noticeable error recovery coverage can be achieved via proposed techniques.

A given behavioral specification can be implemented on a large number of register-transfer level designs. Instead of producing several designs and selecting the best one, synthesis systems may use estimation to reduce the design space. In this paper, we present a new technique for computing a lowerbound completion time for non-pipelined resource-constrained scheduling problem. Given a data flow graph, a set of resources, resource delays and a clock cycle, we derive a lower-bound on the completion time of a schedule, Our technique can handle chaining, multi-cycle operations and pipelined modules. The technique is very fast and experimental results show that it is also very tight.

Program analysis is useful for debugging, testing, and maintaining software systems due to availability of information about the structure and relationship of the program modules. In general, program analysis is performed either based on control flow graph (CFG) or dependence graph (DG). However, in the case of aspect-oriented programming (AOP), control flow graph or dependence graph are not enough to model the features of Aspect-oriented (AO) programs. Although AOP is good for modular representation and crosscutting concern, a suitable graph model for program analysis is required to gather information on its structure for the purpose of minimizing maintenance effort. In this thesis, a graph model known as Slicing Aspect-Oriented Program by Using Dependence Flow Graph For Software Maintenance Purpose is proposed to represent the structure of aspect-oriented programs. The graph is formed by merging CFG and DG.  As a consequence, more information about dependencies involving the features of AOP, such as join point, advice, aspects, their related constructs, and the flow of control are able to be gathered. Based on AODFG, slicing criteria are defined for aspect-oriented features. The concept of slicing AODFG model is also proposed. A prototype tool called Aspect-oriented Slicing Tool was developed to implement AODFG. The performance of AODFG was evaluated by analysing some AspectJ  programs taken from AspectJ  Development Tools. The analysis showed the consistency of the output compared with DG and CFG. In addition, an empirical study was conducted to find out the effect of AOST in terms of effectiveness,  understandability , and modifiability in maintenance purpose. The results of the empirical analysis showed positive responses.

Stream languages explicitly describe fork-join parallelism and pipelines, offering a powerful programming model for many-core Multi-Processor Systems on Chip (MPSoC). In an embedded resource-constrained system, adapting stream programs to fit memory requirements is particularly important. In this paper we present a new approach to reduce the memory footprint required to run stream programs on MPSoC. Through an exploration of equivalent program variants, the method selects parallel code minimizing memory consumption. For large program instances, a heuristic accelerating the exploration phase is proposed and evaluated. We demonstrate the interest of our method on a panel of ten significant benchmarks. Using a multi-core modulo scheduling technique, our approach lowers considerably the minimal amount of memory required to run seven of these benchmarks while preserving throughput.

Damia is a lightweight enterprise data integration service where line of business users can create and catalog high value data feeds for consumption by situational applications. Damia is inspired by the Web 2.0 mashup phenomenon. It consists of (1) a browserbased user-interface that allows for the specification of data mashups as data flow graphs using a set of operators, (2) a server with an execution engine, as well as APIs for searching, debugging, executing and managing mashups. Damia offers a framework and functionality for dynamic entity resolution, streaming and other higher value features particularly important in the enterprise domain. Damia is currently in perpetual beta in the IBM Intranet.

In this paper we present a new temporal partitioning methodology used for the data-path part of an algorithm for the reconfigurable embedded system design. This temporal partitioning uses an assessing trade-offs in time constraint, design size and field programmable gate arrays device parameters (circuit speed, reconfiguration time). The originality of our method is that we use the dynamic reconfiguration in order to minimize the number of cells needed to implement the data-path of an application under a time constraint. Our method consists, by taking into account the used technology, in evaluating the algorithm area and operators execution time from data flow graph. Thus, we deduce the right number of reconfigurations and the algorithm partitioning for Run-Time Reconfiguration implementation. This method allows avoiding an oversizing of implementation resources needed. This optimizing approach can be useful for the design of an embedded device or system. Our approach is illustrated by various reconfigurable implementations of real time image processing data-path. q

This work discusses CHARM, a Composable Heterogeneous Accelerator-Rich Microprocessor design that provides scalability, flexibility, and design reuse in the space of accelerator-rich CMPs. CHARM features a hardware structure called the accelerator block composer (ABC), which can dynamically compose a set of accelerator building blocks (ABBs) into a loosely coupled accelerator (LCA) to provide orders of magnitude improvement in performance and power efficiency. Our software infrastructure provides a data flow graph to describe the composition, and our hardware components dynamically map available resources to the data flow graph to compose the accelerator from components that may be physically distributed across the CMP. Our ABC is also capable of providing load balancing among available compute resources to increase accelerator utilization. Running medical imaging benchmarks, our experimental results show an average speedup of 2.1X (best case 3.7X) compared to approaches that use LCAs together with a hardware resource manager. We also gain in terms of energy consumption (average 2.4X; best case 4.7X).

The Threaded Abstract Machine (TAM) refines dataflow execution models to address the critical constraints that modern parallel architectures place on the compilation of general-purpose parallel programming languages. TAM defines a self-scheduled machine language of parallel threads, which provides a path from dataflowgraph program representations to conventional control flow. The most important feature of TAM is the way it exposes the interaction between the handling of asynchronous message events, the scheduling of computation, and the utilization of the storage hierarchy.

Due to exponential behavior of gate-oxide leakage current with temperature and technology scaling, leakage power plays important role in nano − CM OS circuit. In this paper, we present simultaneous scheduling and binding algorithm for optimizing leakage current during behavioral synthesis. It uses T ED (Taylor Expansion Diagram) for generating optimized DF G (Data Flow Graph). Once DF G is obtained, it selectively binds non-critical components to corresponding functional unit consisting of transistors of high oxide thickness and critical components with low oxide thickness. As the algorithm considers time-constraint explicitly, it reduces leakage current without degrading the performance of the design. Experimental results on a set of behavioral synthesis benchmarks for 45nm process show 30% to 70% reduction in leakage current compared to the results obtained by a conventional optimization flow.

Software test-data generation research primarily focuses on using control flow graphs for producing an optimum set of test cases. This paper proposes the integration of a data flow graph module with an existing testing framework and the utilisation of a specially designed genetic algorithm for automatically generating test cases based on data flow coverage criteria. The enhanced framework aims to explore promising aspects of software testing that have not yet received adequate research attention, by exploiting the data information of a program and provide a different testing coverage approach compared to existing control flow-oriented ones. The performance of the proposed approach is assessed and validated on a number of sample programs of different levels of size and complexity. The associated experimental results indicate successful performance in terms of testing coverage, which is significantly better when compared to those of existing dynamic data flow-oriented test data generation methods.

This paper focuses on the design process for reconfigurable architecture. Our contribution focuses on introducing a new temporal partitioning algorithm. Our algorithm is based on typical mathematic flow to solve the temporal partitioning problem. This algorithm optimizes the transfer of data required between design partitions and the reconfiguration overhead. Results show that our algorithm considerably decreases the communication cost and the latency compared with other well known algorithms.

In this paper, we present a typical temporal partitioning methodology that temporally partitions a data flow graph on reconfigurable system. Our approach optimizes the communication cost of the design. This aim can be reached by minimizing the transfer of data required between design partitions and the routing cost between FPGA modules. Consequently, our algorithm is composed by two main steps. The first step aims to find a temporal partitioning of the graph. This step gives the optimal solution in term of communication cost. Next, our approach builds the best architecture, on a partially reconfigurable FPGA, that gives the lowest routing cost between modules. The proposed methodology was tested on several examples on the Xilinx Virtex-II pro. The results show significant reduction in the communication cost compared with others famous approaches used in this field.

Modern multimedia applications use an increasing number of sensors including cameras, microphones and microphone arrays. These applications must acquire and process data from sensors in real-time, which is usually beyond the capabilities of single machines. We present our distributed sensor data transport middleware, the NIST Data Flow System II, which offers network transparent services for data acquisition and processing across a local network of computers. An application is thus represented as a data flow graph, with streaming media flowing between the different computational components. This is highlighted by presenting a multimedia application tracking persons using a sensor fusion of audio and video streams.

The design of a common architecture that can support multiple data-flow patterns (or contexts) embedded in complex control flow structures, in applications like multimedia processing, is particularly challenging when the target platform is an FPGA with heterogeneous mixture of device primitives. In this paper, we present scheduling and mapping algorithms that use a novel area cost metric to generate resource aware context adaptable architectures. We present the results of a rigorous analysis of the methodology on multiple test cases. Post place and route results are compared against published techniques and show an area savings and execution time savings of 46% each.

To answer new challenges, systems on chip need to gain flexibility and fpgas need to gain structure. We propose a general framework for SoC architectures and software tools in which different kind of processing units are programmed at high level. We show a reconfigurable unit suitable for this framework and we draw the outline of a super-compiler able to address such an architecture.

Most existing solutions achieve this by matching structure of patterns corresponding to CFUs with sub-graphs of application data flow graphs. Often it happens that the computations performed by the two are equivalent, but due to structural dissimilarities the match is missed. What is needed is a method that can match two graphs functionally rather than structurally. In this paper, we present a novel method to do this and give implementation results to show its effectiveness.

Data-flow is a natural approach to parallelism. However, describing dependencies and control between fine-grained data-flow tasks can be complex and present unwanted overheads. TALM (TALM is an Architecture and Language for Multi-threading) introduces a user-defined coarse-grained parallel data-flow model, where programmers identify code blocks, called super-instructions, to be run in parallel and connect them in a data-flow graph. TALM has been implemented as a hybrid Von Neumann/data-flow execution system: the \emph{Trebuchet}. We have observed that TALM's usefulness largely depends on how programmers specify and connect super-instructions. Thus, we present \emph{Couillard}, a full compiler that creates, based on an annotated C-program, a data-flow graph and C-code corresponding to each super-instruction. We show that our toolchain allows one to benefit from data-flow execution and explore sophisticated parallel programming techniques, with small effort. To evaluate our system we have executed a set of real applications on a large multi-core machine. Comparison with popular parallel programming methods shows competitive speedups, while providing an easier parallel programing approach.

In object-oriented terms, one of the goals of integration testing is to ensure that messages from objects in one class or component are sent and received in the proper order and have the intended effect on the state of the objects that receive the messages. This research extends an existing single-class testing technique to integration testing of multiple classes. The single-class technique models the behavior of a single class as a finite state machine, transforms the representation into a data flow graph that explicitly identifies the definitions and uses of each state variable of the class, and then applies conventional data flow testing to produce test case specifications that can be used to test the class. This paper extends those ideas to inter-class testing by developing flow graphs, finding paths between pairs of definitions and uses, detecting some infeasible paths, and automatically generating tests for an arbitrary number of classes and components. It introduces flexible representations for message sending and receiving among objects and allows concurrency among any or all classes and components. Data flow graphs are stored in a relational database, and database queries are used to gather def-use information. This approach is conceptually simple, mathematically precise, quite powerful, and general enough to be used for traditional data flow analysis. This testing approach relies on finite state machines, database modeling and processing techniques, and algorithms for analysis and traversal of directed graphs. The paper presents empirical results of the approach applied to an automotive system. This work was prepared by United States Government employees as part of their official duties and is, therefore, a work of the U.S. Government and not subject to copyright.

This paper presents a novel approach to algebraic optimization of data-flow graphs in the domain of computationally intensive applications. The presented approach is based upon the paradigm of simulated evolution which has been proven to be a powerful method for solving large non-linear optimization problems. We introduce a genetic algorithm with a new chromosomal representation of dataflow graphs that serves as a basis for preserving the correctness of algebraic transformations and allows an efficient implementation of the genetic operators. Furthermore, we introduce a new class of hardware-related transformation rules which for the first time allow to take existing component libraries into account. The efficiency of our method is demonstrated by encouraging experimental results for several standard benchmarks.

This paper presents a methodology for the integration of scheduling and allocation in high-level synthesis. It shows how a previous global analysis of the data flow graph structure and the module library features can be used as an appropriate guide to accelerate the process of finding solutions in the design space. Several bounding and guiding heuristics for a branch-and-bound-based exploration are presented. In addition to dealing with basic blocks, the scheduling and allocation method addresses also the treatment of conditional branches and loops.

This paper presents an efficient software technique to detect and correct control-flow and data errors through addition of redundant codes in a given program. This technique is performed using both control-flow and data-flow graphs. Based on this method, most of control-flow errors in the program are, first detected, and next corrected automatically, so that not only errors in the control flow are detected / corrected but also, errors in the data of program because of control flow errors are repaired. In order to evaluate this technique, we use a simulator which can simulate an assembly code on the 80X86 microprocessors. We use three benchmarks: quick sort, matrix multiplication and linked list, and 1000 transient faults were injected on several executable points in the program code. The experimental results demonstrate that on average 93.5% of control flow errors are detected and corrected by CCDA automatically without any data error generation. It also shows that the performance and memory overheads of CCDA are noticeably less than previous related works.

Synchronous Data Flow Graphs (SDFGs) are a useful tool for modeling and analyzing embedded data flow applications, both in a single processor and a multiprocessing context or for application mapping on platforms. Throughput analysis of these SDFGs is an important step for verifying throughput requirements of concurrent real-time applications, for instance within design-space exploration activities. Analysis of SDFGs can be hard, since the worst-case complexity of analysis algorithms is often high. This is also true for throughput analysis. In particular, many algorithms involve a conversion to another kind of data flow graph, the size of which can be exponentially larger than the size of the original graph. In this paper, we present a method for throughput analysis of SDFGs, based on explicit state-space exploration and we show that the method, despite its worst-case complexity, works well in practice, while existing methods often fail. We demonstrate this by comparing the method with state-ofthe-art cycle mean computation algorithms. Moreover, since the state-space exploration method is essentially the same as simulation of the graph, the results of this paper can be easily obtained as a byproduct in existing simulation tools.

In this paper we present a new temporal partitioning methodology used for the data-path part of an algorithm for the reconfigurable embedded system design. This temporal partitioning uses an assessing trade-offs in time constraint, design size and field programmable gate arrays device parameters (circuit speed, reconfiguration time). The originality of our method is that we use the dynamic reconfiguration in order to minimize the number of cells needed to implement the data-path of an application under a time constraint. Our method consists, by taking into account the used technology, in evaluating the algorithm area and operators execution time from data flow graph. Thus, we deduce the right number of reconfigurations and the algorithm partitioning for Run-Time Reconfiguration implementation. This method allows avoiding an oversizing of implementation resources needed. This optimizing approach can be useful for the design of an embedded device or system. Our approach is illustrated by various reconfigurable implementations of real time image processing data-path. q

An architectural synthesis tool dedicated to Digital Signal Processing, GAUT 1 , will be presented here. Synthesis is achieved under both real time and silicon cost constraints. The algorithm is first described using a high level behavioral language. The control and data flow graph (CDFG) obtained is synthesized into processing, control, memorization and communication units. These specifications are in VHDL, thus enabling the interconnection with CAD and simulation tools. An application of acoustic echo cancellation was synthesized, and we show that our method may also be used to evaluate the complexity of various Signal Processing algorithms that satisfy the application constraints.

To facilitate data mining and integration (DMI) processes in a generic way, we investigate a parallel pipeline streaming model. We model a DMI task as a streaming data-flow graph: a directed acyclic graph (DAG) of Processing Elements (PEs). The composition mechanism links PEs via data streams, which may be in memory, buffered via disks or inter-computer data-flows. This makes it

Stream languages explicitly describe fork-join parallelism and pipelines, offering a powerful programming model for many-core Multi-Processor Systems on Chip (MPSoC). In an embedded resource-constrained system, adapting stream programs to fit memory requirements is particularly important. In this paper we present a new approach to reduce the memory footprint required to run stream programs on MPSoC. Through an exploration of equivalent program variants, the method selects parallel code minimizing memory consumption. For large program instances, a heuristic accelerating the exploration phase is proposed and evaluated. We demonstrate the interest of our method on a panel of ten significant benchmarks. Using a multi-core modulo scheduling technique, our approach lowers considerably the minimal amount of memory required to run seven of these benchmarks while preserving throughput.

Customization of processor architectures through instruction set extensions (ISEs) is an effective way to meet the growing performance demands of embedded applications. A high-quality ISE generation approach needs to obtain results close to those achieved by experienced designers, particularly for complex applications that exhibit regularity: expert designers are able to exploit manually such regularity in the data flow graphs to generate high-quality ISEs. In this paper, we present ISEGEN, an approach that identifies high-quality ISEs by iterative improvement following the basic principles of the well-known Kernighan-Lin min-cut heuristic. Experimental results on a number of MediaBench, EEMBC, and cryptographic applications show that our approach matches the quality of the optimal solution obtained by exhaustive search. We also show that our ISEGEN technique is on average 20 faster than a genetic formulation that generates equivalent solutions. Furthermore, the ISEs identified by our technique exhibit 35% more speedup than the genetic solution on a large cryptographic application by effectively exploiting its regular structure.

We present new results concerning the integration of high level designed ips into a complete System on Chip. We first introduce a new computation model that can be used for cycle accurate simulation of register transfer level synthesized hardware. Then we provide simulation of a SoC integrating a data-flow ip synthesized with MMAlpha and the So-cLib cycle accurate simulation environment. This integration also validates an efficient generic interface mechanism for data-flow ips.

Extracting frequently executed (hot) portions of the application and executing their corresponding data flow graph (DFG) on the hardware accelerator brings about more speedup and energy saving for embedded systems comprising a base processor integrated with a tightly coupled accelerator. Extending DFGs to support control instructions and using Control DFGs (CDFGs) instead of DFGs results in more coverage of application code portion are being accelerated hence, more speedup and energy saving. In this paper, motivations for extending DFGs to CDFGs and handling control instructions are introduced. In addition, basic requirements for an accelerator with conditional execution support are proposed. Then, two algorithms are presented for temporal partitioning of CDFGs considering the target accelerator architectural constraints. To demonstrate effectiveness of the proposed ideas, they are applied to the accelerator of a reconfigurable processor called AMBER. Experimental results approve the remarkable effectiveness of covering control instructions and using CDFGs versus DFGs in the aspects of performance and energy reduction.