: This report describes a computer-aided verification tool, called Spectool, for a class of synchronous hardware designs. The tool reduces the effort required for verifying a design in the targeted class by automating most of the routine, but cumbersome, parts of the verification process. The input to the tool is a circuit diagram of the design. This diagram is drawn using the graphical user-interface provided by the tool. Spectool has been used on several examples including a large pipelined microprocessor design. Hardware Verification, Computer Security, Formal Methods.