Rad-Hard 2.5 GBPS SpaceFibre Interface Device

Aerospace, 2019

SpaceFibre is an upcoming on-board high-speed communication protocol for space applications. It has been developed in collaboration with the European Space Agency to answer the growing data-rate requirement of satellite payloads such as Synthetic Aperture Radars or hyper-spectral imagers. SpaceFibre offers a complete set of features (i.e., Fault Detection, Isolation and Recovery, and Quality of Service) that guarantees robust communication at the price of higher complexity. This article proposes an innovative modified implementation of the SpaceFibre standard: R-SpaceFibre. It has been designed to reduce hardware resources while keeping high data-rate capability and flow control. Attention is given to the trade-off between Data link layer complexity reduction and protocol features. The proposed protocol is particularly suitable in scenarios where very low bit error rate is foreseen and data integrity is not critical, for example in imaging instruments. The main advantage is a reduct...

This paper describes basics methods of transferring data through serial data buses, using serializer/deserializer (SerDes) as main device in this operation. It explains function of SerDes and different techniques for implementing it.

IAEME PUBLICATION, 2021

A SerDes is a transceiver with an integrated circuit (IC or chip) that converts parallel data into serial data and vice versa. SerDes has generally been used in the high-speed serial interface for the past few years and is widely used as an ASIC type and explicitly standard part of the application. Use both frequency adjustment and jitter as components. However, the actual incentive for a particular ser/des must be estimated experimentally. Intermediate frequency behavior Interactions in the IF range are generally complex. With technology slowdowns and processing speeds increasing, electrical connections are seen as a bottleneck for high-speed signal transmission between chips. The wide range of SerDes drive covers large distances at multi-gigabit speeds with a simple FPGA interface. A ser/des is a pair of functional squares commonly used in high-speed communications. The paper surveys with the SERDES technology for networking capacity regions. A data switch concept is presented to illustrate the intended useful backplane and switch SERDES ICs.

Acta Astronautica, 2020

In the last few years, satellite on-board data handling bandwidth requirements grew significantly, as well as production volume of these systems. A series of different protocols currently try to answer this need. In particular, the European Space Agency developed an open protocol solution: SpaceFibre. The SpaceFibre protocol can sustain a line rate of 6.25 Gb/s per lane (up to 16 lanes). It offers advanced and flexible Quality-of-Service features, as well as Fault Detection Isolation and Recovery services. The protocol structure has been developed so that full hardware implementation of its core layers is straightforward, granting high performances at low price in terms of complexity and power consumption, one of the most stringent requirements in space applications. In this paper, a FPGA implementation on both rad-hardened (RTAX2000, RTG4, Virtex-5) and commercial (ZYNQ 7000) devices of the SpaceFibre CODEC is presented together with its verification environment and a hardware validation setup. Particular attention is given to the trade-off between resources utilisation, power consumption and CODEC configurations, in order to enable future system adopters to efficiently explore the design space.

2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021

Over the last decade, the growing influence of open source software has necessitated the need to reduce the abstraction levels in hardware design. Open source hardware significantly reduces the development time, increasing the probability of firstpass success and enable developers to optimize software solutions based on hardware features, thereby reducing the design costs. The recent introduction of open source Process Development Kit (OpenPDK) by Skywater technologies in June 2020 has eliminated the barriers to Application-Specific Integrated Circuit (ASIC) design, which is otherwise considered expensive and not easily accessible. The OpenPDK is the first concrete step towards achieving the goal of open source circuit blocks that can be imported to reuse and modify in ASIC design. With process technologies scaling down for better performance, the need for entirely digital designs, which can be synthesized in any standard Automatic Placeand-Route (APR) tool, has increased considerably, for mapping physical design to the new process technology. This work presents a first open source all-digital Serializer/Deserializer (SerDes) for multi-GHz serial links designed using Skywater OpenPDK 130nm process node. To ensure that the design is fully synthesizable, the SerDes uses CMOS inverter based drivers at the transmitter, while the receiver front end comprises a resistive feedback inverter as a sensing element, followed by sampling elements. A fully digital oversampling CDR at the receiver end recovers the transmitter clock for proper decoding of data bits. The physical design flow utilizes OpenLANE, which is an open source end-to-end tool for generating GDS from RTL. Cadence Virtuoso has been used for extracting parasitics for post-layout simulations, which exhibit the SerDes functionality at 2 Gbps for 34 dB channel loss while consuming 438 mW power. The generated GDS and netlist files of the SerDes, along with the required documentation, are uploaded in a GitHub repository for public access.

In satellite systems, large amount of high speed data is required to be transmitted from one system to another. High speed parallel data transmission encounters issues like crosstalk and skew with additional penalty of weight and volume. Various types of high speed data transmission options were studied. SERDES (SERializer/DESerializer) is a special device meant for high speed serial data transmission which overcomes above mentioned signal integrity and hardware issues. Serial data can be encoded for clock embedding, DC balancing and synchronization. DC balancing further helps in reduction of Inter-symbol Interference (ISI). Data can be pre emphasized for lossy cables. One such SERDES device has been identified for space use. This device transforms 24-bit parallel data into a single differential stream with output serial data rate in excess of 1 Gbps. Device is evaluated for operating conditions and planned to be used after qualification. These devices are easy to use but their eval...

Sensors, 2019

This article presents a complete test equipment for the promising on-board serial high-speed SpaceFibre protocol, published by the European Committee for Space Standardization. SpaceFibre and SpaceWire are standard communication protocols for the latest technology sensor devices intended for on-board satellites and spacecrafts in general, especially for sensors based on image acquisition, such as scanning radiometers or star-tracking devices. The new design aims to provide the enabling tools to the scientific community and the space industry in order to promote the adoption of open standards in space on-board communications for current- and future-generation spacecraft missions. It is the first instrument expressly designed for LabVIEW users, and it offers tools and advanced features for the test and development of new SpaceFibre devices. In addition, it supports the previous SpaceWire standard and cross-communications. Thanks to novel cutting-edge design methods, the system complex...

2008

This paper introduces a standard cell based design for a Serializer and Deserializer (SerDes) communication link. The proposed design is area, power and design time efficient as compared to conventional SerDes Designs, making it very attractive for modest budget multi-core and multi-processor ASICs with wide communication buses that are difficult to accommodate within the pin count of commonly available packaging. The design employs a “Statistical Random Sampling Technique ” to observe and adjust the synchronization and serialization signals at start up rather than using a resource-heavy PLL or DLL based frequency multiplier/synthesizer and clock data recovery circuits. The serialization and deserialization logic is based on standard cell technology that makes the design highly portable. Multiple serial lines are bundled with a strobe that is used as a reference signal for deserialization. Data-to-strobe timing skew is compensated by adjusting the launch times of strobe and data sym...

IEEE Communications Magazine, 2001

The architecture and critical circuit design issues for high-speed serial data links operating in excess of 1 Gb/s are described. Trade-offs in power vs. performance are presented for SONET/SDH transceivers and backplane transceivers for Infiniband or similar standards.

2007

A mixed-signal radiation hardened computer ASIC that includes a four port SpaceWire router is currently in development. Based on the RAD6000 TM microprocessor currently flying on numerous space missions and commanding the Mars Exploration Rovers, this massively integrated system-on-chip is capable of performing flight computer and instrument controller functions and can reuse existing RAD6000 software and test infrastructure. The ASIC will be manufactured in a 150nm radiation hardened CMOS technology. Initiated in 2005 as a NASA technology project, development has continued with funding from the Air Force Research Laboratory's Space Vehicles Directorate, Kirtland Air Force Base, N.M.. The ASIC incorporates an enhanced version of the reusable SpaceWire router core with four SpaceWire links and dual internal ports that was previously created for the BAE Systems SpaceWire ASIC. This newer version reduces both die area and power dissipation while improving link performance. The ASIC employs a flight-proven reusable core architecture with a common bus medium. In addition to the RAD6000 microprocessor and SpaceWire cores, the ASIC includes a pipelined 12-bit A/D converter with a programmable multiplexer, three channels of 12-bit D/A conversion, 192KB of on-chip SRAM, 32KB of chalcogenide-based CRAM TM non-volatile memory, a 64-bit PCI interface, a 1553 interface, a DMA controller, and an external memory controller. A 2 nd smaller microcontroller core called the EMC has also been incorporated on the ASIC. It is supported by a compiler developed by BAE Systems and software supporting the SpaceWire transport layer has already been developed. This paper discusses the architecture and functions of the microcontroller ASIC, including the SpaceWire core implementation and features. Operational configurations matched to a variety of applications will also be shown.