A 2.5 Gbit/s CMOS optical receiver frontend

z zyxwvuts zyxwv A M-GBIT/S CMOS OPTICAL RECEIVER FRONTEND Patrick Mitran, Francis Beaudoin, and Mourad N. El-Gamal Microelectronics And Computer Systems Laboratory, McGill University 3480 University Street MontrCal, QuCbec, Canada H3A 2A7 { patrickm, francis, mourad}@macs.ece.mcgill.ca zyxwvutsrqp ABSTRACT An optical receiver achieving 2.5 Gbith bit-rate was realized in a 0.25pm CMOS process. The preamplifier has a gain of 250 ohms, a bandwidth of 1.5 GHZ, and an input referred current noise of g p A It is followed by three post amplification stages with automatic offset control. The receiver is fully packaged and consumes only 36 mA (65 mA with the complete test circuits and output buffers) from a low power supply voltage of 2V. /& . 6 I I Optid Receiver Fig. 1: Overall receiver architecture with input electrical test. Ail,, zyx zyxwvutsr zyxwvutsr 1. INTRODUCTION Increasing demand for high-performance networks has led to the explosion of low-cost fiber-optic links. The objective ofthe work presented in this paper was to design a frontend for a 2.5Gb/s optical receiver. CMOS optical receivers with bit-rates varying from 50-MBitds up to 2.4-Gbitds have already been reported in the literature [ 161. Of particular interest is the design proposed by Ingels et al. [4]: a 1.O-Gbits/s receiver in a 0.7pm CMOS technology using a singleended approach. Also, Tanabe [5,6] reported a 2.4-Gbit/s receiver using a fully differential approach. V, Va. Fig. 2: The transimpedance pre-amplifier. 2.1 The Pre-Amplifier Designing in a CMOS sub-micron technology is challenging due to the failure of the Shockley model to take into account short channel effects. One consequence of this is that the current drawn by a transistor no longer relates to its gate-tosourcevoltage VGsaccording to the theoretical quadratic relation. Nevertheless, it is still possible to analyze the preamplifier in Fig. 2 using the following three assumptions: 1. The drain current is proportional to the width of the transistor. 2. The drain current is proportional to the mobility of the device. 3. The gate-source voltage determines the drain current of the device. Under these assumptions, we can see that M,, M2, and M3 constitute a high-frequency inverting amplifier. M1 is used to reduce the gain of the amplifier and extend its bandwidth. The voltage gain of the amplifier can be shown to be: 2. CIRCUITRY AND DESIGNEQUATIONS The system presented in this paper is based on the topology in [4], while extending the operating speed from 1Gb/s to 2.5Gb/s. A pre-amplifier converts the input current into a voltage signal (Fig. 1). Multiple post-gain stages with automatic offset control are then used to amplify the signal to a rail-to-rail amplitude. An output stage, capable of delivering a large voltage signal offdnp, is used to measure the output. An input test circuit is used to replace an actual photodiode in order to simplify testing. It feeds the TIA pre-amplifier with an input current from a highimpedance capacitive node (Section 2.5). The proposed receiver compares to that in [4] as follows: 1. The -3dB frequency of the TIA is extended from about 500 MHzto 1.5 GHz. A= g m , + g m ~ . (1) 2. The receiver operates from a 2 Volt power supply instead of gm 1 5V while consuming 76 mW instead of 1OOmW. For a high speed design, the gain should be limited to between 2 3. The TIA gain is controllable using an off-chip voltage. and 3 V N in order to maximize the open-loop voltage gain A . M4 4. The test-circuit used allows a more accurate measurement and acts as a feedback resistance, with the off-chip voltage VTIA characterization of the device performance. controlling its value. With no current input to the TIA, the circuit is 5. The maximum achievable gain of the feedback differential in its DC condition position, with = V,. To maximize the stage used for offset cancellation is limited due to channel voltage swing at the output, it is desirable to set V, = VouT= length modulation. This is shown to be of no negative VDD/2 at DC. This implies that: consequences. 'GS3 = 'GS2 I S G ' ' (2) 6. The implementation of the large resistance used in the and feedback path of the post-gain stages (Fig. 3) is made more linear by using an NMOS and PMOS transistors in parallel. This also extends (doubles) the tuning range of these =" (W,+w,) (3) resistances. pup 7. The receiver is designed to be driven by a photodetector with where ,U is the mobility, and is the width of a CMOS transistor. 275 fF of parasitic input capacitance in order to cope with the In our design, this would make W, be large, and an excessive higher targeted bit rate. amount of capacitance would be associated with M3.Instead, one 0-7803-7448-7/02/$17.00 02002 IEEE V - 441 w, w. zy zyxw zyxwvutsrqpo zyxwvutsrqp zyxwvutsr zyxwvutsr zyxw zyxwvutsrqp zyxwvutsrqpo can make W, = K(W, + W,) with K’< pn/pup.The trade-off would be a lower DC biasing voltage at the output. Since the output swing signal is in the millivolts range, this should be acceptable. It was found that a large range of feedback resistances could be achieved with limited variations in the drain and source capacitances of M4.As noted in [4], under the condition that the feedback impedance is independent of C3s2,3, the optimal input capacitance necessary to minimize noise is the same as that of the photodiode Cdiode. A more exact expression for the optimal input capacitance in the case of a single transistor TIA is CGS - 1 , - - J pLm T ~ . F ~ ~ . o ~ (4) 4 where X, = 2 for a 45-degree phase margin, FNBis a constant representing how high above the bandwidth ofthe TIA the noise is to be integrated, L is the length of M4. This allows the scaling of M I ,M2, and M3 to their respective values such that Cin=C& For stability, the dominant pole (at the input node) should be at half or less the frequency of the second pole (at the output node). The dominant pole can be shown to be situated at: 1+A where Rfis the value of the feedback resistance due to M4,while A is the open-loop gain of the amplifier in V N .The second pole can be shown to be at: P2 = Fig. 3: The post-gain stage. 2.3 The Level Shifter The level shifter (Fig. 3) is responsible for providing an appropriate DC biasing to the post-amplification stages. Since transistor @ is Lnnected to the output of the TIA, it must minimally load the TIA, a;?&hence is required to be kept small. To minimize the Miller effect between the gate and drain of M6, the gain of the level shifter should be kept to a minimum: transistor M7 is used to achieve this purpose. As a result of this requirement, the level shifter was designed to have a gain of one. This complziely eliminates the Miller effect and maximizes the bandwidth. zyxwvuts 1 (6) cout~out The total output capacitance CO, is dependent on M 1,MbandM3, and the output resistance is dominated by the g, of M,.’Ihe second pole can be adjusted through ? = W2 I W I while keeping W2 + W, fixed. This leaves W, as an extra degree of freedom, which can be used to maximize the bandwidth until the TIA reaches the limit of stability. Since the wideband nature of the circuit limits the TIA gain, it is critical to minimize the noise generated by the circuitry. The input-referred current noise spectral density for a single transistor TIA can be shown to be: 2.4 Feedback f o r Automatic DC Biasing The purpose of the feedback circuit in Fig. 3 is to maintain an optimally biased DC output and ensure the symmetry ofthe signal. The feedback loop is composed of a differential amplifier and a low-pass filter. In [4], a single PMOS transistor was used to construct the filter’s large resistance R. However, this approach has limitations for short channel CMOS transistors. The reason is that such a resistance would be highly non-hearandcaninbduce considerable distortion, especially for the large output signals of the later post amplification stages. This nonlinearity can result in large voltage swings being given more “weight” than low voltage swings by the low-pass filter, and therefore misestimating the actual DC component. A better approach is to use an NMOS transistor in parallel with the PMOS one. By scaling the size of the PMOS transistor to compensate for the mobility ratio, the resistance of the device can be made nearly linear for large voltages (Fig. 4). The final component of the low-pass feedback circuit is the RC filter formed by the large resistance R and a Miller capacitance CMiller: CMiller =AC, where A is the gain of the amplifier (Ma, M b ) and C is as shown in Fig. 3. To provide a pole as low as possible, it is desirable to have a large differential gain A. However, due to short channel effects, the maximum differential gain that could be achieved by this simple stage was in the order of 20 V N . It was verified by simulation and verified experimentally that this amount of gain, with C = 1.2pF, was enough for the low-pass feedback loop to function correctly. In the following we show that the performance of this circuit, with respect to suppressing the high-frequency components, is determined by R and C alone, and is independent of the value of the differential gain A . The low pass feedback can be analyzed with the help of Fig. 5. It is evident that: zyxwvut Equation (7) suggests that a TIA that is to operate at high speed must either employ a large feedback resistance R+ or have a large biasing voltage V,, in order to minimize the noise. Spice simulations predicted an input-referred noise of less than 9 PA for frequencies up to 3 GHZ. /& 2.2 Post-Amplification To achieve a large output digital signal, it is necessary to post amplify the signal beyond the TIA. This is accomplished by cascading 3 post-amplification stages (Fig. 3). Each postamplification stage consists of a string of identical reduced-gain inverting amplifiers. The amplifiers are designed such that the DC biasing at the input of one stage is provided by the previous stage. To maintain an optimal biasing of the string, a low-pass feedback loop is used in conjunction with a level-shifter at the input. V - 442 ~ zyxwvutsrqponm zyxwvutsrqponmlkjih "1-1- 6 PMOS only 2translstora Vdd Vdd 4- 05 1 1.5 Applied Voltage (Volts) zyxwvutsrqpon * * * 2 25 Fig. 4: Simulated I-V curve for large feedback resistance. Fig. 6: The input test circuit. Fig. 5: Lowpass feedback. zy * where d(s) is the Laplace of the impulse function. Equation (9) has 2 terms - a DC component and a frequency dependent component. Only the latter is of interest for now. At high frequencies, e.g. s > 10/(RCMiIlm),the frequency dependent term can be approximated by: -current that could be applied as input to the TIA (in this particular design, 1 mA). The input signal Vi" is converted to a current by transistor MP This current is the test signal that is fed into the TIA. Transistor M loisa cascode buffer used to increase the bandwidth. To simulate a tml photodiode, the output impedance of M 11 MI1must not load the input impedance of the TIA. Also, a photodiode mainly acts as a capacitive current source. The test circuit was therefore designed to have a total output capacitance of 275fF, equivalent to the capacitance of the photodiode envisaged to be used with this design. This included the parasitics of Mlo and M I I as well as a capacitor C that was intentionally added at the input of the TIA. Transistor M8 is sized identical to M9. The current I8 in MBtracks Is and can be measured off-chip using an oscilloscope. This is done to help estimate the exact amount of current getting into the TIA. In practice, b and I9 can differ for two reasons: VD8is different from V, and, k8is not the same as k9. These differences can however be accounted for mathematically. zyxwvutsrqp which is independent of A as suggested. In this paper, 1/(2pRCMiller) = 500 M z . This means that for s > SMHz, the above equation applies. Since the circuit operates in the gigahertz range, the attenuation is therefore sufficient. Simulations indicated that the DC output of the post-amplifier tracks the DC reference within 10mV. This is also adequate. The differential amplifier, in conjunction with the large resistance R and Gillen had a zero at around 1 GHz. To cancel this zero, a PMOS transistor is added in series with the output of the differential stage. In combination with the parasitics of M5, an additional pole is introduced and can be optimized to cancel the undesired zero. 2.6 The Output Buner To drive the off-chip test equipment, a buffer is needed at the output of the circuit. The buffer used consists of three geometrically sized inverters. In order to set a 50 0 output impedance and minimize signal reflections, a resistor is placed in parallel with the output of the last inverter. Figure 7 shows the complete output buffer circuitry. zyxwvutsrqpo zyxwvutsrqpo 2.5 Test Circuit Essentially, an optical receiver frontend consists of a large gain TIA with current input and voltage output. Unfortunately, most laboratory test signal generators do not produce current waveforms. Therefore, a method to convert a voltage waveform into a known current value intemally to the IC was required in order to be able to test the chip without having to resort to integrating a photodiode in our prototype. A simple method could be to add a large resistance in series with the input voltage signal. One problem with this technique is that large resistances are difficult to manufacture in a CMOS process, and more importantly they have large tolerances. Furthermore, no measurements can be made to confirm the actual magnitude of the current generated. A better approach was proposed by Razavi [7] (Fig. 6). The DC current mirror formed by M II and M 1 2 generates the maximum 3. LAYOUT AND PACKAGING A micrograph of the 2.5Gbls receiver is shown in Fig. 8. The chip was packaged in a 24-pin ceramic flat package (CFP24). A model of the package was used to simulate non-idealities during the design phase. The package was soldered on a two-layerPCBusing 50 0 transmission lines where necessary (Fig. 9). Multiple pins connected to ground are used to avoid ground bouncing and crosstalk. Also, cross-talk between signal lines is reduced by altemating the power supply lines and the signal lines. To minimize reflections, all inputs and outputs of the chip have impedances of 50 O.for matching. A double guard ring is used to protect sensitive parts of the circuit. This protects to a certain extent the sensitive pre-amplifier from substrate noise. The area of the conplete chipis 1.6x1.2mm2. zyxwvut v - 443 Vdd Vdd Vdd zyx zyxwvutsrqpon * * ** Fig. 7: Output buffer stage. zyxwvu 4. MEASUREMENT RESULTS To allow the measurement of intermediate signals in the circuit, two buffers were added. One was placed immediately after the TIA, while the second one was placed after the postgain stages and before the output stage. From these, the gain of the TIA, as well as that of the whole receiver, could be measured. Fig. 8: Micrograph of the complete receiver frontend. The receiver was designed for operation from a 2.0V supply and consumes 65 mA. Without the test circuitry and the buffers, current consumption is 36 mA. Figure 10 shows an eye diagram measurement from a 2.5Gb/s, 2-1 pseudo-random pattern generator. The performance of the circuit is summarized in Table 1. 5. CONCLUSION A CMOS optical receiver frontend was presented. To our knowledge, this is the fastest 0.25ym receiver that has been reported to date operating from a 2V supply. The results clearly indicate that low-power CMOS receivers are capable of handling the fast data rates that are required by modern demands. Fig. 9: Picture of test PCB. I zyxwvutsr REFERENCES M. Pietruszynski, J. M. Steininger, E. J. Swanson, “A 50Mbit/s CMOS Monolithic Optical Receiver,” IEEE J. Solid-state Circuits, vol. 23, pp. 1426-1432, Dec. 1988. M. Nakamura, N.Ishihara, Y. Akazawa, “A 156-Mb/s Optical Receiver for Burst-Mode Transmission,” IEEE J. Solid-state Circuits, vol. 33, pp. 1179-1187, August 1998. M. Ingels, G. van der Plash, J. Crols, and M. Steyaert, “A CMOS 18 THz Ohm 240Mb/s Transimpedance Amplifier and 155 Mb/s LED-driver for Low Cost Optical Fibre Links,” IEEE J. Solid-state Circuits, vol. 29, pp. 15521559, Dec 1994. . . M. Ingels, M. Steyaert, “A 1Gb/s 0.7pm CMOS Optical Receiver with Full Rail-to-Rail Output Swing,” IEEE J. Solid-state Circuits, vol. 34, pp. 971-977, July 1999. [5] A. Tanabe, M. Soda, Y. Nakahara, T. Tamura, K. Yoshida, A. Furukawa, “A Single-Chip 2.4-Gb/s CMOS Optical Receiver IC with Low Substrate Cross-Talk Preamplifier,” IEEE J. Solid-state Circuits, vol. 33, pp. 2148-2153, Dec. 1998. [6] A. Tanabe, M. Soda, Y. Nakahara, T. Tamura, K. Yoshida, A. Furukawa, “A Single-Chip 2.4-Gb/s CMOS Optical Receiver IC with Low Substrate Cross-Talk Preamplifier,” ISSCC Digest of Technical Papers, pp.304-305,1998. [7] B. Razavi, “A 622Mb/s 4.5pAl1-t Hz CMOS Transimpedance Amplifier,” ISSCC Digest of Technical Papers, pp. 162-163, Feb. 2000. v - 444 -15 IIn.! 122, = ~ ” I _ - -- l0U”i zyxw I Ji, _ 134,s- Fig. 10: Measured output eye diagram for a 2.5Gb/s, 2’4 pseudo-random pattern generator. I I zyxw zy Table 1: Summary of receiver’s performance. Maximum data rate II 2.5 Gb/s 1.5 GHz 3 dB cutoff ‘Input current noise density 9pA/& Supply voltage Supply power including test circuit Supply power without test circuit MaximumGain Photodiode Capacitance 2.0 v 137 mW 76mW 250 ohm 215 fF 1 -