Fast Optimization for VCOs Using GSA Algorithm

26th Iranian Conference on Electrical Engineering (ICEE2018) Fast Optimization for VCOs Using GSA Algorithm Marzieh Ghasemi Master Student Department of Electrical Engineering Shahid Bahonar University of Kerman Kerman, Iran, 761694111 Email: [email protected] Afsaneh Mahanipour Master Student Department of Electrical Engineering Shahid Bahonar University of Kerman Kerman, Iran, 761694111 Email: [email protected] Abstract—Finding the optimal size in VLSI circuits such as voltage controlled oscillator is one of the challenging tasks for IC designers. VCO is one of the most widely used blocks in both digital and analog circuits. In this paper, a new approach has been presented to find the optimum size of transistors in order to optimize phase noise and power in ring VCOs. In this work, the gravitational search algorithm (GSA) is employed to optimize the size of transistors for the purpose of reaching the best phase noise and power. Tested differential ring VCOs are simulated in 65nm Cadence Virtuoso by considering the size of transistors extracted from GSA in MATLAB environment. Keywords-voltage controlled oscillator (VCO); gravitational search algorithm (GSA); phase noise; power; optimization I. INTRODUCTION The voltage controlled oscillator (VCO) has been used in many applications for a long time. It is a critical block in high speed Clock and Data Recovery (CDR) circuits for optical communications, frequency dividers of high frequency synthesizers, clock generators of digital circuits, chip to chip interconnects, and many more applications [1-3]. There are two common VCO topologies: ring oscillator based and inductorcapacitor-tank (LC-tank) based [3-5]. A simple ring oscillator is composed of the odd number of delay cells, arranged in a positive feedback loop. The LC-tank based VCOs use a resonant circuit to produce oscillation [4]. In ring VCOs the frequency of oscillation is controlled by some control voltages. Fig. 1 shows a simple ring oscillator with three stages. In comparison with LC-tank based VCOs, ring oscillators are more popular because of their low chip area, wide tuning range, multiple clock generation, design simplicity, and low power consumption. The main drawback of ring oscillators is their low phase noise (in frequency domain) or timing jitter (in time domain) performance because they do not have passive resonant elements [5-8]. The most important factors in the design of the ring oscillators are phase noise, power, tuning range, and frequency of oscillation. Due to the advancement of submicron complementary metal oxide semiconductor (CMOS) technology, and reducing the dimensions of transistors as well as increasing the frequency of oscillation in VCOs, the importance of phase noise in the design of VCOs has 978-1-5386-4916-9/18/$31.00 ©2018 IEEE Mohsen Saneei Associate Professor Department of Electrical Engineering Shahid Bahonar University of Kerman Kerman, Iran, 761694111 Email: [email protected] increased. Especially, the phase noise is reduced in highfrequency applications and by technology scaling. Figure 1. A typical ring oscillator [4]. Several techniques have been proposed to reduce phase noise of oscillators in recent years, including reducing oscillator supply noise [9], injection locking [10], reducing ripples in the VCO control voltage [11], and so on. All these techniques are useful, but in all of them, there is a need to adjust the size of transistors. Generally, in every ring VCO structure, finding the best size of each element is essential. After appropriate calculations and finding the special limits of each element size, achieving the best one can be made by hand using trial an error method. There are some techniques in previous works for optimizing VCOs [12-15]. This article presents a new method to reach the optimal sizes in a simple and fast way with the help of heuristic algorithms. The tested circuit is a ring VCO which is simulated in Cadence Virtuoso. In this paper, we have tried to obtain the best and most optimal phase noise of VCOs with the help of heuristic algorithms to achieve the best phase noise while at the same time achieving the desired power and frequency. According to the presented result in [16], the gravitational search algorithm (GSA) algorithm provides superior results compared with Particle swarm optimization (PSO), Regularized Global Approximation (RGA), and central force optimization (CFO); hence we use GSA algorithm to optimize the transistor sizes. The paper is organized as follows. Section II provides a brief review of Ring VCOs. In section III, the GSA algorithm is introduced. In section IV, the optimization procedure is 26th Iranian Conference on Electrical Engineering (ICEE2018) described. The final results are presented in section V, and finally, we concluded in section VI. II. the input loops. In order to get wider tuning range, two control voltages on the gate are used, vctrl1 and vcrtl2 [17] CIRCUIT UNDER TEST Ring VCOs can be categorized into three groups according to the type of their delay cell: 1) single-ended, 2) fully differential, and 3) pseudo-differential ring VCO. Figure 3. Pseudo-differential delay cell [18] Figure 2. (a) Differential delay cell, (b) four stages and, (c) three stages RING VCO. A single ended ring VCO is composed of a chain of inverters, in the simplest form (Fig. 1). In these VCOs, the number of delay cells must be odd meanwhile the number of delay cells in second and third groups can be the odd or even. Differential delay cells usually include a passive or active load and a differential pairs of NMOS which is used as input that is shown in Fig. 2(a), in this figure, the transistor N3 is the tail current source of this differential delay cell. A differential ring VCO is made by using three or four of this delay cell as shown in Fig. 2(b) and (c). The VCO with three delay cells is used for low power applications, while the one with four delay cells is used to generate quadrature outputs. Note that the connection of the delay cells must satisfy the phase shift of an odd multiple of 180° in both, differential or pseudo-differential RING VCOs [3]. There is a pseudo-differential delay cell in Fig. 3. The difference between fully and pseudo-differential ring VCO is the existence of the tail current source in differential forms, which has the advantage of better common-mode noise rejection and reduced harmonic distortion [3]. The single-ended structure consumes very low power and performs better in the presence of thermal noise in comparison with differential and pseudo-differential RING VCOs. On the other hand, the RING VCOs of differential and pseudodifferential have performed better than single-ended ones in digital circuits, because of better common mode rejection of supply and substrate noise. Furthermore, these two types have in-phase and quadrature outputs which make them to achieve very high-frequency performance [3]. Fully and pseudo-differential RING VCOs can be used in multiple pass structures for higher oscillation frequency. The block diagram of a multiple pass structure is depicted in Fig. 4. The architecture of a pseudo-differential delay cell is shown in Fig. 5. In this delay cell, the differential NMOS pair (N1, N2) works as the primary input loop, while the differential PMOS pair (P1, P2) makes up the secondary input loop. The operating frequency is directly determined by the current passing through Figure 4. Block diagram of three-stage multiple pass ring oscillator [17]. Figure 5. Pseudo-differential delay cell [17]. The circuit of Fig. 5 uses a cross-coupled NMOS pair (N3, N4) to improve the phase noise performance of the oscillator by the positive feedback of this pair and reducing the transition time of the output voltage. Moreover, due to the faster switching speed of NMOS than PMOS transistors, the essential self-balance of the delay cell is provided and prevent the differential outputs from common-mode voltage [17]. Our approach is tested on the circuits of Fig. 3 and Fig. 5 to optimize both single and multiple pass ring VCO structures, and the circuit of Fig. 6 is also tested as a multiple pass four stages ring VCO. III. GRAVITATIONAL SEARCH ALGORITHM GSA is created based on the gravity law and the concept of mass interactions. In this algorithm, there is an isolated system of masses; and these masses are as searcher agents. Using the 26th Iranian Conference on Electrical Engineering (ICEE2018) gravitational force, every mass in the system can see the situation of other masses; and the information can be transfer between different masses by the gravitational force [16]. In this article, the netlist of the simulated circuit is extracted from Cadence. Then its parameters (size of transistors) are given as inputs to the GSA, with the help of MATLAB and HSPICE link (because of the limitations in the version of Cadence which we used, in this work we use HSPICE as a link to join Cadence and MATLAB together). In GSA, these parameters are as masses (agents), and the fitness function is the FOM in equation (1) which can optimize phase noise, power, and frequency simultaneously. Figure 6. Delay cell of [19] The gravitational search algorithm is described in two general steps: a) the formation of a system with discrete time in the problem environment, initial positioning for the objects, governing rules, and setting parameters; b) time passage, the motion of objects and updating of parameters to reach the stopping time [16]. The principle of GSA is shown in Fig. 7. In this algorithm, possible solutions of the problem in hand are considered as objects whose performance is determined by their masses, all these objects attract each other by the gravity force that causes a global movement of the objects towards the objects with heavier masses. The position of each object corresponds to a solution of the problem, determined by a fitness function. The heavy masses, which represented good solutions, move more slowly than lighter ones, this represents the exploitation of the algorithm [20]. The GSA starts with a set of agents, selected at random or based on some criteria, with certain positions and masses representing possible solutions to a problem, and iterates by changing the positions based on some values like fitness function, velocity, and acceleration that gets updated in every iteration [20]. IV. OPTIMIZATION PROCEDURE Tuning the size of transistors in digital blocks is a challenging and time-consuming task for IC designers. When simulating a digital block in Cadence Virtuoso, for example, a simple differential VCO (e.g. the one in Fig. 3) which has a delay cell of seven transistors, because of its differential form, at least size of four transistors should be tuned. If we assumed that the width of each transistor can be from 120nm to 1um, and due to limits of the software, the least variation step is 5nm, for each transistor’s size, there are 176 conditions. So for just four sizes conditions are (176)4, which makes the hand tuning impossible. Although some of these conditions are not suitable for the VCO and is never tested by the designer, the conditions are still outnumbered. Using heuristic algorithms such as GSA can help the designers to solve this problem. Figure 7. The general principle of GSA [16]. = (∆ ) + 10 log − 20log( ∆ ) (1) In the first iteration, parameters are initialized by initial function in GSA. After that, at each iteration, FOM is calculated in HSPICE, according to the size of transistors. Then the new sizes are calculated according to the FOM of the previous iteration (Fig. 8). Figure 8. Optimization procedure 26th Iranian Conference on Electrical Engineering (ICEE2018) Since in the GSA, the masses can be anything in the specified bound, and the ring VCO may not oscillate in some sizes, we add this condition in fitness function of the GSA algorithm. Therefore, for the situation of non-oscillating, the FOM calculated by HSPICE is not a number (NAN), and the previous FOM is replaced with the agents of its own. The next change in the algorithm is about the limit of Cadence that the size of transistors must be multiples of five. The pseudo codes of these changes are as follows: In fitness function: = ()= ()= ( − 1); ( − 1); In main code: ℎ ; ℎ ≤ > = = () ( ); ℎ ℎ V. () ( + 1); TABLE I. Circuit characteristics Measurements in Cadence With optimization (65nm) RESULTS ring VCO with the delay cell of Fig. 3 ring VCO with the delay cell of Fig. 5 ring VCO with the delay cell of Fig. 6 technolgy 90nm 90nm 65nm FOM -144.99 - -157 Freq. (GHz) Power (mW) 1.74 11.59 0.465 9.61 - 10 PN (dBc/Hz) -90.01 -91.06 -110.8 FOM -154.3 -149 -156.5 Power (mW) 1.1 3.7 1.33 PN (dBc/Hz) -73.8 -92.1 -84.65 Freq. (GHz) 11.3 2 4.5 parameters VI. RESULTS The ring VCOs of delay cells of Fig. 3, Fig. 5, and Fig. 6 are simulated in 65nm Cadence Virtuoso by considering the size of their transistors extracted from GSA in MATLAB environment. The GSA agents in these circuits are the width of NMOS transistor N1-N2, and PMOS transistors of P1-P3, and P5 in Fig. 3, NMOS transistors of N1-N2, N3-N4, and PMOS transistors of P1-P2, P3-P4, and P5-P6 in Fig. 5, and NMOS transistors of N1-N2, and PMOS transistors of P1-P4, P2-P5, and P3-P6 in Fig. 6. The up and low limits for these widths are 10u and 200n, respectively. At first, the values of each agent is initialized and according to these values, the FOM is calculated in HSPICE. New values are determined according to the FOM received. In each iteration, a [50 × number of variables] matrix is made as the agent matrix, and a [1 × 50] matrix is calculated as the fitness. After 100 iterations, the best fitness (FOM) is founded by the algorithm. The FOM, power, phase noise (PN) and frequency of the original circuits are depicted in table I and can be compare with the final results of optimized ones in ; Cadence Virtuoso. CONCLUSION This paper presents a new approach to optimize size of transistors in ring oscillators using GSA algorithm. Three circuits are chosen to test this approach. In each circuit one parameter is optimized according to the FOM function. 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