Deep levels in ion implanted field effect transistors on SiC

Solid-State Electronics 47 (2003) 193–198 www.elsevier.com/locate/sse Deep levels in ion implanted field effect transistors on SiC S. Mitra a, M.V. Rao a a,* , K. Jones b, N. Papanicolaou c, S. Wilson d Department of Electrical and Computer Engineering, George Mason University, Fairfax, VA 22030-4444, USA b Army Research Laboratory, Adelphi, MD 20783-1197, USA c Naval Research Laboratory, Washington, DC 20375, USA d Digital DNA Labs, SPS, Motorola, Tempe, AZ 85284, USA Received 19 March 2002; received in revised form 1 May 2002; accepted 6 May 2002 Abstract N-channel FETs fabricated in SiC by ion implantation are studied by using deep level transient spectroscopy (DLTS) to detect deep levels, which may influence device performance significantly. Enhancement mode MISFETs, made on 6H-SiC p-type epilayer using nitrogen source/drain implantation and MESFETs, made on semi-insulating bulk 4H-SiC using nitrogen as the channel and source/drain implantations were used for the DLTS characterization. For both of these devices, effective channel mobility is much smaller than the bulk mobility, due to possible residual implant lattice damage or dielectric/SiC interface traps. For MESFETs five different traps were identified and characterized by activation energies of 0.51, 0.6, 0.68, 0.768 and 0.89 eV above the valence band edge Ev . Five gate dielectric traps and eight interface hole/electron traps were revealed for MISFETs. Gate dielectric traps were distinguished by different activation energies of 0.109, 0.132, 0.15, 0.4 and 0.6 eV. Two shallow gate dielectric/semiconductor interface traps were identified at Ev þ 0:2 eV (hole trap) and Ec  0:362 eV (electron trap). Four deep level traps were found in the activation energy range of 0.6–0.8 eV above the valence band edge with capture cross-section 1016 –1017 cm2 . Other traps were detected at DE ¼ 0:437 and 0.47 eV above Ev . Ó 2002 Elsevier Science Ltd. All rights reserved. Keywords: SiC; Ion implantation; Annealing; Deep levels; MESFET; MISFET; DLTS 1. Introduction Silicon carbide (SiC) is emerging as an important material for fabricating high power [1–4], high temperature [5–7] and high frequency [8,9] devices because it has high thermal conductivity, large saturation electron drift velocity, high electric breakdown field and excellent thermal stability. Ion implantation of donor impurities into SiC is an attractive method for making planar FET devices [10–13]. However, the performance and reliability of these devices still remain a serious problem for industrial applications. This is partially due to channel/insulator or channel/substrate interface * Corresponding author. Tel.: +1-703-993-1612; fax: +1-703993-1601. E-mail address: [email protected] (M.V. Rao). traps, which reduce the mobilities in metal–insulator–semiconductor field-effect-transistors (MISFETs) and metal–semiconductor field-effect-transistors (MESFETs) to values much lower than those measured in bulk material. Deep level transient spectroscopy (DLTS) is an excellent way to evaluate these traps, but only a few studies [14–16] have been performed using this technique on the deep levels in devices made on SiC. In this work interface traps are studied in detail for two FET device structures: MISFET on p-type 6H-SiC and MESFET on semi-insulating (SI) bulk 4H-SiC. For MISFETs the traps at the gate insulator/semiconductor interface and the traps in the gate dielectric material are examined and characterized by their activation energies and respective origins. Similarly for MESFETs, the traps at the channel/substrate interface introduced by the ion implantation process are studied and characterized. 0038-1101/02/$ - see front matter Ó 2002 Elsevier Science Ltd. All rights reserved. PII: S 0 0 3 8 - 1 1 0 1 ( 0 2 ) 0 0 1 9 4 - 6 194 S. Mitra et al. / Solid-State Electronics 47 (2003) 193–198 2. Device fabrication For this study, n-channel MESFETs (W =L ¼ 280 lm/2 lm) were fabricated on bulk (1 0 0 0) Si-face, 8° offaxis, SI 4H-SiC by ion implantation of both the channel and source/drain regions. The channel region and source/drain regions were formed by two separate room temperature ion implantations of nitrogen in box profiles to a depth of 0.3 lm, with a projected volumetric concentration of 6  1017 cm3 for the channel region and 2  1019 cm3 for the source/drain regions. The wafer was capped with AlN to protect the sample surface during annealing. The sample was annealed at 1450 °C for 15 min in an inductively heated furnace with a graphite susceptor and an argon ambient. Ohmic contacts were formed on the source/drain areas by e-beam evaporation and lift-off of Ni (100 nm), followed by a 1200 °C/3 min anneal in vacuum. In order to achieve the required pinch-off voltage, the channel thickness was tailored by reactive ion etching in SF6 using the Ni ohmic contacts as the etching mask. Al gate metallization (100 nm) was done by e-beam evaporation. For other half of the study, large dimension (W =L ¼ 250 lm/200, 100, 50 lm), non-self aligned nchannel enhancement mode MISFETs were fabricated on a p-type epilayer doped to 2:8  1016 cm3 , grown on a pþ 6H-SiC substrate with a 2:3  1018 cm3 doping concentration. Nitrogen ions were implanted (energies 20–360 keV) at room temperature to form source/ drain regions down to a depth of 0.45 lm. The postimplantation anneal was performed at 1400 °C in an argon ambient with the samples encased in a SiC crucible. Both the field oxide (110–130 nm) and oxide– nitride–oxide gate stack (10–20–10 nm) were deposited by the jet vapor deposition (JVD) process, followed by a sequential post-deposition anneal of 900 °C in nitrogen and 950 °C in a water vapor ambient, each for 30 min. Aluminum was used as the contact metal for the gate, source and drain. 3. DLTS setup The detection of deep levels in SiC FETs was performed using a computer controlled fully automated DLTS system from BIORAD. The accuracy of the measurement was improved by compensating and calibrating sample capacitance, by optimizing physical/ experimental parameters and by averaging a large number of temperature transients. The DLTS system used in this study works well in the temperature range of 100 to 550 K. We performed our measurements in the temperature range from 200 to 550 K. It should be noted that since thermal scans were performed below 600 K due to the system limitations, this restricts observation of deep levels to about 1 eV from the band edges. We Fig. 1. Typical C–V characteristics of the (a) 4H-SiC MESFET and (b) 6H-SiC MISFET at room temperature. did not perform measurements below 200 K, as in that regime the capacitance decreases to zero indicating a possible freezing out of the carriers due to large carrier ionization energies of dopants in SiC. We performed the C–V measurement (shown in Fig. 1(a) and (b)) to find out the onset of the depletion at the interface of interest. The capacitance measurements were done at 1 MHz. To observe the deep level traps and their behavior in FETs, we intentionally pushed the relevant interface into depletion by applying the required voltage (as obtained from Fig. 1) at the gate of the FETs and shorting the source and drain to ground. This C–V data can also be used for calculating the trap density. 4. Results and discussion 4.1. DC characteristics MESFETS with the nitrogen implanted channel exhibited pinch-off voltages around 18 V and drain saturation currents 30–40 mA. The bulk mobility of the S. Mitra et al. / Solid-State Electronics 47 (2003) 193–198 195 channel implant was found to be 240 cm2 /V s, while the effective channel mobility of the devices was measured to be less than 58 cm2 /V s [10]. For MISFETs, the channel mobility was observed to be in the range of 40–50 cm2 / V s and the measured saturation drain current was in the range of 70–90 lA depending on the test temperature [12]. Both the channel/SI substrate interface (MESFET) and the insulator/semiconductor interface (MISFET) were characterized and analyzed using C–V and I–V measurements and reported in [10], [11] and [12]. Both of these FETs showed almost stable I–V characteristics even up to a temperature of 400 °C. A significantly low leakage current up to a 20 V gate bias at room temperature offered suitable conditions for performing a capacitance DLTS measurement on both FET structures in this study. 4.2. DLTS measurements For the case of a hole/electron trap, the emission rate is given by the following expression [17]: ep=n ¼ rp=n hvp=n iNV=C expðDE=kT Þ ð1Þ where p and n denote holes and electrons, e is the emission rate, r is the capture cross-section, hvi is the thermal velocity, NV=C is the effective density of states in the valence/conduction band and DE is the energy separation between the trap level and the valence/conduction band. For MESFETs, a Schottky gate reverse bias voltage of 10 V was applied to push the depletion region into the vicinity of the nitrogen implanted channel and SI substrate interface. With a proper choice of the rate window (ranging from 20.48 ms to 2.03 s) several traps in relatively high concentration (Nt  0:01Ns , where Ns is the net carrier concentration) were detected at the channel/substrate interface in the MESFET. Fig. 2(a) and (b) show the DLTS spectrum at a rate window tw ¼ 20:48 ms and the corresponding Arrhenius plots for the traps, respectively. The trap located at Ev þ 0:51 eV (P10 ) could be due to a defect created by nitrogen implantation [14] and the trap at Ev þ 0:6 eV (P20 ) could be related to the deep acceptor level introduced by the V dopant in the SI material [18]. It should be noted that V usually have deep donor level at 1.6 eV above the valence band edge and no such level was observed in this study due to the DLTS system specification which sets 600 K as the upper limit of temperature scan and thus restricts deep level detection limit to about 1 eV from the band edges. Other trap levels are observed at Ev þ 0:68 eV (P30 ), Ev þ 0:768 eV (P40 ) and Ev þ 0:89 eV (P50 ), but their origins are unknown at this time. In addition, we found that the peak amplitude of the DLTS spectrum (corresponding to the peak at Ev þ 0:51 eV) achieved a constant value with the filling pulse time, tp , and it clearly emphasizes the role of a point defect as the origin Fig. 2. (a) DLTS signal and (b) Arrhenius plots of the channel/ substrate interface traps in 4H-SiC MESFET. of this peak. Also, the normalized amplitude of the peaks P10 , P40 and P50 change linearly as a function of reverse bias. This indicates that the defect concentration decreases as the distance from the channel/substrate interface increases. This is verified by double correlation data, which showed a consistently increasing Nt profile towards the channel–substrate interface. This is clearly obvious from Fig. 3, which shows a monotonically increasing trap density for P10 , from channel surface towards the channel/substrate interface and also from inside the bulk substrate towards the channel/substrate interface. These traps that are present at the implanted region/substrate interface strongly influence the channel carrier mobility. Most of these traps fall under residual implant lattice damage or implant–defect complexes category. After post-implant annealing, the majority of unrepaired lattice damage exists at the implant region/ substrate interface. The residual lattice damage at this interface can be in the form of dislocation loops even for low implant doses. These dislocations may not exist in the as-implanted material but can be generated during annealing due to the coalescing of point defects at the implant region/substrate interface because of the stress at that region [19]. Residual lattice damage can be of higher degree for room temperature implantation compared to the elevated temperature implantation. Hence, 196 S. Mitra et al. / Solid-State Electronics 47 (2003) 193–198 Fig. 3. Variation of trap density across the channel/substrate interface for trap P10 (Ev þ 0:51 eV) in 4H-SiC MESFET. ion implantation at an elevated temperature (500 °C and higher) and annealing at a higher temperature need to be done to minimize residual implant lattice damage in SiC [20]. An optimized implantation/annealing temperature is required to achieve a higher mobility value and improved device behavior. For MISFETs a significantly low bulk trap density (6–9  1010 cm2 ) in the gate dielectric and a moderately high trap density (2  104 Ns ) at insulator/semiconductor interface were observed. This lower value of defect concentration in gate dielectric is corroborated by a very low leakage current and very weak temperature dependence of these devices [12]. When measurements for identifying gate dielectric trap charges were performed with the rate window tw ¼ 204:8 ms at a gate voltage of 2 V, one prominent DLTS signal peak was revealed at Ev þ 0:109 eV (OX3) with a capture crosssection of 1017 cm2 . Four other smaller peaks were observed during the gate dielectric trap measurement study and identified as two groups of nearly overlapping gate dielectric trap related shallow level defect centers at DE ¼ 0:4 eV (OX1), 0.6 eV (OX2) above the valence band edge and 0.132 eV (OX4), 0.15 eV (OX5) below the conduction band edge. The DLTS signal and corresponding Arrhenius plots for these traps are shown in Fig. 4(a) and (b), respectively. Several discrete peaks and a few nearly superimposing peaks were recorded in Fig. 5(a) and (b) at the gate dielectric/semiconductor interface in the temperature range of 275–550 K. The deepest defect center was identified as a hole trap at Ev þ 0:845 eV (P8) with a capture cross-section of 2:66  1016 cm2 . Three other deep level traps are detected at Ev þ 0:6 eV (P5), Rv þ 0:713 eV (P6) and Ev þ 0:77 eV (P7) with capture cross-sections 1016 –1017 cm2 . The two trap levels at P5 and P7 nearly match with BE4 and BE5 traps, respectively, as reported earlier by Chen et al. [21] for Fig. 4. (a) DLTS signal and (b) Arrhenius plots of the gate dielectric related traps in 6H-SiC MISFET. n-type 6H-SiC. The same group also reported traps H1 and H2 for p-type 6H-SiC [22], of which H2 was at a similar energy position as that of BE5 (at Ev þ 0:78 eV, associated with a Be-induced complex). But the trap we detected is unlikely to originate from the same defect as that of H2, as the defect associated with H2 is supposed to fade out for a post-implantation annealing temperature above 300 °C. Post-nitrogen ion implantation annealing for MISFETs in this study was performed at 1400 °C. So this trap can be attributed to a vacancy related intrinsic defect configuration [23]. Other hole traps were found at moderately deep levels at Ev þ 0:437 eV (P3) and Ev þ 0:47 eV (P4). Both the P3– P4 and P6–P7 group form two nearly superimposing peaks with flat hump over a temperature range (349– 365 K and 460–493 K). This confirms the presence of nearly overlapping trap centers. The shallow trap detected at Ev þ 0:2 eV (P1) can be related to the L center, entirely or partially formed by an intrinsic SiC defect [24]. Also the electron trap at Ec  Et ¼ 0:362 eV (P2) can be attributed to some intrinsic damage-produced defect [21]. Table 1 presents a comprehensive characteristics of all hole/electron traps found in both FET structures. 197 S. Mitra et al. / Solid-State Electronics 47 (2003) 193–198 Fig. 5. (a) DLTS signal and (b) Arrhenius plots of the gate dielectric/semiconductor interface traps in 6H-SiC MISFET. 5. Summary and conclusion Deep levels in the implanted channel/bulk substrate and semiconductor/insulator interfaces in FETs made on SI 4H-SiC and p-type 6H-SiC, respectively are investigated and the study revealed several deep traps. One hole trap believed to be due to nitrogen implantation is detected with an activation energy of 0.51 eV above the valence band and capture cross-section of about 6:4  1015 cm2 in n-channel 4H SiC MESFET made on SI substrate. DLTS measurement showed that the trap is localized near the channel/substrate interface in a significantly high concentration. One other detected trap at Ev þ 0:6 eV in MESFET could be related to deep acceptor level created by the V dopant in the substrate. In MISFETs made on p-type 6H SiC, five gate dielectric related traps are detected in a relatively low concentration, which supports a significantly low leakage current in these devices. But interestingly, a moderately high defect concentration (2  104 Ns ) is found for hole/ electron related traps at the insulator/semiconductor interface. Three of these traps (0.2 and 0.77 eV above the valence band and 0.362 below the conduction band with Nt 1015 cm3 ) could be related to intrinsic material defects. Origins for most of these traps are not known at this time. Therefore, further experimental investigations are needed to determine the origins of these traps precisely. All these residual implant lattice damage or the implant defect related traps at the relevant interface are believed to play an important role in lowering the channel carrier mobility for FETs. Optimization of the implant/annealing temperatures either by using elevated temperature implantation or by using higher annealing temperatures is expected to yield improved device performance by reducing the damage and trap density due to implantation. This will also justify choosing selective area ion implantation, as the most attractive doping process for SiC FET fabrication. Acknowledgements The authors are grateful to X.W. Wang of Yale University for providing MISFETs and would like to thank R.D. Vispute of University of Maryland and Table 1 Characteristics of hole/electron traps observed in 4H-SiC MESFET and 6H-SiC MISFET structures Device Name of the trap Trap location (eV) Trap density, Nt (cm3 ) Trap cross-section, r (cm2 ) 4H-SiC MESFET 0 P1 P20 P30 P40 P50 Ev þ 0:51 Ev þ 0:60 Ev þ 0:68 Ev þ 0:768 Ev þ 0:89 10 1014 1015 1015 1015 6:4  1015 3:2  1016 8:3  1016 1:2  1015 9:0  1015 6H-SiC MISFET P1 P2 P3 P4 P5 P6 P7 P8 Ev þ 0:20 Ec  0:362 Ev þ 0:437 Ev þ 0:47 Ev þ 0:60 Ev þ 0:713 Ev þ 0:77 Ev þ 0:845 1015 1015 1015 1015 1014 1015 1014 1014 3:2  1015 6:2  1017 5:0  1015 3:2  1016 2:9  1016 1:9  1016 6:0  1017 2:66  1016 16 198 S. Mitra et al. / Solid-State Electronics 47 (2003) 193–198 M. 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