Exclusion Constraints

em Proceedings of the IEEE International Conference on Computer-Aided Design: ICCAD-85. Digest of Technical Papers (Cat. No. 85CH2233-5), Santa Clara, CA, USA, 1985

Cornell University, School of Electrical Engineering (also in Computer Science Department) Abstract: Exclusion constraints are boolean equations that must always be satisfied for an MOS circuit to be adequately modeled by simple switch models. The constraints are generated by a new set of electrical design rules, which are simple enough to be checked automatically. Violating an exclusion constraint does not necessarily mean a circuit is unusable, but careful analysis or analog simulation is needed to ensure digital operation. ...

… of the conference on Design, automation …, 1999

1999

Design methodology of digital circuits is a rapidly changing eld. In the last 20 years, the number of transistors on a single chip has increased from thousands to tens of millions. This sets new demands on the design tools involved, their ability to capture speci cations on a high level, and nally synthesize them into hardware implementations. The introduction of Decision Diagrams DDs has brought new means towards solving many of the problems raised by the increasing complexity of todays designs. In this thesis, we study their use in VLSI CAD and develop a number of novel applications. Incomplete speci cations are inherent to the functionality of almost all digital circuits. We present a design methodology providing a common basis between design validation and logic synthesis, namely the semantics of Kleenean Strong Ternary Logic. This is called upon as commonly used design methodologies, based e.g. on VHDL, are shown to put design correctness in jeopardy. By an extension of DDs, we can e ciently represent and manipulate incompletely speci ed functions. The method p r esented, not only guarantees correctness of the nal circuit, but also o ers potential towards expressing and utilizing incompleteness in ways other methodologies are incapable of. The increasing density and speed of todays target technologies also changes the conditions for logic synthesis; e.g., traditional quality measures based on gate delays are becoming less accurate as delays caused by interconnections are raising their heads. To address this problem we propose methodologies allowing quality measures of the nal circuit to be foreseen and considered throughout the whole synthesis process. In general this is a very hard task. We approach the problem by limiting our synthesis methodologies to those rendering regular layouts such as computational arrays and lattices. The regularity allows us to predict properties of the nal circuit and at the same time, ensure design criteria to be met, e.g., path delays and routability of the nal circuit. In this thesis, we develop new design methodologies and their algorithms. By our experimental results, they are shown to o er signi cant improvements to both state of the art two-level and multi-level based tools in the area of layout driven synthesis. Our minimization methods are b ased o n Pseudo Kronecker Decision Diagrams PKDDs, which are the most general type of ordered bit-level diagrams for switching functions. In the thesis we elaborate on the properties of PKDDs and Ternary PKDDs TPKDDs and develop an e cient minimization method based on local variable exchange for TPKDDs. Furthermore, the problem of PKDD minimization is discussed and a number of di erent strategies are introduced and evaluated; the potential compactness of PKDDs is con rmed. The thesis spans from validation and veri cation of high-level speci cations all the way down to layout driven synthesis, combining logic minimization, mapping and routing to the target architecture at hand. We conclude our work to o er new means towards solving many of the crucial problems occurring along the design process of modern digital circuits.

IEEE Transactions on Circuits and Systems II: Express Briefs, 2006

In this paper, we propose a novel symbolic analysis method for analog behavioral modeling by Boolean logic operations and graph representation. The exact symbolic analysis problem is formulated as a logic circuit synthesis problem where we build a logic circuit which detects whether or not a given symbolic term is a valid product term from a determinant. The logic circuit is represented by binary decision diagrams (BDDs), which can be trivially transformed into zero-suppressed binary decision diagrams(ZBDDs). ZBDDs are essentially determinant decision diagrams (DDDs) representation of a determinant. The proposed BBD-based method gives the circuit logic interpretation of symbolic terms in a determinant and exploits such logic interpretation during the BDD/DDD construction process. It demonstrates an inherent relationship between symbolic circuit analysis and logic synthesis. It is the first symbolic analysis method that is not based on traditional Laplace expansion or topological methods. Experimental results show the speedup of our new method over the existing flat method and its improved analysis capacity over both existing flat and hierarchical symbolic analyzers.

1987

BMAS 2005. Proceedings of the 2005 IEEE International Behavioral Modeling and Simulation Workshop, 2005.

In this paper, we propose a novel symbolic analysis method for analog behavioral modeling by Boolean logic operations and graph representation. The exact symbolic analysis problem is formulated as a logic circuit synthesis problem where we build a logic circuit which detects whether or not a given symbolic term is a valid product term from a determinant. The logic circuit is represented by binary decision diagrams (BDDs), which can be trivially transformed into zero-suppressed binary decision diagrams(ZBDDs). ZBDDs are essentially determinant decision diagrams (DDDs) representation of a determinant. The significance of the new method is that all product terms can be constructed implicitly and simultaneously, in contrast to all previous symbolic analysis methods where symbolic terms are generated explicitly and sequentially by Laplace expansion or topological methods. We further apply the logic synthesis idea to generating symbolic coefficients of s-expanded polynomials and present a method to compute coefficients individually and selectively. Our new approach demonstrates an inherent relationship between circuit simulation and logic synthesis for the first time. Experimental results show the speedup of our new method over the existing flat method and its greater capacity over both existing flat and hierarchical symbolic analyzers.

2009 10th International Symposium on Quality of Electronic Design, 2009

This paper presents a comprehensive investigation of how transistor level optimizations can be used to increase design quality of CMOS logic gate networks. Different properties of transistor networks are used to explain features and limitations of different methods. We describe which figures of merit, including the logical effort, affect the design quality of cell transistor networks. Further, we compare six different approaches that generate transistor networks, including two with guaranteed theoretical minimum length transistor chains. This comparison shows that minimum length chains reduce the logical effort of the networks.

1994

Automatic synthesis of digital circuits has gained increasing importance. The synthesis process consists of transforming an abstract representation of a system into an implementation in a target technology. The set of transformations has traditionally been broken into three steps: high-level synthesis, logic synthesis and physical design. This dissertation is concerned with logic synthesis. More specifically, we study technology mapping, which is the link between logic synthesis and physical design. The object of technology mapping is to transform a technology-independent logic description into an implementation in a target technology. One of teh key operations during technology mapping is to recognize logic equivalence between a portion of the initial logic description and an element of the target technology. We introduce new methods for establishing logic equivalence between two logic functions. The techniques, based on Boolean comparisons, use Binary Decision Diagrams (BDDs). An ...

International Journal on Software Tools for Technology Transfer, 2011

In this paper, a simple approach for detection of adjacent minterms and minimization technique is proposed. The proposed method factorized each minterms and 'don't –care' conditions into a group of maximum three inputs variables and these groups of minterms further coupled as per laws of simplification. The entire detection procedure is described here by mix binary –octal representations. A chart proposed in this paper for easy detection of adjacent minterms with fewer numbers of comparisons and can use for any number of variables. Logic adjacency property is played a significant role for logic circuit simplification. This novel method reduces the complexity of two-level simplification procedure. This paper also represents the performance of octal minterms based combinational circuit minimization technique in comparison with other traditional methods. The paper deals with a method based on representing minterms in the octal system that can be better suited for the manual method of logic minimization and hence may be worth considering.