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A design for digital, dynamic clock deskew

A design for digital, dynamic clock deskew

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408), 2003
Priyadarsan Patra
Abstract
Page 1. 2-4 A Design for Digital, Dynamic Clock Deskew Charles E. Dike, Nasser A. Kurd, Priyadarsan Patra, Javed Barkatuhh Intel Corporation, Hillsboro, OR 97124 ... 35. no. 11, pp 1545-1552. Nov. 2ooO. [3] N. Kurd I. Barkatullah, R.Dizon, T Fletcher, and P. Madland. ...

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