The effect of interface quality on Si / SiO2resonant tunnel diodes

Superlattices and Microstructures, Vol. 30, No. 4, 2001 doi:10.1006/spmi.2001.1008 Available online at http://www.idealibrary.com on The effect of interface quality on Si/SiO2 resonant tunnel diodes T. S ANDU NanoFAB Center, University of Texas at Arlington, Arlington, Texas 76019, U.S.A. R. L AKE Department of Electrical Engineering, University of California, Riverside, CA 92521-0204, U.S.A. W. P. K IRK NanoFAB Center, University of Texas at Arlington, Arlington, Texas 76019, U.S.A. (Received 9 October 2001) The effect of monolayer roughness on the peak-to-valley ratio of Si/SiO2 resonant tunnel diodes is numerically modeled. Atomic scale roughness is shown to be acceptable. As the roughness, that is the island size increases above the atomic scale, the peak-to-valley ratio quickly degrades to less than 5 for 1 nm roughness and less than 2 for 2 nm roughness. c 2001 Academic Press Key words: silicon, oxide, resonant tunnel diode, interface roughness. Integrated circuit applications of resonant tunnel diodes range from low-power tunnelling SRAMs to highspeed logic and mixed-signal circuits. The introduction of RTDs into mixed-signal FET technology such as ADCs and DACs can provide a 5 × increase in speed. RTDs have been integrated with HEMTs and HBTs in InP-, InAs-, and GaAs-based systems [1–4]. There has been considerable effort to introduce RTD technology into Si-based systems [5], but, so far, there exists no satisfactory method of fabricating high-quality, Si-based RTDs. Integrated circuit designs require a minimum peak-to-valley current ratio of approximately 5. One approach that has been explored is to grow a double-barrier Si/SiO2 /Si/SiO2 /Si structure [6, 7]. If the oxide is thermally grown or deposited, the active SiO2 /Si/SiO2 region is amorphous. NDR has been observed in such a structure at 4.2 K. Recent experiments open the possibility of growing crystalline SiOx barriers with a crystalline silicon well. Calculations indicate that a high quality RTD can be fabricated with amorphous barriers as long as the well is crystalline [8]. In this work, we theoretically examine the design requirements on the Si/SiO2 interfaces for fabricating useful RTDs in such a system. The strength of interface roughness scattering is proportional to the square of the conduction band offset at the Si/SiO2 interface. The conduction band offset in this system is approximately three times larger than that in the InP and InAs III–V material systems. We therefore expect that the requirements on the interface quality to be more restrictive than those in the III–V systems. Our theoretical and numerical approach is documented in references [9–11], and the calculations are performed with the NEMO software [12]. For the Si-based system, we use a multiple, decoupled, single-band model. Assuming transport in the (001) direction, a single-band calculation is performed for the two 12 valleys in the (001) and (001) directions and the results are multiplied by two. A second single-band calculation is performed for the 4 14 valleys in the (100), (100), (010) and (010) directions and the results are multiplied 0749–6036/01/100201 + 04 $35.00/0 c 2001 Academic Press 202 Superlattices and Microstructures, Vol. 30, No. 4, 2001 Fig. 1. I –V of Si/SiO2 RTD with 2.17 nm SiO2 barriers. by 4. For both calculations, the SiO2 barriers are given an effective mass of 0.3 [13]. We find that a singleband calculation of single-barrier tunnelling current compares well over the entire 10 order-of-magnitude range of the data in reference [13]. We have calculated the entire current–voltage (I –V ) characteristic resulting from both the 12 and 14 electrons using coherent tunnelling theory. We have calculated the valley current resulting from the 14 electrons using multiple sequential scattering (MSS) theory with four scattering events. We have previously shown that incoherent scattering, when included to all orders in a self-consistent Born approximation and calculated self-consistently with Poisson’s equation, has a negligible effect on the shape, position, and magnitude of the coherent resonant RTD current [11]. Therefore, we restrict our calculation of the incoherent scattering assisted current to the valley region. Also, we have shown that in this region, only a few scattering events are needed in the MSS algorithm to converge with a self-consistent Born calculation [10]. The results for three different RTDs with peak current densities ranging from 0.07 to 1100 A cm−2 are shown in Figs 1–3. All of the RTDs have n-type emitters and collectors doped 1 × 1018 cm−3 seperated from the SiO2 barriers by 2.7 nm undoped spacer layers. The RTD wells are 3 nm for Figs 1 and 2 and 3.5 nm for Fig. 3. The SiO2 barrier thicknesses are 2.17, 1.35 and 1.09 nm, respectively, for Figs 1–3, and the barriers are symmetric. The structure is discretized on the Si atomic lattice spacing of 0.2715 nm. The on-site energy and nearest-neighbor matrix elements for the first and last node of each barrier are averaged in a virtual crystal approximation to represent a layer of 50% Si and 50% SiO2 . The valley current is calculated for three different ranges of roughness at the interface where the average island sizes in the in-plane direction is 0.27, 1 and 2 nm, as labeled in the figures. An exponential correlation model is used [9, 10]. The coherent tunnelling calculations of the entire I –V include the contributions of both the 12 and 14 valleys. The contribution from the 12 valleys is negligible and almost imperceptible on a linear scale. There are two reasons for this. The first is the result of state counting. The current from each equivalent set of valleys is proportional to the two-dimensional (2D) density of states mass, m 2D , times the valley degeneracy, N . For the 14 valleys, N m 2D = 1.73 mo and for the 12 valleys, N m 2D = 0.38 mo . The ratio is 4.5. The second, and more important, reason is that the coherent energy linewidths of the 12 resonances are more than an order of magnitude less the coherent energy linewidths of the 14 resonances. The magnitude of the current is proportional to the coherent energy linewidth. For this reason, we have ignored the 12 valleys for the MSS calculations of the interface roughness assisted valley current. The simulations for all three RTDs show that monolayer roughness with atomic scale islands (0.27 nm) has negligible effect on the valley current. However, when the island size increases to 1 nm, the PVR is Superlattices and Microstructures, Vol. 30, No. 4, 2001 203 Fig. 2. I –V of Si/SiO2 RTD with 1.63 nm SiO2 barriers. Fig. 3. I –V of Si/SiO2 RTD with 1.09 nm SiO2 barriers. degraded below the desired value of 5. When the average island size increases to 2 nm, the PVR is reduced to below 2. Also, the higher current density devices appear to be slightly more sensitive to roughness than the lower current density devices. The strength of the scattering is proportional to the product of the square of the average in-plane island size, 3, times the square of the conduction band offset, δV [9, 10]. Initially, the scattering assisted valley current increases as 32 . However, 3 also provides a momentum cutoff to the in-plane momentum transfer, so that the current increases and saturates as 3 is increased further. Thus, the valley current only increases by a factor of approximately 2 as 3 is increased from 1 to 2 nm. A good estimate of the valley current for 3 lying between 0.27 and 1 nm can be obtained by multiplying the 1 nm curve by 32 . As expected, the overall effect of interface roughness is stronger in the Si/SiO2 system than that found in III–V devices [9]. These results provide design guidelines for fabricating electronic device quality Si/SiO2 -based RTDs. Monolayer, atomic-scale roughness is acceptable. Any increase in the in-plane roughness scale rapidly degrades device performance by reducing the PVR. 1 nm roughness reduces the PVR to below the value of 5 desired for circuit designs. 204 Superlattices and Microstructures, Vol. 30, No. 4, 2001 Acknowledgements—This work was supported in part by NASA grant NCC3-516, and by the Texas Advanced Technology Program under grant No. 003594-00326-1998. References [1] T. P. E. Broekaert, B. Brar, J. P. A. van der Wagt, A. C. Seabaugh, F. J. Morris, T. S. Moise, E. A. Beam III, and G. A. Frazier, IEEE J. Solid-State Circuits 33, 1342 (1998). [2] P. Fay, L. Jiang, Y. Xu, G. H. Bernstein, A. Gonzalez, P. Mazumder, D. H. Chow, and J. N. Schulman, Electron. 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