Fundamentals of digital logic with VHDL design

Fundamentals of DIGITAL LOGIC with VHDL design Chapter 1 Design Concepts • Stephen Brown and Zvonko Vranesic • McGraw-Hill, 2000 • Read as introduction • Slides prepared by P.J. Bakkes (2000) (Edited in June 2003) July 2000 Univ. of Stellenbosch - Digital Systems 144 1 July 2000 Chapter 2 Introduction to Logic Circuits • • • • Univ. of Stellenbosch - Digital Systems 144 2 2.1 Variables and Functions • • • • Reference figure 2.1 Controlled switches Input variable controls a switch Logic expression e.g. L(x) = x describes the output as a function of the input variable • If x = 0, L = 0 and light is off • If x = 1, L = 1 and light is on Digital versus analog circuits Binary logic (Afr. Binêre logika) Switches 0 or 1, ON or OFF, HIGH or LOW July 2000 Univ. of Stellenbosch - Digital Systems 144 3 July 2000 Univ. of Stellenbosch - Digital Systems 144 4 S Battery x = 0 x L Light x = 1 (a) Two states of a switch (a) Simple connection to a battery S S Power supply x x L (b) Symbol for a switch (b) Using a ground connection as the return path July 2000 Figure 2.1 A binary switch 5 July 2000 Figure 2.2 A light controlled by a switch 6 1 Other functions • • • • Power supply Reference figure 2.3 and 2.4 AND (Afr. EN): L(x1,x2) = x1 • x2 OR (Afr. OF): L(x1,x2) = x1 + x2 Other: L(x1,x2,x3) = (x1 + x2) • x3 S S x x 1 2 L Light (a) The logical AND function (series connection) S x Power supply 1 S x L Light 2 (b) The logical OR function (parallel connection) July 2000 Univ. of Stellenbosch - Digital Systems 144 7 July 2000 Figure 2.3 Two basic functions 8 2.2 Inversion (Afr. Inversie) S Power supply x1 S S x3 • • • • • Light L x2 July 2000 Figure 2.4 9 A series-parallel connection L(x) = x’ L(x) = !x L(x) = not x If x = 0, L = 1 If x = 1, L = 0 July 2000 July 2000 x Figure 2.5 10 2.3 Truth tables (Afr. Waarheidstabelle) R Power supply Univ. of Stellenbosch - Digital Systems 144 S An inverting circuit • Reference figures 2.6 and 2.7 • Alternative description of a logic function for combinatorial circuits L 11 July 2000 Univ. of Stellenbosch - Digital Systems 144 12 2 July 2000 Figure 2.6 A truth table for AND and OR 13 July 2000 Figure 2.7 2.4 Logic gates and networks (Afr. Logiese hekke en netwerke) x1 x2 Univ. of Stellenbosch - Digital Systems 144 x1 x2 x1 ⋅ x2 x1 ⋅ x2 ⋅ … ⋅ xn xn • The three basic functions (AND, OR and NOT) can be combined to form logic functions of any complexity. • They can be represented by symbols (Afr. Simbole) (figure 2.8) • A combination of these symbols in a drawing is called a circuit diagram or a schematic (Afr. Stroombaandiagram). Figure 2.9. • Larger circuit uses a network of gates July 2000 14 Three-input AND and OR (a) AND gates x1 x2 x1 x2 x1 + x2 + … + xn x1 + x2 xn (b) OR gates x 15 Figure 2.8 The basic gates x (c) NOT gate 16 2.4.1 Analysis of a Logic Network • Analysis (Afr. analise) x x x – Determine the function of an existing circuit 1 f = (x + x ) ⋅ x 1 2 3 2 3 • Synthesis (Afr. sintese) – Create a new circuit for an application (main task of an engineer!) – Optimization is important • Reference figure 2.10a July 2000 Figure 2.9 An OR-AND function 17 July 2000 Univ. of Stellenbosch - Digital Systems 144 18 3 x x 1→ 1→0→ 0 0→ 0→1→ 1 1 1→1→ 0→ 1 A 0→ 0→0→ 1 0→ 1→0→ 1 Timing diagram (Afr. tyddiagram) f • Reference figure 2.10b • Logic variables can change rapidly with time (up to 1 GHz) B 2 f = x +x ⋅x (a) Network that implements 1 x x f (x , x ) 0 0 1 0 1 1 1 0 0 1 1 1 1 2 1 1 2 2 (b) Truth table for f July 2000 Figure 2.10 a 19 Logic network July 2000 Univ. of Stellenbosch - Digital Systems 144 20 1 x 1 0 Functional equivalent networks x 1 2 0 A 1 0 B 1 0 f 1 0 • Reference figure 2.10d • Function g is functionally equivalent to f, but timing, cost, etc. can be different. • Optimization offunctions (later). Time (c) Timing diagram x x 0→ 0→1→ 1 1 1→ 1→ 0→ 0 0→ 1→0→ 1 1→1→ 0→ 1 g 2 (d) Network that implements g = x + x 1 2 July 2000 Figure 2.10 b Logic network 21 July 2000 2.5 Boolean Algebra 22 Axioms of Boolean Algebra • In 1849 George Boole defined an algebraic description of processes involved in thought and reasoning. • In the late 1930’s Shannon applied this to logic circuits. • Boolean algebra developed into a powerful tool to describe logic circuits. • • • • • • • • July 2000 July 2000 Univ. of Stellenbosch - Digital Systems 144 Univ. of Stellenbosch - Digital Systems 144 23 0• 0=0 1+1=1 1• 1 = 1 0+0=0 0• 1=1• 0=0 1+0=0+1=1 If x = 0, then x’ = 1 If x = 1, then x’ = 0 Univ. of Stellenbosch - Digital Systems 144 24 4 Single variable theorems • • • • • • • • • Duality x• 0=0 x+1 = 1 x• 1=x x+0 = x x• x=x x+x = x x • x’ = 0 x+x’ = 1 x’’ = x July 2000 • Replace all 0’s with 1’s,all 1’s with 0’s, all AND’s with OR’s and all OR’s with AND’s • More later Univ. of Stellenbosch - Digital Systems 144 25 July 2000 Univ. of Stellenbosch - Digital Systems 144 26 Two and three variable properties • Commutative • Absorption – x• y = y • x – x+y = y+x – x+x • y = x – x • (x+y) = x • Associative • Combining – x • (y • z) = (x • y) • z – x+(y+z) = (x+y)+z – x • y + x • y’ = x – (x+y) • (x+y’) = x • Distributive • x + x’ • y = x + y • x • (x’ + y) = x • y – x • (y+z) = x • y + x • z – x+(y • z) = (x+y) • (x+z) July 2000 Univ. of Stellenbosch - Digital Systems 144 27 July 2000 29 July 2000 Univ. of Stellenbosch - Digital Systems 144 28 DeMorgan’s Theorem • (x • y)’ = x’ + y’ • (x+y)’ = x’ • y’ Next page: prove by perfect induction July 2000 Univ. of Stellenbosch - Digital Systems 144 Figure 2.11 Proof of DeMorgan’s theorem 30 5 Applying identities (a) Constant 1 (b) Constant 0 x x x (c) Variable x x (d) x • See examples 2.1 and 2.2 x y x (e) x ⋅ y y (f) x + y x x y y z (g) x ⋅ y July 2000 Univ. of Stellenbosch - Digital Systems 144 31 July 2000 x x y x y z z (a) x (d) x ⋅ y x y x y z (e) x ⋅ z x⋅y x⋅y y x x y z z (c) x ⋅ ( y + z ) (f) x ⋅ y + x ⋅ z y z z x y 32 y z x⋅z x⋅z z (b) y + z x x z x y x⋅y+z (h) The Venn diagram representation Figure 2.12 y x y z z y⋅z x⋅y+x⋅z x y z x⋅y+x⋅z+y⋅z July 2000 Figure 2.13 Verification of the distributive property 33 Figure 2.14 2.5.2 Alternative Notation Verification of x ⋅ y + x ⋅ z + y ⋅ z = x ⋅ y + x ⋅ z 34 2.5.3 Precedence of Operators • AND: x∧ y • OR: x∨ y July 2000 July 2000 • NOT, AND and then OR Univ. of Stellenbosch - Digital Systems 144 35 July 2000 Univ. of Stellenbosch - Digital Systems 144 36 6 2.6 Synthesis using AND, OR and NOT gates • Synthesis: generate a circuit that implements a function from specifications. • Simple example: July 2000 Univ. of Stellenbosch - Digital Systems 144 37 July 2000 Figure 2.15 38 A function to be synthesized x1 x2 Example • • • • • • • • f Reference figure 2.15 and 2.16 Concept of sum-of-products Simplify expression using theorems f(x1,x2) = x1 • x2 + x1’ • x2’ + x1’ • x2 = x1 • x2 + x1’ • x2’ + x1’ • x2 + x1’ • x2 = x1 • x2 + x1’ • x2 + x1’ • x2’ + x1’ • x2 = (x1 + x1’) • x2 + x1’ • (x2’ + x2) = x2 + x1’ July 2000 Univ. of Stellenbosch - Digital Systems 144 (a) Canonical sum-of-products x1 f x2 (b) Minimal-cost realization 39 July 2000 Figure 2.16 Two implementations of a function 40 2.6.1 Sum-of-Products and Product-of-Sums • Introduce more formal terms • Minterm: for a function of n variables, a product term in which each of the n variables appears once, is called a minterm. • Sum-of-Products form: A function f can be represented by an expression that is a logical sum of sum of the minterms. • See figure 2.17 July 2000 Figure 2.17 Three-variable Minterms and Maxterms 41 July 2000 Univ. of Stellenbosch - Digital Systems 144 42 7 Another example • See figure 2.18 and 2.19 • f(x1,x2,x3) = x1’ • x2’ • x3 + x1 • x2’ • x3’ + x1 • x2’ • x3 + x1 • x2 • x2’ • This form is not minimal, but can be reduced to: f = x2’ • x3 + x1 • x3’ • Alternative forms: – f= July 2000 Figure 2.18 A three-variable function 43 July 2000 Univ. of Stellenbosch - Digital Systems 144 44 8 2.7 Design examples 2.7.1 Three-way light control • Design process: – Specification of solution to a problem in words – Formal specification with truth table – Synthesis – Implementation – Testing – Possible iteration July 2000 Univ. of Stellenbosch - Digital Systems 144 49 • • • • • • Three doors in room each with switch One or three on switches must turn light on See truth table in figure 2.20 f = m1 + m2 + m4 + m7 or f = M0• M3 • M5 • M6 See figure 2.21. For implementation July 2000 Univ. of Stellenbosch - Digital Systems 144 50 f x 1 x 2 x 3 (a) Sum-of-products realization July 2000 Figure 2.20 51 Truth table for a three-way light controller July 2000 Figure 2.21 SOP implementation of the three-way light controller 52 2.7.2 Multiplexer Circuit x 3 x 2 x 1 • Circuit often used in digital and computer designs • Switches one of multiple sources of data to a single destination • See figure 2.22 f (b) Product-of-sums realization July 2000 Figure 2.21 POS implementation of the three-way light controller 53 July 2000 Univ. of Stellenbosch - Digital Systems 144 54 9 s x1 x2 f (s, x1, x2) 000 0 001 0 010 1 011 1 100 0 101 1 110 0 111 1 2.8 Introduction to CAD tools x1 f • Lecturers comment: Read only at this stage • 2.8.1 Design Entry s x2 (a)Truth table – Truth table (figure 2.23) – Schematic entry (figure 2.24) – Hardware description languages (HDL) (b) Circuit s s x1 0 x2 1 f (c) Graphical symbol July 2000 July 2000 Figure 2.22 Figure 2.23 f (s, x1, x2) 0 x1 1 x2 • 2.8.2 Synthesis • 2.8.3 Functional simulation (d) More compact truth-table representation Multiplexer Screen capture of the Waveform Editor 55 July 2000 57 July 2000 Univ. of Stellenbosch - Digital Systems 144 Figure 2.24 Screen capture of the Graphic Editor 56 58 Design conception 2.9 Introduction to VHDL DESIGN ENTRY Schematic capture Truth table Simple synthesis (see section 2.8.2) VHDL • IEEE standard 1164 • Used for the algorithmic description of digital circuits • Used for synthesis and simulation • See figures 2.27 to 2.31 Translation Merge INITIAL SYNTHESIS TOOLS Boolean equations Functional simulation No Design correct? Yes Logic synthesis, physical design, timing simulation (see section 4.12) July 2000 Figure 2.25 The first stages of a CAD system 59 July 2000 Univ. of Stellenbosch - Digital Systems 144 60 10 x1 x2 f x3 July 2000 Figure 2.26 A simple logic function and corresponding VHDL code 61 July 2000 Figure 2.30 VHDL code for a four-input function 62 x1 x3 f x2 g x4 July 2000 Figure 2. 31 Logic circuit for four-input function 63 11