CMOS Imager Has Better Cross-Talk and Full-Well Performance

Electronics/ Computers SpaceCube 2.0: An Advanced Hybrid Onboard Data Processor Two FPGAs maximize data and computing performance while minimizing physical size. Goddard Space Flight Center, Greenbelt, Maryland The SpaceCube 2.0 is a compact, highperformance, low-power onboard processing system that takes advantage of cuttin g-edge h ybrid ( CPU/ FPGA/ DSP) processing elements. The SpaceCube 2.0 design concept includes two commercial Virtex-5 field-programmable gate array ( FPGA) parts protected by “radiation hardened by software” technology, and possesses exceptional size, weight, and power characteristics [5×5×7 in., 3.5 lb (≈12.7×12.7×17.8 cm, 1.6 kg) 5–25 W, depending on the application’s required clock rate]. The two Virtex-5 FPGA parts are implemented in a unique back-toback con figuration to maximize data transfer and computing performance. Draft computing power specifications for the SpaceCube 2.0 unit include four PowerPC 440s ( 1100 DMIPS each) , 500+ DSP48Es ( 2×580 GMACS) , 100+ LVDS high-speed serial I/ Os ( 1.25 Gbps each) , and 2×190 GFLOPS single-precision ( 65 GFLO PS double-precision ) floatin g point per formance. The SpaceCube 2.0 includes PROM memory for CPU boot, health and safety, and basic command and telemetry functionality; RAM memor y for program execution ; an d FLASH/ EEPROM memory to store algorith ms an d application code for th e CPU, FPGA, and DSP processing elements. Program execution can be reconfigured in real time and algorithms can be updated, modified, and/ or replaced at any point during the mission. Gigabit Ethernet, Spacewire, SATA and highspeed LVDS serial/ parallel I/ O chan- nels are available for instrument/ sensor data ingest, and mission-unique instrument inter faces can be accommodated using a compact PCI ( cPCI) expansion card inter face. The SpaceCube 2.0 can be utilized in NASA Earth Scien ce, H elio/ Astrophysics and Exploration missions, and Department of Defense satellites for onboard data processing. It can also be used in commercial communication and mapping satellites. T his work was done by Michael Lin, T homas Flatley, John Godfrey, Alessandro Geist, Daniel Espinosa, and David Petrick of Goddard Space Flight Center. Further information is contained in a T SP (see page 1). GSC-15760-1 CMOS Imager Has Better Cross-Talk and Full-Well Performance Electrically isolated areas containing imaging and readout structures are optimized separately. NASA’s Jet Propulsion Laboratory, Pasadena, California A complemen tary metal oxide/ semicon d u ctor ( CMO S) im age d etector n ow un dergoin g developmen t is design ed to exh ibit less cross-talk an d greater full-well capacity th an do prior CMO S image detectors of th e same type. Imagers of th e type in question are design ed to operate from low-voltage power supplies an d are fabricated by processes th at yield device features h avin g dimen sion s in th e deep submicron ran ge. Because of the use of low supply poten tials, m axim um in tern al electric fields and depletion widths are correspon din gly limited. In turn , th ese limitations are responsible for increases in cross-talk and decreases in charge-handlin g capacities. Moreover, for small pixels, lateral depletion can n ot be extended. These adverse effects are even more accentuated in a back-illuminated CMOS imager, in which photogenerated charge carriers must travel across the entire thickness of the device. NASA Tech Briefs, February 2011 The figure shows a partial cross section of the structure in the device layer of the present developmental CMOS imager. ( In a practical imager, the device layer would sit atop eith er a h eavily doped silicon substrate or a thin silicon oxide layer on a silicon substrate, not shown here.) The imager chip is divided into two areas: area C, which contains readout circuits and other electronic circuits; and area I, which contains the imaging ( photodetector and photogenerated-charge-collecting) pixel structures. Areas C and I are electrically isolated from each other by means of a trench filled with silicon oxide. Th e electrical isolation between areas C an d I makes it possible to apply differen t supply poten tials to th ese areas, th ereby en ablin g optimization of th e supply poten tial an d associated design features for each area. More specifically, metal oxide semicon ductor fieldeffect tran sistors ( MO SFETs) th at are typically in cluded in CMO S imagers n ow reside in area C an d can remain un ch an ged from establish ed design s an d operated at supply poten tials prescribed for th ose design s, wh ile th e dopin gs an d th e lower supply poten tials in area I can be tailored to optimize imager per forman ce. In area I, th e device layer in cludes an n +-d op ed silicon layer on wh ich is grown an n –-doped silicon layer. A p –doped silicon layer is grown on top of th e n –-doped layer. Th e total imagin g device th ickn ess is th e sum of th e th ickn ess of th e n +, n , an d p – layers. A pixel ph otodiode is formed between a surface n + implan t, a p implan t un dern eath it, th e aforemen tion ed p – layer, an d th e n an d n + layers. Adjacen t to th e diode is a gate for tran sferrin g ph otogen erated ch arges out of th e ph otodiod e an d in to a floatin g d iffu sion formed by an implan ted p + layer on an implan ted n -doped region . Metal con tact pads are added to th e back-side for providin g back-side bias. 9 Deplet ion Region p Gat e n n+ p+ n Trench Filled Wit h Silicon Oxide C C I p– n+ n– M et al Cont act Pads This Simplified Cross Section (not t o scale) show s essent ial f eat ures of t he development al device st ruct ure. A key f eat ure of t he st ruct ure is t he deplet ion region (indicat ed by t he dashed out line) along t he ent ire n –/p – junct ion. The n – and p – doping concentrations are chosen such that everywhere in area I, a depletion region exists between the n – and p – layers. This depletion region enables electrical isolation between the several front (top) doped regions and the back (bottom) n and n + layers. Consequently, the bias potentials applied to the top of the diode and the adjacent transfer gate can be different from the bias applied to the bottom. Thus, while CMOS-compatible potentials (e.g., 3 V) are applied at the top, the bottom of the structure can be biased to greater potential (e.g., 5 V) via the back-side metal contact pads to completely deplete the photodiode. The re- sulting depletion region is indicated in the figure as the area enclosed by the dashed outline. Complete depletion of the photodiode results in collection of charge carriers (holes in this case) under the influence of an electric field, and hence, a significant reduction of cross-talk. Complete depletion also increases the chargestorage volume, and, hence, the chargehandling capacity. Thus, the structure described here provides for large depletion width around each photodiode, independent of the CMOS power-supply voltage and pixel size. This work was done by Bedabrata Pain and Thomas J. Cunningham of Caltech for NASA’s Jet Propulsion Laboratory. Further information is contained in a T SP (see page 1). In accordan ce with Pu blic Law 96-517, the con tractor has elected to retain title to this in v en tion . In qu iries con cern in g rights for its commercial u se shou ld be addressed to: Innovative Technology Assets Management JPL Mail Stop 202-233 4800 Oak Grove Drive Pasadena, CA 91109-8099 E-mail: [email protected] Refer to NPO-45964, volume and number of this NASA Tech Briefs issue, and the page number. High-Performance Wireless Telemetry This technology is applicable to any kind of aviation or power-plant turbine testing. John H. Glenn Research Center, Cleveland, Ohio Prior technology for machinery data acquisition used slip rings, FM radio communication, or non-real-time digital commun ication . Slip rin gs are often noisy, require much space that may not be available, and require access to the shaft, which may not be possible. FM radio is not accurate or stable, and is limited in the number of channels, often with channel crosstalk, and intermittent as the shaft rotates. Non-real-time digital communication is very popular, but complex, with long development time, and objections from users who need continuous waveforms from many channels. This innovation extends the amount of information conveyed from a rotating machine to a data acquisition system 10 wh ile keepin g th e developmen t time short and keeping the rotating electronics simple, compact, stable, and rugged. The data are all real time. The product of the number of channels, times the bit resolution, times the update rate, gives a data rate higher than available by older methods. The telemetry system consists of a data-receiving rack that supplies magnetically coupled power to a rotating instrument amplifier ring in the machine being monitored. The ring digitizes the data and magnetically couples the data back to the rack, where it is made available. The transformer is generally a ring positioned around the axis of rotation with one side of the transformer free to rotate and the other side held stationary. The windings are laid in the ring; this gives the data immunity to any rotation that may occur. A medium-frequency sine-wave power source in a rack supplies power through a cable to a rotating ring transformer that passes the power on to a rotating set of electronics. The electronics power a set of up to 40 sensors and provides instrument amplifiers for the sensors. The outputs from the amplifiers are filtered and multiplexed into a serial ADC. The output from the ADC is connected to another rotating ring transformer that con veys th e serial data from th e rotatin g section to the stationary section. From there, a cable conveys the serial data to NASA Tech Briefs, February 2011