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Bogong Su

William Paterson University, Computer Science, Faculty Member

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Papers by Bogong Su

Some experiments in global microcode compaction

ACM SIGMICRO Newsletter, 1985

Global microcode compaction is an open problem in firmware engineering. Although Fisher's tra... more Global microcode compaction is an open problem in firmware engineering. Although Fisher's trace scheduling method may produce significant reductions in the execution time of compacted microcode, it has some drawbacks. There have been four methods. Tree, SRDAG, ITSC , and GDDG, presented recently to mitigate those drawbacks in different ways. The purpose of the research reported in this paper is to evaluate these new methods. In order to do this, we have tested the published algorithms on several unified microcode sequences of two real machines and compared them on the basis of the results of experiments using three criteria: time efficiency, space efficiency, and complexity.

Decomposition and allocation of flat-structured problems

[1991] Proceedings The Fifteenth Annual International Computer Software & Applications Conference

A classification is made of the applications of distributed problem solving (DPS) into hierarchic... more A classification is made of the applications of distributed problem solving (DPS) into hierarchically structured problems (HP) and flatly structured problems (FP). A formal description is given of an FP and its solving system. An improved problem decomposition (IPD) algorithm is presented by which a problem is decomposed in size into several tasks of identical property and each task is allocated to a proximate agent. Heuristic state space search is used to balance load. Experiments on a distributed transport dispatching system, DTD-1, indicate that this algorithm is effective and superior.<<ETX>>

A Study of Machine Learning Inference Benchmarks

Machine learning (ML) is becoming a powerful tool for a variety of applications where artificial ... more Machine learning (ML) is becoming a powerful tool for a variety of applications where artificial intelligence solutions are required. A ML benchmark is a standard suite to measure, evaluate and compare the performance and efficiency of ML systems. This study analyzes the benchmark results from two famous benchmarks MLMark and MLPerf to provide a basis of comparison between both benchmarks as well as to provide recommendations on computer architectures to utilize for ML inferencing. Lastly, special emphasis is placed on the performance of edge AI devices.

Instruction Level Loop De-optimization

Studies in Computational Intelligence, 2015

Instruction level loop optimization has been widely used in modern compilers. Decompilation—the r... more Instruction level loop optimization has been widely used in modern compilers. Decompilation—the reverse of compilation—has also generated much interest for its applications in porting legacy software written in assembly language to new architectures, re-optimizing assembly code, and more recently, in detecting and analyzing malware. However, little work has been reported on loop decompilation at instruction level. In this paper, we report our work on loop de-optimization at instruction level. We demonstrate our approach with a practical working example and carried out experiments on TIC6x, a digital signal processor with a compiler supporting instruction level parallelism. The algorithms developed in this paper should help interested readers gain insight especially in the difficult tasks of loop rerolling and software de-pipelining, the necessary steps to decompile loops at instruction level.

Nortel Networks

Performance measurement is essential for the users and manufacturers of DSP processors. However, ... more Performance measurement is essential for the users and manufacturers of DSP processors. However, due to the diversity and complexity of DSP architectures and the large overhead of DSP compilers, metrics that effectively and objectively measure and compare the performance of various DSP processors from different manufacturers remain elusive. We introduce in this paper a new concept of instruction group where instructions in an instruction group are executed in parallel. Among other parameters such as the total execution time and the instruction count, we define the instruction group count of a DSP program as a new metric and study the impact of the group count as one of the parameters on various performance aspects of a DSP processor. Extensive experiments have been conducted by compiling the C code of a collection of DSP kernels and application programs and then executing the compiled code on several popular DSP processors. Both static and dynamic experimental data are analyzed and ...

The Architecture of a Distributed Knowledge Base System

IFIP Working Conference on Database Semantics, 1988

Software performance prediction at source level

2017 IEEE 15th International Conference on Software Engineering Research, Management and Applications (SERA)

Impact of Source-Level Loop Optimization on DSP Architecture Design

How to select an architecture which has better performance cost ratio, how to design a balanced a... more How to select an architecture which has better performance cost ratio, how to design a balanced architecture which can fit most DSP programs and how to generate a custom-fit DSP processor are important topics now. This paper presents a novel methodology based on source-level loop optimization which can avoid expensive retargetable compiler and simulator, and exhaustive experiments.

Distributed problem solving system for transport dispatching

Proceedings of the third international conference on Industrial and engineering applications of artificial intelligence and expert systems - IEA/AIE '90, 1990

ABSTRACT This paper introduces the architecture of a distributed problem solving system for trans... more ABSTRACT This paper introduces the architecture of a distributed problem solving system for transport dispatching, presents two algorithms for problem decomposition and task allocation and a cooperation mechanism based on meta-level communication, and evaluates both the architecture and algorithms by experiments on a prototype system.

Software de-pipelining technique

Source Code Analysis and Manipulation, Fourth IEEE International Workshop on

Performance Analysis of Digital Signal Processors Using SMV Benchmark

World Academy of Science, Engineering and Technology, International Journal of Electrical, Computer, Energetic, Electronic and Communication Engineering, 2009

Unlike general-purpose processors, digital signal processors (DSP processors) are strongly applic... more Unlike general-purpose processors, digital signal processors (DSP processors) are strongly application-dependent. To meet the needs for diverse applications, a wide variety of DSP processors based on different architectures ranging from the traditional to VLIW have been introduced to the market over the years. The functionality, performance, and cost of these processors vary over a wide range. In order to select a processor that meets the design criteria for an application, processor performance is usually the major concern for digital signal processing (DSP) application developers. Performance data are also essential for the designers of DSP processors to improve their design. Consequently, several DSP performance benchmarks have been proposed over the past decade or so. However, none of these benchmarks seem to have included recent new DSP applications. In this paper, we use a new benchmark that we recently developed to compare the performance of popular DSP processors from Texas ...

Comparing DSP Software Performance Prediction Models at Source Code Level — From Analytical to Statistical

Journal of Software

Efficient performance prediction at source code level is essential in reducing the turnaround tim... more Efficient performance prediction at source code level is essential in reducing the turnaround time of software development, particularly when the source code is subject to changes due to modification of problem specification. In this paper, we investigate and compare five performance prediction models from practical standpoint to determine the usefulness of these models. To verify the effectiveness of these models, we select a set of functions from PHY DSP Benchmark and TIC64 DSP processor for experiment. Comparing the predicted performance to the actual measured execution time, we observed that the relative prediction error generated from two of the five models are low and can thus be used for practical purposes.

An preliminary evaluation of trace scheduling for global microcode compaction

Fisher has recently described a new procedure for global microcode compaction which he calls "tra... more Fisher has recently described a new procedure for global microcode compaction which he calls "trace scheduling." We have implemented this procedure and tested it on several microcode sequences. We report in this correspondence on the relative effectiveness of local compaction, manual compaction, and trace scheduling on these sequences.

TST � An algorithm for global microcode compaction with timing constraints

Jcst, 1991

ABSTRACT Existing global microcode compaction approaches have all assumed a target architecture t... more ABSTRACT Existing global microcode compaction approaches have all assumed a target architecture that has microoperation conflicts and data dependencies as the two fundamental compaction constraints. However, new practical micromachine features demand that the timing constraint be introduced into the traditional compaction model to guarantee compaction correctness. This paper starts by an analysis on the nature of timing constraints, then modifies the rules for microoperation motions, presents an algorithm, TST, based on Trace Scheduling, for global compaction under timing constraints, and finally shows results of experiments.

A New Source-Level Benchmarking for DSP Processors

Performance measurement is essential for the users and manufacturers of DSP processors. However, ... more Performance measurement is essential for the users and manufacturers of DSP processors. However, due to the diversity and complexity of DSP architectures and the large overhead of DSP compilers, metrics that effectively and objectively measure and compare the performance of various DSP processors from different manufacturers remain elusive. We propose a new approach to DSP benchmarking with a new CPU time equation. Using a narrow spectrum benchmarking technique, we design special benchmark programs in C language to evaluate various aspects of DSP architecture such as the number of registers, number of function units, calling convention, the impact of hardware loop control, and load latency. Extensive experiments are conducted on several modern DSP processors including Texas Instruments' TIC62, TIC55 and StarCore's SC series. Both dynamic and static measurements on the benchmark programs are taken and the parameters in the new CPU time equation are used as metrics to analyze and evaluate the performance of various processors. It is noted that our approach does not require handoptimized assembly code. Also, the experimental results provide some useful information regarding how various aspects of the architectural design of a DSP processor are related to its performance.

Performance Analysis of Digital Signal Processors Using SMV Benchmark

Unlike general-purpose processors, digital signal processors (DSP processors) are strongly applic... more Unlike general-purpose processors, digital signal processors (DSP processors) are strongly application-dependent. To meet the needs for diverse applications, a wide variety of DSP processors based on different architectures ranging from the traditional to VLIW have been introduced to the market over the years. The functionality, performance, and cost of these processors vary over a wide range. In order to select a processor that meets the design criteria for an application, processor performance is usually the major concern for digital signal processing (DSP) application developers. Performance data are also essential for the designers of DSP processors to improve their design. Consequently, several DSP performance benchmarks have been proposed over the past decade or so. However, none of these benchmarks seem to have included recent new DSP applications. In this paper, we use a new benchmark that we recently developed to compare the performance of popular DSP processors from Texas Instruments and StarCore. The new benchmark is based on the Selectable Mode Vocoder (SMV), a speech-coding program from the recent third generation (3G) wireless voice applications. All benchmark kernels are compiled by the compilers of the respective DSP processors and run on their simulators. Weighted arithmetic mean of clock cycles and arithmetic mean of code size are used to compare the performance of five DSP processors. In addition, we studied how the performance of a processor is affected by code structure, features of processor architecture and optimization of compiler. The extensive experimental data gathered, analyzed, and presented in this paper should be helpful for DSP processor and compiler designers to meet their specific design goals.

A Study of Performance Measurement of DSP Processors

Performance measurement is essential for the users and manufacturers of DSP processors. However, ... more Performance measurement is essential for the users and manufacturers of DSP processors. However, due to the diversity and complexity of DSP architectures and the large overhead of DSP compilers, metrics that effectively and objectively measure and compare the performance of various DSP processors from different manufacturers remain elusive. We introduce in this paper a new concept of instruction group where instructions in an instruction group are executed in parallel. Among other parameters such as the total execution time and the instruction count, we define the instruction group count of a DSP program as a new metric and study the impact of the group count as one of the parameters on various performance aspects of a DSP processor. Extensive experiments have been conducted by compiling the C code of a collection of DSP kernels and application programs and then executing the compiled code on several popular DSP processors. Both static and dynamic experimental data are analyzed and

New DSP Benchmark based on Selectable Mode Vocoder (SMV)

Cdes, 2006

Digital signal processing (DSP) industry has been growing rapidly over the past few years; it rem... more Digital signal processing (DSP) industry has been growing rapidly over the past few years; it remains the technology driver for the recovering semiconductor industry. Performance evaluation is essential for the users and manufacturers of DSP processors. Since DSP application programs become larger and more complicated, people need new benchmarks for performance evaluation of different DSP processors. We build a new DSP benchmark based on Selectable Mode Vocoder (SMV), a speech-coding program from the 3G wireless applications. Our new DSP benchmark, called SMV benchmark, consists of eight kernel functions. In this paper, we introduce the criteria of selecting kernels and our methodology to build SMV benchmark. We also discuss the characteristics and static analysis of the kernels.

Assembly Code Conversion of Software-pipelined Loop between two VLIW DSP Processors

In order to fully utilize the instruction level parallelism of VLIW DSP processors, DSP programs ... more In order to fully utilize the instruction level parallelism of VLIW DSP processors, DSP programs have to be optimized by software pipelining. Software pipelining has been studied for many years and widely implemented in optimizing compilers. However, due to the rearrangement of the original instructions, it is often very difficult to re-use or port the code of a software-pipelined loop to other processors. In this paper we present a practical approach to solve this problem. Our approach involves the following steps: (1) Using a newly developed software de-pipelining algorithm to convert the assembly code of a software-pipelined loop to a semantically equivalent sequential loop; (2) Using our pattern mapping technique to convert the sequential loop to a machineindependent high-level intermediate code; (3) Converting the machine-independent intermediate code to that of the target machine; (4) Feed the intermediate code of the target machine to the backend of the compiler of the target machine to obtain the optimized assembly code of the target DSP processor We have conducted a series of experiments using the popular TIC62 as the source DSP and SC140 as the target DSP. Six DSP kernel programs have been selected for the experiments. To verify the validity of the converted code, we have used a simulator to compare the results of various steps in the conversion process. All the results of our experiments show that the converted assembly code of target DSP processor are correct with comparable performance to the assembly code directly generated by compiling the source code with the optimizing compiler of the target machine.

Code Migration from Conventional DSPs to VLIW DSPs

It is a challenge to convert the existing conventional DSPs&amp;#x27; assembly code to that o... more It is a challenge to convert the existing conventional DSPs&amp;#x27; assembly code to that of VLIW DSPs&amp;#x27;. We propose a new code migration method, which performs semantically equivalent code conversion. Key issues such as semantics of the conventional DSP code, specialized addressing modes and different data types are discussed.

Some experiments in global microcode compaction

ACM SIGMICRO Newsletter, 1985

Global microcode compaction is an open problem in firmware engineering. Although Fisher's tra... more Global microcode compaction is an open problem in firmware engineering. Although Fisher's trace scheduling method may produce significant reductions in the execution time of compacted microcode, it has some drawbacks. There have been four methods. Tree, SRDAG, ITSC , and GDDG, presented recently to mitigate those drawbacks in different ways. The purpose of the research reported in this paper is to evaluate these new methods. In order to do this, we have tested the published algorithms on several unified microcode sequences of two real machines and compared them on the basis of the results of experiments using three criteria: time efficiency, space efficiency, and complexity.

Decomposition and allocation of flat-structured problems

[1991] Proceedings The Fifteenth Annual International Computer Software & Applications Conference

A classification is made of the applications of distributed problem solving (DPS) into hierarchic... more A classification is made of the applications of distributed problem solving (DPS) into hierarchically structured problems (HP) and flatly structured problems (FP). A formal description is given of an FP and its solving system. An improved problem decomposition (IPD) algorithm is presented by which a problem is decomposed in size into several tasks of identical property and each task is allocated to a proximate agent. Heuristic state space search is used to balance load. Experiments on a distributed transport dispatching system, DTD-1, indicate that this algorithm is effective and superior.<<ETX>>

A Study of Machine Learning Inference Benchmarks

Machine learning (ML) is becoming a powerful tool for a variety of applications where artificial ... more Machine learning (ML) is becoming a powerful tool for a variety of applications where artificial intelligence solutions are required. A ML benchmark is a standard suite to measure, evaluate and compare the performance and efficiency of ML systems. This study analyzes the benchmark results from two famous benchmarks MLMark and MLPerf to provide a basis of comparison between both benchmarks as well as to provide recommendations on computer architectures to utilize for ML inferencing. Lastly, special emphasis is placed on the performance of edge AI devices.

Instruction Level Loop De-optimization

Studies in Computational Intelligence, 2015

Instruction level loop optimization has been widely used in modern compilers. Decompilation—the r... more Instruction level loop optimization has been widely used in modern compilers. Decompilation—the reverse of compilation—has also generated much interest for its applications in porting legacy software written in assembly language to new architectures, re-optimizing assembly code, and more recently, in detecting and analyzing malware. However, little work has been reported on loop decompilation at instruction level. In this paper, we report our work on loop de-optimization at instruction level. We demonstrate our approach with a practical working example and carried out experiments on TIC6x, a digital signal processor with a compiler supporting instruction level parallelism. The algorithms developed in this paper should help interested readers gain insight especially in the difficult tasks of loop rerolling and software de-pipelining, the necessary steps to decompile loops at instruction level.

Nortel Networks

Performance measurement is essential for the users and manufacturers of DSP processors. However, ... more Performance measurement is essential for the users and manufacturers of DSP processors. However, due to the diversity and complexity of DSP architectures and the large overhead of DSP compilers, metrics that effectively and objectively measure and compare the performance of various DSP processors from different manufacturers remain elusive. We introduce in this paper a new concept of instruction group where instructions in an instruction group are executed in parallel. Among other parameters such as the total execution time and the instruction count, we define the instruction group count of a DSP program as a new metric and study the impact of the group count as one of the parameters on various performance aspects of a DSP processor. Extensive experiments have been conducted by compiling the C code of a collection of DSP kernels and application programs and then executing the compiled code on several popular DSP processors. Both static and dynamic experimental data are analyzed and ...

The Architecture of a Distributed Knowledge Base System

IFIP Working Conference on Database Semantics, 1988

Software performance prediction at source level

2017 IEEE 15th International Conference on Software Engineering Research, Management and Applications (SERA)

Impact of Source-Level Loop Optimization on DSP Architecture Design

How to select an architecture which has better performance cost ratio, how to design a balanced a... more How to select an architecture which has better performance cost ratio, how to design a balanced architecture which can fit most DSP programs and how to generate a custom-fit DSP processor are important topics now. This paper presents a novel methodology based on source-level loop optimization which can avoid expensive retargetable compiler and simulator, and exhaustive experiments.

Distributed problem solving system for transport dispatching

Proceedings of the third international conference on Industrial and engineering applications of artificial intelligence and expert systems - IEA/AIE '90, 1990

ABSTRACT This paper introduces the architecture of a distributed problem solving system for trans... more ABSTRACT This paper introduces the architecture of a distributed problem solving system for transport dispatching, presents two algorithms for problem decomposition and task allocation and a cooperation mechanism based on meta-level communication, and evaluates both the architecture and algorithms by experiments on a prototype system.

Software de-pipelining technique

Source Code Analysis and Manipulation, Fourth IEEE International Workshop on

Performance Analysis of Digital Signal Processors Using SMV Benchmark

World Academy of Science, Engineering and Technology, International Journal of Electrical, Computer, Energetic, Electronic and Communication Engineering, 2009

Unlike general-purpose processors, digital signal processors (DSP processors) are strongly applic... more Unlike general-purpose processors, digital signal processors (DSP processors) are strongly application-dependent. To meet the needs for diverse applications, a wide variety of DSP processors based on different architectures ranging from the traditional to VLIW have been introduced to the market over the years. The functionality, performance, and cost of these processors vary over a wide range. In order to select a processor that meets the design criteria for an application, processor performance is usually the major concern for digital signal processing (DSP) application developers. Performance data are also essential for the designers of DSP processors to improve their design. Consequently, several DSP performance benchmarks have been proposed over the past decade or so. However, none of these benchmarks seem to have included recent new DSP applications. In this paper, we use a new benchmark that we recently developed to compare the performance of popular DSP processors from Texas ...

Comparing DSP Software Performance Prediction Models at Source Code Level — From Analytical to Statistical

Journal of Software

Efficient performance prediction at source code level is essential in reducing the turnaround tim... more Efficient performance prediction at source code level is essential in reducing the turnaround time of software development, particularly when the source code is subject to changes due to modification of problem specification. In this paper, we investigate and compare five performance prediction models from practical standpoint to determine the usefulness of these models. To verify the effectiveness of these models, we select a set of functions from PHY DSP Benchmark and TIC64 DSP processor for experiment. Comparing the predicted performance to the actual measured execution time, we observed that the relative prediction error generated from two of the five models are low and can thus be used for practical purposes.

An preliminary evaluation of trace scheduling for global microcode compaction

Fisher has recently described a new procedure for global microcode compaction which he calls "tra... more Fisher has recently described a new procedure for global microcode compaction which he calls "trace scheduling." We have implemented this procedure and tested it on several microcode sequences. We report in this correspondence on the relative effectiveness of local compaction, manual compaction, and trace scheduling on these sequences.

TST � An algorithm for global microcode compaction with timing constraints

Jcst, 1991

ABSTRACT Existing global microcode compaction approaches have all assumed a target architecture t... more ABSTRACT Existing global microcode compaction approaches have all assumed a target architecture that has microoperation conflicts and data dependencies as the two fundamental compaction constraints. However, new practical micromachine features demand that the timing constraint be introduced into the traditional compaction model to guarantee compaction correctness. This paper starts by an analysis on the nature of timing constraints, then modifies the rules for microoperation motions, presents an algorithm, TST, based on Trace Scheduling, for global compaction under timing constraints, and finally shows results of experiments.

A New Source-Level Benchmarking for DSP Processors

Performance measurement is essential for the users and manufacturers of DSP processors. However, ... more Performance measurement is essential for the users and manufacturers of DSP processors. However, due to the diversity and complexity of DSP architectures and the large overhead of DSP compilers, metrics that effectively and objectively measure and compare the performance of various DSP processors from different manufacturers remain elusive. We propose a new approach to DSP benchmarking with a new CPU time equation. Using a narrow spectrum benchmarking technique, we design special benchmark programs in C language to evaluate various aspects of DSP architecture such as the number of registers, number of function units, calling convention, the impact of hardware loop control, and load latency. Extensive experiments are conducted on several modern DSP processors including Texas Instruments' TIC62, TIC55 and StarCore's SC series. Both dynamic and static measurements on the benchmark programs are taken and the parameters in the new CPU time equation are used as metrics to analyze and evaluate the performance of various processors. It is noted that our approach does not require handoptimized assembly code. Also, the experimental results provide some useful information regarding how various aspects of the architectural design of a DSP processor are related to its performance.

Performance Analysis of Digital Signal Processors Using SMV Benchmark

Unlike general-purpose processors, digital signal processors (DSP processors) are strongly applic... more Unlike general-purpose processors, digital signal processors (DSP processors) are strongly application-dependent. To meet the needs for diverse applications, a wide variety of DSP processors based on different architectures ranging from the traditional to VLIW have been introduced to the market over the years. The functionality, performance, and cost of these processors vary over a wide range. In order to select a processor that meets the design criteria for an application, processor performance is usually the major concern for digital signal processing (DSP) application developers. Performance data are also essential for the designers of DSP processors to improve their design. Consequently, several DSP performance benchmarks have been proposed over the past decade or so. However, none of these benchmarks seem to have included recent new DSP applications. In this paper, we use a new benchmark that we recently developed to compare the performance of popular DSP processors from Texas Instruments and StarCore. The new benchmark is based on the Selectable Mode Vocoder (SMV), a speech-coding program from the recent third generation (3G) wireless voice applications. All benchmark kernels are compiled by the compilers of the respective DSP processors and run on their simulators. Weighted arithmetic mean of clock cycles and arithmetic mean of code size are used to compare the performance of five DSP processors. In addition, we studied how the performance of a processor is affected by code structure, features of processor architecture and optimization of compiler. The extensive experimental data gathered, analyzed, and presented in this paper should be helpful for DSP processor and compiler designers to meet their specific design goals.

A Study of Performance Measurement of DSP Processors

Performance measurement is essential for the users and manufacturers of DSP processors. However, ... more Performance measurement is essential for the users and manufacturers of DSP processors. However, due to the diversity and complexity of DSP architectures and the large overhead of DSP compilers, metrics that effectively and objectively measure and compare the performance of various DSP processors from different manufacturers remain elusive. We introduce in this paper a new concept of instruction group where instructions in an instruction group are executed in parallel. Among other parameters such as the total execution time and the instruction count, we define the instruction group count of a DSP program as a new metric and study the impact of the group count as one of the parameters on various performance aspects of a DSP processor. Extensive experiments have been conducted by compiling the C code of a collection of DSP kernels and application programs and then executing the compiled code on several popular DSP processors. Both static and dynamic experimental data are analyzed and

New DSP Benchmark based on Selectable Mode Vocoder (SMV)

Cdes, 2006

Digital signal processing (DSP) industry has been growing rapidly over the past few years; it rem... more Digital signal processing (DSP) industry has been growing rapidly over the past few years; it remains the technology driver for the recovering semiconductor industry. Performance evaluation is essential for the users and manufacturers of DSP processors. Since DSP application programs become larger and more complicated, people need new benchmarks for performance evaluation of different DSP processors. We build a new DSP benchmark based on Selectable Mode Vocoder (SMV), a speech-coding program from the 3G wireless applications. Our new DSP benchmark, called SMV benchmark, consists of eight kernel functions. In this paper, we introduce the criteria of selecting kernels and our methodology to build SMV benchmark. We also discuss the characteristics and static analysis of the kernels.

Assembly Code Conversion of Software-pipelined Loop between two VLIW DSP Processors

In order to fully utilize the instruction level parallelism of VLIW DSP processors, DSP programs ... more In order to fully utilize the instruction level parallelism of VLIW DSP processors, DSP programs have to be optimized by software pipelining. Software pipelining has been studied for many years and widely implemented in optimizing compilers. However, due to the rearrangement of the original instructions, it is often very difficult to re-use or port the code of a software-pipelined loop to other processors. In this paper we present a practical approach to solve this problem. Our approach involves the following steps: (1) Using a newly developed software de-pipelining algorithm to convert the assembly code of a software-pipelined loop to a semantically equivalent sequential loop; (2) Using our pattern mapping technique to convert the sequential loop to a machineindependent high-level intermediate code; (3) Converting the machine-independent intermediate code to that of the target machine; (4) Feed the intermediate code of the target machine to the backend of the compiler of the target machine to obtain the optimized assembly code of the target DSP processor We have conducted a series of experiments using the popular TIC62 as the source DSP and SC140 as the target DSP. Six DSP kernel programs have been selected for the experiments. To verify the validity of the converted code, we have used a simulator to compare the results of various steps in the conversion process. All the results of our experiments show that the converted assembly code of target DSP processor are correct with comparable performance to the assembly code directly generated by compiling the source code with the optimizing compiler of the target machine.

Code Migration from Conventional DSPs to VLIW DSPs

It is a challenge to convert the existing conventional DSPs&amp;#x27; assembly code to that o... more It is a challenge to convert the existing conventional DSPs&amp;#x27; assembly code to that of VLIW DSPs&amp;#x27;. We propose a new code migration method, which performs semantically equivalent code conversion. Key issues such as semantics of the conventional DSP code, specialized addressing modes and different data types are discussed.