... The platform proposed is based on an embedded system implemented on a Cyclone FPGA. ... and t... more ... The platform proposed is based on an embedded system implemented on a Cyclone FPGA. ... and the project Digital processing platfrom for Active Power Line Filters granted by Fundación Hermanos Agustín y Enrique Rocca. ...
The purpose of the paper is to present a method to validate tentative routes to establish calls w... more The purpose of the paper is to present a method to validate tentative routes to establish calls with end-to-end timing-constraints in a multihop packet-switching network. Timing release counters are proposed as a mechanism to guarantee that intervals between consecutive releases of messages of the same call are not shorter than the call period. A comparative evaluation of the proposed timing
FPGA devices allows designer to implement complex digital architectures that involve hardware and... more FPGA devices allows designer to implement complex digital architectures that involve hardware and software components. Because of the different features of hardware and software design, diverse mechanisms and tools have been proposed for debugging and verification of architectures implemented on FPGA devices. Bus level transactions and data processing algorithms are usually difficult to manage together because differences between the inspection times involved. While hardware transactions are related to system clock periods, data processing algorithms are related to software execution times. In this paper, an Ethernet controller is proposed as a low invasive component to extract runtime hardware and software information for system debugging and verification. The information produced may be analyzed to locate hardware and software failures as well as to improve the system performance tuning its configuration parameters. A case study is proposed as a real application.
Nowadays, Field Programmable Gate Arrays (FPGAs) are used in very diverse applications. Modern FP... more Nowadays, Field Programmable Gate Arrays (FPGAs) are used in very diverse applications. Modern FPGA devices offer high capacity to implement digital design with a wide range of specific resources. Typically, FPGA vendors categorize theirs devices in families suitable for: (1) high performance applications or (2) low-cost designs. On the other hand, FPGA manufacturers offer different design tools with diverse configuration options to get the most of the available FPGA resources for each design implemented. Usually, designers adopt for new projects the same criteria, devices and tools used in previous projects since it is time consuming to evaluate alternatives from others FPGA manufacturers. In this paper, we present an automated design platform used to evaluate different alternatives to implement FPGA designs. Evaluation involved technical as well as economic criteria that may help the designer to find the most adequate alternative to its design.
Real-time systems are used in control applications. However, real-time systems may introduce unde... more Real-time systems are used in control applications. However, real-time systems may introduce undesirable effects on the control application. Stability, overshoot and settling time are affected when an inadequate real-time system is used. The uRT51 is an embedded processor designed for real-time applications. In this paper we analyse the perturbations that the uRT51 produces on a control application using two of
In this paper we propose and analyze a hardware architecture for Discrete Wavelet Transform (DWT)... more In this paper we propose and analyze a hardware architecture for Discrete Wavelet Transform (DWT) computation. Wavelet transform is a very useful alternative when it is desired to analyze signals with a non-stationary behavior (i.e. frequency spectrum of the signal varies in time). As it happens with the Fast Fourier Transform (FFT), the Discrete Wavelet Transform is a faster alternative that operates on vectors whose length is a power of two. However, even the DWT may be not faster enough when it is implemented as a software algorithm executed by a processor. In this paper, we propose a hardware architecture processing unit of a DAUB4 discrete wavelet transform, compatible with the Altera Avalon Specification. The performance of the processing unit is analyzed for different configuration parameters and FPGA devices.
In this paper we describe and analyze the main features of the Hardware Real-Time Scheduler Copro... more In this paper we describe and analyze the main features of the Hardware Real-Time Scheduler Coprocessor unit (HRTC) for NIOS II processor. We describe how the HRTSC supports time, events, task and priorities. The HRTSC was designed as a SOPC component to incorporate real-time features for embedded real-time applications. The hardware architecture has an easy integration with the IDE programming environment. The Avalon interface showed to be an efficient specification to share memory and data communication among memory, processor and HRTSC. The performance of the HRTSC architecture is analyzed considering real-time flexibility, programmability and power consumption reduction.
Se presenta un método que trata el problema de asignación de Wl conjunto de tareas apropiables, s... more Se presenta un método que trata el problema de asignación de Wl conjunto de tareas apropiables, sobre un conjunto de procesadores heterogéneos distribuidos que deben trabajar en un entorno de tiempo real duro. Las tareas son cooperativas y utilizan como vía de comunicación una red. Sobre el sistema tareas-procesadores-red, existen restricciones de ubicación, diagramabilidad, memoria, comunicaciones y precedencia.
In this paper we describe and evaluate the main features of the uRT51 processor. The uRT51 proces... more In this paper we describe and evaluate the main features of the uRT51 processor. The uRT51 processor was designed for embedded realtime control applications. It is a processor architecture that incorporates the specific functions of a real-time system in hardware. It was described using synthesizable VHDL and it was implemented on FPGA devices. We describe how the uRT51 processor supports time, events, task and priorities. The performance of the uRT51 processor is evaluated using a control application as a case study. The experiments show that the uRT51 processor scheduling features outperform the ones obtained using a traditional RTOS-based real-time system.
En este trabajo se muestran algunos resultados abtenidos a partir del analisis de sistemas de tie... more En este trabajo se muestran algunos resultados abtenidos a partir del analisis de sistemas de tiempo-real diagramados por un diagramador por Periodos Monotonicos Crecientes (PMC). Los mismos muestran que la diagramabilidad del sistema aumenta si se establecen relaciones de precedencia entre las tareas. Luego, una adecuada particion de tareas en subtareas con relaciones de precedencia de menor duracion, facilita la diagramabilidad del sistema.
... The platform proposed is based on an embedded system implemented on a Cyclone FPGA. ... and t... more ... The platform proposed is based on an embedded system implemented on a Cyclone FPGA. ... and the project Digital processing platfrom for Active Power Line Filters granted by Fundación Hermanos Agustín y Enrique Rocca. ...
The purpose of the paper is to present a method to validate tentative routes to establish calls w... more The purpose of the paper is to present a method to validate tentative routes to establish calls with end-to-end timing-constraints in a multihop packet-switching network. Timing release counters are proposed as a mechanism to guarantee that intervals between consecutive releases of messages of the same call are not shorter than the call period. A comparative evaluation of the proposed timing
FPGA devices allows designer to implement complex digital architectures that involve hardware and... more FPGA devices allows designer to implement complex digital architectures that involve hardware and software components. Because of the different features of hardware and software design, diverse mechanisms and tools have been proposed for debugging and verification of architectures implemented on FPGA devices. Bus level transactions and data processing algorithms are usually difficult to manage together because differences between the inspection times involved. While hardware transactions are related to system clock periods, data processing algorithms are related to software execution times. In this paper, an Ethernet controller is proposed as a low invasive component to extract runtime hardware and software information for system debugging and verification. The information produced may be analyzed to locate hardware and software failures as well as to improve the system performance tuning its configuration parameters. A case study is proposed as a real application.
Nowadays, Field Programmable Gate Arrays (FPGAs) are used in very diverse applications. Modern FP... more Nowadays, Field Programmable Gate Arrays (FPGAs) are used in very diverse applications. Modern FPGA devices offer high capacity to implement digital design with a wide range of specific resources. Typically, FPGA vendors categorize theirs devices in families suitable for: (1) high performance applications or (2) low-cost designs. On the other hand, FPGA manufacturers offer different design tools with diverse configuration options to get the most of the available FPGA resources for each design implemented. Usually, designers adopt for new projects the same criteria, devices and tools used in previous projects since it is time consuming to evaluate alternatives from others FPGA manufacturers. In this paper, we present an automated design platform used to evaluate different alternatives to implement FPGA designs. Evaluation involved technical as well as economic criteria that may help the designer to find the most adequate alternative to its design.
Real-time systems are used in control applications. However, real-time systems may introduce unde... more Real-time systems are used in control applications. However, real-time systems may introduce undesirable effects on the control application. Stability, overshoot and settling time are affected when an inadequate real-time system is used. The uRT51 is an embedded processor designed for real-time applications. In this paper we analyse the perturbations that the uRT51 produces on a control application using two of
In this paper we propose and analyze a hardware architecture for Discrete Wavelet Transform (DWT)... more In this paper we propose and analyze a hardware architecture for Discrete Wavelet Transform (DWT) computation. Wavelet transform is a very useful alternative when it is desired to analyze signals with a non-stationary behavior (i.e. frequency spectrum of the signal varies in time). As it happens with the Fast Fourier Transform (FFT), the Discrete Wavelet Transform is a faster alternative that operates on vectors whose length is a power of two. However, even the DWT may be not faster enough when it is implemented as a software algorithm executed by a processor. In this paper, we propose a hardware architecture processing unit of a DAUB4 discrete wavelet transform, compatible with the Altera Avalon Specification. The performance of the processing unit is analyzed for different configuration parameters and FPGA devices.
In this paper we describe and analyze the main features of the Hardware Real-Time Scheduler Copro... more In this paper we describe and analyze the main features of the Hardware Real-Time Scheduler Coprocessor unit (HRTC) for NIOS II processor. We describe how the HRTSC supports time, events, task and priorities. The HRTSC was designed as a SOPC component to incorporate real-time features for embedded real-time applications. The hardware architecture has an easy integration with the IDE programming environment. The Avalon interface showed to be an efficient specification to share memory and data communication among memory, processor and HRTSC. The performance of the HRTSC architecture is analyzed considering real-time flexibility, programmability and power consumption reduction.
Se presenta un método que trata el problema de asignación de Wl conjunto de tareas apropiables, s... more Se presenta un método que trata el problema de asignación de Wl conjunto de tareas apropiables, sobre un conjunto de procesadores heterogéneos distribuidos que deben trabajar en un entorno de tiempo real duro. Las tareas son cooperativas y utilizan como vía de comunicación una red. Sobre el sistema tareas-procesadores-red, existen restricciones de ubicación, diagramabilidad, memoria, comunicaciones y precedencia.
In this paper we describe and evaluate the main features of the uRT51 processor. The uRT51 proces... more In this paper we describe and evaluate the main features of the uRT51 processor. The uRT51 processor was designed for embedded realtime control applications. It is a processor architecture that incorporates the specific functions of a real-time system in hardware. It was described using synthesizable VHDL and it was implemented on FPGA devices. We describe how the uRT51 processor supports time, events, task and priorities. The performance of the uRT51 processor is evaluated using a control application as a case study. The experiments show that the uRT51 processor scheduling features outperform the ones obtained using a traditional RTOS-based real-time system.
En este trabajo se muestran algunos resultados abtenidos a partir del analisis de sistemas de tie... more En este trabajo se muestran algunos resultados abtenidos a partir del analisis de sistemas de tiempo-real diagramados por un diagramador por Periodos Monotonicos Crecientes (PMC). Los mismos muestran que la diagramabilidad del sistema aumenta si se establecen relaciones de precedencia entre las tareas. Luego, una adecuada particion de tareas en subtareas con relaciones de precedencia de menor duracion, facilita la diagramabilidad del sistema.
Uploads
Papers by Edgardo Ferro