Papers by jean-luc Dekeyser
Models in Software Engineering, 2011
One of the most important tasks in object-oriented analysis and design (OOAD) is the abstraction ... more One of the most important tasks in object-oriented analysis and design (OOAD) is the abstraction of the problem domain into specific concepts or objects. Information technology (IT) students need appropriate skills of abstraction in order to identify the essential concepts and relationships within a problem domain. However students in higher education generally find difficulty performing abstractions of real-world problems within the context of OOAD. In this paper, we present a framework comprising four teaching modules for teaching object-oriented (OO) modelling using concept maps. We also report results of an evaluative study on the effectiveness of integrating concept mapping techniques into an introductory OOAD course by classifying the UML diagrams produced by the participants in design categories.
HAL is a multi-disciplinary open access archive for the deposit and dissemination of sci-entific ... more HAL is a multi-disciplinary open access archive for the deposit and dissemination of sci-entific research documents, whether they are pub-lished or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers. L’archive ouverte pluridisciplinaire HAL, est destinée au dépôt et a ̀ la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d’enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.
HAL is a multi-disciplinary open access archive for the deposit and dissemination of sci-entific ... more HAL is a multi-disciplinary open access archive for the deposit and dissemination of sci-entific research documents, whether they are pub-lished or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers. L’archive ouverte pluridisciplinaire HAL, est destinée au dépôt et a ̀ la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d’enseignement et de recherche français ou étrangers, des laboratoires publics ou privés. appor t de r ech er ch e
In this contribution, we propose an efficient power estima-tion methodology for complex RISC proc... more In this contribution, we propose an efficient power estima-tion methodology for complex RISC processor-based plat-forms. In this methodology, the Functional Level Power Analysis (FLPA) is used to set up generic power models for the different parts of the system. Then, a simulation framework based on virtual platform is developed to evalu-ate accurately the activities used in the related power mod-els. The combination of the two parts above leads to a het-erogeneous power estimation that gives a better trade-off be-tween accuracy and speed. The usefulness and effectiveness of our proposed methodology is validated through ARM9 and ARM CortexA8 processor designed respectively around the OMAP5912 and OMAP3530 boards. This efficiency and the accuracy of our proposed methodology is evaluated by using a variety of basic programs to complete media bench-marks. Estimated power values are compared to real board measurements for the both ARM940T and ARM CortexA8 architectures. Our obtained pow...
In this contribution, we propose an efficient power estima-tion methodology for complex RISC proc... more In this contribution, we propose an efficient power estima-tion methodology for complex RISC processor-based plat-forms. In this methodology, the Functional Level Power Analysis (FLPA) is used to set up generic power models for the different parts of the system. Then, a simulation framework based on virtual platform is developed to evalu-ate accurately the activities used in the related power mod-els. The combination of the two parts above leads to a het-erogeneous power estimation that gives a better trade-off be-tween accuracy and speed. The usefulness and effectiveness of our proposed methodology is validated through ARM9 and ARM CortexA8 processor designed respectively around the OMAP5912 and OMAP3530 boards. This efficiency and the accuracy of our proposed methodology is evaluated by using a variety of basic programs to complete media bench-marks. Estimated power values are compared to real board measurements for the both ARM940T and ARM CortexA8 architectures. Our obtained pow...
Membrane-based design and management methodology for parallel dynamically reconfigurable embedded... more Membrane-based design and management methodology for parallel dynamically reconfigurable embedded systems
HAL is a multi-disciplinary open access archive for the deposit and dissemination of sci-entific ... more HAL is a multi-disciplinary open access archive for the deposit and dissemination of sci-entific research documents, whether they are pub-lished or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers. L’archive ouverte pluridisciplinaire HAL, est destinée au dépôt et a ̀ la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d’enseignement et de recherche français ou étrangers, des laboratoires publics ou privés. Software Implementation vs. Hardware Implementation:
HAL is a multi-disciplinary open access archive for the deposit and dissemination of sci-entific ... more HAL is a multi-disciplinary open access archive for the deposit and dissemination of sci-entific research documents, whether they are pub-lished or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers. L’archive ouverte pluridisciplinaire HAL, est destinée au dépôt et a ̀ la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d’enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.
HAL is a multi-disciplinary open access archive for the deposit and dissemination of sci-entific ... more HAL is a multi-disciplinary open access archive for the deposit and dissemination of sci-entific research documents, whether they are pub-lished or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers. L’archive ouverte pluridisciplinaire HAL, est destinée au dépôt et a ̀ la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d’enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.
WSEAS Transactions on Circuits and Systems archive, 2015
Nowadays, recent intensive signal processing applications are evolving and are characterized by t... more Nowadays, recent intensive signal processing applications are evolving and are characterized by the diversity of algorithms (filtering, correlation, etc.) and their numerous parameters. Having a flexible and pro-grammable system that adapts to changing and various characteristics of these applications reduces the design cost. In this context, we propose in this paper Generic Massively Parallel architecture (G-MPSoC). G-MPSoC is a System-on-Chip based on a grid of clusters of Hardware and Software Computation Elements with different size, performance, and complexity. It is composed of parametric IP-reused modules: processor, controller, accelerator, memory, interconnection network, etc. to build different architecture configurations. The generic structure of G-MPSoC facilitates its adaptation to the intensive signal processing applications requirements. This paper presents G-MPSoC architecture and details its different components. The FPGA-based implementation and the experimental re...
i-manager's Journal on Embedded Systems, 2015
One goal of reconfiguration is to save power and occupied resources. In this paper we compare two... more One goal of reconfiguration is to save power and occupied resources. In this paper we compare two different kinds of reconfiguration available on field-programmable gate arrays (FPGA) and we discuss their pros and cons. The first method that we study is circuit merging. This type of reconfiguration methods consists in sharing common resources between different circuits. The second method that we explore is dynamic partial reconfiguration (DPR). It is specific to some FPGA, allowing well defined reconfigurable parts to be modified during run-time. We show that DPR, when available, has good and more predictable result in terms of occupied area. There is still a huge overhead in term of time and power consumption during the reconfiguration phase. Therefore we show that circuit merging remains an interesting solution on FPGA because it is not vendor specific and the reconfiguration time is around a clock cycle. Besides, good merging algorithms exist even-though FPGA physical synthesis flow makes it hard to predict the real performance of the merged circuit during the optimization. We establish our comparison in the context of the HoMade processor.
2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC), 2016
Nowadays, Field Programmable Gate Arrays (FPGAs) platforms offer a high density to allow designin... more Nowadays, Field Programmable Gate Arrays (FPGAs) platforms offer a high density to allow designing Multi Processor-based System on Chip. SPMD (Single Program Multiple Data) is a massively parallel execution model based on the assembly of a given number of homogeneous Processing Elements (PEs). This model is often relaying on Master/Slaves architecture composed by a Master PE that manages the parallel execution of a set of identical slave PEs. Furthermore, Dynamic Partial Reconfiguration (DPR) feature allows such computing system to be reconfigured on the fly for a given application requirement. Given the growing number of PEs in Master/Slaves architecture, it is difficult to estimate the time of specification and design during the phase of allocation and floorplanning of Partial Reconfigurable Regions (PRRs) because it is still performed manually. In this work, we present AFFORDe, a tool enable to automate the Xilinx DPR flow for SPMD architecture that allows parsing the resource requirements of the static and the dynamically reconfigurable parts to perform an automatic floorplanning. The floorplanning is based on a Heuristic Algorithm for Automatic Floorplanning in SPMD Architectures (HAAFSA). This tool is used to generate a configuration file that allows floorplanning of reconfigurable regions in an automatic way of a given Master/Slaves configuration. Experimental results show the effectiveness of our tool to increase the design productivity for dynamically reconfigurable SPMD-based architecture.
Scalable Computing: Practice and Experience, 2009
The study presented in this paper concerns the safe design of high-performance embedded systems, ... more The study presented in this paper concerns the safe design of high-performance embedded systems, specifically dedicated to intensive data-parallel processing as found, for instance, in modern multimedia applications or radar/sonar signal processing. Among the important requirements of such systems are the efficient execution, reliability and quality of service. Unfortunately, the complexity of modern embedded systems makes it difficult to meet all these requirements. As an answer to this issue, this paper proposes a combination of two models of computation (MoCs) within a framework, called Gaspard, in order to deal with the design and validation of high-performance embedded systems. On the one hand, the repetitive MoC offers a powerful expression of the parallelism available in both system functionality and architecture. On the other hand, the synchronous MoC serves as a formal model on which a trustworthy verification can be applied. Here, the high-level models specified with the repetitive MoC are translated into an equational model in the synchronous MoC so as to be able to formally analyze different properties of the modeled systems. As an example, a clock synchronizability analysis is illustrated on a multimedia system in order to guarantee a correct interaction between its components. For the implementation and validation of our proposition, a Model-Driven Engineering (MDE) approach is adopted. MDE is well-suited to deal with design complexity and productivity issues. In our case, the OMG standard MARTE profile is used to model embedded systems. Then, automatic transformations are applied to these models to produce the corresponding synchronous programs for analysis.
Applications for Flexibility and Agility
Massive parallel processing systems, particularly Single Instruction Multiple Data architectures,... more Massive parallel processing systems, particularly Single Instruction Multiple Data architectures, play a crucial role in the field of data intensive parallel applications. One of the primary goals in using these systems is their scalability and their linear increase in processing power by increasing the number of processing units. However, communication networks are the big challenging issue facing researchers. One of the most important networks on chip for parallel systems is the multistage interconnection network. In this paper, we propose a design methodology of multistage interconnection networks for massively parallel systems on chip. The framework covers the design step from algorithm level to RTL. We first develop a functional formalization of MIN-based on-chip network at a high level of abstraction. The specification and the validation of the model have been defined in the logic of ACL2 proving system. The main objective in this step is to provide a formal description of the network that integrates architectural parameters which have a huge impact on design costs. After validating the functional model,
2015 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2015
Reconfigurable technology fits for real-time video streaming applications. It is considered as a ... more Reconfigurable technology fits for real-time video streaming applications. It is considered as a promising solution due to the offered performance per watt compared to other technologies. Since FPGA evolved, several techniques at different design levels starting from the circuit-level up to the system-level were proposed to reduce the power consumption of the FPGA devices. In this paper, we present a flexible parallel hardware-based architecture in conjunction with frequency scaling as a technique for reducing power consumption in video streaming applications. In this work, we derived equations to ease the calculation for the level of parallelism and the maximum depth for the FIFOs used for clock domain crossing. Accordingly, a design space was formed including all the design alternatives for the application. The preferable design alternative is selected in aware of how much hardware it costs and what power reduction goal it can satisfy. We used Xilinx Zynq ZC706 evaluation board to implement two video streaming applications: Video downscaler (1:16) and AES encryption algorithm to verify our approach. The experimental results showed up to 19.6% power reduction for the video downscaler and up to 5.4% for the AES encryption.
2008 Forum on Specification, Verification and Design Languages, 2008
Digital television (DTV) is an advanced broadcasting technology that is spreading fast today. It ... more Digital television (DTV) is an advanced broadcasting technology that is spreading fast today. It gives broadcasters the capability to send programs with a better picture and sound quality. Moreover, broadcasters can send several programming choices, called multicasting. DTV consists of a high-performance system combining both control and intensive data processing. In this paper, we first show how the OMG MARTE profile can serve to model such a system. Then, we use the synchronous approach to formally check some temporal properties of the expected system implementation for validation purpose.
Lecture Notes in Computer Science, 1996
ABSTRACT Data-parallel languages support a single instruction flow; the parallelism is expressed ... more ABSTRACT Data-parallel languages support a single instruction flow; the parallelism is expressed atthe instruction level. Actually, data-parallel languages have chosen arrays to support theparallelism. This regular data structure allows a natural development of regular parallelalgorithms. The implementation of irregular algorithms necessitates a programming effort toproject the irregular data structures onto regular structures. In this article we present thedifferent techniques used to manage...
2010 International Symposium on System on Chip, 2010
This paper presents the design and analysis of a multimedia system-on-chip consisting of the H.26... more This paper presents the design and analysis of a multimedia system-on-chip consisting of the H.264 encoder implemented on a multiprocessor architecture. A model-driven approach is adopted by using the standard MARTE profile of UML. An abstract clock analysis is applied to deal with the correctness of the system temporal properties and to find the most suitable execution platform configurations regarding
2007 International Conference on Field Programmable Logic and Applications, 2007
ABSTRACT This paper introduces a new flow able to lit a parallel application onto an FPGA accordi... more ABSTRACT This paper introduces a new flow able to lit a parallel application onto an FPGA according to the FPGA characteristics such as computing power and IOs. The flow is based on iterative refactoring and transformations of the application. From the resulting application, a VHDL code is generated. This code is finally used to simulate or synthesize the application. Significant experiments have validated the approach.
We present a methodology to visually model intensive signal processing applications forembedded s... more We present a methodology to visually model intensive signal processing applications forembedded systems. This methodology is based on the Array-OL language. The idea is to representan application as a graph of dependencies between tasks and arrays. It differs from the classicalreactive programming or message passing paradigm. A task may iterate the same code ondifferent patterns tilling its depending arrays. In this case, visual specifications of dependenciesbetween the pattern...
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Papers by jean-luc Dekeyser