Papers by ronald lesnikoski
2006 IEEE International Test Conference, 2006
The multi-core microprocessors are driving IO architecture to 100% SERDES across the processors&#... more The multi-core microprocessors are driving IO architecture to 100% SERDES across the processors' memory, network and system IO interfaces. This scale of SERDES integration is that traditional DFT approaches adequately screen for functional verification of the IO macros and some amount of PHY parametrics, but fall short when used to test an integrated product with >200, 4.8 Gb/s lanes Detailed AC parametric margin testing is still necessary to achieve adequate defect coverage.
IEEE International Conference on Test, 2005.
Throughput computing requires chip I/O bandwidth of the order of Tbits/sec which can be met by hi... more Throughput computing requires chip I/O bandwidth of the order of Tbits/sec which can be met by highspeed, large scale implementation of SerDes I/Os (Serial/Deserial differential I/Os with clock embedded in data stream). The traditional test philosophy and existing ATE do not meet the challenges of testing chip interfaces with few hundreds of I/Os operating at multi-Gbps. In this paper we present the test challenges and describe onchip DFT modes and new ATE directions for chip level characterization and test of such interfaces used in throughput computing chip sets.
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Papers by ronald lesnikoski