As a new paradigm, fog computing (FC) has several characteristics that set it apart from the clou... more As a new paradigm, fog computing (FC) has several characteristics that set it apart from the cloud computing (CC) environment. Fog nodes and edge computing (EC) hosts have limited resources, exposing them to cyberattacks while processing large streams and sending them directly to the cloud. Intrusion detection systems (IDS) can be used to protect against cyberattacks in FC and EC environments, while the large-dimensional features in networking data make processing the massive amount of data difficult, causing lower intrusion detection efficiency. Feature selection is typically used to alleviate the curse of dimensionality and has no discernible effect on classification outcomes. This is the first study to present an Effective Seeker Optimization model in conjunction with a Machine Learning-Enabled Intrusion Detection System (ESOML-IDS) model for the FC and EC environments. The ESOML-IDS model primarily designs a new ESO-based feature selection (FS) approach to choose an optimal subs...
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017
With increasing resolutions the volume of data generated by image processing applications is esca... more With increasing resolutions the volume of data generated by image processing applications is escalating dramatically. When coupled with real-time performance requirements, reducing energy consumption for such a large volume of data is proving challenging. In this paper, we propose a novel approach for image processing applications using signi cance-driven approximate computing. Core to our approach is the fundamental tenet that image data should be processed intelligently based on their informational value, i.e. signi cance. Using quanti ed de nition of signi cance, for the rst time, we show how the complexity of data processing tasks can be drastically reduced when computing decisions are synergistically adapted to signi cance learning principles. A variable-kernel convolution lter case study running on an Odroid XU-4 platform is demonstrated to evaluate the e ectiveness of our approach, with up to 45% energy reduction for a given performance requirement.
International Workshop on Power and Timing Modeling, Optimization and Simulation, 2017
Approximate computing introduces a new era of low-power and high-speed circuit designs. Instead o... more Approximate computing introduces a new era of low-power and high-speed circuit designs. Instead of strict accurate computation, relaxed requirements might increase performance and reduce power consumption with a simplified or inaccurate circuit. One of the recent remarkable research efforts is the accuracy-configurable approximate adder designs, which can gracefully operate in both approximate (inaccurate) and accurate modes. In this paper, a novel technique for segmenting approximate adders was proposed by adding new bit locations that exploit the carry kill signal definition to limit carry propagation at specific locations. Moreover, a lightweight carry-in prediction and error detection techniques were proposed. For error recovery circuit, a significance-driven configurable correction stages were implemented, which imply a fast convergence to exact outputs with a very low magnitude of errors. The proposed design showed improvements of (16%) and (18.6%) for dynamic power and area respectively. Nevertheless, outputs reserved a general high accuracy level, which limited between 99% and 100% for the majority of input space. The proposed design was implemented in an image filter application, which resulted in high PSNR values of (53 and 83 db) for the two premier correction stages, and 100% exact results for the highest accuracy mode.
2017 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2017
With increasing resolutions the volume of data generated by image processing applications is esca... more With increasing resolutions the volume of data generated by image processing applications is escalating dramatically. When coupled with real-time performance requirements, reducing energy con- sumption for such a large volume of data is proving challenging.
2017 IEEE International Workshop on Signal Processing Systems (SiPS), 2017
In this paper, we propose an energy-efficient approximate multiplier design approach. Fundamental... more In this paper, we propose an energy-efficient approximate multiplier design approach. Fundamental to this approach is configurable lossy logic compression, coupled with low-cost error mitigation. The logic compression is aimed at reducing the number of product rows using progressive bit significance, and thereby decreasing the number of reduction stages in Wallace-tree accumulation. This accounts for substantially lower number of logic counts and lengths of the critical paths at the cost of errors in lower significant bits. These errors are minimised through a parallel error detection logic and compensation vector. To validate the effectiveness of our approach, multiple 8-bit multipliers are designed and synthesized using Synopses Design Compiler with different logic compression levels. Post synthesis experiments showed the trade-offs between energy and accuracy for these compression levels, featuring up to 70% reduction in power-delay product (PDP) and 60% lower area in the case of...
Approximate computing has recently introduced a new era of low-power and high-speed circuit desig... more Approximate computing has recently introduced a new era of low-power and high-speed circuit designs. Recent efforts in the domain of configurable-accuracy approximate designs have proposed substantial performance gains and energy savings by allowing performance-energy-accuracy trade-offs. In this paper, we propose a configurable-accuracy approximate adder with new lightweight error detection technique. This is followed by significance-driven error correction stages during run-time. The correction starts by recovering the higher magnitude errors at premier correction stages, which results in fast convergence and higher precision outputs. Compared to other equivalent approximate adders, the proposed design has drastically reduced the logic counts used for error detection process; hence, achieving lower overhead of silicon area and improving the energy-efficiency of the adder design with faster convergence to the exact results. A number of different bitwidths of the proposed adder (32-bit to 256-bit) are designed in Verilog and synthesized using Synopsys Design Compiler. Our post-synthesis experiments showed significant reductions of 12% and 10% for Dynamic and Leakage Power respectively, and 8% in the silicon area for the design with full correction stages. Moreover, the proposed adder with large bit-widths has reserved these reduction ratios while presenting better scalability overhead. Additionally, our low overhead proposed design has presented the chance to be improved in terms of increasing accuracy to reach 100% exact results as accurate conventional adder at the final correction stage.
Designing energy-efficient hardware continues to be challenging due to arithmetic complexities. T... more Designing energy-efficient hardware continues to be challenging due to arithmetic complexities. The problem is further exacerbated in systems powered by energy harvesters as variable power levels can limit their computation capabilities. In this work, we propose a run-time configurable adaptive approximation method for multiplication that is capable of managing the energy and performance tradeoffs — ideally suited in these systems. Central to our approach is a Significance-Driven Logic Compression (SDLC) multiplier architecture that can dynamically adjust the level of approximation depending on the run-time power/accuracy constraints. The architecture can be configured to operate in the exact mode (no approximation) or in progressively higher approximation modes (i.e. 2 to 4-bit SDLC). Our method is implemented in both ASIC and FPGA. The implementation results indicate that our design has only a 2.3% silicon overhead, on top of what is required by a traditional exact multiplier. We ...
1 OVERVIEW With increasing resolutions the volume of data generated by image processing applicati... more 1 OVERVIEW With increasing resolutions the volume of data generated by image processing applications is escalating dramatically. When coupled with real-time performance requirements, reducing energy consumption for such a large volume of data is proving challenging. In this paper, we propose a novel approach for image processing applications using signi cance-driven approximate computing. Core to our approach is the fundamental tenet that image data should be processed intelligently based on their informational value, i.e. signi cance. Using quanti ed de nition of signi cance, for the rst time, we show how the complexity of data processing tasks can be drastically reduced when computing decisions are synergistically adapted to signi cance learning principles. A variable-kernel convolution lter case study running on an Odroid XU-4 platform is demonstrated to evaluate the e ectiveness of our approach, with up to 45% energy reduction for a given performance requirement.
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017
Approximate arithmetic has recently emerged as a promising paradigm for many imprecision-tolerant... more Approximate arithmetic has recently emerged as a promising paradigm for many imprecision-tolerant applications. It can offer substantial reductions in circuit complexity, delay and energy consumption by relaxing accuracy requirements. In this paper, we propose a novel energy-efficient approximate multiplier design using a significance-driven logic compression (SDLC) approach. Fundamental to this approach is an algorithmic and configurable lossy compression of the partial product rows based on their progressive bit significance. This is followed by the commutative remapping of the resulting product terms to reduce the number of product rows. As such, the complexity of the multiplier in terms of logic cell counts and lengths of critical paths is drastically reduced. A number of multipliers with different bit-widths (4-bit to 128-bit) are designed in SystemVerilog and synthesized using Synopsys Design Compiler. Post-synthesis experiments showed that up to an order of magnitude energy savings, and reductions of 65% in critical delay and almost 45% in silicon area can be achieved for a 128-bit multiplier compared to an accurate equivalent. These gains are achieved with low accuracy losses estimated at less than 0.00071 mean relative error. Additionally, we demonstrate the energy-accuracy trade-offs for different degrees of compression, achieved through configurable logic clustering. In evaluating the effectiveness of our approach, a case study image processing application showed up to 68.3% energy reduction with negligible losses in image quality expressed as peak signal-to-noise ratio (PSNR).
Approximate arithmetic has recently emerged as a promising paradigm for many imprecision-tolerant... more Approximate arithmetic has recently emerged as a promising paradigm for many imprecision-tolerant applications. It can offer substantial reductions in circuit complexity, delay and energy consumption by relaxing accuracy requirements. In this paper, we propose a novel energy-efficient approximate multiplier design using a significance-driven logic compression (SDLC) approach. Fundamental to this approach is an algorithmic and configurable lossy compression of the partial product rows based on their progressive bit significance. This is followed by the commutative remapping of the resulting product terms to reduce the number of product rows. As such, the complexity of the multiplier in terms of logic cell counts and lengths of critical paths is drastically reduced. A number of multipliers with different bit-widths (4-bit to 128-bit) are designed in SystemVerilog and synthesized using Synopsys Design Compiler. Post-synthesis experiments showed that up to an order of magnitude energy savings, and reductions of 65% in critical delay and almost 45% in silicon area can be achieved for an 128-bit multiplier, compared to an accurate equivalent. These gains are achieved with low accuracy losses estimated at less than 0.0028 mean relative error. Additionally, we demonstrate the performance-energyquality (PEQ) trade-offs for different degrees of compression, achieved through configurable logic clustering. While evaluating the effectiveness of the proposed approach three case studies were set up. First, a Gaussian blur filter was designed, which demonstrated up to 80% energy reduction with a meagre loss of image quality. Second, we evaluate our approach in machine learning application using perceptron classifier, showed up to 74% energy reduction with negligible error rate. Third, the proposed multiplier designs were used in a power-constrained image processing application. We showed that SDLC can achieve 60x improvement in computation capability, with potential to be employed in ubiquitous systems.
As a new paradigm, fog computing (FC) has several characteristics that set it apart from the clou... more As a new paradigm, fog computing (FC) has several characteristics that set it apart from the cloud computing (CC) environment. Fog nodes and edge computing (EC) hosts have limited resources, exposing them to cyberattacks while processing large streams and sending them directly to the cloud. Intrusion detection systems (IDS) can be used to protect against cyberattacks in FC and EC environments, while the large-dimensional features in networking data make processing the massive amount of data difficult, causing lower intrusion detection efficiency. Feature selection is typically used to alleviate the curse of dimensionality and has no discernible effect on classification outcomes. This is the first study to present an Effective Seeker Optimization model in conjunction with a Machine Learning-Enabled Intrusion Detection System (ESOML-IDS) model for the FC and EC environments. The ESOML-IDS model primarily designs a new ESO-based feature selection (FS) approach to choose an optimal subs...
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017
With increasing resolutions the volume of data generated by image processing applications is esca... more With increasing resolutions the volume of data generated by image processing applications is escalating dramatically. When coupled with real-time performance requirements, reducing energy consumption for such a large volume of data is proving challenging. In this paper, we propose a novel approach for image processing applications using signi cance-driven approximate computing. Core to our approach is the fundamental tenet that image data should be processed intelligently based on their informational value, i.e. signi cance. Using quanti ed de nition of signi cance, for the rst time, we show how the complexity of data processing tasks can be drastically reduced when computing decisions are synergistically adapted to signi cance learning principles. A variable-kernel convolution lter case study running on an Odroid XU-4 platform is demonstrated to evaluate the e ectiveness of our approach, with up to 45% energy reduction for a given performance requirement.
International Workshop on Power and Timing Modeling, Optimization and Simulation, 2017
Approximate computing introduces a new era of low-power and high-speed circuit designs. Instead o... more Approximate computing introduces a new era of low-power and high-speed circuit designs. Instead of strict accurate computation, relaxed requirements might increase performance and reduce power consumption with a simplified or inaccurate circuit. One of the recent remarkable research efforts is the accuracy-configurable approximate adder designs, which can gracefully operate in both approximate (inaccurate) and accurate modes. In this paper, a novel technique for segmenting approximate adders was proposed by adding new bit locations that exploit the carry kill signal definition to limit carry propagation at specific locations. Moreover, a lightweight carry-in prediction and error detection techniques were proposed. For error recovery circuit, a significance-driven configurable correction stages were implemented, which imply a fast convergence to exact outputs with a very low magnitude of errors. The proposed design showed improvements of (16%) and (18.6%) for dynamic power and area respectively. Nevertheless, outputs reserved a general high accuracy level, which limited between 99% and 100% for the majority of input space. The proposed design was implemented in an image filter application, which resulted in high PSNR values of (53 and 83 db) for the two premier correction stages, and 100% exact results for the highest accuracy mode.
2017 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2017
With increasing resolutions the volume of data generated by image processing applications is esca... more With increasing resolutions the volume of data generated by image processing applications is escalating dramatically. When coupled with real-time performance requirements, reducing energy con- sumption for such a large volume of data is proving challenging.
2017 IEEE International Workshop on Signal Processing Systems (SiPS), 2017
In this paper, we propose an energy-efficient approximate multiplier design approach. Fundamental... more In this paper, we propose an energy-efficient approximate multiplier design approach. Fundamental to this approach is configurable lossy logic compression, coupled with low-cost error mitigation. The logic compression is aimed at reducing the number of product rows using progressive bit significance, and thereby decreasing the number of reduction stages in Wallace-tree accumulation. This accounts for substantially lower number of logic counts and lengths of the critical paths at the cost of errors in lower significant bits. These errors are minimised through a parallel error detection logic and compensation vector. To validate the effectiveness of our approach, multiple 8-bit multipliers are designed and synthesized using Synopses Design Compiler with different logic compression levels. Post synthesis experiments showed the trade-offs between energy and accuracy for these compression levels, featuring up to 70% reduction in power-delay product (PDP) and 60% lower area in the case of...
Approximate computing has recently introduced a new era of low-power and high-speed circuit desig... more Approximate computing has recently introduced a new era of low-power and high-speed circuit designs. Recent efforts in the domain of configurable-accuracy approximate designs have proposed substantial performance gains and energy savings by allowing performance-energy-accuracy trade-offs. In this paper, we propose a configurable-accuracy approximate adder with new lightweight error detection technique. This is followed by significance-driven error correction stages during run-time. The correction starts by recovering the higher magnitude errors at premier correction stages, which results in fast convergence and higher precision outputs. Compared to other equivalent approximate adders, the proposed design has drastically reduced the logic counts used for error detection process; hence, achieving lower overhead of silicon area and improving the energy-efficiency of the adder design with faster convergence to the exact results. A number of different bitwidths of the proposed adder (32-bit to 256-bit) are designed in Verilog and synthesized using Synopsys Design Compiler. Our post-synthesis experiments showed significant reductions of 12% and 10% for Dynamic and Leakage Power respectively, and 8% in the silicon area for the design with full correction stages. Moreover, the proposed adder with large bit-widths has reserved these reduction ratios while presenting better scalability overhead. Additionally, our low overhead proposed design has presented the chance to be improved in terms of increasing accuracy to reach 100% exact results as accurate conventional adder at the final correction stage.
Designing energy-efficient hardware continues to be challenging due to arithmetic complexities. T... more Designing energy-efficient hardware continues to be challenging due to arithmetic complexities. The problem is further exacerbated in systems powered by energy harvesters as variable power levels can limit their computation capabilities. In this work, we propose a run-time configurable adaptive approximation method for multiplication that is capable of managing the energy and performance tradeoffs — ideally suited in these systems. Central to our approach is a Significance-Driven Logic Compression (SDLC) multiplier architecture that can dynamically adjust the level of approximation depending on the run-time power/accuracy constraints. The architecture can be configured to operate in the exact mode (no approximation) or in progressively higher approximation modes (i.e. 2 to 4-bit SDLC). Our method is implemented in both ASIC and FPGA. The implementation results indicate that our design has only a 2.3% silicon overhead, on top of what is required by a traditional exact multiplier. We ...
1 OVERVIEW With increasing resolutions the volume of data generated by image processing applicati... more 1 OVERVIEW With increasing resolutions the volume of data generated by image processing applications is escalating dramatically. When coupled with real-time performance requirements, reducing energy consumption for such a large volume of data is proving challenging. In this paper, we propose a novel approach for image processing applications using signi cance-driven approximate computing. Core to our approach is the fundamental tenet that image data should be processed intelligently based on their informational value, i.e. signi cance. Using quanti ed de nition of signi cance, for the rst time, we show how the complexity of data processing tasks can be drastically reduced when computing decisions are synergistically adapted to signi cance learning principles. A variable-kernel convolution lter case study running on an Odroid XU-4 platform is demonstrated to evaluate the e ectiveness of our approach, with up to 45% energy reduction for a given performance requirement.
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017
Approximate arithmetic has recently emerged as a promising paradigm for many imprecision-tolerant... more Approximate arithmetic has recently emerged as a promising paradigm for many imprecision-tolerant applications. It can offer substantial reductions in circuit complexity, delay and energy consumption by relaxing accuracy requirements. In this paper, we propose a novel energy-efficient approximate multiplier design using a significance-driven logic compression (SDLC) approach. Fundamental to this approach is an algorithmic and configurable lossy compression of the partial product rows based on their progressive bit significance. This is followed by the commutative remapping of the resulting product terms to reduce the number of product rows. As such, the complexity of the multiplier in terms of logic cell counts and lengths of critical paths is drastically reduced. A number of multipliers with different bit-widths (4-bit to 128-bit) are designed in SystemVerilog and synthesized using Synopsys Design Compiler. Post-synthesis experiments showed that up to an order of magnitude energy savings, and reductions of 65% in critical delay and almost 45% in silicon area can be achieved for a 128-bit multiplier compared to an accurate equivalent. These gains are achieved with low accuracy losses estimated at less than 0.00071 mean relative error. Additionally, we demonstrate the energy-accuracy trade-offs for different degrees of compression, achieved through configurable logic clustering. In evaluating the effectiveness of our approach, a case study image processing application showed up to 68.3% energy reduction with negligible losses in image quality expressed as peak signal-to-noise ratio (PSNR).
Approximate arithmetic has recently emerged as a promising paradigm for many imprecision-tolerant... more Approximate arithmetic has recently emerged as a promising paradigm for many imprecision-tolerant applications. It can offer substantial reductions in circuit complexity, delay and energy consumption by relaxing accuracy requirements. In this paper, we propose a novel energy-efficient approximate multiplier design using a significance-driven logic compression (SDLC) approach. Fundamental to this approach is an algorithmic and configurable lossy compression of the partial product rows based on their progressive bit significance. This is followed by the commutative remapping of the resulting product terms to reduce the number of product rows. As such, the complexity of the multiplier in terms of logic cell counts and lengths of critical paths is drastically reduced. A number of multipliers with different bit-widths (4-bit to 128-bit) are designed in SystemVerilog and synthesized using Synopsys Design Compiler. Post-synthesis experiments showed that up to an order of magnitude energy savings, and reductions of 65% in critical delay and almost 45% in silicon area can be achieved for an 128-bit multiplier, compared to an accurate equivalent. These gains are achieved with low accuracy losses estimated at less than 0.0028 mean relative error. Additionally, we demonstrate the performance-energyquality (PEQ) trade-offs for different degrees of compression, achieved through configurable logic clustering. While evaluating the effectiveness of the proposed approach three case studies were set up. First, a Gaussian blur filter was designed, which demonstrated up to 80% energy reduction with a meagre loss of image quality. Second, we evaluate our approach in machine learning application using perceptron classifier, showed up to 74% energy reduction with negligible error rate. Third, the proposed multiplier designs were used in a power-constrained image processing application. We showed that SDLC can achieve 60x improvement in computation capability, with potential to be employed in ubiquitous systems.
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