We present a digital implementation of a TX precoder/ equalizer that, similar to a Tomlinson-Hara... more We present a digital implementation of a TX precoder/ equalizer that, similar to a Tomlinson-Harashima Precoder (THP), provides a decision feedback equalizer (DFE) function on the transmitter side. The TX-DFE avoids error propagation together with the complexity and power overhead of an RX-DFE. The I-tap precoder is implemented using a table-based digital FFE, which also shapes the channel pulse to a 1 +0.5D response and cancels pre-cursor inter-symbol interference (lSI). The combined precoder/8-tap FFE was implemented in 14nm FinFet CMOS, and was measured to operate at 112Gb/s consuming 0.3pJ/bit energy.
In this work, we review progress in III-V transistor technologies. Key approaches for silicon int... more In this work, we review progress in III-V transistor technologies. Key approaches for silicon integration are described, with a distinction being made between large area layer transfer and selective growth techniques. We show how the integration approach must be tailored for the intended application to maximize performance, functionality and minimize cost. We also highlight performance boosters such as heterostructure channel stacks, which offer increased carrier mobility towards improved RF and RF-CMOS performance. Recent progress in tunneling field-effect transistors (TFETs) have enabled the TFET architecture as a process module, allowing for dense integration with MOSFETs on the same chip towards an extremely low-power CMOS technology. Finally, we highlight emerging applications for III-V devices at cryogenic temperatures, where there is a rising need for lowpower electronics to support the scaling of quantum computers. The unique properties of III-V, their high mobility and band gap engineering make them highly suitable for this application.
... NICK MOLL Hewlett-Packard Labs. ... Department Staff Director: FRAN ZAPPULLA Editorial Direct... more ... NICK MOLL Hewlett-Packard Labs. ... Department Staff Director: FRAN ZAPPULLA Editorial Director: VALERIE CAMMARATA Production Director: ROBERT SMREK Transactions Manager: GAIL S. FERENC Electronic Publishing Manager: TOM BONTRAGER Managing Editor ...
Integrated Voltage Regulators (IVRs) are attractive substitutes for conventional voltage regulato... more Integrated Voltage Regulators (IVRs) are attractive substitutes for conventional voltage regulators located on the motherboards, due to outstanding dynamic performances and superior power densities. IVRs operate with switching frequencies in the range of 100 MHz and are assembled in highly compact packages close to the microprocessor load. This paper presents a comprehensive characterization of a PCBand inductor-based four-phase ANPC-type IVR that uses a Power Management IC (PMIC) implemented in a 14 nm CMOS technology node. The characterization is based on the results of electrical measurements, thermal inspections of the chip surface, and simulations, which enables the separation of the total losses into on-chip and off-chip loss components and the allocation of important loss components inside the chip. The investigated IVR achieves a maximum efficiency of 84.1% at an output power of P out = 640 mW and a switching frequency of f s = 50 MHz. The thermal measurements reveal that the maximum efficiency of the PMIC itself is between 88 % and 90 % at f s = 50 MHz and P out ∈ [500 mW, 600 mW]; at P out = 890 mW, a chip current density of 24.7 A/mm 2 is achieved. The findings in particular point out that the losses in the chip-internal interconnections, i.e., the conductors of the Power Distribution Network (PDN) and the twelve stacked metal layers below the PDN, have a substantial contribution to the total losses. Furthermore, the combination of Cadence post-layout simulations with impedance networks obtained from an appropriate software tool, e.g., FastHenry, is found to establish a suitable toolbox for estimating losses in IVRs. INDEX TERMS 14 nm technology, ANPC, CMOS, half-bridge, IVR, multi-phase, PMIC, stacked transistors, thermal electrical characterization.
We report a low-power 4-channel NRZ optical RX including a digital burst-mode CDR measured up to ... more We report a low-power 4-channel NRZ optical RX including a digital burst-mode CDR measured up to 40Gb/s/lane in 14nm CMOS. The RX, designed for 850nm VCSEL based optical links, can wake-up and achieve phase-lock in 8ns at BER<2×10<sup>−12</sup>
2018 European Conference on Optical Communication (ECOC), 2018
The CMOS-compatible front-end integration of ultra-compact lateral current collection III-V/Si ph... more The CMOS-compatible front-end integration of ultra-compact lateral current collection III-V/Si photodetectors on a Silicon Photonics platform is demonstrated for the first time. The novel waveguide-coupled photodiodes show sub-nA dark current, ultra-low capacitance, a high responsivity, and data transmission at 25Gbps.
This work presents an NRZ receiver (RX) implementation for microprocessor application in 7nm FinF... more This work presents an NRZ receiver (RX) implementation for microprocessor application in 7nm FinFET CMOS technology. It covers data rate from 25 to 50Gb/s and features on-chip AC coupling to support a wide input common-mode range. The RX includes two identical banks with their own clock and data recovery (CDR) to dynamically tackle parameter drift over time. A quarter-rate 3-tap fully speculative decision feedback equalizer (DFE) opens eyes over channel with 30dB insertion loss. Current-mode logic (CML) based clock path boasts three degrees of freedom of phase adjustment and random jitter (RJ) attenuation to broaden the eyes. At 0.9V supply the energy efficiency is 2.22pJ/b with 28% eye opening (BER=10−12) at 50Gb/s with PRBS31 and channel loss of 20dB.
A single-channel 12-bit SAR ADC achieving 250-340 MS/s and consuming 4.8-8.0 mW from 0.75 to 0.9 ... more A single-channel 12-bit SAR ADC achieving 250-340 MS/s and consuming 4.8-8.0 mW from 0.75 to 0.9 V is presented. At 300 MS/s, the ADC exhibits 61.6-dB peak SNDR and reaches 60.5-dB SNDR and 78.7-dB SFDR with 0.8-V pp, diff input amplitude at Nyquist. It consumes 7.0 mW from a single 0.85-V supply, where 3.7 mW is contributed by the reference buffer. The key element is a comparator with an inverter-based preamplifier to achieve low-noise performance with below 1-V pp, diff input amplitude. The common-mode (CM) sensitivity of the inverter is counteracted by an SAR-based CM regulation (CMREG). The regulation adjusts the sampled CM to the optimal CM for the maximum inverter gain using a second capacitive DAC. It adjusts the CM on a sample-by-sample basis and, thus, can correct time-varying CM. The implemented CMREG maintains SNDR above 60 dB for a differential input amplitude mismatch of up to 2 dB or a phase mismatch of up to 15 •. Index Terms-14-nm CMOS FinFET common-moderegulation (CMREG) DAC, inverter amplifier, SAR ADC, SAR-based common-mode (CM) rejection.
2015 40th International Conference on Infrared, Millimeter, and Terahertz waves (IRMMW-THz), 2015
A 19×8 pixel array with a read-out integrated circuit was designed and fabricated in a micro-mach... more A 19×8 pixel array with a read-out integrated circuit was designed and fabricated in a micro-machined SOI-CMOS process. The pixels are antenna-coupled MOSFET bolometers operating at room temperature in a wide 0.6-1.2 THz band. The read-out circuit features column multiplexed differential amplifiers, offset calibration capability and chopper stabilization. We present the performance of the read-out circuit building blocks, as well as characterization results of the pixels, which demonstrate good detection sensitivity.
A GaAs integrating optical receiver has been designed and realized using a commercial foundry pro... more A GaAs integrating optical receiver has been designed and realized using a commercial foundry process. The receiver was then transplanted by epitaxial lift off (ELO) onto an InP substrate. This technology allows the monolithical integration of previously incompatible materials onto one chip. To our knowledge the chip described is the most complex chip that has been transplanted by ELO. The
IEEE Transactions on Microwave Theory and Techniques, 2006
The continuous decrease of the supply voltage to 1 V and below in CMOS makes the design of laser ... more The continuous decrease of the supply voltage to 1 V and below in CMOS makes the design of laser drivers a challenging task. Hence, a detailed comparison of three basic driver architectures, namely, common source (CS), CS with source degeneration, and source follower (SF) is presented using transistor models including short channel effects. Based on this comparison, two power-optimized driver topologies are implemented in a 90-nm silicon-on-insulator CMOS technology. The SF driver features a bandwidth of 18 GHz on a 50-/spl Omega/ load. The required chip area is only 140 /spl mu/m/spl times/140 /spl mu/m, which is very beneficial for high-density short-distance optical interconnects. This allows a data rate of 12.5 Gb/s at a bit error ratio of less than 10/sup -12/ to be achieved even with a 10-Gb/s oxide confined vertical-cavity surface-emitting laser (VCSEL). The power consumption is 27 mW. The drivers were optimized for maximal eye opening by applying a fast and accurate VCSEL model.
IEEE Transactions on Terahertz Science and Technology, 2015
In this paper, we present a comprehensive study on the operation of an antenna-coupled THz bolome... more In this paper, we present a comprehensive study on the operation of an antenna-coupled THz bolometer based on a micro-machined SOI-CMOS thermal sensor. The pixels are designed to operate at room temperature in vacuum. We focus on a new planar skirt antenna, which combines high sensitivity within a 0.6-1.2 THz band and 30 HPBW. We present an overview of the design considerations, as well as the characterization results which were obtained with both broadband and CW THz sources. The NEP of the pixel is of the order of 25 pW/Hz , with responsivity 100 mA/W at the optimal operating point. The peak responsivity to a broadband THz signal is 600 mA/W. The ease of integration with a read-out circuit and the low power dissipation make this type of pixel a good candidate for focal plane array architecture. Index Terms-Antenna-coupled bolometers, micromachined sensors, silicon-on-insulator, terahertz (THz) imaging, uncooled sensors. I. INTRODUCTION D RIVEN by a multitude of attractive practical applications, ranging from security to medical diagnostics, from the food industry to material inspection and astronomy, THz imaging is a fast developing research area [1]. The challenges involved with pushing electronic detection up to the THz frequency range are tackled today by adopting a number of complementary approaches. Cryogenic cooled detectors such as transition-edge superconductor (TES) bolometers [2], [3] and kinetic inductance detectors (KIDs) [4], [5] have demonstrated very high sensitivity. The large footprint and large power consumption of these detectors, as well as the reduced pixel count may, however, limit their exploitation potential to high-end systems only. The interest in commercial THz applications was a main driver in recent years to efforts aimed Manuscript
2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018
Optical communication standards, such as ITU OTU-4, OIF 112G and 100/400Gb/s Ethernet, require AD... more Optical communication standards, such as ITU OTU-4, OIF 112G and 100/400Gb/s Ethernet, require ADCs with more than 50GS/s and at least 5 ENOB to enable complex digital equalization, and a growing number of appropriate designs have been presented [1-4], mostly time-interleaved SAR ADCs. Most of these ADCs were not intended for input frequencies up to Nyquist and report an input range up to approximately 20GHz, often equivalent to the analog 3dB bandwidth. Ultimately, the analog bandwidth is less relevant than SNDR at high frequencies because an FIR filter can equalize amplitude degradation, but not increase SNDR. The design presented in this paper does not focus on the 3dB bandwidth, but it is optimized for best SNDR at the Nyquist frequency of up to 36GHz. Low power and area are critical for many applications and are achieved by an optimized SAR that allows low supply voltages while still maintaining high speed and accuracy. At 72GS/s, the ADC achieves 39.3dB at low input frequencies and 30.4dB at Nyquist. It consumes 235mW at 72GS/s and 97mW at 48GS/s, which results in 3.3pJ and 2.0pJ per conversion, respectively. The ADC is implemented in an area of 0.15mm2 in 14nm CMOS FinFET technology.
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018
This paper presents a parallel implementation technique of digital equalizer for high-speed wirel... more This paper presents a parallel implementation technique of digital equalizer for high-speed wireline serial link receiver (RX). In wireline RX, inter-symbol interference (ISI) is mitigated by continuous-time linear equalizer, and the remaining ISI is cancelled out by decision-feedback equalizer (DFE). However, due to the existence of feedback loop in DFE, there is no trivial way to parallelize it, making it difficult to be realized in digital circuits for wireline RX based on analog-to-digital converter (ADC) with ≥ 56 Gb/s data rate. In this work, convolution theorem is applied for achieving parallel digital equalizer implementation. The digital equalizer datapath consists of discrete Fourier transform (DFT) core, inverse-DFT (IDFT) core, complex multipliers between DFT and IDFT cores, and overlap-add circuit. Design considerations for low-area VLSI implementation of such architecture is discussed.
We report a 5Gb/s data link implemented in 14nm FinFET CMOS SOI technology in which a single tran... more We report a 5Gb/s data link implemented in 14nm FinFET CMOS SOI technology in which a single transmitter (TX) broadcasts NRZ data to eight receivers (RXs) distributed along an on-chip RC-dominated 10mm-long channel. The TX comprises a full-rate AC-coupled 2-tap FIR driver with a quarter-rate pre-driver and aligner. Each RX is equipped with a novel decision-gated 1-tap speculative DFE optimized for low-power. The RX architecture is half-rate and sliced data are de-multiplexed and aligned at quarter-rate so that all the bus interfaces are at 1.25Gb/s. PRBS generator and checker are available on-chip. Correct operation was verified with PRBS31 data transmitted at 5Gb/s and concurrently received error-free at each drop with >40% horizontal margin (BER<10 −12) at the RX connected at the end of the channel. At this data-rate the efficiency is 7.1fJ/b/mm, resulting in the best performance among multi-drop on-chip data links so far published (to the best of our knowledge). The TX and eight RXs are running on a 0.5V power supply and consume 0.62 and 0.98mW, respectively.
We present a digital implementation of a TX precoder/ equalizer that, similar to a Tomlinson-Hara... more We present a digital implementation of a TX precoder/ equalizer that, similar to a Tomlinson-Harashima Precoder (THP), provides a decision feedback equalizer (DFE) function on the transmitter side. The TX-DFE avoids error propagation together with the complexity and power overhead of an RX-DFE. The I-tap precoder is implemented using a table-based digital FFE, which also shapes the channel pulse to a 1 +0.5D response and cancels pre-cursor inter-symbol interference (lSI). The combined precoder/8-tap FFE was implemented in 14nm FinFet CMOS, and was measured to operate at 112Gb/s consuming 0.3pJ/bit energy.
In this work, we review progress in III-V transistor technologies. Key approaches for silicon int... more In this work, we review progress in III-V transistor technologies. Key approaches for silicon integration are described, with a distinction being made between large area layer transfer and selective growth techniques. We show how the integration approach must be tailored for the intended application to maximize performance, functionality and minimize cost. We also highlight performance boosters such as heterostructure channel stacks, which offer increased carrier mobility towards improved RF and RF-CMOS performance. Recent progress in tunneling field-effect transistors (TFETs) have enabled the TFET architecture as a process module, allowing for dense integration with MOSFETs on the same chip towards an extremely low-power CMOS technology. Finally, we highlight emerging applications for III-V devices at cryogenic temperatures, where there is a rising need for lowpower electronics to support the scaling of quantum computers. The unique properties of III-V, their high mobility and band gap engineering make them highly suitable for this application.
... NICK MOLL Hewlett-Packard Labs. ... Department Staff Director: FRAN ZAPPULLA Editorial Direct... more ... NICK MOLL Hewlett-Packard Labs. ... Department Staff Director: FRAN ZAPPULLA Editorial Director: VALERIE CAMMARATA Production Director: ROBERT SMREK Transactions Manager: GAIL S. FERENC Electronic Publishing Manager: TOM BONTRAGER Managing Editor ...
Integrated Voltage Regulators (IVRs) are attractive substitutes for conventional voltage regulato... more Integrated Voltage Regulators (IVRs) are attractive substitutes for conventional voltage regulators located on the motherboards, due to outstanding dynamic performances and superior power densities. IVRs operate with switching frequencies in the range of 100 MHz and are assembled in highly compact packages close to the microprocessor load. This paper presents a comprehensive characterization of a PCBand inductor-based four-phase ANPC-type IVR that uses a Power Management IC (PMIC) implemented in a 14 nm CMOS technology node. The characterization is based on the results of electrical measurements, thermal inspections of the chip surface, and simulations, which enables the separation of the total losses into on-chip and off-chip loss components and the allocation of important loss components inside the chip. The investigated IVR achieves a maximum efficiency of 84.1% at an output power of P out = 640 mW and a switching frequency of f s = 50 MHz. The thermal measurements reveal that the maximum efficiency of the PMIC itself is between 88 % and 90 % at f s = 50 MHz and P out ∈ [500 mW, 600 mW]; at P out = 890 mW, a chip current density of 24.7 A/mm 2 is achieved. The findings in particular point out that the losses in the chip-internal interconnections, i.e., the conductors of the Power Distribution Network (PDN) and the twelve stacked metal layers below the PDN, have a substantial contribution to the total losses. Furthermore, the combination of Cadence post-layout simulations with impedance networks obtained from an appropriate software tool, e.g., FastHenry, is found to establish a suitable toolbox for estimating losses in IVRs. INDEX TERMS 14 nm technology, ANPC, CMOS, half-bridge, IVR, multi-phase, PMIC, stacked transistors, thermal electrical characterization.
We report a low-power 4-channel NRZ optical RX including a digital burst-mode CDR measured up to ... more We report a low-power 4-channel NRZ optical RX including a digital burst-mode CDR measured up to 40Gb/s/lane in 14nm CMOS. The RX, designed for 850nm VCSEL based optical links, can wake-up and achieve phase-lock in 8ns at BER<2×10<sup>−12</sup>
2018 European Conference on Optical Communication (ECOC), 2018
The CMOS-compatible front-end integration of ultra-compact lateral current collection III-V/Si ph... more The CMOS-compatible front-end integration of ultra-compact lateral current collection III-V/Si photodetectors on a Silicon Photonics platform is demonstrated for the first time. The novel waveguide-coupled photodiodes show sub-nA dark current, ultra-low capacitance, a high responsivity, and data transmission at 25Gbps.
This work presents an NRZ receiver (RX) implementation for microprocessor application in 7nm FinF... more This work presents an NRZ receiver (RX) implementation for microprocessor application in 7nm FinFET CMOS technology. It covers data rate from 25 to 50Gb/s and features on-chip AC coupling to support a wide input common-mode range. The RX includes two identical banks with their own clock and data recovery (CDR) to dynamically tackle parameter drift over time. A quarter-rate 3-tap fully speculative decision feedback equalizer (DFE) opens eyes over channel with 30dB insertion loss. Current-mode logic (CML) based clock path boasts three degrees of freedom of phase adjustment and random jitter (RJ) attenuation to broaden the eyes. At 0.9V supply the energy efficiency is 2.22pJ/b with 28% eye opening (BER=10−12) at 50Gb/s with PRBS31 and channel loss of 20dB.
A single-channel 12-bit SAR ADC achieving 250-340 MS/s and consuming 4.8-8.0 mW from 0.75 to 0.9 ... more A single-channel 12-bit SAR ADC achieving 250-340 MS/s and consuming 4.8-8.0 mW from 0.75 to 0.9 V is presented. At 300 MS/s, the ADC exhibits 61.6-dB peak SNDR and reaches 60.5-dB SNDR and 78.7-dB SFDR with 0.8-V pp, diff input amplitude at Nyquist. It consumes 7.0 mW from a single 0.85-V supply, where 3.7 mW is contributed by the reference buffer. The key element is a comparator with an inverter-based preamplifier to achieve low-noise performance with below 1-V pp, diff input amplitude. The common-mode (CM) sensitivity of the inverter is counteracted by an SAR-based CM regulation (CMREG). The regulation adjusts the sampled CM to the optimal CM for the maximum inverter gain using a second capacitive DAC. It adjusts the CM on a sample-by-sample basis and, thus, can correct time-varying CM. The implemented CMREG maintains SNDR above 60 dB for a differential input amplitude mismatch of up to 2 dB or a phase mismatch of up to 15 •. Index Terms-14-nm CMOS FinFET common-moderegulation (CMREG) DAC, inverter amplifier, SAR ADC, SAR-based common-mode (CM) rejection.
2015 40th International Conference on Infrared, Millimeter, and Terahertz waves (IRMMW-THz), 2015
A 19×8 pixel array with a read-out integrated circuit was designed and fabricated in a micro-mach... more A 19×8 pixel array with a read-out integrated circuit was designed and fabricated in a micro-machined SOI-CMOS process. The pixels are antenna-coupled MOSFET bolometers operating at room temperature in a wide 0.6-1.2 THz band. The read-out circuit features column multiplexed differential amplifiers, offset calibration capability and chopper stabilization. We present the performance of the read-out circuit building blocks, as well as characterization results of the pixels, which demonstrate good detection sensitivity.
A GaAs integrating optical receiver has been designed and realized using a commercial foundry pro... more A GaAs integrating optical receiver has been designed and realized using a commercial foundry process. The receiver was then transplanted by epitaxial lift off (ELO) onto an InP substrate. This technology allows the monolithical integration of previously incompatible materials onto one chip. To our knowledge the chip described is the most complex chip that has been transplanted by ELO. The
IEEE Transactions on Microwave Theory and Techniques, 2006
The continuous decrease of the supply voltage to 1 V and below in CMOS makes the design of laser ... more The continuous decrease of the supply voltage to 1 V and below in CMOS makes the design of laser drivers a challenging task. Hence, a detailed comparison of three basic driver architectures, namely, common source (CS), CS with source degeneration, and source follower (SF) is presented using transistor models including short channel effects. Based on this comparison, two power-optimized driver topologies are implemented in a 90-nm silicon-on-insulator CMOS technology. The SF driver features a bandwidth of 18 GHz on a 50-/spl Omega/ load. The required chip area is only 140 /spl mu/m/spl times/140 /spl mu/m, which is very beneficial for high-density short-distance optical interconnects. This allows a data rate of 12.5 Gb/s at a bit error ratio of less than 10/sup -12/ to be achieved even with a 10-Gb/s oxide confined vertical-cavity surface-emitting laser (VCSEL). The power consumption is 27 mW. The drivers were optimized for maximal eye opening by applying a fast and accurate VCSEL model.
IEEE Transactions on Terahertz Science and Technology, 2015
In this paper, we present a comprehensive study on the operation of an antenna-coupled THz bolome... more In this paper, we present a comprehensive study on the operation of an antenna-coupled THz bolometer based on a micro-machined SOI-CMOS thermal sensor. The pixels are designed to operate at room temperature in vacuum. We focus on a new planar skirt antenna, which combines high sensitivity within a 0.6-1.2 THz band and 30 HPBW. We present an overview of the design considerations, as well as the characterization results which were obtained with both broadband and CW THz sources. The NEP of the pixel is of the order of 25 pW/Hz , with responsivity 100 mA/W at the optimal operating point. The peak responsivity to a broadband THz signal is 600 mA/W. The ease of integration with a read-out circuit and the low power dissipation make this type of pixel a good candidate for focal plane array architecture. Index Terms-Antenna-coupled bolometers, micromachined sensors, silicon-on-insulator, terahertz (THz) imaging, uncooled sensors. I. INTRODUCTION D RIVEN by a multitude of attractive practical applications, ranging from security to medical diagnostics, from the food industry to material inspection and astronomy, THz imaging is a fast developing research area [1]. The challenges involved with pushing electronic detection up to the THz frequency range are tackled today by adopting a number of complementary approaches. Cryogenic cooled detectors such as transition-edge superconductor (TES) bolometers [2], [3] and kinetic inductance detectors (KIDs) [4], [5] have demonstrated very high sensitivity. The large footprint and large power consumption of these detectors, as well as the reduced pixel count may, however, limit their exploitation potential to high-end systems only. The interest in commercial THz applications was a main driver in recent years to efforts aimed Manuscript
2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018
Optical communication standards, such as ITU OTU-4, OIF 112G and 100/400Gb/s Ethernet, require AD... more Optical communication standards, such as ITU OTU-4, OIF 112G and 100/400Gb/s Ethernet, require ADCs with more than 50GS/s and at least 5 ENOB to enable complex digital equalization, and a growing number of appropriate designs have been presented [1-4], mostly time-interleaved SAR ADCs. Most of these ADCs were not intended for input frequencies up to Nyquist and report an input range up to approximately 20GHz, often equivalent to the analog 3dB bandwidth. Ultimately, the analog bandwidth is less relevant than SNDR at high frequencies because an FIR filter can equalize amplitude degradation, but not increase SNDR. The design presented in this paper does not focus on the 3dB bandwidth, but it is optimized for best SNDR at the Nyquist frequency of up to 36GHz. Low power and area are critical for many applications and are achieved by an optimized SAR that allows low supply voltages while still maintaining high speed and accuracy. At 72GS/s, the ADC achieves 39.3dB at low input frequencies and 30.4dB at Nyquist. It consumes 235mW at 72GS/s and 97mW at 48GS/s, which results in 3.3pJ and 2.0pJ per conversion, respectively. The ADC is implemented in an area of 0.15mm2 in 14nm CMOS FinFET technology.
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018
This paper presents a parallel implementation technique of digital equalizer for high-speed wirel... more This paper presents a parallel implementation technique of digital equalizer for high-speed wireline serial link receiver (RX). In wireline RX, inter-symbol interference (ISI) is mitigated by continuous-time linear equalizer, and the remaining ISI is cancelled out by decision-feedback equalizer (DFE). However, due to the existence of feedback loop in DFE, there is no trivial way to parallelize it, making it difficult to be realized in digital circuits for wireline RX based on analog-to-digital converter (ADC) with ≥ 56 Gb/s data rate. In this work, convolution theorem is applied for achieving parallel digital equalizer implementation. The digital equalizer datapath consists of discrete Fourier transform (DFT) core, inverse-DFT (IDFT) core, complex multipliers between DFT and IDFT cores, and overlap-add circuit. Design considerations for low-area VLSI implementation of such architecture is discussed.
We report a 5Gb/s data link implemented in 14nm FinFET CMOS SOI technology in which a single tran... more We report a 5Gb/s data link implemented in 14nm FinFET CMOS SOI technology in which a single transmitter (TX) broadcasts NRZ data to eight receivers (RXs) distributed along an on-chip RC-dominated 10mm-long channel. The TX comprises a full-rate AC-coupled 2-tap FIR driver with a quarter-rate pre-driver and aligner. Each RX is equipped with a novel decision-gated 1-tap speculative DFE optimized for low-power. The RX architecture is half-rate and sliced data are de-multiplexed and aligned at quarter-rate so that all the bus interfaces are at 1.25Gb/s. PRBS generator and checker are available on-chip. Correct operation was verified with PRBS31 data transmitted at 5Gb/s and concurrently received error-free at each drop with >40% horizontal margin (BER<10 −12) at the RX connected at the end of the channel. At this data-rate the efficiency is 7.1fJ/b/mm, resulting in the best performance among multi-drop on-chip data links so far published (to the best of our knowledge). The TX and eight RXs are running on a 0.5V power supply and consume 0.62 and 0.98mW, respectively.
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Papers by Thomas Morf