A structure device known as the Reed-Muller universal logic module (RM-ULM) is developed based on... more A structure device known as the Reed-Muller universal logic module (RM-ULM) is developed based on a theorem extended from Shannon's expansion theorem to modulo-2 logic. To realize Reed-Muller polynomials in fixed-polarity using RM-ULMs, the problem becomes one of minimization for multiple-output functions. An existing algorithm for minimization of RM polynomials in fixed polarity is modified and applied to the realization of switching functions using RM-ULMs.
Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)
One of the major differences in partitioning for codesign is in the way the communication cost is... more One of the major differences in partitioning for codesign is in the way the communication cost is evaluated. Generally the size of the edge cut-set is used. When communication between components is through buffered channels, the size of the edge cut-set is not adequate to estimate the buffer size. A second important factor to measure the quality of partitioning is the system delay. Most partitioning approaches use the number of nodes/functions in each partition as constraints and attempt to minimize the communication cost. The data dependencies among nodes/functions, and their delays are not considered. In this paper we present partitioning with two objectives: (1) buffer size, which is estimated by analyzing the data flow patterns of the CDFG, and solved as a clique partitioning problem, and (2) the system delay that is estimated using List Scheduling. We pose the problem as a combinatorial optimization and use an efficient non-deterministic search algorithm called Problem-Space Genetic Algorithm to search for the optimum. Experimental results indicate that, according to a proposed quality metric, our approach can attain an average 87% of the optimum for two-way partitioning.
Proceedings IEEE SOUTHEASTCON '97. 'Engineering the New Century', 1997
The trends of high-level synthesis are moving from using elementary operations to more complicate... more The trends of high-level synthesis are moving from using elementary operations to more complicated operations. These complex operations are implemented by using complicated functional units. Most complex components only have single data I/O ports (buses) so that memory devices, such as stacks, are inside the components to hold the input operands and results for execution. Traditional register allocation algorithms can not be applied directly because the internal memory devices can used to hold the intermediate values. An algorithm which is based on the Hungarian Method has been developed to minimize the use of registers when complex functional units are used.
A structure device known as the Reed-Muller universal logic module (RM-ULM) is developed based on... more A structure device known as the Reed-Muller universal logic module (RM-ULM) is developed based on a theorem extended from Shannon's expansion theorem to modulo-2 logic. To realize Reed-Muller polynomials in fixed-polarity using RM-ULMs, the problem becomes one of minimization for multiple-output functions. An existing algorithm for minimization of RM polynomials in fixed polarity is modified and applied to the realization of switching functions using RM-ULMs.
Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273)
Partitioning is a very important task in hardware/software co-design. Generally the size of the e... more Partitioning is a very important task in hardware/software co-design. Generally the size of the edge cut-set is used to evaluate the communication cost. When communication between components is through buffered channels, the size of the edge cut-set is not adequate to estimate the buffer size. A second important factor to measure the quality of partitioning is the system delay. Most partitioning approaches use the number of nodes/functions in each partition as constraints and attempt to minimize the communication cost. The data dependencies among nodes/functions, and their delays are not considered. In this paper we present partitioning with two objectives: (1) buffer size, which is estimated by analyzing the data flow patterns of the CDFG, and solved as a clique partitioning problem, and (2) the system delay that is estimated using List Scheduling. We pose the problem as a combinatorial optimization and use an efficient non-deterministic search algorithm called Problem-Space Genetic Algorithm to search for the optimum. Results are compared with those produced by simulated annealing.
A structure device known as the Reed-Muller universal logic module (RM-ULM) is developed based on... more A structure device known as the Reed-Muller universal logic module (RM-ULM) is developed based on a theorem extended from Shannon's expansion theorem to modulo-2 logic. To realize Reed-Muller polynomials in fixed-polarity using RM-ULMs, the problem becomes one of minimization for multiple-output functions. An existing algorithm for minimization of RM polynomials in fixed polarity is modified and applied to the realization of switching functions using RM-ULMs.
Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)
One of the major differences in partitioning for codesign is in the way the communication cost is... more One of the major differences in partitioning for codesign is in the way the communication cost is evaluated. Generally the size of the edge cut-set is used. When communication between components is through buffered channels, the size of the edge cut-set is not adequate to estimate the buffer size. A second important factor to measure the quality of partitioning is the system delay. Most partitioning approaches use the number of nodes/functions in each partition as constraints and attempt to minimize the communication cost. The data dependencies among nodes/functions, and their delays are not considered. In this paper we present partitioning with two objectives: (1) buffer size, which is estimated by analyzing the data flow patterns of the CDFG, and solved as a clique partitioning problem, and (2) the system delay that is estimated using List Scheduling. We pose the problem as a combinatorial optimization and use an efficient non-deterministic search algorithm called Problem-Space Genetic Algorithm to search for the optimum. Experimental results indicate that, according to a proposed quality metric, our approach can attain an average 87% of the optimum for two-way partitioning.
Proceedings IEEE SOUTHEASTCON '97. 'Engineering the New Century', 1997
The trends of high-level synthesis are moving from using elementary operations to more complicate... more The trends of high-level synthesis are moving from using elementary operations to more complicated operations. These complex operations are implemented by using complicated functional units. Most complex components only have single data I/O ports (buses) so that memory devices, such as stacks, are inside the components to hold the input operands and results for execution. Traditional register allocation algorithms can not be applied directly because the internal memory devices can used to hold the intermediate values. An algorithm which is based on the Hungarian Method has been developed to minimize the use of registers when complex functional units are used.
A structure device known as the Reed-Muller universal logic module (RM-ULM) is developed based on... more A structure device known as the Reed-Muller universal logic module (RM-ULM) is developed based on a theorem extended from Shannon's expansion theorem to modulo-2 logic. To realize Reed-Muller polynomials in fixed-polarity using RM-ULMs, the problem becomes one of minimization for multiple-output functions. An existing algorithm for minimization of RM polynomials in fixed polarity is modified and applied to the realization of switching functions using RM-ULMs.
Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273)
Partitioning is a very important task in hardware/software co-design. Generally the size of the e... more Partitioning is a very important task in hardware/software co-design. Generally the size of the edge cut-set is used to evaluate the communication cost. When communication between components is through buffered channels, the size of the edge cut-set is not adequate to estimate the buffer size. A second important factor to measure the quality of partitioning is the system delay. Most partitioning approaches use the number of nodes/functions in each partition as constraints and attempt to minimize the communication cost. The data dependencies among nodes/functions, and their delays are not considered. In this paper we present partitioning with two objectives: (1) buffer size, which is estimated by analyzing the data flow patterns of the CDFG, and solved as a clique partitioning problem, and (2) the system delay that is estimated using List Scheduling. We pose the problem as a combinatorial optimization and use an efficient non-deterministic search algorithm called Problem-Space Genetic Algorithm to search for the optimum. Results are compared with those produced by simulated annealing.
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