JICS. Journal of integrated circuits and systems, Feb 3, 2022
This Special Issues brings four invited papers that describe the state of the art techniques to i... more This Special Issues brings four invited papers that describe the state of the art techniques to improve fault tolerance on complex designs. Integrated circuits operating under radiation can experience undesirable faults that must be evaluated and mitigated. Mitigation can be implemented by redundancy in hardware or in software, and by selecting and protecting the most critical parts of the system. Radiation effects test and analysis also play an important step in identifying the criticality of the system and helping designers to better apply fault mitigation techniques.
Approximate Triple Modular Redundancy (ATMR), which is the implementation of TMR with approximate... more Approximate Triple Modular Redundancy (ATMR), which is the implementation of TMR with approximate versions of the target circuit, has emerged in recent years as an alternative to partial hardware replication where designers can explore reduced area overhead combined with some compromise on fault masking. This work presents a novel approach for implementing approximate TMR that combines the approximate gate library (ApxLib) technique with heuristics. The algorithm initially defines the gates to be approximated using testability and observability measures and then chooses the gate transformation based on the bits difference. Experimental results showed good trade-off between the ATMR schemes efficiency in terms of area and fault masking and the computational effort needed to generate them. 2. TMR and approximate-TMR TMR increases the area by 200%, plus the area of the majority
There is an increasing interest in aerospace industry to increment the flexibility of the systems... more There is an increasing interest in aerospace industry to increment the flexibility of the systems and reduce their cost. In this way, FPGAs offer several advantages as low-cost platform to deploy customized systems. However, the use of sub-micron technologies has increased their sensitivity to radiation-induced transient faults. Therefore, the mitigation of soft errors in systems based on soft-core microprocessors has become a major concern not only in the case of configuration memory protection, but also in the case of data and control-flow maintenance. Software-based fault tolerance techniques represent a valid alternative to improve the reliability in such systems at a reduced cost, but the associated time and memory overheads can limit their applicability. This chapter provides different implementation alternatives of software-based techniques in order to reduce overheads while keeping the reliability at the same level.
A software technique is presented to protect commercial multi-core microprocessors against radiat... more A software technique is presented to protect commercial multi-core microprocessors against radiation-induced soft errors. Important time overheads associated with conventional software redundancy techniques limit the feasibility of advanced critical electronic systems. In our approach, redundant bare-metal threads are used, so that critical computation is distributed over the different microprocessor cores. In doing so, software redundancy can be applied to Commercial Off-The-Shelf (COTS) microprocessors without incurring highperformance penalties. The proposed technique was evaluated using a low-cost single board computer (Raspberry Pi 4) under neutron irradiation. The results showed that the Redundant Multi-Threading versions detected and recovered all the Silent Data Corruption (SDC) events, and only increased HANG sensitivity with respect to the unhardened original versions. In addition, higher Mean Work to Failure (MWTF) estimations are achieved with our bare-metal technique than with the state-of-the-art bare-metal software-based techniques that only implement temporal redundancy.
Statistical fault injection is widely used to estimate the reliability of mission-critical microp... more Statistical fault injection is widely used to estimate the reliability of mission-critical microprocessor-based systems when exposed to radiation and to evaluate the performance of fault mitigation strategies. However, further research is needed to gain a better understanding of the accuracy of the results and the feasibility of their application under realistic radiation conditions. In this article, an understanding of scenarios in which Instruction Set Architecture simulators or emulators may be relied upon for realistic statistical fault injection campaigns is advanced. An analysis is presented of the results from two simulation-based fault injection tools versus a set of fault emulation results on a real processor. The conclusions of the analysis assist the selection of the most efficient tool and method for testing many different software-based fault mitigation techniques within reasonable time periods and at affordable costs throughout an irradiation campaign. In particular, it was established that a partially ordered set of relations could be defined on the basis of statistical fault injection in relation to the effects of different versions of an application and a given simulator that remained unaltered during the irradiation experiments. The tests were conducted with a Texas Instruments MSP430 microcontroller to perform both fault injection campaigns and irradiation experiments using neutrons at the Los Alamos Neutron Science Center (LANSCE) Weapons Neutron Research Facility at Los Alamos, USA.
2019 IEEE Latin American Test Symposium (LATS), 2019
This paper presents a technique to mitigate faults induced by radiation in standalone embedded sy... more This paper presents a technique to mitigate faults induced by radiation in standalone embedded systems based on multi-core processors. To achieve this goal, the well known Modular Redundancy technique has been extended to take advantage of several instruction flows running on different cores. Particularly, results showing softerror mitigation using three instruction flows (threads) are presented in this work. Our technique defines a relaxed lockstep model to synchronize the execution of redundant threads on different cores. Simulated fault injection campaigns were carried out using a multi-core ARM system. The results obtained show that multi-thread versions presents similar or improved protection compared to single-threaded versions, but with reduced performance overhead.
This paper presents a fault injection tool and methodology for performing Single-Event-Upsets (SE... more This paper presents a fault injection tool and methodology for performing Single-Event-Upsets (SEUs) injection campaigns on Commercial-off-the-shelf (COTS) microprocessors. This method takes advantage of the debug facilities of modern microprocessors along with standard GNU Debugger (GDB) for executing and debugging benchmarks. The developed experiments on real boards, as well as on virtual machines, demonstrate the feasibility and flexibility of the proposal as a low-cost solution for assessing the reliability of COTS microprocessors
El profesorado de la red docente presenta durante el curos 2012/2013 el presente proyecto de segu... more El profesorado de la red docente presenta durante el curos 2012/2013 el presente proyecto de seguimiento y coordinacion de las asignaturas que forman parte del Master en Ingenieria de Telecomunicacion. Este master que se imparte desde la Escuela Politecnica Superior, es el titulo que habilita para el ejercicio de la profesion regulada de Ingeniero de Telecomunicacion. Consta de 90 ECTS y se imparte a lo largo de 2 cursos academicos. El master esta implantado desde el curso 2011-2012 por lo que durante el actual curso 2012-2013 tendremos egresados de la primera promocion. Este proyecto tiene como objetivo principal el seguimiento, coordinacion, evaluacion y mejora de la planificacion realizada previamente con las experiencias recogidas y registradas a lo largo de estos primeros cursos de imparticion.
En el curso 2015-16 se implanto la nueva titulacion de grado en Ingenieria Robotica en la Univers... more En el curso 2015-16 se implanto la nueva titulacion de grado en Ingenieria Robotica en la Universidad de Alicante. Este grado es el primero en el territorio nacional de estas caracteristicas. El perfil de los estudiantes es una combinacion entre un ingeniero industrial y uno informatico, perfil muy demandado por las empresas. Por lo tanto, esta es la segunda vez que se imparte el primer curso de esta titulacion. Se hace necesario una coordinacion de los contenidos de las asignaturas para evitar posibles solapes o carencias y mas cuando ya se ha implantado el segundo curso de la titulacion, donde se pueden identificar posibles carencias en los contenidos.
A high-level C++ hardening library is designed for the protection of critical software against th... more A high-level C++ hardening library is designed for the protection of critical software against the harmful effects of radiation environments that can damage systems. A mathematical and empirical model to predict system behavior in the presence of radiation induced faults is also presented. This model generates a quick evaluation and adjustment of several reliability vs. performance trade-offs, to optimize radiation hardening based on the proposed C++ hardening library. Several simulations and irradiation campaigns with protons and neutrons are used to build the model and to tune it. Finally, the effects of our hardening approach are compared with other hardened and non-hardened approaches.
Este articulo expone un metodo para incrementar la fiabilidad de las aplicaciones embebidas guian... more Este articulo expone un metodo para incrementar la fiabilidad de las aplicaciones embebidas guiando la compilacion con algoritmos geneticos y una estrategia de optimizacion multi-objetivo.
El control de calidad se ha convertido en un elemento clave del proceso productivo, tanto en las ... more El control de calidad se ha convertido en un elemento clave del proceso productivo, tanto en las industriales de materias primas como manufactureras, La deteccion de forma temprana de determinadas taras en la produccion, puede acarrear un ahorro sustancial en tiempo y dinero, con el consiguiente aumento de la competitividad de las empresas. Por otro lado, la clasificacion de los productos en funcion de ciertos parametros de calidad permite diversificar la oferta y aprovechar al maximo los recursos. Tradicionalmente las tareas de inspeccion y evaluacion de calidad, son llevadas a cabo por personal especializado, por lo que este tipo de control adolece de las limitaciones propias del factor humano. Como consecuencia, existe un creciente interes en las dos ultimas decadas, por la aplicacion de metodos automaticos en los controles de calidad industrial. La informacion visual, y en concreto la textura que presentan las superficies, juega un papel fundamental a la hora de evaluar la calidad de muchos productos (frutas, hortalizas, papel, aluminio, tejidos, etc..). Ademas, el desarrollo de metodos de vision artificial cada vez mas sofisticados unido al estado de la tecnologia, hace prever que, en principio, una gran cantidad de problemas de inspeccion puedan ser abordados con garantias de exito. A pesar de todo, los sistemas de inspeccion visual automaticos no han conseguido implantarse en el sector productivo de una manera clara debido a diversas causas, entre las que cabria destacar la complejidad de los algoritmos y el elevado coste de los sistemas necesarios para ejecutarlos eficientemente. El presente trabajo se enmarca dentro de la problematica del diseno de estos sistemas, incidiendo en dos aspectos, que a mi juicio pueden mejorar y facilitar su implantacion. En primer lugar, el diseno de nuevos algoritmos de analisis de texturas, que conjuguen una banda complejidad computacional con una elevada capacidad de
Approximate Triple Modular Redundancy (ATMR), which is the implementation of TMR with approximate... more Approximate Triple Modular Redundancy (ATMR), which is the implementation of TMR with approximate versions of the target circuit, has emerged in recent years as an alternative to partial replication. This work presents a novel approach for implementing approximate TMR that combines an approximate gate library (ApxLib) with a Multi-Objective Optimization Genetic Algorithm (MOOGA). The algorithm initially performs a blind search, over the huge solution space, optimizing error coverage and area overhead altogether over the next interactions. Experiments compare our approach with a state of the art technique showing an improvement of trade-offs for different benchmark circuits.
Commercial off-the-shelf microprocessors are the core of low-cost embedded systems due to their p... more Commercial off-the-shelf microprocessors are the core of low-cost embedded systems due to their programmability and cost-effectiveness. Recent advances in electronic technologies have allowed remarkable improvements in their performance. However, they have also made microprocessors more susceptible to transient faults induced by radiation. These non-destructive events (soft errors), may cause a microprocessor to produce a wrong computation result or lose control of a system with catastrophic consequences. Therefore, soft error mitigation has become a compulsory requirement for an increasing number of applications, which operate from the space to the ground level. In this context, this paper uses the concept of selective hardening, which is aimed to design reduced-overhead and flexible mitigation techniques. Following this concept, a novel flexible version of the software-based fault recovery technique known as SWIFT-R is proposed. Our approach makes possible to select different registers subsets from the microprocessor register file to be protected on software. Thus, design space is enriched with a wide spectrum of new partially protected versions, which offer more flexibility to designers. This permits to find the best tradeoffs between performance, code size, and fault coverage. Three case studies have been developed to show the applicability and flexibility of the proposal.
JICS. Journal of integrated circuits and systems, Feb 3, 2022
This Special Issues brings four invited papers that describe the state of the art techniques to i... more This Special Issues brings four invited papers that describe the state of the art techniques to improve fault tolerance on complex designs. Integrated circuits operating under radiation can experience undesirable faults that must be evaluated and mitigated. Mitigation can be implemented by redundancy in hardware or in software, and by selecting and protecting the most critical parts of the system. Radiation effects test and analysis also play an important step in identifying the criticality of the system and helping designers to better apply fault mitigation techniques.
Approximate Triple Modular Redundancy (ATMR), which is the implementation of TMR with approximate... more Approximate Triple Modular Redundancy (ATMR), which is the implementation of TMR with approximate versions of the target circuit, has emerged in recent years as an alternative to partial hardware replication where designers can explore reduced area overhead combined with some compromise on fault masking. This work presents a novel approach for implementing approximate TMR that combines the approximate gate library (ApxLib) technique with heuristics. The algorithm initially defines the gates to be approximated using testability and observability measures and then chooses the gate transformation based on the bits difference. Experimental results showed good trade-off between the ATMR schemes efficiency in terms of area and fault masking and the computational effort needed to generate them. 2. TMR and approximate-TMR TMR increases the area by 200%, plus the area of the majority
There is an increasing interest in aerospace industry to increment the flexibility of the systems... more There is an increasing interest in aerospace industry to increment the flexibility of the systems and reduce their cost. In this way, FPGAs offer several advantages as low-cost platform to deploy customized systems. However, the use of sub-micron technologies has increased their sensitivity to radiation-induced transient faults. Therefore, the mitigation of soft errors in systems based on soft-core microprocessors has become a major concern not only in the case of configuration memory protection, but also in the case of data and control-flow maintenance. Software-based fault tolerance techniques represent a valid alternative to improve the reliability in such systems at a reduced cost, but the associated time and memory overheads can limit their applicability. This chapter provides different implementation alternatives of software-based techniques in order to reduce overheads while keeping the reliability at the same level.
A software technique is presented to protect commercial multi-core microprocessors against radiat... more A software technique is presented to protect commercial multi-core microprocessors against radiation-induced soft errors. Important time overheads associated with conventional software redundancy techniques limit the feasibility of advanced critical electronic systems. In our approach, redundant bare-metal threads are used, so that critical computation is distributed over the different microprocessor cores. In doing so, software redundancy can be applied to Commercial Off-The-Shelf (COTS) microprocessors without incurring highperformance penalties. The proposed technique was evaluated using a low-cost single board computer (Raspberry Pi 4) under neutron irradiation. The results showed that the Redundant Multi-Threading versions detected and recovered all the Silent Data Corruption (SDC) events, and only increased HANG sensitivity with respect to the unhardened original versions. In addition, higher Mean Work to Failure (MWTF) estimations are achieved with our bare-metal technique than with the state-of-the-art bare-metal software-based techniques that only implement temporal redundancy.
Statistical fault injection is widely used to estimate the reliability of mission-critical microp... more Statistical fault injection is widely used to estimate the reliability of mission-critical microprocessor-based systems when exposed to radiation and to evaluate the performance of fault mitigation strategies. However, further research is needed to gain a better understanding of the accuracy of the results and the feasibility of their application under realistic radiation conditions. In this article, an understanding of scenarios in which Instruction Set Architecture simulators or emulators may be relied upon for realistic statistical fault injection campaigns is advanced. An analysis is presented of the results from two simulation-based fault injection tools versus a set of fault emulation results on a real processor. The conclusions of the analysis assist the selection of the most efficient tool and method for testing many different software-based fault mitigation techniques within reasonable time periods and at affordable costs throughout an irradiation campaign. In particular, it was established that a partially ordered set of relations could be defined on the basis of statistical fault injection in relation to the effects of different versions of an application and a given simulator that remained unaltered during the irradiation experiments. The tests were conducted with a Texas Instruments MSP430 microcontroller to perform both fault injection campaigns and irradiation experiments using neutrons at the Los Alamos Neutron Science Center (LANSCE) Weapons Neutron Research Facility at Los Alamos, USA.
2019 IEEE Latin American Test Symposium (LATS), 2019
This paper presents a technique to mitigate faults induced by radiation in standalone embedded sy... more This paper presents a technique to mitigate faults induced by radiation in standalone embedded systems based on multi-core processors. To achieve this goal, the well known Modular Redundancy technique has been extended to take advantage of several instruction flows running on different cores. Particularly, results showing softerror mitigation using three instruction flows (threads) are presented in this work. Our technique defines a relaxed lockstep model to synchronize the execution of redundant threads on different cores. Simulated fault injection campaigns were carried out using a multi-core ARM system. The results obtained show that multi-thread versions presents similar or improved protection compared to single-threaded versions, but with reduced performance overhead.
This paper presents a fault injection tool and methodology for performing Single-Event-Upsets (SE... more This paper presents a fault injection tool and methodology for performing Single-Event-Upsets (SEUs) injection campaigns on Commercial-off-the-shelf (COTS) microprocessors. This method takes advantage of the debug facilities of modern microprocessors along with standard GNU Debugger (GDB) for executing and debugging benchmarks. The developed experiments on real boards, as well as on virtual machines, demonstrate the feasibility and flexibility of the proposal as a low-cost solution for assessing the reliability of COTS microprocessors
El profesorado de la red docente presenta durante el curos 2012/2013 el presente proyecto de segu... more El profesorado de la red docente presenta durante el curos 2012/2013 el presente proyecto de seguimiento y coordinacion de las asignaturas que forman parte del Master en Ingenieria de Telecomunicacion. Este master que se imparte desde la Escuela Politecnica Superior, es el titulo que habilita para el ejercicio de la profesion regulada de Ingeniero de Telecomunicacion. Consta de 90 ECTS y se imparte a lo largo de 2 cursos academicos. El master esta implantado desde el curso 2011-2012 por lo que durante el actual curso 2012-2013 tendremos egresados de la primera promocion. Este proyecto tiene como objetivo principal el seguimiento, coordinacion, evaluacion y mejora de la planificacion realizada previamente con las experiencias recogidas y registradas a lo largo de estos primeros cursos de imparticion.
En el curso 2015-16 se implanto la nueva titulacion de grado en Ingenieria Robotica en la Univers... more En el curso 2015-16 se implanto la nueva titulacion de grado en Ingenieria Robotica en la Universidad de Alicante. Este grado es el primero en el territorio nacional de estas caracteristicas. El perfil de los estudiantes es una combinacion entre un ingeniero industrial y uno informatico, perfil muy demandado por las empresas. Por lo tanto, esta es la segunda vez que se imparte el primer curso de esta titulacion. Se hace necesario una coordinacion de los contenidos de las asignaturas para evitar posibles solapes o carencias y mas cuando ya se ha implantado el segundo curso de la titulacion, donde se pueden identificar posibles carencias en los contenidos.
A high-level C++ hardening library is designed for the protection of critical software against th... more A high-level C++ hardening library is designed for the protection of critical software against the harmful effects of radiation environments that can damage systems. A mathematical and empirical model to predict system behavior in the presence of radiation induced faults is also presented. This model generates a quick evaluation and adjustment of several reliability vs. performance trade-offs, to optimize radiation hardening based on the proposed C++ hardening library. Several simulations and irradiation campaigns with protons and neutrons are used to build the model and to tune it. Finally, the effects of our hardening approach are compared with other hardened and non-hardened approaches.
Este articulo expone un metodo para incrementar la fiabilidad de las aplicaciones embebidas guian... more Este articulo expone un metodo para incrementar la fiabilidad de las aplicaciones embebidas guiando la compilacion con algoritmos geneticos y una estrategia de optimizacion multi-objetivo.
El control de calidad se ha convertido en un elemento clave del proceso productivo, tanto en las ... more El control de calidad se ha convertido en un elemento clave del proceso productivo, tanto en las industriales de materias primas como manufactureras, La deteccion de forma temprana de determinadas taras en la produccion, puede acarrear un ahorro sustancial en tiempo y dinero, con el consiguiente aumento de la competitividad de las empresas. Por otro lado, la clasificacion de los productos en funcion de ciertos parametros de calidad permite diversificar la oferta y aprovechar al maximo los recursos. Tradicionalmente las tareas de inspeccion y evaluacion de calidad, son llevadas a cabo por personal especializado, por lo que este tipo de control adolece de las limitaciones propias del factor humano. Como consecuencia, existe un creciente interes en las dos ultimas decadas, por la aplicacion de metodos automaticos en los controles de calidad industrial. La informacion visual, y en concreto la textura que presentan las superficies, juega un papel fundamental a la hora de evaluar la calidad de muchos productos (frutas, hortalizas, papel, aluminio, tejidos, etc..). Ademas, el desarrollo de metodos de vision artificial cada vez mas sofisticados unido al estado de la tecnologia, hace prever que, en principio, una gran cantidad de problemas de inspeccion puedan ser abordados con garantias de exito. A pesar de todo, los sistemas de inspeccion visual automaticos no han conseguido implantarse en el sector productivo de una manera clara debido a diversas causas, entre las que cabria destacar la complejidad de los algoritmos y el elevado coste de los sistemas necesarios para ejecutarlos eficientemente. El presente trabajo se enmarca dentro de la problematica del diseno de estos sistemas, incidiendo en dos aspectos, que a mi juicio pueden mejorar y facilitar su implantacion. En primer lugar, el diseno de nuevos algoritmos de analisis de texturas, que conjuguen una banda complejidad computacional con una elevada capacidad de
Approximate Triple Modular Redundancy (ATMR), which is the implementation of TMR with approximate... more Approximate Triple Modular Redundancy (ATMR), which is the implementation of TMR with approximate versions of the target circuit, has emerged in recent years as an alternative to partial replication. This work presents a novel approach for implementing approximate TMR that combines an approximate gate library (ApxLib) with a Multi-Objective Optimization Genetic Algorithm (MOOGA). The algorithm initially performs a blind search, over the huge solution space, optimizing error coverage and area overhead altogether over the next interactions. Experiments compare our approach with a state of the art technique showing an improvement of trade-offs for different benchmark circuits.
Commercial off-the-shelf microprocessors are the core of low-cost embedded systems due to their p... more Commercial off-the-shelf microprocessors are the core of low-cost embedded systems due to their programmability and cost-effectiveness. Recent advances in electronic technologies have allowed remarkable improvements in their performance. However, they have also made microprocessors more susceptible to transient faults induced by radiation. These non-destructive events (soft errors), may cause a microprocessor to produce a wrong computation result or lose control of a system with catastrophic consequences. Therefore, soft error mitigation has become a compulsory requirement for an increasing number of applications, which operate from the space to the ground level. In this context, this paper uses the concept of selective hardening, which is aimed to design reduced-overhead and flexible mitigation techniques. Following this concept, a novel flexible version of the software-based fault recovery technique known as SWIFT-R is proposed. Our approach makes possible to select different registers subsets from the microprocessor register file to be protected on software. Thus, design space is enriched with a wide spectrum of new partially protected versions, which offer more flexibility to designers. This permits to find the best tradeoffs between performance, code size, and fault coverage. Three case studies have been developed to show the applicability and flexibility of the proposal.
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