Papers by Sanket S Dessai
Graphical Processing Units (GPUs) have become an integral part of today’s mainstream computing sy... more Graphical Processing Units (GPUs) have become an integral part of today’s mainstream computing systems. They are also being used as reprogrammable General Purpose GPUs (GP-GPUs) to perform complex scientific computations. Reconfigurability is an attractive approach to embedded systems allowing hardware level modification. Hence, there is a high demand for GPU designs based on reconfigurable hardware. This paper presents the architectural design, modelling and simulation of reconfigurable stream processor and texture filtering unit of a GPU. Stream processor consists of clusters of functional units which provide a bandwidth hierarchy, supporting hundreds of arithmetic units. The arithmetic cluster units are designed to exploit instruction level parallelism and subword parallelism within a cluster and data parallelism across the clusters. The texture filter unit is designed to process geometric data like vertices and convert these into pixels on the screen. This process involves numbe...
Background noise has always been undesirable in end user communication devices while conversing o... more Background noise has always been undesirable in end user communication devices while conversing over a mobile phone if the speaker is on a busy road or noisy environment. Noise cancellation mechanism can be implemented in these mobiles devices to suppress the background noise and pass only speech signal to the other end. Android is fast growing mobiles phone and expanding to all segments of the market; thus a noise cancellation mechanism can benefit a wide range of user. This paper describes the design and development of Noise Cancellation System (NCS) to cancel the background noise from the speech signal of speaker in android mobile phones. NCS system has been implemented using an adaptive filter, which changes its filter characteristic according to the change in behavior of the input signal to minimize the noise in signal. Least Mean Square (LMS) algorithm has been used for adapting the filter weights. The adaptive filter has two inputs one as desired signal corrupted by noise and another only background noise. Two separate microphones are used to capture these signals respectively; the regular microphone into which the speaker speaks captures signal with noise. The other microphone is directed away from the speaker and thus captures background noise. The system has been modelled and its performance tuned in MATLAB. The tuned adaptive filter is implemented in C on a GNU/Linux environment which is then ported to android SDK and tested for its functionality in android emulator. The tested NCS application has been installed on friendlyARM mini2440 board with android OS. The performance of the adaptive filter has been compared with different filter taps and stepsize for speech signal. A filter length 128 and stepsize 0.9 for the adaptive filter in NCS provided the best performance. With these tuned parameters, the NCS application has been able to perform acceptable adaptive noise cancellation. The quality of the required signal can be further improved by enhancing the adaptive filter algorithm.
International Journal of Reconfigurable and Embedded Systems (IJRES), 2013
Graphical Processing Units (GPUs) have become an integral part of today's mainstream computing sy... more Graphical Processing Units (GPUs) have become an integral part of today's mainstream computing systems. They are also being used as reprogrammable General Purpose GPUs (GP-GPUs) to perform complex scientific computations. Reconfigurability is an attractive approach to embedded systems allowing hardware level modification. Hence, there is a high demand for GPU designs based on reconfigurable hardware. Stream processor consists of clusters of functional units which provide a bandwidth hierarchy, supporting hundreds of arithmetic units. The arithmetic cluster units are designed to exploit instruction level parallelism and subword parallelism within a cluster and data parallelism across the clusters.For decreasing the area and power, a single controller is used to control data flow between clusters and between host processor and GPU. The designed of stream processor unit has been carried out in Verilog on Altera Quartus II and simulated using ModelSim tools. The functionality of the modelled blocks is verified using test inputs in the simulator.The simulated execution time of 8bit pipelined multiplier is 60 ps and 100 ns for 8-bit pipelined adder while operating at 90 MHz.
International Journal of Reconfigurable and Embedded Systems (IJRES), 2012
Graphical Processing Units (GPUs) have become an integral part of today's mainstream computing sy... more Graphical Processing Units (GPUs) have become an integral part of today's mainstream computing systems. They are also being used as reprogrammable General Purpose GPUs (GP-GPUs) to perform complex scientific computations. Reconfigurability is an attractive approach to embedded systems allowing hardware level modification. Hence, there is a high demand for GPU designs based on reconfigurable hardware. The texture filter unit is designed to process geometric data like vertices and convert these into pixels on the screen. This process involves number of operations, like circle and cube generation, rotator, and scaling. The texture filter unit is designed with all necessary hardware to deal with all the different filtering operations. The designed texture filtering units are modelled in Verilog on Altera Quartus II and simulated using ModelSim tools. The functionality of the modelled blocks is verified using test inputs in the simulator.Circle and cube coordinates are generated for circle and cube generation. The work can form the basis for designing a complete reconfigurable GPU.
International Journal of …, 2009
AbstractAs the World-Wide Web (WWW) continues to evolve, it is clear that its underlying technol... more AbstractAs the World-Wide Web (WWW) continues to evolve, it is clear that its underlying technologies are useful for much more than just browsing the web. Web browsers have become the de facto standard user interface for a variety of applications including embedded real time ...
... Determine the Performance of Tractor Sumitkumar Ingle1, Sanket Dessai1, and Rekha Gore2 1 MS ... more ... Determine the Performance of Tractor Sumitkumar Ingle1, Sanket Dessai1, and Rekha Gore2 1 MS Ramaiah School of Advanced Studies in Collaboration with Coventry University (UK)/Embedded Design Centre, ... [4] HA Dwyer, CV Kulkarni and CJ Brodrick, Analysis of the ...
International Journal of Reconfigurable and Embedded Systems (IJRES), 2013
Mobile phones are backbone of the mobile communications and have experienced fastest growing segm... more Mobile phones are backbone of the mobile communications and have experienced fastest growing segment in the consumer market. In the 3G and 4G mobiles, video recording is an essential entertainment features so the user can record and play the video within the mobile phone. In this paper, video capture and playback implementation had been carried out by integrating the camera module to the GSM phone. An alaysis of the video processing had been carried out. Image sensor and LCD module had been interfaced with the base band processor through the video processor. To interface the different module necessary PCB schematic diagram had been arrived. Software implementation had been carried out for the Human Machine Interface for various settings of the camera module, which is integrated with the video processor. The developed playback system had been tested for the various senerious. In this video has been captured through the camera sensor and at the time of playback measured the resolution, power consumption and image transfer rates of the various modules used in the developed camera phone.
Traffic congestion has been a major problem on roads around the world. In addition, there is incr... more Traffic congestion has been a major problem on roads around the world. In addition, there is increase in volume of traffic vehicle density at a steady rate. Thus traffic on major roads has to be controlled to keep the traffic flowing at an acceptable rate. Several schemes for replacing the predominantly used Round Robin (RR) scheme for reducing congestion at traffic junctions have been proposed. Dynamic traffic control schemes adapt to the changing traffic by monitoring the state (such as the number queued up on each lane.). These need appropriate sensing and monitoring systems. In this paper a traffic monitoring and control system based on AMR (Anistropic Magneto Resistive) vehicle sensors, wireless sensor network and a proiritised Weighted Round Robin (WRR) scheduling technique, is developed.AMR sensors installed in road pavement detect the number of vehicles waiting in a traffic lane. The AMR sensors are connected to the master controller to form a ZigBee based sensor network. The master node consists of an ARM processor integrated with a ZigBee masternode. The traffic control algorithm is implemented at master node which is responsible for taking traffic signaling decision. It receives sensor data from all the lanes. A two level priority algorithm with weighted round robin scheduling, where first and second maximum weighted lane are to pass the signal is developed, To avoid starving the least loaded lanes, a cycle of normal round robin scheduling is performed after four rounds of proiritised weighted round robin schedule. The proposed algorithm is simulated and compared with the standard round robin algorithm. The developed algorithm decreases the average waiting time for a commuter while maintaining the average throughput up to average loads. The development traffic monitoring system is successfully demonstrated for a four lane junction.
International Journal of Reconfigurable and Embedded Systems (IJRES)
Office automation is the process using machines with the help of embedded computing perform the o... more Office automation is the process using machines with the help of embedded computing perform the office activities and its tools and applications. The office automated using computer-aided processing stored, visual and audio data to simplify, improve, and automate the power saving and time management of the organization. A very important component of office automation concerns the automation of employee centred activities such as authentication, automatic alerting of appointments and automatic powering on/off personal computer. The employee image is captured using Java media framework, attendance records for all employees is gathered and processed automatically, and they can be accessed from the database on a monthly or weekly basis. The various software and hardware components of the system were developed and integrated to form the Exypnos Office System and validated on real life scenarios. Java proved to be a versatile platform for implementing a project of this nature with diverse...
Face recognition is the biometric application to recognise the identity. Face recognition applica... more Face recognition is the biometric application to recognise the identity. Face recognition application holds a set of images which are called databases stored by the user at cloud database. Cloud computing environment, database can be stored in the cloud environment to achieve huge data storage area. The problem with these data storages are that because of that huge size processing on this storage takes too much of compiling time. This paper aims to develop face recognition in mobile cloud environment by exploiting data or task parallelism in existing face recognition algorithms. To design and develop parallel PCA based face recognition algorithm. The parallel PCA face recognition algorithm has been deployed in the cloud server for performing PCA by request of user. It matches the image on the cloud server and gives response back to the user in the fewer amounts of time and with reduced latency. The developed Parallel PCA face recognition algorithm has minimized the overall response ...
Processor efficiency is a important in embedded system. The efficiency of the processor depends o... more Processor efficiency is a important in embedded system. The efficiency of the processor depends on the L1 cache and translation lookaside buffer (TLB). It is required to understand the L1 cache and TLB performances during varied load for the execution on the processor and hence studies the performance of the varing load and its performance with caches with MIPS and operating system (OS) are studied in this paper. The proposed methods of implementation in the paper considers the counting of the instruction exxecution for respective cache and TLB management and the events are measured using a dedicated counters in software. The software counters are used as there are limitation to hardware counters in the MIPS32. Twenty-seven metrics are considered for analysis and proper identification and implemented for the performance measurement of L1 cache and TLB on the MIPS32 processor. The generated data helps in future research in compiler tuning, memory management design for OS, analysing a...
International Journal of Reconfigurable and Embedded Systems (IJRES)
With an increasing usage of ARM9 core for different kinds of applications ranging from data acqui... more With an increasing usage of ARM9 core for different kinds of applications ranging from data acquisition to Mobile application, there arises the need for developing ARM9 based board. To bring up this board, board supporting package (BSP) is must. Board supporting package virtualizes the platform hardware so that the different drivers can be ported easily on any hardware. The boot loader is the initial stage of firmware, which initializes the hardware components presents on the board. A universal Bootloader is chosen and is to be customized with respect to target board. In the later section bootloader is interfaced to the kernel which is obtained form an authorized distributor under general purpose license. The customized board specific routines as well drivers are ported onto the hardware. Then the compiled kernel image is ported onto the target board using a debugger and SAM-BA utility. Linux kernel has seen major releases; the basic architecture of the Linux kernel has remained mor...
International Journal of Reconfigurable and Embedded Systems (IJRES)
This paper aims for providing a viable solution for security in streaming media technology. Servi... more This paper aims for providing a viable solution for security in streaming media technology. Service providers do not want the end users to capture and duplicate streaming media data. Once captured data can be re-distributed to millions without any control from the source. Licensing issues also dictate the number of times end user may utilize the data. Encryption is not sufficient as it leaves the system vulnerable to duplication and recording after decryption. In this paper an attempt has been made to transmit digital multimedia data to multiple users. The transmission of the video/audio data has been attempted from one PC to another PC. While doing this, security considerations have to be taken care by using suitable encryption/decryption techniques. A research carried out on the different data transmission protocols reveals that the Secure Real Time Transport Protocol (SRTP) is one of the best available protocols. Hence the SRTP has been deployed in this project on Linux OS usin...
International Journal of Reconfigurable and Embedded Systems (IJRES)
To access any device, it is necessary to have an access point. A device driver is an entry point ... more To access any device, it is necessary to have an access point. A device driver is an entry point to access a device. This project is aimed to customize the Wi-Fi and general packet radio service (GPRS) device drivers in Linux OS for PXA270 (Intel Xscale ARM processor). Customizing a device driver is a special way of designing software that can be more easily ported from one architecture to another without rewriting it from scratch. The paper is discussing about the customisation of Wi-Fi and GPRS device driver in Linux OS for PXA270 (Intel Xscale ARM processor). To develop a device driver, it is necessary to understand the processor architecture and Linux kernel internals and other design constraints. Since dynamically loaded driver module is attached to the existing kernel, and any error in the driver will crash the entire system. Resource allocation and implementation for a device is one of the main concerns for device driver developers. The device resources are input/output, memo...
International Journal of Software Engineering and Technologies (IJSET)
Efficiency of a processor is a critical factor for an embedded system. One of the deciding factor... more Efficiency of a processor is a critical factor for an embedded system. One of the deciding factors for efficiency is the functioning of the L1 cache and Translation Lookaside Buffer (TLB). Certain processors have the L1 cache and TLB managed by the operating system, MIPS32 is one such processor. The performance of the L1 cache and TLB necessitates a detailed study to understand its management during varied load on the processor. This paper presents an implementation to analyse the performance of the MIPS32 processor L1 cache and TLB management by the operating system (OS) using software engineering approach. Software engineering providing better clearity for the system developemt and its performance analysis.In the initial stage if the requirement analysis for the performance measurment sort very clearly,the methodologies for the implementation becomes very economical without any ambigunity.In this paper a implementation is proposed to determine the processor performance metrics usi...
International Journal of Reconfigurable and Embedded Systems, Mar 1, 2015
Beverage vending machine systems are becoming popular in the Indian market. These systems are tod... more Beverage vending machine systems are becoming popular in the Indian market. These systems are today available in Indian MNCs and some top rated restaurants and hotels. In most systems the operation are carried manually by the operator in which the billing and change making is carried out by the owner who runnig the shop or restaurant. In India tea and coffee habits were cultured by the colonial rule of the British and the Portuguese, even tody the colonial rule had been over but the habits of tea and coffee beverage consumptions becomes as the routine daily life. Hence there is a need to understand beverage vending machine systems to serve the Indian Market. In this paper, a critical analysis of requirement has been carried out and the system design had been arrived at.The system requirement demand an ARM based controller for better system performance. To meet the system performance criteria and richest of peripherals an LPC2148 with low cost had been selected. The system is more efficient to analyse the change making and the identification had been carried out using the motors, LCDs, water heater, solenoid valve, money box, change making and dispensing unit. The system is tested and validated for the specified test cases. The milk motor run for 10 rotations to drive 200 milligrams of milk powder to the container to make to tea or coffee beverage. In this system a stepper motor had been used can be replaced by using dc motors to avaoid power losses. In future an ATM or credit card based payment system can be incorporated to these systems.
International Journal of Reconfigurable and Embedded Systems, Nov 1, 2014
An IP (intellectual property) core is a block of logic or data that is used in making a field pro... more An IP (intellectual property) core is a block of logic or data that is used in making a field programmable gate array (FPGA) or application-specific integrated circuit (ASIC) for a product. As essential elements of design reuse, IP cores are part of the growing electronic design automation (EDA) industry trend towards repeated use of previously designed components. Ethernet continues to be one of the most popular LAN technologies. Due to the robustness resulting from its wide acceptance and deployment, there has been an attempt to build Ethernet-based real-time control networks for manufacturing automation. There is a growing demand for low cost, power efficient MAC IP Core for various embedded applications. In this paper a project is discussed to design an Ethernet MAC IP Core solution for such embedded applications. The proposed 10_100_1000 Mbps tri-mode Ethernet MAC implements a MAC controller conforming to IEEE 802.3 specification. It is designed to use less than 2000 LCs/LEs to implement full function. It will use inferred RAMs and PADs to reduce technology dependence. To increase the flexibility, three optional modules can be added to or removed from the project. A GUI configuration interface, created by Tcl/tk script language, is convenient for configuring optional modules, FIFO depth and verification parameters. Furthermore, a verification system was designed with Tcl/tk user interface, by which the stimulus can be generated automatically and the output packets can be verified with CRC-32 checksum. A solution which would consume a smaller part of the targeted FPGA, and thus giving room for other on-chip peripherals or enable the use of a smaller sized FPGA. To employ a smaller FPGA is desirable since it would reduce power consumption and device price.
International Journal of Reconfigurable and Embedded Systems, Nov 1, 2014
Traffic congestion has been a major problem on roads around the world. In addition, there is incr... more Traffic congestion has been a major problem on roads around the world. In addition, there is increase in volume of traffic vehicle density at a steady rate. Thus traffic on major roads has to be controlled to keep the traffic flowing at an acceptable rate. Several schemes for replacing the predominantly used Round Robin (RR) scheme for reducing congestion at traffic junctions have been proposed. Dynamic traffic control schemes adapt to the changing traffic by monitoring the state (such as the number queued up on each lane). These need appropriate sensing and monitoring systems. In this paper a traffic monitoring and control system based on AMR (Anistropic Magneto Resistive) vehicle sensors, wireless sensor network and a proiritised Weighted Round Robin (WRR) scheduling technique, is developed.AMR sensors installed in road pavement detect the number of vehicles waiting in a traffic lane. The AMR sensors are connected to the master controller to form a Zigbee based sensor network. The master node consists of an ARM processor integrated with a Zigbee masternode. The traffic control algorithm is implemented at master node which is responsible for taking traffic signaling decision. It receives sensor data from all the lanes. A two level priority algorithm with weighted round robin scheduling, where first and second maximum weighted lane are to pass the signal is developed, To avoid starving the least loaded lanes, a cycle of normal round robin scheduling is performed after four rounds of proiritised weighted round robin schedule. The proposed algorithm is simulated and compared with the standard round robin algorithm. The developed algorithm decreases the average waiting time for a commuter while maintaining the average throughput up to average loads. The development traffic monitoring system is successfully demonstrated for a four lane junction.
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Papers by Sanket S Dessai