2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), 2017
Runtime hardware Trojan detection techniques are required in third party IP based SoCs as a last ... more Runtime hardware Trojan detection techniques are required in third party IP based SoCs as a last line of defense. Traditional techniques rely on golden data model or exotic signal processing techniques such as utilizing Choas theory or machine learning. Due to cumbersome implementation of such techniques, it is highly impractical to embed them on the hardware, which is a requirement in some mission critical applications. In this paper, we propose a methodology that generates a digital power profile during the manufacturing test phase of the circuit under test. A simple processing mechanism, which requires minimal computation of measured power signals, is proposed. For the proof of concept, we have applied the proposed methodology on a classical Advanced Encryption Standard circuit with 21 available Trojans. The experimental results show that the proposed methodology is able to detect 75% of the intrusions with the potential of implementing the detection mechanism on-chip with minimal overhead compared to the state-of-the-art techniques.
With ongoing advances of semiconductor technology, power dissipation has been moving higher on th... more With ongoing advances of semiconductor technology, power dissipation has been moving higher on the list of VLSI design constraints. In most high-performance synchronous VLSI designs, the distribution of low-skew global clock signals approaching GigaHertz range is the single largest source of power consumption. GALS design style offers a solution to this issue by dividing synchronous design into smaller locally synchronous sub-blocks. Smaller sub-blocks reduce capacitance in clock distribution networks because they need less H-tree levels. However, this implies a large number of sub-blocks, which increases the asynchronous power overhead. This work investigates these GALS power tradeoffs. This is, to our knowledge, the first paper to propose closed form models for optimum number of partitions that gives minimum power for a GALS array of identical processors. The models can serve as a useful firsthand guideline for designers in initial design stages. Experimental results verify the ef...
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018
The recent advancements in system-on-chip (SoC) and network-on-chip (NoC) have enormously increas... more The recent advancements in system-on-chip (SoC) and network-on-chip (NoC) have enormously increased the number of on-chip frequency domains that are originating from multiple on-chip clock sources. In modern battery-operated internet of things (IoT) devices, limited power budget and requirement for complex clock distribution schemes increases the usage clock multipliers. These multiple clock signal requirements are usually catered for by using frequency multipliers with clock generators. However, most of these multipliers are based on analog components that require a customized layout, involve timing uncertainties, and are power hungry and highly prone to mismatches in the process variations and environmental changes. Moreover, in modern battery-operated smart devices for IoT have very limited power budget, which makes the design of clock multipliers even more challenging. To address these issues, we propose a delay-based digital frequency multiplier, which uses 2-input XNOR gates and a true single-phase clock (TSPC) flip-flop because of pulse generation and edge detection properties, respectively. The proposed multiplier is based on the digital components, therefore, it reduces the power consumption significantly, i.e., 1.6mW, which is almost 50% lesser than other low power state-of-the-art designs. Moreover, it can operate for a wide range of input frequencies, ∼400MHz to 1GHz. The Monte-Carlo simulation results are very promising as they indicate the robustness of the design against process and environmental variations.
2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017
Deep learning is gaining popularity in the recent years due to its impressive performance in diff... more Deep learning is gaining popularity in the recent years due to its impressive performance in different application areas. Convolutional Neural Network (CNN) is the state-of-the-art deep learning architecture that is being used widely in the areas of image recognition, speech recognition and many other applications. CNN is computationally intensive and resource hungry architecture. Hence, its efficient hardware implementation is one of the challenges faced by researchers. FPGAs are the dominating platform choice when it comes to implementation of such architectures. This paper presents an efficient implementation of convolutional layer of CNN, that can substantially reduce the long computational time by utilizing the parallel usage of memories. The technique proposed distributes the input image to be classified into P memories; where P is obtained as an optimum trade-off between number of clock cycles and memory resources. Reading concurrently from all P memories reduces the required...
2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), 2017
This paper proposes novel soft error detection and mitigation technique in reduced instruction se... more This paper proposes novel soft error detection and mitigation technique in reduced instruction set computer (RISC) based pipeline processors. We leveraged the data encoding techniques (re-computing with rotated operands (RERO)) in conjunction with back pressure controlling mechanism in pipeline architecture. In order to alleviate the performance degradation due to potential stalling, we exploited the inherent ALU redundancy in conjunction with data encoding. Synthesis results on Stratix II FPGA from Altera suggested that if 5% of the instructions are subject to soft error then for 2.25 additional stall cycles (on average) our proposed ALU-redundancy based solution in conjunction with data encoding provides better execution time even if the clock cycle time increases up to 11% because of additional hardware. Area wise our technique requires up to 3 times lesser area compared to other contemporary techniques and provides soft error tolerance in combinational blocks along with intermed...
2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), 2017
In most power analysis attack, power traces obtained from the cryptographic device are aligned us... more In most power analysis attack, power traces obtained from the cryptographic device are aligned using a crypto device based triggering signal. In reality, the attacker does not have the luxury of inserting a trigger in the encryption device source code. This paper aims to execute a CPA attack on an 8 bit PIC-microcontroller (μC) implementation of AES-128 encryption without a crypto μC-based triggering signal. To address the misalignment, a unique methodology that features the introduction of an intermediate μC coupled with a suitable alignment method is applied. The proposed method is able to extract each byte of the key of an AES-128 using 200 power traces with a correlation coefficient of 0.6225.
A large-scale integration of plug-in electric vehicles (PEVs) into the power grid system has nece... more A large-scale integration of plug-in electric vehicles (PEVs) into the power grid system has necessitated the design of online scheduling algorithms to accommodate the after-effects of this new type of load, i.e., PEVs, on the overall efficiency of the power system. In online settings, the low computational complexity of the corresponding scheduling algorithms is of paramount importance for the reliable, secure, and efficient operation of the grid system. Generally, the computational complexity of an algorithm is computed using asymptotic analysis. Traditionally, the analysis is performed using the paper-pencil proof method, which is error-prone and thus not suitable for analyzing the mission-critical online scheduling algorithms for PEV charging. To overcome these issues, this paper presents a formal asymptotic analysis approach for online scheduling algorithms for PEV charging using higher-order-logic theorem proving, which is a sound computer-based verification approach. For illu...
2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST), 2016
It is a consensus among the researchers, although not proven, that it is close to impossible to g... more It is a consensus among the researchers, although not proven, that it is close to impossible to guarantee completely secure hardware design. Therefore, it is desired to have run-time hardware Trojan detection techniques. This paper is toward developing a framework of how to achieve run-time hardware Trojan detection units. Although it is difficult to predict the stage of circuit design at which hardware intruder would insert Trojan as well as the hardware Trojan detection methodology that should be applied, behavior patterns of certain design units in the hardware can indicate malicious activities in the design. We propose to translate such behavior patterns using formal verification approaches to establish run-time hardware Trojan detection technique leading which can improve the resiliency of hardware designs against hardware Trojan. We examine the possibility of malicious intrusions in both combinational and sequential circuits that may result in functional incorrectness, and applied our methodology in two example circuits.
Glitches due to the secondary neutron particles from cosmic rays cause soft errors in integrated ... more Glitches due to the secondary neutron particles from cosmic rays cause soft errors in integrated circuits (IC) that are becoming a major threat in modern sub 45nm ICs. Therefore, researchers have developed many techniques to mitigate the soft errors and some of them utilize the built in error detection schemes of low-power asynchronous null conventional logic (NCL). However, it requires extensive simulations and emulations for careful and complete analysis of the design, which can be costly, time consuming and cannot encompass all the possible input conditions. In this paper, we propose a framework to improve the soft error tolerant asynchronous pipelines by identifying and formally analyzing the vulnerable paths using the nuXmv model checker. The proposed framework translates the design behavior and specification into a state-space model
2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS), 2014
3-D ICs provide more logic space by introducing a multiple tier structure. Through silicon vias (... more 3-D ICs provide more logic space by introducing a multiple tier structure. Through silicon vias (TSVs) are utilized for signal propagation between multiple tiers. However, TSVs are vulnerable to fracture, which leads to lower yield. This paper analyzes different yield aware TSV redundancy techniques from a hardware overhead and effective redundancy perspective. A set of mathematical relationships is derived to obtain a first-order approximation of effective redundancy and hardware design overhead. One of the results indicates that for 250 inter-tier TSV signals, the hardware overhead for 3x3 router based redundancy technique is about 3 times more than 1:4 TSV redundancy technique, while providing 5 times more effective redundancy per cell. Such results provide an early design stage estimate for the ASIC designer. We applied our proposed technique to clock domain crossing (CDC) interfaces.
2013 14th European Conference on Radiation and Its Effects on Components and Systems (RADECS), 2013
A new investigation of the dependence of the Single Event Transient (SET) pulse broadening on the... more A new investigation of the dependence of the Single Event Transient (SET) pulse broadening on the input pattern i.e. fan-in, propagation paths, pulse polarity and re-convergent paths is presented. Worst and best SET pulse propagation paths are identified.
2007 IEEE International Symposium on Circuits and Systems, 2007
Systems-on-chip (SoCs) designed in ultra-deep sub-micron technologies (90nm and beyond) often com... more Systems-on-chip (SoCs) designed in ultra-deep sub-micron technologies (90nm and beyond) often comprise modules in multiple clock domains (MCD), which are usually interconnected using asynchronous interfaces. At the same time, in ultra-deep sub-micron (DSM) technologies, minimum width, spacing, inter-metal dielectric lengths are reduced, as well as distances between metal layers. These trends raise the coupling capacitance resulting in more severe crosstalks.
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014
ABSTRACT Due to shrinking feature sizes and significant reduction in noise margins, as CMOS techn... more ABSTRACT Due to shrinking feature sizes and significant reduction in noise margins, as CMOS technologies evolve toward ultra-deep sub-micron, digital circuits have become more susceptible to soft errors. Therefore, researchers have recently reported several approaches to model Single Event Transient (SET) propagation at gate or higher abstraction levels. However, contemporary techniques model only the possibility that SET pulse may be masked electrically, logically, or by time windowing. In this paper, the propagation induced pulse broadening (PIPB) phenomenon is further investigated and a new model which abstracts this phenomenon is proposed. This paper also investigates and abstracts the impact of input patterns and propagation paths on SET pulse width. Through electrical simulations, we validated our analysis.
2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS), 2014
Glitches due to soft errors have become a major concern in circuits designed in ultra-deep sub-mi... more Glitches due to soft errors have become a major concern in circuits designed in ultra-deep sub-micron technologies. Most of the soft error mitigation techniques require redundancy and are power hungry. Recently, low power quasi delay insensitive (QDI) null conventional logic based asynchronous circuits have been proposed, but these circuits work for pure asynchronous designs only. This paper extends the lowpower soft-error-tolerant asynchronous technique for conventional synchronous circuits. The main idea is to accommodate asynchronous standard cells within the synchronous pipeline, and thus giving rise to a macro synchronous micro asynchronous (MSMA) pipeline. An important application of this design is found in detecting the hardware Trojans. The state-of-the-art signature based hardware Trojan detection is implemented using the clock referencing signals for timing signatures. However, an intruder can intrude into clock distribution network itself and may lead to many false positive or even false negative cases. Asynchronous handshake signals, on the other hand, provide event trigger nature to the digital system, and hence the timing analysis is unique to the data path itself alone, without getting affected by the clock distribution network. This paper provides a proof of concept soft error tolerant MSMA design. Time delay based signature without using clock distribution network is obtained to detect hardware Trojan insertion in MSMA.
IEEE Transactions on Circuits and Systems I: Regular Papers, 2010
This paper proposes a novel solution to make asynchronous handshake interfaces tolerant to crosst... more This paper proposes a novel solution to make asynchronous handshake interfaces tolerant to crosstalk-glitch propagation (GP). This study leverages our recently proposed crosstalkglitch modeling technique for asynchronous systems, which models the crosstalk GP in asynchronous interfaces. In this paper, a novel set of solutions to quench the GP is proposed. This set of solutions is called crosstalk-glitch gating, as the quenching is obtained by using carefully generated control signals. A step-by-step method is recommended to apply crosstalk-glitch gating to conventional asynchronous handshake interfaces. Transistor-level electrical simulations demonstrate that our method effectively generates crosstalkglitch gate-controlling signals. In comparison with contemporary signal-integrity management techniques, our gating methodology can be applied to fewer nodes and earlier in the design cycle.
Globalization trends in integrated circuit (IC) design using deep sub-micron (DSM) technologies a... more Globalization trends in integrated circuit (IC) design using deep sub-micron (DSM) technologies are leading to increased vulnerability against malicious intrusions. Various techniques have been proposed to detect such threats during design or testing phases of ICs. However, due to infinitely many possibilities of Trojans, there exists a possibility that some of these intrusions go undetected. Therefore, runtime Trojan detection techniques are needed to detect the Trojans for complete operation lifetime as a last line of defense. In this paper, we proposed a generic methodology, which leverages the burst mode communication protocol, to detect the intrusions during runtime. Our methodology has three phases: 1) behavioral modeling of design specifications along with its verification using linear temporal logic (LTL) in the model checker. 2) Counterexamples generated in phase 1 are used to insert run-time monitors at vulnerable paths. 3) Embed run-time monitors into the system and validate it. Unlike the other state-of-the-art techniques, the proposed methodology can be easily used to design the runtime monitoring setup without having netlist information of IP modules. We validated our approach by applying it on the AES Trojan benchmarks that utilize intermodule interface to communicate with other modules in the system on chip (SoC).
2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), 2017
Runtime hardware Trojan detection techniques are required in third party IP based SoCs as a last ... more Runtime hardware Trojan detection techniques are required in third party IP based SoCs as a last line of defense. Traditional techniques rely on golden data model or exotic signal processing techniques such as utilizing Choas theory or machine learning. Due to cumbersome implementation of such techniques, it is highly impractical to embed them on the hardware, which is a requirement in some mission critical applications. In this paper, we propose a methodology that generates a digital power profile during the manufacturing test phase of the circuit under test. A simple processing mechanism, which requires minimal computation of measured power signals, is proposed. For the proof of concept, we have applied the proposed methodology on a classical Advanced Encryption Standard circuit with 21 available Trojans. The experimental results show that the proposed methodology is able to detect 75% of the intrusions with the potential of implementing the detection mechanism on-chip with minimal overhead compared to the state-of-the-art techniques.
With ongoing advances of semiconductor technology, power dissipation has been moving higher on th... more With ongoing advances of semiconductor technology, power dissipation has been moving higher on the list of VLSI design constraints. In most high-performance synchronous VLSI designs, the distribution of low-skew global clock signals approaching GigaHertz range is the single largest source of power consumption. GALS design style offers a solution to this issue by dividing synchronous design into smaller locally synchronous sub-blocks. Smaller sub-blocks reduce capacitance in clock distribution networks because they need less H-tree levels. However, this implies a large number of sub-blocks, which increases the asynchronous power overhead. This work investigates these GALS power tradeoffs. This is, to our knowledge, the first paper to propose closed form models for optimum number of partitions that gives minimum power for a GALS array of identical processors. The models can serve as a useful firsthand guideline for designers in initial design stages. Experimental results verify the ef...
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018
The recent advancements in system-on-chip (SoC) and network-on-chip (NoC) have enormously increas... more The recent advancements in system-on-chip (SoC) and network-on-chip (NoC) have enormously increased the number of on-chip frequency domains that are originating from multiple on-chip clock sources. In modern battery-operated internet of things (IoT) devices, limited power budget and requirement for complex clock distribution schemes increases the usage clock multipliers. These multiple clock signal requirements are usually catered for by using frequency multipliers with clock generators. However, most of these multipliers are based on analog components that require a customized layout, involve timing uncertainties, and are power hungry and highly prone to mismatches in the process variations and environmental changes. Moreover, in modern battery-operated smart devices for IoT have very limited power budget, which makes the design of clock multipliers even more challenging. To address these issues, we propose a delay-based digital frequency multiplier, which uses 2-input XNOR gates and a true single-phase clock (TSPC) flip-flop because of pulse generation and edge detection properties, respectively. The proposed multiplier is based on the digital components, therefore, it reduces the power consumption significantly, i.e., 1.6mW, which is almost 50% lesser than other low power state-of-the-art designs. Moreover, it can operate for a wide range of input frequencies, ∼400MHz to 1GHz. The Monte-Carlo simulation results are very promising as they indicate the robustness of the design against process and environmental variations.
2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017
Deep learning is gaining popularity in the recent years due to its impressive performance in diff... more Deep learning is gaining popularity in the recent years due to its impressive performance in different application areas. Convolutional Neural Network (CNN) is the state-of-the-art deep learning architecture that is being used widely in the areas of image recognition, speech recognition and many other applications. CNN is computationally intensive and resource hungry architecture. Hence, its efficient hardware implementation is one of the challenges faced by researchers. FPGAs are the dominating platform choice when it comes to implementation of such architectures. This paper presents an efficient implementation of convolutional layer of CNN, that can substantially reduce the long computational time by utilizing the parallel usage of memories. The technique proposed distributes the input image to be classified into P memories; where P is obtained as an optimum trade-off between number of clock cycles and memory resources. Reading concurrently from all P memories reduces the required...
2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), 2017
This paper proposes novel soft error detection and mitigation technique in reduced instruction se... more This paper proposes novel soft error detection and mitigation technique in reduced instruction set computer (RISC) based pipeline processors. We leveraged the data encoding techniques (re-computing with rotated operands (RERO)) in conjunction with back pressure controlling mechanism in pipeline architecture. In order to alleviate the performance degradation due to potential stalling, we exploited the inherent ALU redundancy in conjunction with data encoding. Synthesis results on Stratix II FPGA from Altera suggested that if 5% of the instructions are subject to soft error then for 2.25 additional stall cycles (on average) our proposed ALU-redundancy based solution in conjunction with data encoding provides better execution time even if the clock cycle time increases up to 11% because of additional hardware. Area wise our technique requires up to 3 times lesser area compared to other contemporary techniques and provides soft error tolerance in combinational blocks along with intermed...
2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), 2017
In most power analysis attack, power traces obtained from the cryptographic device are aligned us... more In most power analysis attack, power traces obtained from the cryptographic device are aligned using a crypto device based triggering signal. In reality, the attacker does not have the luxury of inserting a trigger in the encryption device source code. This paper aims to execute a CPA attack on an 8 bit PIC-microcontroller (μC) implementation of AES-128 encryption without a crypto μC-based triggering signal. To address the misalignment, a unique methodology that features the introduction of an intermediate μC coupled with a suitable alignment method is applied. The proposed method is able to extract each byte of the key of an AES-128 using 200 power traces with a correlation coefficient of 0.6225.
A large-scale integration of plug-in electric vehicles (PEVs) into the power grid system has nece... more A large-scale integration of plug-in electric vehicles (PEVs) into the power grid system has necessitated the design of online scheduling algorithms to accommodate the after-effects of this new type of load, i.e., PEVs, on the overall efficiency of the power system. In online settings, the low computational complexity of the corresponding scheduling algorithms is of paramount importance for the reliable, secure, and efficient operation of the grid system. Generally, the computational complexity of an algorithm is computed using asymptotic analysis. Traditionally, the analysis is performed using the paper-pencil proof method, which is error-prone and thus not suitable for analyzing the mission-critical online scheduling algorithms for PEV charging. To overcome these issues, this paper presents a formal asymptotic analysis approach for online scheduling algorithms for PEV charging using higher-order-logic theorem proving, which is a sound computer-based verification approach. For illu...
2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST), 2016
It is a consensus among the researchers, although not proven, that it is close to impossible to g... more It is a consensus among the researchers, although not proven, that it is close to impossible to guarantee completely secure hardware design. Therefore, it is desired to have run-time hardware Trojan detection techniques. This paper is toward developing a framework of how to achieve run-time hardware Trojan detection units. Although it is difficult to predict the stage of circuit design at which hardware intruder would insert Trojan as well as the hardware Trojan detection methodology that should be applied, behavior patterns of certain design units in the hardware can indicate malicious activities in the design. We propose to translate such behavior patterns using formal verification approaches to establish run-time hardware Trojan detection technique leading which can improve the resiliency of hardware designs against hardware Trojan. We examine the possibility of malicious intrusions in both combinational and sequential circuits that may result in functional incorrectness, and applied our methodology in two example circuits.
Glitches due to the secondary neutron particles from cosmic rays cause soft errors in integrated ... more Glitches due to the secondary neutron particles from cosmic rays cause soft errors in integrated circuits (IC) that are becoming a major threat in modern sub 45nm ICs. Therefore, researchers have developed many techniques to mitigate the soft errors and some of them utilize the built in error detection schemes of low-power asynchronous null conventional logic (NCL). However, it requires extensive simulations and emulations for careful and complete analysis of the design, which can be costly, time consuming and cannot encompass all the possible input conditions. In this paper, we propose a framework to improve the soft error tolerant asynchronous pipelines by identifying and formally analyzing the vulnerable paths using the nuXmv model checker. The proposed framework translates the design behavior and specification into a state-space model
2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS), 2014
3-D ICs provide more logic space by introducing a multiple tier structure. Through silicon vias (... more 3-D ICs provide more logic space by introducing a multiple tier structure. Through silicon vias (TSVs) are utilized for signal propagation between multiple tiers. However, TSVs are vulnerable to fracture, which leads to lower yield. This paper analyzes different yield aware TSV redundancy techniques from a hardware overhead and effective redundancy perspective. A set of mathematical relationships is derived to obtain a first-order approximation of effective redundancy and hardware design overhead. One of the results indicates that for 250 inter-tier TSV signals, the hardware overhead for 3x3 router based redundancy technique is about 3 times more than 1:4 TSV redundancy technique, while providing 5 times more effective redundancy per cell. Such results provide an early design stage estimate for the ASIC designer. We applied our proposed technique to clock domain crossing (CDC) interfaces.
2013 14th European Conference on Radiation and Its Effects on Components and Systems (RADECS), 2013
A new investigation of the dependence of the Single Event Transient (SET) pulse broadening on the... more A new investigation of the dependence of the Single Event Transient (SET) pulse broadening on the input pattern i.e. fan-in, propagation paths, pulse polarity and re-convergent paths is presented. Worst and best SET pulse propagation paths are identified.
2007 IEEE International Symposium on Circuits and Systems, 2007
Systems-on-chip (SoCs) designed in ultra-deep sub-micron technologies (90nm and beyond) often com... more Systems-on-chip (SoCs) designed in ultra-deep sub-micron technologies (90nm and beyond) often comprise modules in multiple clock domains (MCD), which are usually interconnected using asynchronous interfaces. At the same time, in ultra-deep sub-micron (DSM) technologies, minimum width, spacing, inter-metal dielectric lengths are reduced, as well as distances between metal layers. These trends raise the coupling capacitance resulting in more severe crosstalks.
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014
ABSTRACT Due to shrinking feature sizes and significant reduction in noise margins, as CMOS techn... more ABSTRACT Due to shrinking feature sizes and significant reduction in noise margins, as CMOS technologies evolve toward ultra-deep sub-micron, digital circuits have become more susceptible to soft errors. Therefore, researchers have recently reported several approaches to model Single Event Transient (SET) propagation at gate or higher abstraction levels. However, contemporary techniques model only the possibility that SET pulse may be masked electrically, logically, or by time windowing. In this paper, the propagation induced pulse broadening (PIPB) phenomenon is further investigated and a new model which abstracts this phenomenon is proposed. This paper also investigates and abstracts the impact of input patterns and propagation paths on SET pulse width. Through electrical simulations, we validated our analysis.
2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS), 2014
Glitches due to soft errors have become a major concern in circuits designed in ultra-deep sub-mi... more Glitches due to soft errors have become a major concern in circuits designed in ultra-deep sub-micron technologies. Most of the soft error mitigation techniques require redundancy and are power hungry. Recently, low power quasi delay insensitive (QDI) null conventional logic based asynchronous circuits have been proposed, but these circuits work for pure asynchronous designs only. This paper extends the lowpower soft-error-tolerant asynchronous technique for conventional synchronous circuits. The main idea is to accommodate asynchronous standard cells within the synchronous pipeline, and thus giving rise to a macro synchronous micro asynchronous (MSMA) pipeline. An important application of this design is found in detecting the hardware Trojans. The state-of-the-art signature based hardware Trojan detection is implemented using the clock referencing signals for timing signatures. However, an intruder can intrude into clock distribution network itself and may lead to many false positive or even false negative cases. Asynchronous handshake signals, on the other hand, provide event trigger nature to the digital system, and hence the timing analysis is unique to the data path itself alone, without getting affected by the clock distribution network. This paper provides a proof of concept soft error tolerant MSMA design. Time delay based signature without using clock distribution network is obtained to detect hardware Trojan insertion in MSMA.
IEEE Transactions on Circuits and Systems I: Regular Papers, 2010
This paper proposes a novel solution to make asynchronous handshake interfaces tolerant to crosst... more This paper proposes a novel solution to make asynchronous handshake interfaces tolerant to crosstalk-glitch propagation (GP). This study leverages our recently proposed crosstalkglitch modeling technique for asynchronous systems, which models the crosstalk GP in asynchronous interfaces. In this paper, a novel set of solutions to quench the GP is proposed. This set of solutions is called crosstalk-glitch gating, as the quenching is obtained by using carefully generated control signals. A step-by-step method is recommended to apply crosstalk-glitch gating to conventional asynchronous handshake interfaces. Transistor-level electrical simulations demonstrate that our method effectively generates crosstalkglitch gate-controlling signals. In comparison with contemporary signal-integrity management techniques, our gating methodology can be applied to fewer nodes and earlier in the design cycle.
Globalization trends in integrated circuit (IC) design using deep sub-micron (DSM) technologies a... more Globalization trends in integrated circuit (IC) design using deep sub-micron (DSM) technologies are leading to increased vulnerability against malicious intrusions. Various techniques have been proposed to detect such threats during design or testing phases of ICs. However, due to infinitely many possibilities of Trojans, there exists a possibility that some of these intrusions go undetected. Therefore, runtime Trojan detection techniques are needed to detect the Trojans for complete operation lifetime as a last line of defense. In this paper, we proposed a generic methodology, which leverages the burst mode communication protocol, to detect the intrusions during runtime. Our methodology has three phases: 1) behavioral modeling of design specifications along with its verification using linear temporal logic (LTL) in the model checker. 2) Counterexamples generated in phase 1 are used to insert run-time monitors at vulnerable paths. 3) Embed run-time monitors into the system and validate it. Unlike the other state-of-the-art techniques, the proposed methodology can be easily used to design the runtime monitoring setup without having netlist information of IP modules. We validated our approach by applying it on the AES Trojan benchmarks that utilize intermodule interface to communicate with other modules in the system on chip (SoC).
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