Papers by Prof Ibrahim ahmad
Semiconductor physics, quantum electronics and optoelectronics, 2006
A 0.14 µm CMOS transistor with two levels of interconnection was designed and simulated to invest... more A 0.14 µm CMOS transistor with two levels of interconnection was designed and simulated to investigate its functionality and characteristics. ATHENA and ATLAS simulators were used to simulate the fabrication process and to validate the electrical characteristics, respectively. A scaling factor of 0.93 was applied to a 0.13 µm CMOS. The parameters being scaled are the effective channel length, the density of ion implantation for threshold voltage (V th ) adjustment, and the gate oxide thickness. In order to minimize high field effects, the following additional techniques were implemented: shallow trench isolation, sidewall spacer deposition, silicide formation, lightly doped drain implantation, and retrograde well implantation. The results show that drain current (I D ) increases as the levels of interconnection increases. The important parameters for NMOS and PMOS were measured. For NMOS, the gate length (L g ) is 0.133 µm, V th is 0.343138 V, and the gate oxide thickness (T ox ) is 3.46138 nm. For PMOS, L g is 0.133 µm, V th is -0.378108 V, and T ox is 3.46167 nm. These parameters were validated and the device was proven to be operational.
A study on reflow soldering process for Sn3.5Ag solder on ENIG substrate was performed using the ... more A study on reflow soldering process for Sn3.5Ag solder on ENIG substrate was performed using the rapid thermal processing (RTP) system. The reflow soldering process by RTP system can be successful, but it is sensitive to some typical defects. A poor RTP system design can lead to significant temperature differences where non-uniform heating or cooling may result in material failure due to increase in thermal stresses or serious damage. From this study, it was found that at a peak temperature (T peak ) of 251°C, the reflowed solder was observed to be smooth joint appearance over the solder pad and formed a regular joint shape of the solder due to the efficient reflow profile and sufficient heating input during the reflow process. The Ni 3 Sn 4 intermetallic compounds were found to be continuous, thus resulting in a good metallurgical bonding between Sn3.5Ag solder and ENIG substrate. Meanwhile, an uneven reflowed solder and defect mechanism was detected at T peak of 246 and 260°C. This is due to the inadequate reflow profile and insufficient heating input during the reflow soldering process in the RTP system. Visual micrographs of reflowed solder and cross-sectional micrograph and elemental analysis were presented in this paper for better understanding of the defect mechanism in order to optimize the reflow soldering process using RTP system. The reflow soldering process can be performed better with appropriate reflow profile in the RTP system in order to achieve a good solder joint of Sn3.5Ag solder and ENIG substrate.
Proceedings of the 7th …, 2008
Haya Shida, Subscribe (Full Service), Register (Limited Service, Free), Login. ... ZA Aziz, Facul... more Haya Shida, Subscribe (Full Service), Register (Limited Service, Free), Login. ... ZA Aziz, Faculty of Engineering, Universiti Kebangsaan Malaysia, Bangi, Selangor, Malaysia. I. Ahmad, Faculty of Engineering, Universiti Kebangsaan Malaysia, Bangi, Selangor, Malaysia. ...
Journal of Science and …, 2009
The objective of this study was ot measure the electrical characteristics, observe the structure ... more The objective of this study was ot measure the electrical characteristics, observe the structure and characterize the material of 0.21 μm CMOS devices. The material characterization of the 0.21 μm CMOS devices were carried out using FIB milling ...
Indonesian Journal of Electrical Engineering and Computer Science, Jun 1, 2018
This research paper is about the investigation of Halo Implantation, Halo Implantation Energy, Ha... more This research paper is about the investigation of Halo Implantation, Halo Implantation Energy, Halo Tilt, Compensation Implantation and Source/Drain Implantation. They are types of control factors that used in achievement of the threshold voltage value. To support the successfully of the threshold voltage (VTH) producing, Taguchi method by using L27 orthogonal array was used to optimize the control factors variation. This analysis has involved with 2 main factors which are break down into five control factors and two noise factors. The five control factors were varied with three levels of each and the two noise factors were varied with two levels of each in 27 experiments. In Taguchi method, the statistics data of 18 nm PMOS transistor are from the signal noise ratio (SNR) with nominal-the best (NTB) and the analysis of variance (ANOVA) are executed to minimize the variance of threshold voltage. This experiment implanted by using Virtual Wafer Fabrication SILVACO software which is to design and fabricate the transistor device. Experimental results revealed that the optimization method is achieved to perform the threshold voltage value with least variance and the percent, which is only 2.16%. The threshold voltage value from the experiment shows-0.308517 volts while the target value that is-0.302 volts from value of International Technology Roadmap of semiconductor, ITRS 2012. The threshold voltage value for 18 nm PMOS transistor is well within the range of-0.302 ± 12.7% volts that is recommendation by the International Roadmap for Semiconductor prediction 2012.
Microsystem Technologies, 2007
Deflection behavior of several encapsulant materials under uniform pressure was studied to determ... more Deflection behavior of several encapsulant materials under uniform pressure was studied to determine the best encapsulant for MEMS device. Encapsulation is needed to protect movable parts of MEMS devices during high pressure transfer molded packaging process. The selected encapsulant material has to have surface deflection of less than 5 μm under 100 atm vertical loading. Deflection was simulated using CoventorWare ver.2005 software and verified with calculation results obtained using shell bending theory. Screening design was used to construct a systematic approach for selecting the best encapsulant material and thickness under uniform pressure up to 100 atm. Materials considered for this study were polyimide, parylene C and carbon based epoxy resin. It was observed that carbon based epoxy resin has deflection of less than 5 μm for all thickness and pressure variations. Parylene C is acceptable and polyimide is unsuitable as high strength encapsulant. Carbon based epoxy resin is considered the best encapsulation material for MEMS under high pressure packaging process due to its high strength.
Microelectronics Reliability, 2009
This study investigates the effects of two different catalytic activation techniques on the therm... more This study investigates the effects of two different catalytic activation techniques on the thermal performance of the flip-chip heat spreaders. The two activation techniques studied are thin nickel-copper strike and galvanic initiation. Thermal diffusivity and surface roughness of these heat spreaders were studied using the Nano-flash Apparatus and Infinite Focus Microscopy. High temperature storage tests were carried out to investigate the extent of intermetallic diffusion between the nickel and copper layers. The results show that heat spreaders with thin nickel-copper strike catalytic activation technique have a lower thermal diffusivity due to the low thermal conductivity of nickel-copper layer. Moreover, the nickel-copper layers grew thicker from around 0.2 lm at initial time to around 0.55 lm after high temperature storage duration of 168 h. On the other hand, heat spreaders processed using the galvanic initiation technique did not form any nickel-copper intermetallic diffusion layer. As a conclusion, the galvanic initiation technique can potentially provide better thermal performance for heat spreaders used in semiconductor packages.
Jurnal Teknologi, 2006
Bagi merealisasikan MOSFET submikron, simpangan cetek ultra berkerintangan rendah diperlukan bagi... more Bagi merealisasikan MOSFET submikron, simpangan cetek ultra berkerintangan rendah diperlukan bagi menghalang kesan saluran pendek dan bagi meningkatkan peranti. Dalam kajian ini, pembentukan simpangan cetek ultra disimulasikan menggunakan perisian ATHENA dan Silvaco Inc. bagi memodelkan resapan dari SOD ke dalam silikon. Simpangan ultra P+N berkualiti tinggi dengan kedalaman 40 nm telah dibentuk menggunakan ciri–ciri yang baik dengan arus bocor serendah 0.5 na/cm2. Simpangan cetek kurang daripada turut diperoleh tetapi kualiti simpangan–simpangan cetek ini kurang baik disebabkan oleh arus bocor permukaan yang tinggi. Pembentukan simpangan dari resapan lapisan polisilikon di atas silikon diikuti oleh SOD di atasnya menghasilkan simpangan yang lebih cetek yang berkerintangan rendah. Kata kunci: Simpangan cetek ultra, resapan, SOD, ATHENA, MOSFET For realizing deep submicron MOSFETs, ultra shallow junctions with low sheet resistance and high doping concentrations are required to suppre...
Int. Scientific J. of Semiconductor Physics …, 2006
A 0.14 µm CMOS transistor with two levels of interconnection was designed and simulated to invest... more A 0.14 µm CMOS transistor with two levels of interconnection was designed and simulated to investigate its functionality and characteristics. ATHENA and ATLAS simulators were used to simulate the fabrication process and to validate the electrical characteristics, respectively. A scaling factor of 0.93 was applied to a 0.13 µm CMOS. The parameters being scaled are the effective channel length, the density of ion implantation for threshold voltage (V th) adjustment, and the gate oxide thickness. In order to minimize high field effects, the following additional techniques were implemented: shallow trench isolation, sidewall spacer deposition, silicide formation, lightly doped drain implantation, and retrograde well implantation. The results show that drain current (I D) increases as the levels of interconnection increases. The important parameters for NMOS and PMOS were measured. For NMOS, the gate length (L g) is 0.133 µm, V th is 0.343138 V, and the gate oxide thickness (T ox) is 3.46138 nm. For PMOS, L g is 0.133 µm, V th is −0.378108 V, and T ox is 3.46167 nm. These parameters were validated and the device was proven to be operational.
Abstract The main objective of this research is to optimize the trench depth, trench width, epita... more Abstract The main objective of this research is to optimize the trench depth, trench width, epitaxial resistivity and epitaxial thickness in trench power MOSFET so as to obtain high breakdown voltage but low on-resistance. Optimisation of these parameters are based on ...
Device and Process Technologies For Microelectronics Mems and Photonics Iv, 2006
This paper presents a method to form thick spin-on glass (SOG) sacrificial layer for acceleromete... more This paper presents a method to form thick spin-on glass (SOG) sacrificial layer for accelerometer encapsulation fabrication. SOG is chosen as the sacrificial material because it is easy to apply, has good thickness uniformity, and can be easily etched back before densification. ...
AIP Conference Proceedings, 2008
The application of Infrared Thermography (IRT) as passive method is widely used and accepted by i... more The application of Infrared Thermography (IRT) as passive method is widely used and accepted by industry. However, IRT technology as transient or active method is considerably new for industry in term of measuring defect in Non-Destructive Testing (NDT) activities. The primary objective of this paper is to present an experimental study of determination of artificial defect in material using active thermography, in particular to pulsed thermal NDT (TNDT). Both terminology and basic principles in TNDT will be discussed. It is shown that several factors may influences TNDT results. As a conclusion, this study has confirmed the ability and potential of TNDT as a technique for defect determination in material.
Pakistan Journal of Statistics and Operation Research, 2007
A single outlier detection procedure for data generated from BL(1,1,1,1) models is developed. It ... more A single outlier detection procedure for data generated from BL(1,1,1,1) models is developed. It is carried out in three stages. Firstly, the measure of impact of an IO and AO denoted by IO ω , AO ω , respectively are derived based on least squares method. Secondly, test statistics and test criteria are defined for classifying an observation as an outlier of its respective type. Finally, a general single outlier detection procedure is presented to distinguish a particular type of outlier at a time point t.
2006 Thirty-First IEEE/CPMT International Electronics Manufacturing Technology Symposium, 2006
This paper study SnAg -Cu solder alloy compositions towards mechanical, surface elemental and the... more This paper study SnAg -Cu solder alloy compositions towards mechanical, surface elemental and thermal properties. Mechanical properties were evaluated by shear strength, while the solder surface oxide depth profile and melting properties were obtained by Auger and Differential Scanning Calorimetry (DSC) respectively. Overall results indicates that Sn3.8AgO.7Cu having the most favorable results with highest shear strength, narrow melting peak and low surface oxidation. Further works done to understand in depth of the microstructure and elemental properties reveals that Sn3.8AgO.7Cu has dendritic microstructure with Ag-Sn plate and Cu-Ni-Sn IMC interface.
2007 32nd IEEE/CPMT International Electronic Manufacturing Technology Symposium, 2007
The purpose of this paper is to discuss the effect of Nickel (Ni) thickness on lead free solder j... more The purpose of this paper is to discuss the effect of Nickel (Ni) thickness on lead free solder joint material for tape ball grid array (TBGA) application. In this study, four different level of Nickel thickness were chose that is 3um, 4um, 5um and 6 um. Ball pull testing was used to assess the solder joint performance at time zero, after multiple reflow and high temperature storage (HTS). The machine that was used for the ball pull test is Dage 4000 series. A design of experiment (DOE) based approach is used to study and understand ball pull strength data based on effect of Ni thickness. Statistical results performed shows that 4um is the most preferred thickness for the Ni layer, thus giving a significant effect, supported by thinner Intermetallic layer thickness and area.
2004 IEEE International Conference on Semiconductor Electronics, 2004
The effect of temperature change to electrical resistivity of Aluminum bond pad (Al pad) on die s... more The effect of temperature change to electrical resistivity of Aluminum bond pad (Al pad) on die surface of Under Bump Metallurgy (UBM) were discussed in this paper. Four categories of samples were involved in measurement; a sample without UBM and the samples with single, double and
2006 IEEE International Conference on Semiconductor Electronics, 2006
This paper characterizes the effect of various Sn-Ag-Cu solder compositions towards shear strengt... more This paper characterizes the effect of various Sn-Ag-Cu solder compositions towards shear strength and melting behavior. Shear strength is measured by Dage which is representative of the inter-metallic compound (IMC) strength between the solder and solder clad of a C5 bump. Further study on melting properties will be obtained by Differential Scanning Calorimetry (DSC). It was found that lwt%Ag 0.5wt% Cu has larger melting range compared to 3 & 4wt%Ag 0.5wt%Cu which could contribute to IMC growth. Relatively, ball shear results shows that shear strength increases with Ag wt% content. A correlation between melting range and shear results made in this study pointed to 3.8wt%Ag0.5wt%Cu having the most favorable results.
This paper studied the effects of different catalytic activation processes towards intermetallic ... more This paper studied the effects of different catalytic activation processes towards intermetallic diffusion and mechanical properties on nickel plated heat spreader after high temperature storage (HTS). Heat spreader performs as medium to dissipate heat from silicon die towards heat-sink and is normally made by copper that is plated with nickel to improve wear resistance and prevent oxidation of copper. Two types of heat spreader that using galvanic initiation and thin nickel-copper electrodeposition surface treatment technique had been studied on their hardness and moduli by using Micro Tester and Nanoindenter. Besides, HTS tests were performed to investigate intermetallic diffusion between the nickel and copper layers. Young's moduli of the heat spreaders which were plated by galvanic initiation and thin nickel-copper strike electroless nickel plating catalytic activation techniques were 45 to 65 GPa and 60 to 80 GPa, respectively. The results found that thin nickel-copper electrodeposition technique gave a higher modulus for the heat spreader and this also increased the mechanical strength of heat spreader. Diffusion also took place with a very slow rate in nickel-copper layer.
Several optimization techniques are available in the literature and most of them are based on sta... more Several optimization techniques are available in the literature and most of them are based on statistical treatments. Optimization technique helps to identify optimal design parameters in design work. This study used the 2k factorial method to determine optimised design parameters. The control factors used in this study comprise of bottom die thickness, bottom die are, a top die thickness and
ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575), 2002
Abstract This paper presents MATLAB based image analysis software specially developed to perform ... more Abstract This paper presents MATLAB based image analysis software specially developed to perform characteristic analysis of microstructures images such as the Atomic Force Microscopy (AFM), Transmission Electron Microscopy (TEM), Scanning Electron Microscopy (SEM) etc. The developed software is user-friendly with graphical user interface (GUI), allows dynamic 2D and 3D visualization and performs standard statistical analysis to analyze the microstructure morphology automatically. Two examples are given to show ...
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Papers by Prof Ibrahim ahmad