Cortical stimulation via electrocorticography (ECoG) may be an effective method for inducing arti... more Cortical stimulation via electrocorticography (ECoG) may be an effective method for inducing artificial sensation in bi-directional brain-computer interfaces (BD-BCIs). However, strong electrical artifacts caused by electrostimulation may significantly degrade or obscure neural information. A detailed understanding of stimulation artifact propagation through relevant tissues may improve existing artifact suppression techniques or inspire the development of novel artifact mitigation strategies. Our work thus seeks to comprehensively characterize and model the propagation of artifacts in subdural ECoG stimulation. To this end, we collected and analyzed data from eloquent cortex mapping procedures of four subjects with epilepsy who were implanted with subdural ECoG electrodes. From this data, we observed that artifacts exhibited phase-locking and ratcheting characteristics in the time domain across all subjects. In the frequency domain, stimulation caused broadband power increases, as ...
2021 43rd Annual International Conference of the IEEE Engineering in Medicine & Biology Society (EMBC)
This paper presents an ultra-low power mixedsignal neural data acquisition (MSN-DAQ) system that ... more This paper presents an ultra-low power mixedsignal neural data acquisition (MSN-DAQ) system that enables a novel low-power hybrid-domain neural decoding architecture for implantable brain-machine interfaces with high channel count. Implemented in 180nm CMOS technology, the 32channel custom chip operates at 1V supply voltage and achieves excellent performance including 1.07µW/channel, 2.37/5.62 NEF/PEF and 88dB common-mode rejection ratio (CMRR) with significant back-end power-saving advantage compared to prior works. The fabricated prototype was further evaluated with in vivo human tests at bedside, and its performance closely follows that of a commercial recording system.
Brain-computer interfaces (BCIs) have shown promising results in restoring motor function to indi... more Brain-computer interfaces (BCIs) have shown promising results in restoring motor function to individuals with spinal cord injury. These systems have traditionally focused on the restoration of upper extremity function; however, the lower extremities have received relatively little attention. Early feasibility studies used noninvasive electroencephalogram (EEG)-based BCIs to restore walking function to people with paraplegia. However, the limited spatiotemporal resolution of EEG signals restricted the application of these BCIs to elementary gait tasks, such as the initiation and termination of walking. To restore more complex gait functions, BCIs must accurately decode additional degrees of freedom from brain signals. In this study, we used subdurally recorded electrocorticogram (ECoG) signals from able-bodied subjects to design a decoder capable of predicting the walking state and step rate information. We recorded ECoG signals from the motor cortices of two individuals as they walk...
MedRadio 413-419 MHz inductorless transceiver (TRX) for an implantable brain-machine interface (B... more MedRadio 413-419 MHz inductorless transceiver (TRX) for an implantable brain-machine interface (BMI) in a 180 nm CMOS process is presented. Occupying 5.29 mm 2 of die area (including pad ring), this on-off-keying (OOK) TRX employs a non-coherent direct-detection receiver (RX), which exhibits a measured in-band noise figure (NF) of 4.9 dB and S11 of -13.5 dB. An event-driven supply modulation (EDSM) technique is introduced to dramatically lower the RX power consumption. Incorporating an adaptive feedback loop, this RX consumes 42/92 µW power from 1.8 V supply at 1/10 kbps data-rates, achieving -79/-74 dBm sensitivities for 0.1% bit-error-rate (BER). The TX employs a current-starved ring oscillator with an automatic frequency calibration loop, covering 9% supply-voltage variation and 15-78 • C temperature range which guarantees operation within the emission mask. The direct-modulation TX achieves 14% efficiency for a random OOK data sequence at -4 dBm output power. Wireless testing over a 350 cm distance accounting for bio-signal data transfer, multi-user coexistence, and in-vitro phantom measurement results are demonstrated.
IEEE Transactions on Biomedical Circuits and Systems, 2017
Two brain signal acquisition (BSA) front-ends incorporating two CMOS ultra-low power low noise am... more Two brain signal acquisition (BSA) front-ends incorporating two CMOS ultra-low power low noise amplifier arrays and serializers operating in MOSFET weak inversion region are presented. To boost the amplifier's gain for a given current budget, cross-coupled-pair active load topology is used in the first stages of these two amplifiers. These two BSA frontends are fabricated in 130 nm and 180nm CMOS processes, occupying 5.45 mm 2 and 0.352 mm 2 of die areas, respectively (excluding pad rings). The CMOS 130 nm amplifier array is comprised of 64 elements, where each amplifier element consumes 0.216 μW from 0.4 V supply, has input-referred voltage noise (IRNoise) of 2.19 μV RM S corresponding to a power efficiency factor (PEF) of 11.7 and occupies 0.044 mm 2 of die area. The CMOS 180 nm amplifier array employs 4 elements, where each element consumes 0.69 μW from 0.6 V supply with IRNoise of 2.3 μVRMS (corresponding to a PEF of 19.3) and 0.051 mm 2 of die area. Non-invasive electroencephalographic (EEG) and invasive electrocorticographic (ECoG) signals were recorded real-time directly on able-bodied human subjects, showing feasibility of using these analog front-ends (AFEs) for future fully implantable brain signal acquisition and brain computer interface systems. Index Terms -CMOS, Electrocorticography (ECoG), Electroencephalogram (EEG), ultra-low power (ULP), noise efficiency factor (NEF), power efficiency factor (PEF), operational transconductance amplifier (OTA), instrumentation amplifier (InAmp), analog front-end (AFE), weak inversion (WI) region.
Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference, Aug 1, 2016
A fully implantable brain-computer interface (BCI) can be a practical tool to restore independenc... more A fully implantable brain-computer interface (BCI) can be a practical tool to restore independence to those affected by spinal cord injury. We envision that such a BCI system will invasively acquire brain signals (e.g. electrocorticogram) and translate them into control commands for external prostheses. The feasibility of such a system was tested by implementing its benchtop analogue, centered around a commercial, ultra-low power (ULP) digital signal processor (DSP, TMS320C5517, Texas Instruments). A suite of signal processing and BCI algorithms, including (de)multiplexing, Fast Fourier Transform, power spectral density, principal component analysis, linear discriminant analysis, Bayes rule, and finite state machine was implemented and tested in the DSP. The system's signal acquisition fidelity was tested and characterized by acquiring harmonic signals from a function generator. In addition, the BCI decoding performance was tested, first with signals from a function generator, a...
Abstract The availability of vastly unutilized spectra in millimeter-wave (MMW) frequency range t... more Abstract The availability of vastly unutilized spectra in millimeter-wave (MMW) frequency range together with huge interest in high data rate wireless communications and radar sensors has led to research efforts in designing millimeter-wave integrated circuits (MMW-ICs). On the other hand, the aggressive scaling of silicon technologies has created the possibility of developing MMW-ICs using these technologies. Designing ICs at such high frequencies close to unity-gain frequency of the transistor, however, face new challenges ...
A 1-0 MASH ΣΔ analog-to-digital converter (ADC) demonstrates a digital linearization technique fo... more A 1-0 MASH ΣΔ analog-to-digital converter (ADC) demonstrates a digital linearization technique for the first time treating integrator distortion with memory and capacitor mismatch errors. A two-tap sequential polynomial derived from an output-referred error analysis accurately models the non-ideality of a first-order modulator. The model parameters are extracted by correlating various moments of the ADC digital output with a one-bit pseudorandom noise (PN) superimposed on the input, largely reducing the circuit overhead associated with the nonlinear calibration. The prototype ADC employing amplifiers with a gain of roughly 30 dB measures an 85-dBc spurious-free dynamic range (SFDR) and a 67-dB signal-to-noise and distortion ratio (SNDR) for a 1.1-( 1-dBFS), 4.99-MHz sinusoidal input at 240 MHz sampling clock (8× OSR) with a 7.5-msec calibration time. For a 1.1- two-tone input at 14.9 MHz and 15.1 MHz, the third-order intermodulation product (IM3) after calibration is 87.1 dBc, which is over 30 dB better than that without calibration. The core ADC consumes 37 mW from a 1.25-V supply and occupies 0.28 mm 2 in a 65-nm CMOS low-leakage digital process in which the transistor threshold voltages are around 0.5 V.
CIRCUITS covers the 2011 Compound Semiconductor Integrated Circuit (CSIC) Symposium held in Waiko... more CIRCUITS covers the 2011 Compound Semiconductor Integrated Circuit (CSIC) Symposium held in Waikoloa, Hawaii, October 16–19, 2011. For more than 30 years, the CSIC Symposium (formerly known as the GaAs IC Symposium) has been the preeminent conference for presenting latest advances in integrated circuits and technologies targeting high-performance, high-frequency analog, wireless, and digital/OEIC applications. The symposium is focused on developments in compound semiconductors such as GaAs, InP, ...
Abstract The 15 papers in this issue cover a wide range of technical areas, including wireless, R... more Abstract The 15 papers in this issue cover a wide range of technical areas, including wireless, RF, and millimeter-wave integrated circuit design, mixed-signal and analog design, system in package, process variation, limiting standby power and integrated power regulation.
Abstract This special issue of the IEEE Journal of Solid-State Circuits is a selection of papers ... more Abstract This special issue of the IEEE Journal of Solid-State Circuits is a selection of papers published in the IEEE 2007 Custom Integrated Circuits Conference (CICC). The issue consists of 14 papers that cover a wide range of technical areas, including wireless and RF circuit design, mixed-signal and analog design, digital IC design, integrated power regulation, memory design and biological applications of IC technology. The selected papers demonstrate state-of-the-art performance in power, area, or integration along with ...
International Symposium on Low Power Electronics and Design: Proceedings of the 2004 international symposium on Low power electronics and design, 2004
Circuits for low power wireless. Won Namgoong, Payam Heydari International Symposium on Low Power... more Circuits for low power wireless. Won Namgoong, Payam Heydari International Symposium on Low Power Electronics and Design: Proceedings of the 2004 international symposium on Low power electronics and design 2004, 2004. Abstract not available. 80 Computer Applications(General)(CI).
International Symposium on Quality Electronic Design, Mar 24, 2003
In recent years, major breakthroughs have occurred in packaging technology, which have led to the... more In recent years, major breakthroughs have occurred in packaging technology, which have led to the industrialization of several kinds of new packages, more powerful, and yet more flexible, in the attempt to cope with the challenges posed by multi-million gates and multi-GHz systems-on-a-chip (SOC). While offering a great deal of opportunities, ball-grid array (BGA) substrates, flip-chip and multi-stacked dies require an unprecedented level of integration between IC and package design and verification. This integration, however, requires a change in methodology, with the availability of new EDA tools, and a major shift in the profile of the designers and engineers involved which, to a certain extent, have to acquire each other competences. Although necessary, this cannot be given for granted. While BGA is a reality, flip-chip is still a question mark for the majority of the applications, due to both cost reasons and lack of commercial EDA tools. A package re-use discipline is becoming a must to avoid a package design start for each IC design start, with expensive substrates scraps. How to implement it? Interoperability between Cadence and Synopsys and the rest of the EDA world is a key aspect, as customers don't want to be further bound to few vendors-nor wants the FTC! How to enforce it? This panel is not about packages nor about ICs, it's about whether today's electronic systems can be successfully designed and assembled in their target package, without taking into consideration each other requirements since the very early beginning. It's about the requirements, the challenges and the on-going initiatives, if any.
Proceedings of the 1998 international symposium on Physical design
In this paper, we present a new analytical approach for computing the ramp response of an RLC int... more In this paper, we present a new analytical approach for computing the ramp response of an RLC interconnect line with a pure capacitive load. The approach is based on the two-port representation of the transmission line and accounts for the output resistance of the driver and the line inductance. The results of our analysis are compared with the results of HSPICE simulations demonstrating the high accuracy of our solution under various values of driver, interconnect, and load impedances.
Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.
This paper presents a detailed empirical study and analytical derivation of voltage wave-form and... more This paper presents a detailed empirical study and analytical derivation of voltage wave-form and energy dissipation of global lines driven by CMOS drivers. It is shown that at high clock frequencies where the output voltage at the termination point of the transmission line may not reach its steady state value during the clock period, it is possible to reduce energy dissipation while meeting a DC noise margin by driver sizing. This is in sharp contrast with the steady state analysis, which states that driver size has no impact on the energy dissipation per output change. In addition, we propose a new design metric which is the product of energy, delay and some measure of ringing in lossy transmission lines. In particular, this paper provides closed-form expressions for the energy dissipation, 50% propagation delay and the percentage of maximum undershoot when the circuit exhibits an under-damped behavior. This metric is used during the driver sizing problem formulation for minimum energy-delay-ringing product.
Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001
Scaling the minimum feature size of VLSI circuits to sub-quarter micron and the clock frequency t... more Scaling the minimum feature size of VLSI circuits to sub-quarter micron and the clock frequency to 2GHz has caused the crosstalk noise to become a serious problem, degrading the performance and reliability of high speed integrated circuits. This paper presents an efficient method for computing the capacitive crosstalk in sub-quarter micron VLSI circuits. In particular, we provide closed-form expressions for the peak amplitude, the pulse width, and the time-domain waveform of the crosstalk noise. Experiments show that our analytical predictions are at least two times better than the previous models in terms of the prediction accuracy. More precisely, experimental results show that the maximum error of our predictions is less than 10% while the average error is only 4%. Finally, based on the proposed analytical models, we discuss the effects of transistor sizing and buffering on crosstalk noise reduction in VLSI circuits.
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.
ABSTRACT This paper presents a 40GHz flip-flop-based frequency divider incorporating a latch topo... more ABSTRACT This paper presents a 40GHz flip-flop-based frequency divider incorporating a latch topology with two distinct tail current sources and an enabled cross-coupled pair during the tracking mode, to speed up the latch operation and to increase the driving capability. The proposed frequency divider performs at 40GHz without shunt or series peaking inductors. The circuit was fabricated in a 0.18μm SiGe BiCMOS process provided by Jazz Semiconductor, where only CMOS transistors were used. It draws 5mA current from a 1.8V supply voltage.
Cortical stimulation via electrocorticography (ECoG) may be an effective method for inducing arti... more Cortical stimulation via electrocorticography (ECoG) may be an effective method for inducing artificial sensation in bi-directional brain-computer interfaces (BD-BCIs). However, strong electrical artifacts caused by electrostimulation may significantly degrade or obscure neural information. A detailed understanding of stimulation artifact propagation through relevant tissues may improve existing artifact suppression techniques or inspire the development of novel artifact mitigation strategies. Our work thus seeks to comprehensively characterize and model the propagation of artifacts in subdural ECoG stimulation. To this end, we collected and analyzed data from eloquent cortex mapping procedures of four subjects with epilepsy who were implanted with subdural ECoG electrodes. From this data, we observed that artifacts exhibited phase-locking and ratcheting characteristics in the time domain across all subjects. In the frequency domain, stimulation caused broadband power increases, as ...
2021 43rd Annual International Conference of the IEEE Engineering in Medicine & Biology Society (EMBC)
This paper presents an ultra-low power mixedsignal neural data acquisition (MSN-DAQ) system that ... more This paper presents an ultra-low power mixedsignal neural data acquisition (MSN-DAQ) system that enables a novel low-power hybrid-domain neural decoding architecture for implantable brain-machine interfaces with high channel count. Implemented in 180nm CMOS technology, the 32channel custom chip operates at 1V supply voltage and achieves excellent performance including 1.07µW/channel, 2.37/5.62 NEF/PEF and 88dB common-mode rejection ratio (CMRR) with significant back-end power-saving advantage compared to prior works. The fabricated prototype was further evaluated with in vivo human tests at bedside, and its performance closely follows that of a commercial recording system.
Brain-computer interfaces (BCIs) have shown promising results in restoring motor function to indi... more Brain-computer interfaces (BCIs) have shown promising results in restoring motor function to individuals with spinal cord injury. These systems have traditionally focused on the restoration of upper extremity function; however, the lower extremities have received relatively little attention. Early feasibility studies used noninvasive electroencephalogram (EEG)-based BCIs to restore walking function to people with paraplegia. However, the limited spatiotemporal resolution of EEG signals restricted the application of these BCIs to elementary gait tasks, such as the initiation and termination of walking. To restore more complex gait functions, BCIs must accurately decode additional degrees of freedom from brain signals. In this study, we used subdurally recorded electrocorticogram (ECoG) signals from able-bodied subjects to design a decoder capable of predicting the walking state and step rate information. We recorded ECoG signals from the motor cortices of two individuals as they walk...
MedRadio 413-419 MHz inductorless transceiver (TRX) for an implantable brain-machine interface (B... more MedRadio 413-419 MHz inductorless transceiver (TRX) for an implantable brain-machine interface (BMI) in a 180 nm CMOS process is presented. Occupying 5.29 mm 2 of die area (including pad ring), this on-off-keying (OOK) TRX employs a non-coherent direct-detection receiver (RX), which exhibits a measured in-band noise figure (NF) of 4.9 dB and S11 of -13.5 dB. An event-driven supply modulation (EDSM) technique is introduced to dramatically lower the RX power consumption. Incorporating an adaptive feedback loop, this RX consumes 42/92 µW power from 1.8 V supply at 1/10 kbps data-rates, achieving -79/-74 dBm sensitivities for 0.1% bit-error-rate (BER). The TX employs a current-starved ring oscillator with an automatic frequency calibration loop, covering 9% supply-voltage variation and 15-78 • C temperature range which guarantees operation within the emission mask. The direct-modulation TX achieves 14% efficiency for a random OOK data sequence at -4 dBm output power. Wireless testing over a 350 cm distance accounting for bio-signal data transfer, multi-user coexistence, and in-vitro phantom measurement results are demonstrated.
IEEE Transactions on Biomedical Circuits and Systems, 2017
Two brain signal acquisition (BSA) front-ends incorporating two CMOS ultra-low power low noise am... more Two brain signal acquisition (BSA) front-ends incorporating two CMOS ultra-low power low noise amplifier arrays and serializers operating in MOSFET weak inversion region are presented. To boost the amplifier's gain for a given current budget, cross-coupled-pair active load topology is used in the first stages of these two amplifiers. These two BSA frontends are fabricated in 130 nm and 180nm CMOS processes, occupying 5.45 mm 2 and 0.352 mm 2 of die areas, respectively (excluding pad rings). The CMOS 130 nm amplifier array is comprised of 64 elements, where each amplifier element consumes 0.216 μW from 0.4 V supply, has input-referred voltage noise (IRNoise) of 2.19 μV RM S corresponding to a power efficiency factor (PEF) of 11.7 and occupies 0.044 mm 2 of die area. The CMOS 180 nm amplifier array employs 4 elements, where each element consumes 0.69 μW from 0.6 V supply with IRNoise of 2.3 μVRMS (corresponding to a PEF of 19.3) and 0.051 mm 2 of die area. Non-invasive electroencephalographic (EEG) and invasive electrocorticographic (ECoG) signals were recorded real-time directly on able-bodied human subjects, showing feasibility of using these analog front-ends (AFEs) for future fully implantable brain signal acquisition and brain computer interface systems. Index Terms -CMOS, Electrocorticography (ECoG), Electroencephalogram (EEG), ultra-low power (ULP), noise efficiency factor (NEF), power efficiency factor (PEF), operational transconductance amplifier (OTA), instrumentation amplifier (InAmp), analog front-end (AFE), weak inversion (WI) region.
Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference, Aug 1, 2016
A fully implantable brain-computer interface (BCI) can be a practical tool to restore independenc... more A fully implantable brain-computer interface (BCI) can be a practical tool to restore independence to those affected by spinal cord injury. We envision that such a BCI system will invasively acquire brain signals (e.g. electrocorticogram) and translate them into control commands for external prostheses. The feasibility of such a system was tested by implementing its benchtop analogue, centered around a commercial, ultra-low power (ULP) digital signal processor (DSP, TMS320C5517, Texas Instruments). A suite of signal processing and BCI algorithms, including (de)multiplexing, Fast Fourier Transform, power spectral density, principal component analysis, linear discriminant analysis, Bayes rule, and finite state machine was implemented and tested in the DSP. The system's signal acquisition fidelity was tested and characterized by acquiring harmonic signals from a function generator. In addition, the BCI decoding performance was tested, first with signals from a function generator, a...
Abstract The availability of vastly unutilized spectra in millimeter-wave (MMW) frequency range t... more Abstract The availability of vastly unutilized spectra in millimeter-wave (MMW) frequency range together with huge interest in high data rate wireless communications and radar sensors has led to research efforts in designing millimeter-wave integrated circuits (MMW-ICs). On the other hand, the aggressive scaling of silicon technologies has created the possibility of developing MMW-ICs using these technologies. Designing ICs at such high frequencies close to unity-gain frequency of the transistor, however, face new challenges ...
A 1-0 MASH ΣΔ analog-to-digital converter (ADC) demonstrates a digital linearization technique fo... more A 1-0 MASH ΣΔ analog-to-digital converter (ADC) demonstrates a digital linearization technique for the first time treating integrator distortion with memory and capacitor mismatch errors. A two-tap sequential polynomial derived from an output-referred error analysis accurately models the non-ideality of a first-order modulator. The model parameters are extracted by correlating various moments of the ADC digital output with a one-bit pseudorandom noise (PN) superimposed on the input, largely reducing the circuit overhead associated with the nonlinear calibration. The prototype ADC employing amplifiers with a gain of roughly 30 dB measures an 85-dBc spurious-free dynamic range (SFDR) and a 67-dB signal-to-noise and distortion ratio (SNDR) for a 1.1-( 1-dBFS), 4.99-MHz sinusoidal input at 240 MHz sampling clock (8× OSR) with a 7.5-msec calibration time. For a 1.1- two-tone input at 14.9 MHz and 15.1 MHz, the third-order intermodulation product (IM3) after calibration is 87.1 dBc, which is over 30 dB better than that without calibration. The core ADC consumes 37 mW from a 1.25-V supply and occupies 0.28 mm 2 in a 65-nm CMOS low-leakage digital process in which the transistor threshold voltages are around 0.5 V.
CIRCUITS covers the 2011 Compound Semiconductor Integrated Circuit (CSIC) Symposium held in Waiko... more CIRCUITS covers the 2011 Compound Semiconductor Integrated Circuit (CSIC) Symposium held in Waikoloa, Hawaii, October 16–19, 2011. For more than 30 years, the CSIC Symposium (formerly known as the GaAs IC Symposium) has been the preeminent conference for presenting latest advances in integrated circuits and technologies targeting high-performance, high-frequency analog, wireless, and digital/OEIC applications. The symposium is focused on developments in compound semiconductors such as GaAs, InP, ...
Abstract The 15 papers in this issue cover a wide range of technical areas, including wireless, R... more Abstract The 15 papers in this issue cover a wide range of technical areas, including wireless, RF, and millimeter-wave integrated circuit design, mixed-signal and analog design, system in package, process variation, limiting standby power and integrated power regulation.
Abstract This special issue of the IEEE Journal of Solid-State Circuits is a selection of papers ... more Abstract This special issue of the IEEE Journal of Solid-State Circuits is a selection of papers published in the IEEE 2007 Custom Integrated Circuits Conference (CICC). The issue consists of 14 papers that cover a wide range of technical areas, including wireless and RF circuit design, mixed-signal and analog design, digital IC design, integrated power regulation, memory design and biological applications of IC technology. The selected papers demonstrate state-of-the-art performance in power, area, or integration along with ...
International Symposium on Low Power Electronics and Design: Proceedings of the 2004 international symposium on Low power electronics and design, 2004
Circuits for low power wireless. Won Namgoong, Payam Heydari International Symposium on Low Power... more Circuits for low power wireless. Won Namgoong, Payam Heydari International Symposium on Low Power Electronics and Design: Proceedings of the 2004 international symposium on Low power electronics and design 2004, 2004. Abstract not available. 80 Computer Applications(General)(CI).
International Symposium on Quality Electronic Design, Mar 24, 2003
In recent years, major breakthroughs have occurred in packaging technology, which have led to the... more In recent years, major breakthroughs have occurred in packaging technology, which have led to the industrialization of several kinds of new packages, more powerful, and yet more flexible, in the attempt to cope with the challenges posed by multi-million gates and multi-GHz systems-on-a-chip (SOC). While offering a great deal of opportunities, ball-grid array (BGA) substrates, flip-chip and multi-stacked dies require an unprecedented level of integration between IC and package design and verification. This integration, however, requires a change in methodology, with the availability of new EDA tools, and a major shift in the profile of the designers and engineers involved which, to a certain extent, have to acquire each other competences. Although necessary, this cannot be given for granted. While BGA is a reality, flip-chip is still a question mark for the majority of the applications, due to both cost reasons and lack of commercial EDA tools. A package re-use discipline is becoming a must to avoid a package design start for each IC design start, with expensive substrates scraps. How to implement it? Interoperability between Cadence and Synopsys and the rest of the EDA world is a key aspect, as customers don't want to be further bound to few vendors-nor wants the FTC! How to enforce it? This panel is not about packages nor about ICs, it's about whether today's electronic systems can be successfully designed and assembled in their target package, without taking into consideration each other requirements since the very early beginning. It's about the requirements, the challenges and the on-going initiatives, if any.
Proceedings of the 1998 international symposium on Physical design
In this paper, we present a new analytical approach for computing the ramp response of an RLC int... more In this paper, we present a new analytical approach for computing the ramp response of an RLC interconnect line with a pure capacitive load. The approach is based on the two-port representation of the transmission line and accounts for the output resistance of the driver and the line inductance. The results of our analysis are compared with the results of HSPICE simulations demonstrating the high accuracy of our solution under various values of driver, interconnect, and load impedances.
Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.
This paper presents a detailed empirical study and analytical derivation of voltage wave-form and... more This paper presents a detailed empirical study and analytical derivation of voltage wave-form and energy dissipation of global lines driven by CMOS drivers. It is shown that at high clock frequencies where the output voltage at the termination point of the transmission line may not reach its steady state value during the clock period, it is possible to reduce energy dissipation while meeting a DC noise margin by driver sizing. This is in sharp contrast with the steady state analysis, which states that driver size has no impact on the energy dissipation per output change. In addition, we propose a new design metric which is the product of energy, delay and some measure of ringing in lossy transmission lines. In particular, this paper provides closed-form expressions for the energy dissipation, 50% propagation delay and the percentage of maximum undershoot when the circuit exhibits an under-damped behavior. This metric is used during the driver sizing problem formulation for minimum energy-delay-ringing product.
Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001
Scaling the minimum feature size of VLSI circuits to sub-quarter micron and the clock frequency t... more Scaling the minimum feature size of VLSI circuits to sub-quarter micron and the clock frequency to 2GHz has caused the crosstalk noise to become a serious problem, degrading the performance and reliability of high speed integrated circuits. This paper presents an efficient method for computing the capacitive crosstalk in sub-quarter micron VLSI circuits. In particular, we provide closed-form expressions for the peak amplitude, the pulse width, and the time-domain waveform of the crosstalk noise. Experiments show that our analytical predictions are at least two times better than the previous models in terms of the prediction accuracy. More precisely, experimental results show that the maximum error of our predictions is less than 10% while the average error is only 4%. Finally, based on the proposed analytical models, we discuss the effects of transistor sizing and buffering on crosstalk noise reduction in VLSI circuits.
Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.
ABSTRACT This paper presents a 40GHz flip-flop-based frequency divider incorporating a latch topo... more ABSTRACT This paper presents a 40GHz flip-flop-based frequency divider incorporating a latch topology with two distinct tail current sources and an enabled cross-coupled pair during the tracking mode, to speed up the latch operation and to increase the driving capability. The proposed frequency divider performs at 40GHz without shunt or series peaking inductors. The circuit was fabricated in a 0.18μm SiGe BiCMOS process provided by Jazz Semiconductor, where only CMOS transistors were used. It draws 5mA current from a 1.8V supply voltage.
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Papers by Payam Heydari