Conference Record of the 2006 Twenty-Seventh International Power Modulator Symposium, 2006
This paper describes DTI's ongoing development of solid-state, transformerless modulators for the... more This paper describes DTI's ongoing development of solid-state, transformerless modulators for the International Linear Collider (ILC), including Marx Bank (Figure 1) and hard switch (Figure 7) modulator configurations. As these designs are built and tested, the overall ILC program will be in an excellent position to select a design for construction to minimize the overall ILC life cycle cost. I.
Proceedings of the 13th Acm Great Lakes Symposium on Vlsi, 2003
This paper describes a new architecture for VLSI sequential circuits and a method to control the ... more This paper describes a new architecture for VLSI sequential circuits and a method to control the critical races that appears subsequently in their feedback loops. This architecture reduces the number of gates resulting in lower power consumption and smaller area of implementation without incurring significant speed penalty. The critical races are controlled by introducing a delay difference between the sections of the loop. This is implemented by scaling the transmission gates already present in the circuit. This method which sizes transistors in close proximity is insensitive to variations in internal and external operating conditions. The paper presents low-power implementation of conventional circuits and of new circuits providing a higher level of integration. When used with asynchronous circuits this architecture enables the operation of circuits that are unusable using present techniques.
Conference Record of the 2006 Twenty-Seventh International Power Modulator Symposium, 2006
This paper describes DTI's ongoing development of solid-state, transformerless modulators for the... more This paper describes DTI's ongoing development of solid-state, transformerless modulators for the International Linear Collider (ILC), including Marx Bank (Figure 1) and hard switch (Figure 7) modulator configurations. As these designs are built and tested, the overall ILC program will be in an excellent position to select a design for construction to minimize the overall ILC life cycle cost. I.
Proceedings of the 13th Acm Great Lakes Symposium on Vlsi, 2003
This paper describes a new architecture for VLSI sequential circuits and a method to control the ... more This paper describes a new architecture for VLSI sequential circuits and a method to control the critical races that appears subsequently in their feedback loops. This architecture reduces the number of gates resulting in lower power consumption and smaller area of implementation without incurring significant speed penalty. The critical races are controlled by introducing a delay difference between the sections of the loop. This is implemented by scaling the transmission gates already present in the circuit. This method which sizes transistors in close proximity is insensitive to variations in internal and external operating conditions. The paper presents low-power implementation of conventional circuits and of new circuits providing a higher level of integration. When used with asynchronous circuits this architecture enables the operation of circuits that are unusable using present techniques.
Uploads
Papers by Neal Butler