In this paper, a simple macro model of n-channel MOSFET with dual workfunction gate (DWFG) struct... more In this paper, a simple macro model of n-channel MOSFET with dual workfunction gate (DWFG) structure is proposed. The DWFG MOSFET has higher transconductance and lower drain conductance than conventional MOSFET. Thus analog circuit design using the DWFG MOSFET can improve circuit characteristics. Currently, device models of the DWFG MOSFET are insufficient, so simple series connected two MOSFET model is proposed. In addition, a two stage operational amplifier using the proposed DWFG MOSFET macro model is designed to verify the model.
We present a novel single poly-silicon EEPROM cell for embedded memory. The cell is integrated in... more We present a novel single poly-silicon EEPROM cell for embedded memory. The cell is integrated in a 0.13 m RF-CMOS technology without process modifications and is composed of an NMOS transistor and a MOS capacitor on two isolated P-wells sharing a floating poly-silicon layer. A two-polarity voltage of ± 6 V is applied for writing and erasing using uniform channel Fowler-Nordheim tunnelling. Operations faster than 1 ms, endurance over 10 +3 cycles and data retention longer than 10 years are demonstrated.
Analog behaviors of n-channel metal-oxidesemiconductor field-effect transistors (MOSFETs) with du... more Analog behaviors of n-channel metal-oxidesemiconductor field-effect transistors (MOSFETs) with dualworkfunction-gate (DWFG) structure are presented. The gate of the n-channel DWFG MOSFET is composed of p + and n + poly-Si along the channel carrier flowing direction. To investigate the impact of the proportional length of p-and n-type-doped poly-Si on analog behaviors, they are varied within a total physical gate length of 1.0 μm. Various dc characteristics that directly affect analog circuit performances are evaluated from the fabricated devices: I-V characteristics, drain-induced barrier lowering, transconductance (g m), drain conductance (g ds = 1/r out), intrinsic gain (A V = g m /g ds), and Early voltage (V EA = I D /g ds). From the measurements, the DWFG devices always show improved characteristics over conventional devices (n +-doped poly-Si gate). The DWFG device with the shortest p + poly-Si gate length (p/n = 0.4/0.6) shows better g m characteristics than other DWFG devices. The g ds characteristics of the fabricated DWFG devices are improved as the length of the p + poly-Si increases. The best A V and V EA are taken from the device with a p-type-doped poly-Si length of 0.7 μm (p/n = 0.7/0.3). Index Terms-Analog circuit, channel length modulation (CLM), drain conductance (g ds), drain-induced barrier lowering (DIBL), dual workfunction gate (DWFG), Early voltage (V EA), intrinsic gain (A V), transconductance (g m).
High-performance single polysilicon electrically erasable programmable read-only memories (EEPROM... more High-performance single polysilicon electrically erasable programmable read-only memories (EEPROMs) with stacked metal-insulator-metal capacitor as a control gate are investigated. The thickness of the tunnel oxide and the length of the floating gate channel of the fabricated devices were 52 Å and 0.24 µm, respectively. The effective control gate coupling ratio of the proposed EEPROM cell was higher than that of cells with n-well control gate because of the absence of depletion capacitance in the n-well silicon region. The experimental results showed that the program speed of the proposed cells were faster than those of the conventional n-well control gate cells. In addition, the proposed cells had threshold voltage shifts of 3.5 V between program and erase states. Furthermore, there were threshold voltage shifts of 3.0 V without degradation of the read currents after 1000 program/erase cycles.
In this letter, we describe a novel single polysilicon electrically erasable read-only memory cel... more In this letter, we describe a novel single polysilicon electrically erasable read-only memory cell with polyfinger capacitor for the control gate (CG). A finger-type capacitor structure with CoSi 2 is applied to a floating gate and the CG of the proposed cell. The proposed cell is fabricated by using a 0.18-µm standard logic process. The intergate dielectrics of the proposed cell are formed by a conventional lightly doped drain spacer material that is composed of SiO 2 and Si 3 N 4 to avoid any process modification. A Fowler-Nordheim tunneling method is applied for the programming and erasing of the cell. Endurance characteristics of up to 120 000 cycles are demonstrated. The proposed cell shows acceptable data retention characteristics.
A novel single polysilicon electrically erasable programmable read-only memory cell with dual wor... more A novel single polysilicon electrically erasable programmable read-only memory cell with dual work function floating-gate (DWFG) structure is presented in this letter. The floating gate of the proposed DWFG cell is doped with p+ on the source side and n+ on the drain side. For DWFG devices, the floating gate on the source side has a higher work function than that on the drain side. The work function difference and the intrinsic doped region at the middle of the floating-gate affect the channel potential distribution and generate a peak lateral electric field inside the channel, improving the channel's hot electron programming characteristics. The experimental results show that the proposed DWFG cell gives faster programming speeds and program operation at lower voltage than conventional cells. Index Terms-Channel hot electron (CHE) programming, dual work function floating gate (DWFG), high programming speed, single polysilicon electrically erasable programmable read-only memory (EEPROM), standard logic process.
This paper discusses silicon complementary metal-oxide-semiconductor (CMOS) field-effect transist... more This paper discusses silicon complementary metal-oxide-semiconductor (CMOS) field-effect transistors with dual work function gates (DWFG) to improve transconductance (g m) and drain conductance (g ds) characteristics. For a n-channel metaloxide-semiconductor field-effect transistor (MOSFET) device, the polycrystalline silicon (poly-Si) gate on the source and drain side are doped p+ and n+, respectively and vice versa for a p-channel MOSFET. The work function difference in a poly-Si gate affects channel potential distribution and increases the lateral electric field inside the channel. The increased electric field inside the channel improves carrier drift velocity. Experimental results from the fabricated DWFG devices show improved g m and g ds over conventional single work function gate devices.
Journal of the Korean Institute of Electrical and Electronic Material Engineers
In this paper, a simple macro model of n-channel MOSFET with dual workfunction gate (DWFG) struct... more In this paper, a simple macro model of n-channel MOSFET with dual workfunction gate (DWFG) structure is proposed. The DWFG MOSFET has higher transconductance and lower drain conductance than conventional MOSFET. Thus analog circuit design using the DWFG MOSFET can improve circuit characteristics. Currently, device models of the DWFG MOSFET are insufficient, so simple series connected two MOSFET model is proposed. In addition, a two stage operational amplifier using the proposed DWFG MOSFET macro model is designed to verify the model.
The impact of LDD structure on the single-poly EEPROMs is investigated in this paper. The single-... more The impact of LDD structure on the single-poly EEPROMs is investigated in this paper. The single-poly EEPROMs are fabricated using the 0.8㎛ CMOS ASIC process. The single-poly EEPROMs with LDD structure have slower program and erase speeds, but the drain and gate stresses and the endurance characteristics of these devices are much better than those of the single-poly EEPROMs with single-drain structure. The single-poly EEPROMs with LDD structure do not require the process modifications and need no additional masks, hence can be used for microprocessors and logic circuits with low-density and low-cost embedded EEPROMs.
In this paper, a simple macro model of n-channel MOSFET with dual workfunction gate (DWFG) struct... more In this paper, a simple macro model of n-channel MOSFET with dual workfunction gate (DWFG) structure is proposed. The DWFG MOSFET has higher transconductance and lower drain conductance than conventional MOSFET. Thus analog circuit design using the DWFG MOSFET can improve circuit characteristics. Currently, device models of the DWFG MOSFET are insufficient, so simple series connected two MOSFET model is proposed. In addition, a two stage operational amplifier using the proposed DWFG MOSFET macro model is designed to verify the model.
We present a novel single poly-silicon EEPROM cell for embedded memory. The cell is integrated in... more We present a novel single poly-silicon EEPROM cell for embedded memory. The cell is integrated in a 0.13 m RF-CMOS technology without process modifications and is composed of an NMOS transistor and a MOS capacitor on two isolated P-wells sharing a floating poly-silicon layer. A two-polarity voltage of ± 6 V is applied for writing and erasing using uniform channel Fowler-Nordheim tunnelling. Operations faster than 1 ms, endurance over 10 +3 cycles and data retention longer than 10 years are demonstrated.
Analog behaviors of n-channel metal-oxidesemiconductor field-effect transistors (MOSFETs) with du... more Analog behaviors of n-channel metal-oxidesemiconductor field-effect transistors (MOSFETs) with dualworkfunction-gate (DWFG) structure are presented. The gate of the n-channel DWFG MOSFET is composed of p + and n + poly-Si along the channel carrier flowing direction. To investigate the impact of the proportional length of p-and n-type-doped poly-Si on analog behaviors, they are varied within a total physical gate length of 1.0 μm. Various dc characteristics that directly affect analog circuit performances are evaluated from the fabricated devices: I-V characteristics, drain-induced barrier lowering, transconductance (g m), drain conductance (g ds = 1/r out), intrinsic gain (A V = g m /g ds), and Early voltage (V EA = I D /g ds). From the measurements, the DWFG devices always show improved characteristics over conventional devices (n +-doped poly-Si gate). The DWFG device with the shortest p + poly-Si gate length (p/n = 0.4/0.6) shows better g m characteristics than other DWFG devices. The g ds characteristics of the fabricated DWFG devices are improved as the length of the p + poly-Si increases. The best A V and V EA are taken from the device with a p-type-doped poly-Si length of 0.7 μm (p/n = 0.7/0.3). Index Terms-Analog circuit, channel length modulation (CLM), drain conductance (g ds), drain-induced barrier lowering (DIBL), dual workfunction gate (DWFG), Early voltage (V EA), intrinsic gain (A V), transconductance (g m).
High-performance single polysilicon electrically erasable programmable read-only memories (EEPROM... more High-performance single polysilicon electrically erasable programmable read-only memories (EEPROMs) with stacked metal-insulator-metal capacitor as a control gate are investigated. The thickness of the tunnel oxide and the length of the floating gate channel of the fabricated devices were 52 Å and 0.24 µm, respectively. The effective control gate coupling ratio of the proposed EEPROM cell was higher than that of cells with n-well control gate because of the absence of depletion capacitance in the n-well silicon region. The experimental results showed that the program speed of the proposed cells were faster than those of the conventional n-well control gate cells. In addition, the proposed cells had threshold voltage shifts of 3.5 V between program and erase states. Furthermore, there were threshold voltage shifts of 3.0 V without degradation of the read currents after 1000 program/erase cycles.
In this letter, we describe a novel single polysilicon electrically erasable read-only memory cel... more In this letter, we describe a novel single polysilicon electrically erasable read-only memory cell with polyfinger capacitor for the control gate (CG). A finger-type capacitor structure with CoSi 2 is applied to a floating gate and the CG of the proposed cell. The proposed cell is fabricated by using a 0.18-µm standard logic process. The intergate dielectrics of the proposed cell are formed by a conventional lightly doped drain spacer material that is composed of SiO 2 and Si 3 N 4 to avoid any process modification. A Fowler-Nordheim tunneling method is applied for the programming and erasing of the cell. Endurance characteristics of up to 120 000 cycles are demonstrated. The proposed cell shows acceptable data retention characteristics.
A novel single polysilicon electrically erasable programmable read-only memory cell with dual wor... more A novel single polysilicon electrically erasable programmable read-only memory cell with dual work function floating-gate (DWFG) structure is presented in this letter. The floating gate of the proposed DWFG cell is doped with p+ on the source side and n+ on the drain side. For DWFG devices, the floating gate on the source side has a higher work function than that on the drain side. The work function difference and the intrinsic doped region at the middle of the floating-gate affect the channel potential distribution and generate a peak lateral electric field inside the channel, improving the channel's hot electron programming characteristics. The experimental results show that the proposed DWFG cell gives faster programming speeds and program operation at lower voltage than conventional cells. Index Terms-Channel hot electron (CHE) programming, dual work function floating gate (DWFG), high programming speed, single polysilicon electrically erasable programmable read-only memory (EEPROM), standard logic process.
This paper discusses silicon complementary metal-oxide-semiconductor (CMOS) field-effect transist... more This paper discusses silicon complementary metal-oxide-semiconductor (CMOS) field-effect transistors with dual work function gates (DWFG) to improve transconductance (g m) and drain conductance (g ds) characteristics. For a n-channel metaloxide-semiconductor field-effect transistor (MOSFET) device, the polycrystalline silicon (poly-Si) gate on the source and drain side are doped p+ and n+, respectively and vice versa for a p-channel MOSFET. The work function difference in a poly-Si gate affects channel potential distribution and increases the lateral electric field inside the channel. The increased electric field inside the channel improves carrier drift velocity. Experimental results from the fabricated DWFG devices show improved g m and g ds over conventional single work function gate devices.
Journal of the Korean Institute of Electrical and Electronic Material Engineers
In this paper, a simple macro model of n-channel MOSFET with dual workfunction gate (DWFG) struct... more In this paper, a simple macro model of n-channel MOSFET with dual workfunction gate (DWFG) structure is proposed. The DWFG MOSFET has higher transconductance and lower drain conductance than conventional MOSFET. Thus analog circuit design using the DWFG MOSFET can improve circuit characteristics. Currently, device models of the DWFG MOSFET are insufficient, so simple series connected two MOSFET model is proposed. In addition, a two stage operational amplifier using the proposed DWFG MOSFET macro model is designed to verify the model.
The impact of LDD structure on the single-poly EEPROMs is investigated in this paper. The single-... more The impact of LDD structure on the single-poly EEPROMs is investigated in this paper. The single-poly EEPROMs are fabricated using the 0.8㎛ CMOS ASIC process. The single-poly EEPROMs with LDD structure have slower program and erase speeds, but the drain and gate stresses and the endurance characteristics of these devices are much better than those of the single-poly EEPROMs with single-drain structure. The single-poly EEPROMs with LDD structure do not require the process modifications and need no additional masks, hence can be used for microprocessors and logic circuits with low-density and low-cost embedded EEPROMs.
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Papers by Kee-Yeol Na