2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), 2021
Logic encryption is a method to improve hardware security by inserting key gates on carefully sel... more Logic encryption is a method to improve hardware security by inserting key gates on carefully selected signals in a logic design. Various logic encryption schemes have been proposed in the past decade. Many attack methods to thwart these logic locking schemes have also emerged. The satisfiability (SAT) attack can recover correct keys for many logic obfuscation methods. Recently proposed sensitivity analysis attack can decrypt stripped functionality based logic encryption schemes. This article presents a new encryption scheme named SRTLock, which is resilient against both attacks. SRTLock method first generates 0-injection circuits and encrypts the functionality of these nodes with the key inputs. In the next step, these values are used to control the sensitivity of the functionally stripped output for specific input patterns. The resultant locked circuit is resilient against the SAT and sensitivity analysis attacks. Experimental results demonstrating this on several attacks using standard benchmark circuits are presented.
Architectural Wireless Networks Solutions and Security Issues, 2021
Wireless sensor network (WSN) is a collection of sensor nodes that are attached with base station... more Wireless sensor network (WSN) is a collection of sensor nodes that are attached with base station (BS) and sink node to achieve a specific purpose. The main purpose of the WSN is sensing environmental parameters such as energy, temperature, and humidity. There are several parameters of the WSN that changes time to time and frequently based on the operation. Each sensor node contains limited capacity of battery that is insufficient during any operation and fails to send the data packet to the BS. So, there is need of some modeling using some intelligent technique. In this paper, a fuzzy quadratic programming (FQP) is used to optimize network parameters efficiently. FQP is the fusion of fuzzy logic and quadratic programming. Fuzzy logic is a multi-values logic which is used to reduce uncertainty and estimate imprecise parameters efficiently. Quadratic programming is a nonlinear programming based on second order of mathematical polynomial for reducing the main objective. The combinatio...
In this article an analysis of carbon nanotube field effect transistor based ring oscillator is p... more In this article an analysis of carbon nanotube field effect transistor based ring oscillator is performed. After analysis it was found that carbon nanotube transistor consumes less power in comparison to silicon transistor. CNFET is one possible candidate to substitute silicon-based integrated circuit (IC) technology, as the performance increase of conventional transistors witnessed during the last decades will arrive at its ultimate limits in the near future. Its present progress is largely dominated by the materials science community due to many still existing materials-related obstacles for realizing practically competitive transistors. Compared to graphene, carbon nanotube provides better properties for building field-effect transistors, and thus, has higher chances for eventually becoming a production technology. So, in this work it is used carbon nanotube field effect transistor in place of silicon based transistor for making a ring oscillator. Keywords: Carbon nanotube, power...
International Journal of Engineering Trends and Technology, 2017
The low power chip designing is a field of immense interest to the technology for electronics chi... more The low power chip designing is a field of immense interest to the technology for electronics chip designing industries. Operational amplifiers (OpAmps) are an integral parts of many analog and mixed signal systems. There is need to investigate the performance of the forthcoming scaled channel length CMOS devices. In this work a two stage CMOS Operational Amplifier with gain boosting technique, Darlington pair is proposed. The proposed Op-Amp shows high gain as well as high CMRR with reduced leakage current and power supply. This amplifier is highly useful for wireless communication because of low power consumption, high bandwidth, high gain and high CMRR. The designed operational amplifier gain is 93 dB, UnityGain Bandwidth is 538 MHz, CMRR is 100dB, slew rate is 20.13V/μS, power dissipation is 10pW, leakage current is 2.17pA, phase margin is 86o, and settling time is 95ns. The designed circuit is simulated using H-Spice tool at 32nm technology.
In the semiconductor industry, protecting Integrated Circuits (IC) throughout the IC supply chain... more In the semiconductor industry, protecting Integrated Circuits (IC) throughout the IC supply chain has become a major concern. In-depth research has been done on logic encryption, split manufacturing, and layout camouflaging to safeguard ICs against attacks at various stages of the supply chain. In this work, we introduce a hybrid, method called Hybrid Shielding (which amplifies the power of camouflaging and logic locking) to protect ICs at each stage of the supply chain, including the foundry, the testing facility, and the end user. We take advantage of the spin-based device, called the Giant Spin-Hall Effect (GSHE) switch, multi-functionality, post-fabrication reconfigurability, and run-time polymorphism to make dynamic camouflaging resistant to SAT-based attacks and test-data mining-based attacks. These characteristics are not available to designers in CMOS. We define two metrics for circuit nodes: stability and weight. Hybrid Shielding replaces all of the selected gates with polymorphic gates. It uses a simulator to ascertain the internal state of the selected nodes. The camouflaged internal state will be used to corrupt the functionality of the primary outputs. The resulting locked circuit has high output corruption rates and is resilient to the SAT attack, Hack Test, as well as several other attacks. These results are demonstrated experimentally using standard benchmark circuits.
This paper describes the architecture of first and second generation current conveyor (CCI and CC... more This paper describes the architecture of first and second generation current conveyor (CCI and CCII respectively) and designing an amplifier using second generation current conveyor. The designed amplifier through CCII+ can be used in various analog computation circuits and is superior in performance than the classical opamp. It provides better gain with higher accuracy.
International Journal of Electrical and Electronics Research, 2014
Due to the growing impact of subthreshold and gate leakage, static leakage is contributing more a... more Due to the growing impact of subthreshold and gate leakage, static leakage is contributing more and more towards the power dissipation in deep submicron Nano CMOS technology. There have been many works on subthreshold leakage and techniques to reduce it, such as controlling the input vector to the circuit in standby mode, forcing stack and body bias control. In this tutorial paper we have reviewed the leakage current with change in drain source, gate and bulk voltages for 4 different submicron technologies using the latest PTM models. Simulation result shows the effect of gate leakage and subthreshold leakage in total leakage current for different input vectors for a stack of 3 Nano technology NMOS transistors, further analyzes also the subthreshold and total leakage variation with input vector in a stack of 4 Nano technology NMOS transistors.
International Journal of Electrical and Electronics Research, 2014
In this paper, an analysis of different delay lines based on CMOS architecture has been done. Com... more In this paper, an analysis of different delay lines based on CMOS architecture has been done. Comparison has been made on these delay lines in terms of propagation delay, power dissipation, area, and power delay product. After the analysis of those performance parameters, the tradeoff has been made for better performance of delay lines.
Due to rampant leveling of instrument measurements, the stability of an SRAM cell is the biggest ... more Due to rampant leveling of instrument measurements, the stability of an SRAM cell is the biggest anxiety for upcoming technology. In this paper, it is introduced by an 8T (8-transistor) SRAM cell. The enlarged data stability is offered by proposed cell until read operation. The voltage scale of the node keeping ‘0’ is enlarged by introduced cell and thus it achieves a near butterfly curve that is vital to creation a substantial SRAM cell. The read static noise margin or read SNM (RSNM) is as advanced as 223 mV @ 700 mV in 45 nm technology node and it is 3.01 times more stable than standard 6T SRAM cell during read operation. The introduced cell also gets 1.45 times lower latency at the equal voltage similitude to standard 6T SRAM cell . Keyword: CMOS, Read Delay (latency), Read Stability, RSNM Cite this Article Anjali Pachauri, Nikhil Saxena . A Double-Ended Read-Decoupled 8T SRAM Cell with Improved Read Stability and Access Time at 45 nm Technology . Journal of Semiconductor Device...
Architectural Wireless Networks Solutions and Security Issues, 2021
When the fourth generation for wireless communication networks was developed, it was upgraded to ... more When the fourth generation for wireless communication networks was developed, it was upgraded to provide both enhanced coverage area and higher data rates to every mobile user with lower latency. However, wireless communication system for the next-generation network will need to challenge new requirement with a greater diversity of application requirements such as ultra-high data rate, ultra-low latency, flexible use of spectrum and spectrum sharing, and battery-powered sensors that needs extremely low energy consumption, and some other control applications that want a very short round trip time (RTT). Due to problems with orthogonal frequency division multiplexing (OFDM) and next-generation demands, OFDM is not used as a promising waveform for next-generation wireless communication network. In these circumstances, alternative multiplexing schemes such as generalized frequency division multiplexing (GFDM), due to flexibility in pulse shape and single cyclic prefix in a multi-path system, GFDM is becoming common every day, making it eligible for 5G wireless technologies. GFDM looks as generalization of OFDM technique. But one of the common drawbacks of every multicarrier system is their high peak to average power ratio (PAPR). The main effect of strong PAPR is instability in the analog to digital converter (ADC) and digital to analog converter (DAC), decreased its performance and raised costs. A PAPR reduction technique such as clipping and filtering that greatly improves the efficiency compared to the initial GFDM signal PAPR. Overall peak re-growth can be reduced by using repeated clip and filter operations. Simulation is performed for this scheme to evaluate this system’s PAPR output for different values of roll-off variables.
1Scholar Dept. of ECE, ITM, Gwalior, India 2Assistant Professor, Dept. of ECE, ITM, Gwalior, Indi... more 1Scholar Dept. of ECE, ITM, Gwalior, India 2Assistant Professor, Dept. of ECE, ITM, Gwalior, India ---------------------------------------------------------------------***--------------------------------------------------------------------Abstract As technology continues to scale down, leakage power has become a significant component in chip design. Leakage power is a key parameter to design low power devices because it is an important source of total power consumption. Large amount of leakage power is an issue of serious concern in portable electronics devices. Limited energy consumption in multimedia requires very low power circuits. Static Random Access Memory (SRAM) comprises a considerable proportion of the total area and total power for almost all VLSI chips as cache memory for the System on Chip (SOC) and it is expected to increase in the future in both handy devices and highperformance processors. By using low-power FinFET based SRAM cell, we can achieve higher steadfastness...
In this current paper execution of forward body biased True Single Phase Clock (FBBTSPC) and forw... more In this current paper execution of forward body biased True Single Phase Clock (FBBTSPC) and forward body biased extended True Single Phase Clock (FBBETSPC) are investigated. The delay of FBBTSPC and FBBETSPC are analyzed, simulated, executed and compared with the existing TSPC and ETSPC. A high speed divide-by-2 unit of frequency divider divide by two with the body biased is proposed and validated that this frequency divider divide by two can operate with higher frequency of 4 GHz stably on a 180 nm technology. This frequency divider divide by two with the body bias design can be widely used in Communication data analysis probe systems.
Nowadays, the performance parameters should not affect the variation in fixed parameters like lea... more Nowadays, the performance parameters should not affect the variation in fixed parameters like leakage current, leakage power, propagation delay, and power delay product. So this study is basically focused on the effects of changes in supply voltage (0.8–1.2V) on the various performance parameters of 2-stage inverter based delay line based on CMOS architecture. A delay line is a discrete element in digital theory, which simply allows a signal to be delayed by the number of samples. The effects of changes in supply voltage on leakage current, leakage power, and propagation delay and PDP product have been studied. SPICE simulation tool is used for this analysis with 32nm technology node. Keywords: Supply voltage, leakage power, leakage current, power delay product, propagation delay. Cite this Article Bhupendra Dubey, Nikhil Saxena. Analysis of 2-Stage Inverter Delay Line with Supply Voltage Variation. Trends in Electrical Engineering . 2019; 9(1): 31–35p.
International Journal of Engineering Trends and Technology, 2017
SRAM cells are designed exclusively to guarantee that the data of the cell is not altered during ... more SRAM cells are designed exclusively to guarantee that the data of the cell is not altered during read access and the cell can quickly change its state during write operation. These conflicting needs for read and write operations are contented by some specific conditions to provide stable read and write operations, SRAM cell read stability and write ability is most important concerns in nanometer scale technologies, due to the progressive increase in intra die variability and Vdd scaling. In conventional six transistors (6T) SRAM cell, read stability is very low due to the voltage division between the access and driver transistors during read operation. Analysis has been done with the factors responsible to improve the read stability and write ability of 6T SRAM cell structures. SRAM cell stability analysis is typically based on Static Noise Margin (SNM) investigation. Keywords—Read stability, write ability, Cell Ratio, Pull up transistor, SRAM cell, Static Noise Margin (SNM)
2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), 2021
Logic encryption is a method to improve hardware security by inserting key gates on carefully sel... more Logic encryption is a method to improve hardware security by inserting key gates on carefully selected signals in a logic design. Various logic encryption schemes have been proposed in the past decade. Many attack methods to thwart these logic locking schemes have also emerged. The satisfiability (SAT) attack can recover correct keys for many logic obfuscation methods. Recently proposed sensitivity analysis attack can decrypt stripped functionality based logic encryption schemes. This article presents a new encryption scheme named SRTLock, which is resilient against both attacks. SRTLock method first generates 0-injection circuits and encrypts the functionality of these nodes with the key inputs. In the next step, these values are used to control the sensitivity of the functionally stripped output for specific input patterns. The resultant locked circuit is resilient against the SAT and sensitivity analysis attacks. Experimental results demonstrating this on several attacks using standard benchmark circuits are presented.
Architectural Wireless Networks Solutions and Security Issues, 2021
Wireless sensor network (WSN) is a collection of sensor nodes that are attached with base station... more Wireless sensor network (WSN) is a collection of sensor nodes that are attached with base station (BS) and sink node to achieve a specific purpose. The main purpose of the WSN is sensing environmental parameters such as energy, temperature, and humidity. There are several parameters of the WSN that changes time to time and frequently based on the operation. Each sensor node contains limited capacity of battery that is insufficient during any operation and fails to send the data packet to the BS. So, there is need of some modeling using some intelligent technique. In this paper, a fuzzy quadratic programming (FQP) is used to optimize network parameters efficiently. FQP is the fusion of fuzzy logic and quadratic programming. Fuzzy logic is a multi-values logic which is used to reduce uncertainty and estimate imprecise parameters efficiently. Quadratic programming is a nonlinear programming based on second order of mathematical polynomial for reducing the main objective. The combinatio...
In this article an analysis of carbon nanotube field effect transistor based ring oscillator is p... more In this article an analysis of carbon nanotube field effect transistor based ring oscillator is performed. After analysis it was found that carbon nanotube transistor consumes less power in comparison to silicon transistor. CNFET is one possible candidate to substitute silicon-based integrated circuit (IC) technology, as the performance increase of conventional transistors witnessed during the last decades will arrive at its ultimate limits in the near future. Its present progress is largely dominated by the materials science community due to many still existing materials-related obstacles for realizing practically competitive transistors. Compared to graphene, carbon nanotube provides better properties for building field-effect transistors, and thus, has higher chances for eventually becoming a production technology. So, in this work it is used carbon nanotube field effect transistor in place of silicon based transistor for making a ring oscillator. Keywords: Carbon nanotube, power...
International Journal of Engineering Trends and Technology, 2017
The low power chip designing is a field of immense interest to the technology for electronics chi... more The low power chip designing is a field of immense interest to the technology for electronics chip designing industries. Operational amplifiers (OpAmps) are an integral parts of many analog and mixed signal systems. There is need to investigate the performance of the forthcoming scaled channel length CMOS devices. In this work a two stage CMOS Operational Amplifier with gain boosting technique, Darlington pair is proposed. The proposed Op-Amp shows high gain as well as high CMRR with reduced leakage current and power supply. This amplifier is highly useful for wireless communication because of low power consumption, high bandwidth, high gain and high CMRR. The designed operational amplifier gain is 93 dB, UnityGain Bandwidth is 538 MHz, CMRR is 100dB, slew rate is 20.13V/μS, power dissipation is 10pW, leakage current is 2.17pA, phase margin is 86o, and settling time is 95ns. The designed circuit is simulated using H-Spice tool at 32nm technology.
In the semiconductor industry, protecting Integrated Circuits (IC) throughout the IC supply chain... more In the semiconductor industry, protecting Integrated Circuits (IC) throughout the IC supply chain has become a major concern. In-depth research has been done on logic encryption, split manufacturing, and layout camouflaging to safeguard ICs against attacks at various stages of the supply chain. In this work, we introduce a hybrid, method called Hybrid Shielding (which amplifies the power of camouflaging and logic locking) to protect ICs at each stage of the supply chain, including the foundry, the testing facility, and the end user. We take advantage of the spin-based device, called the Giant Spin-Hall Effect (GSHE) switch, multi-functionality, post-fabrication reconfigurability, and run-time polymorphism to make dynamic camouflaging resistant to SAT-based attacks and test-data mining-based attacks. These characteristics are not available to designers in CMOS. We define two metrics for circuit nodes: stability and weight. Hybrid Shielding replaces all of the selected gates with polymorphic gates. It uses a simulator to ascertain the internal state of the selected nodes. The camouflaged internal state will be used to corrupt the functionality of the primary outputs. The resulting locked circuit has high output corruption rates and is resilient to the SAT attack, Hack Test, as well as several other attacks. These results are demonstrated experimentally using standard benchmark circuits.
This paper describes the architecture of first and second generation current conveyor (CCI and CC... more This paper describes the architecture of first and second generation current conveyor (CCI and CCII respectively) and designing an amplifier using second generation current conveyor. The designed amplifier through CCII+ can be used in various analog computation circuits and is superior in performance than the classical opamp. It provides better gain with higher accuracy.
International Journal of Electrical and Electronics Research, 2014
Due to the growing impact of subthreshold and gate leakage, static leakage is contributing more a... more Due to the growing impact of subthreshold and gate leakage, static leakage is contributing more and more towards the power dissipation in deep submicron Nano CMOS technology. There have been many works on subthreshold leakage and techniques to reduce it, such as controlling the input vector to the circuit in standby mode, forcing stack and body bias control. In this tutorial paper we have reviewed the leakage current with change in drain source, gate and bulk voltages for 4 different submicron technologies using the latest PTM models. Simulation result shows the effect of gate leakage and subthreshold leakage in total leakage current for different input vectors for a stack of 3 Nano technology NMOS transistors, further analyzes also the subthreshold and total leakage variation with input vector in a stack of 4 Nano technology NMOS transistors.
International Journal of Electrical and Electronics Research, 2014
In this paper, an analysis of different delay lines based on CMOS architecture has been done. Com... more In this paper, an analysis of different delay lines based on CMOS architecture has been done. Comparison has been made on these delay lines in terms of propagation delay, power dissipation, area, and power delay product. After the analysis of those performance parameters, the tradeoff has been made for better performance of delay lines.
Due to rampant leveling of instrument measurements, the stability of an SRAM cell is the biggest ... more Due to rampant leveling of instrument measurements, the stability of an SRAM cell is the biggest anxiety for upcoming technology. In this paper, it is introduced by an 8T (8-transistor) SRAM cell. The enlarged data stability is offered by proposed cell until read operation. The voltage scale of the node keeping ‘0’ is enlarged by introduced cell and thus it achieves a near butterfly curve that is vital to creation a substantial SRAM cell. The read static noise margin or read SNM (RSNM) is as advanced as 223 mV @ 700 mV in 45 nm technology node and it is 3.01 times more stable than standard 6T SRAM cell during read operation. The introduced cell also gets 1.45 times lower latency at the equal voltage similitude to standard 6T SRAM cell . Keyword: CMOS, Read Delay (latency), Read Stability, RSNM Cite this Article Anjali Pachauri, Nikhil Saxena . A Double-Ended Read-Decoupled 8T SRAM Cell with Improved Read Stability and Access Time at 45 nm Technology . Journal of Semiconductor Device...
Architectural Wireless Networks Solutions and Security Issues, 2021
When the fourth generation for wireless communication networks was developed, it was upgraded to ... more When the fourth generation for wireless communication networks was developed, it was upgraded to provide both enhanced coverage area and higher data rates to every mobile user with lower latency. However, wireless communication system for the next-generation network will need to challenge new requirement with a greater diversity of application requirements such as ultra-high data rate, ultra-low latency, flexible use of spectrum and spectrum sharing, and battery-powered sensors that needs extremely low energy consumption, and some other control applications that want a very short round trip time (RTT). Due to problems with orthogonal frequency division multiplexing (OFDM) and next-generation demands, OFDM is not used as a promising waveform for next-generation wireless communication network. In these circumstances, alternative multiplexing schemes such as generalized frequency division multiplexing (GFDM), due to flexibility in pulse shape and single cyclic prefix in a multi-path system, GFDM is becoming common every day, making it eligible for 5G wireless technologies. GFDM looks as generalization of OFDM technique. But one of the common drawbacks of every multicarrier system is their high peak to average power ratio (PAPR). The main effect of strong PAPR is instability in the analog to digital converter (ADC) and digital to analog converter (DAC), decreased its performance and raised costs. A PAPR reduction technique such as clipping and filtering that greatly improves the efficiency compared to the initial GFDM signal PAPR. Overall peak re-growth can be reduced by using repeated clip and filter operations. Simulation is performed for this scheme to evaluate this system’s PAPR output for different values of roll-off variables.
1Scholar Dept. of ECE, ITM, Gwalior, India 2Assistant Professor, Dept. of ECE, ITM, Gwalior, Indi... more 1Scholar Dept. of ECE, ITM, Gwalior, India 2Assistant Professor, Dept. of ECE, ITM, Gwalior, India ---------------------------------------------------------------------***--------------------------------------------------------------------Abstract As technology continues to scale down, leakage power has become a significant component in chip design. Leakage power is a key parameter to design low power devices because it is an important source of total power consumption. Large amount of leakage power is an issue of serious concern in portable electronics devices. Limited energy consumption in multimedia requires very low power circuits. Static Random Access Memory (SRAM) comprises a considerable proportion of the total area and total power for almost all VLSI chips as cache memory for the System on Chip (SOC) and it is expected to increase in the future in both handy devices and highperformance processors. By using low-power FinFET based SRAM cell, we can achieve higher steadfastness...
In this current paper execution of forward body biased True Single Phase Clock (FBBTSPC) and forw... more In this current paper execution of forward body biased True Single Phase Clock (FBBTSPC) and forward body biased extended True Single Phase Clock (FBBETSPC) are investigated. The delay of FBBTSPC and FBBETSPC are analyzed, simulated, executed and compared with the existing TSPC and ETSPC. A high speed divide-by-2 unit of frequency divider divide by two with the body biased is proposed and validated that this frequency divider divide by two can operate with higher frequency of 4 GHz stably on a 180 nm technology. This frequency divider divide by two with the body bias design can be widely used in Communication data analysis probe systems.
Nowadays, the performance parameters should not affect the variation in fixed parameters like lea... more Nowadays, the performance parameters should not affect the variation in fixed parameters like leakage current, leakage power, propagation delay, and power delay product. So this study is basically focused on the effects of changes in supply voltage (0.8–1.2V) on the various performance parameters of 2-stage inverter based delay line based on CMOS architecture. A delay line is a discrete element in digital theory, which simply allows a signal to be delayed by the number of samples. The effects of changes in supply voltage on leakage current, leakage power, and propagation delay and PDP product have been studied. SPICE simulation tool is used for this analysis with 32nm technology node. Keywords: Supply voltage, leakage power, leakage current, power delay product, propagation delay. Cite this Article Bhupendra Dubey, Nikhil Saxena. Analysis of 2-Stage Inverter Delay Line with Supply Voltage Variation. Trends in Electrical Engineering . 2019; 9(1): 31–35p.
International Journal of Engineering Trends and Technology, 2017
SRAM cells are designed exclusively to guarantee that the data of the cell is not altered during ... more SRAM cells are designed exclusively to guarantee that the data of the cell is not altered during read access and the cell can quickly change its state during write operation. These conflicting needs for read and write operations are contented by some specific conditions to provide stable read and write operations, SRAM cell read stability and write ability is most important concerns in nanometer scale technologies, due to the progressive increase in intra die variability and Vdd scaling. In conventional six transistors (6T) SRAM cell, read stability is very low due to the voltage division between the access and driver transistors during read operation. Analysis has been done with the factors responsible to improve the read stability and write ability of 6T SRAM cell structures. SRAM cell stability analysis is typically based on Static Noise Margin (SNM) investigation. Keywords—Read stability, write ability, Cell Ratio, Pull up transistor, SRAM cell, Static Noise Margin (SNM)
Uploads
Papers by NIKHIL SAXENA