The interchip communication protocols for the WE32100 microprocessor chip set had to be designed ... more The interchip communication protocols for the WE32100 microprocessor chip set had to be designed to support several ambitious architectural goals. T he WE32100 series of VLSI chips is an upgrade and addition to the WE32000 (formerly, Bellmac-32A) 32-bit microprocessor family. The WE32100 family is a CMOS chip set that differs from its predecessor in operating speed as well as in hardware architecture. Some software architecture modifications of the upwardcompatible type were also implemented. Here, we discuss the WE32100 chip set's interchip protocols as they relate to system hardware architectures. These protocols were defined at the same time the WE32100 family was designed. We also examine architectural trade-offs as they pertain to the WE32100 chip family. Goals A number of goals guided the definition of the hardware architecture. We wanted to * provide an interchip protocol that would support competitive performance in a 32-bit microprocessor operating at a prescribed frequency, * provide a true all-VLSI chip set requiring no SSI ''glue,'' * allow for multiple chip set configurations, to permit a system designer to customize the chip set to his needs, * support the software architecture of the entire chip set, * retain some compatibility with predecessor chips so that Bellmac customers desiring higher performance via the WE32100 chip set would not need to perform wholesale architectural changes when upgrading, and * allow for easy interfacing to commercial memories and peripherals. Alternatives investigated We investigated over a dozen alternatives for an interchip communications protocol. They fell into three categories: * asynchronous protocols compatible with the WE32000 (Bellmac-32A) microprocessor module, * asynchronous protocols with pipelined memory transactions, and * fully synchronous protocols with "split-read" memory transactions. The first category included about eight variations on the theme. The WE32000 module has a four-cycle (zero-waitstate) memory transaction. We felt that a cycle could be eliminated from this access and, further, that excess over
The interchip communication protocols for the WE32100 microprocessor chip set had to be designed ... more The interchip communication protocols for the WE32100 microprocessor chip set had to be designed to support several ambitious architectural goals. T he WE32100 series of VLSI chips is an upgrade and addition to the WE32000 (formerly, Bellmac-32A) 32-bit microprocessor family. The WE32100 family is a CMOS chip set that differs from its predecessor in operating speed as well as in hardware architecture. Some software architecture modifications of the upwardcompatible type were also implemented. Here, we discuss the WE32100 chip set's interchip protocols as they relate to system hardware architectures. These protocols were defined at the same time the WE32100 family was designed. We also examine architectural trade-offs as they pertain to the WE32100 chip family. Goals A number of goals guided the definition of the hardware architecture. We wanted to * provide an interchip protocol that would support competitive performance in a 32-bit microprocessor operating at a prescribed frequency, * provide a true all-VLSI chip set requiring no SSI ''glue,'' * allow for multiple chip set configurations, to permit a system designer to customize the chip set to his needs, * support the software architecture of the entire chip set, * retain some compatibility with predecessor chips so that Bellmac customers desiring higher performance via the WE32100 chip set would not need to perform wholesale architectural changes when upgrading, and * allow for easy interfacing to commercial memories and peripherals. Alternatives investigated We investigated over a dozen alternatives for an interchip communications protocol. They fell into three categories: * asynchronous protocols compatible with the WE32000 (Bellmac-32A) microprocessor module, * asynchronous protocols with pipelined memory transactions, and * fully synchronous protocols with "split-read" memory transactions. The first category included about eight variations on the theme. The WE32000 module has a four-cycle (zero-waitstate) memory transaction. We felt that a cycle could be eliminated from this access and, further, that excess over
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Papers by Michael Fuccio