IEEE/ACM International Conference on Computer-Aided Design, 1992
ABSTRACT Linear state variable digital systems, commonly implemented in bit-serial architecture u... more ABSTRACT Linear state variable digital systems, commonly implemented in bit-serial architecture using silicon compilers, are difficult to test for manufacturing defects due to deep sequentiality, low controllability and observability, and high latency. A novel hierarchical ...
VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design
Abstract Success of the fabless model has increased competition and has put pressure on design ho... more Abstract Success of the fabless model has increased competition and has put pressure on design houses to reduce die costs. One method of cost reduction is the application of design for manufacturability (DFM) at the layout stage. Previously DFM has been applied to standard cell libraries and ...
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers
A conditional resource-sharing algorithm for pipeline synthesis is presented. It allows sharing o... more A conditional resource-sharing algorithm for pipeline synthesis is presented. It allows sharing of hardware components among the mutually exclusive parts of any conditional branches appearing in a behavioral description. If done improperly, resource sharing in a conditional branch can increase its critical path delay excessively, causing performance degradation. Given area/time constraints for a pipelined design, finding an optimal conditional sharing
1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers
A scheduling and hardware sharing algorithm is presented. This algorithm is generic and can be us... more A scheduling and hardware sharing algorithm is presented. This algorithm is generic and can be used for synthesizing both nonpipelined and pipelined data paths. The scheduling algorithm tries to distribute operations equally among partitions to maximize hardware sharing. Multiplexer delays are explicitly considered to produce a more accurate scheduling. In hardware sharing, structural parameters such as the size of multiplexers,
2009 10th International Symposium on Quality of Electronic Design, 2009
Abstract We are at the crossroads of some fundamental changes that are taking place in the semico... more Abstract We are at the crossroads of some fundamental changes that are taking place in the semiconductor industry. Power is a primary design criterion for bulk of the semiconductor designs now and a key reason behind the shift towards multi-core designs as increase in power ...
2008 IEEE International High Level Design Validation and Test Workshop, 2008
We are at the crossroads of some fundamental changes that are taking place in the semiconductor i... more We are at the crossroads of some fundamental changes that are taking place in the semiconductor industry. Power consumption has become one of the most important differentiating factors for semiconductor products due to a major shift in the market towards handheld consumer devices. Power is a primary design criterion for bulk of the semiconductor designs now. Power is a key reason behind the shift towards multi-core designs as increase in power consumption limits increases in clock speed at the rate we have seen in the past.
1989 Proceedings of the IEEE Custom Integrated Circuits Conference, 1989
This paper describes a new approach to the silicon compilation of analog functional blocks; an al... more This paper describes a new approach to the silicon compilation of analog functional blocks; an algorithmic approach is adopted for the compiler and its structural components including the synthesis, analog physical assembly, analog module generation, and device compilation The approach is motivated by the need to aid the designer in assembling analog subsystems from a description of the design and parametrized leaf cells/operators. The results from an implementation that is being developed to compile high performance, medium speed sample data systems in BiCMOS technology are presented.
This paper describes a logic simulation system that supports both Bipolar as well as MOS IC desig... more This paper describes a logic simulation system that supports both Bipolar as well as MOS IC design. Some of the underlying concepts implemented in this system, which also supports mixed-level simulation, are described. A brief discussion of the basic Current Mode Logic (CML) primitives, simulation algorithms and basic data structures will also be presented.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143)
... HT Heineken, J. Khare and M. d'Abreu Level One Communications Sacramento. ... 1.0 In... more ... HT Heineken, J. Khare and M. d'Abreu Level One Communications Sacramento. ... 1.0 IntroductionModem IC manufacturing is characterized by steeply ris-ing costs: fabrication line costs have doubled every generation, to $1-2 billion today [1,2]. An important component of cost is ...
We propose a novel Design for Testability technique to apply two pattern tests for path delay fau... more We propose a novel Design for Testability technique to apply two pattern tests for path delay fault testing. Due to stringent timing requirements of deep-submicron VLSI chips, design-for-test schemes have to be tailored for de-tecting stuck-at as well as delay faults quickly and effi- ...
Proceedings of the Sixth Great Lakes Symposium on VLSI
This paper presents a n e w mechanism for power analysis and reduction that exploits the hierarch... more This paper presents a n e w mechanism for power analysis and reduction that exploits the hierarchical nature of circuits. A number of mechanisms have been proposed for power reduction, but they do n o t offer solutions in all cases. An activity-based reduction technique is presented where the clock is turned off for entire modules or sub-modules hierarchically when that portion of t h e circuit is n o t in use. BeLavioral constraints are used to determine when a portion of the circu,it is in use. T h e method shown is a top-down approach independent of the technology used during fabrication of the chip. Experimental results indicate that this method will result in a considerable reduction in i,wwer. System performance has been associated with circuit, speed. The cost depends upon the implementation strategy. For circuits, there is a reasonable correspondence between the axea and the cost. So, t,he designer usually explores the Area-Time space to strike a balance between the performance and the cost. Until recently, these where the only criteria for the designer, and power consumption was of lesser import,ance. Power is an important resocrce that needs to be conserved for the following reasons: e Higher power consumption leads to reduced reliability in the chip. e Higher power makes a computer less portable 0 The cost associated with packaging and cooling of high power consuming chips is prohibitive.
Proceedings of the IEEE 1988 Custom Integrated Circuits Conference
A description is given of the aspects of mixed analog and digital physical assembly relevant to a... more A description is given of the aspects of mixed analog and digital physical assembly relevant to analog silicon compilation. The approach addresses system-level analog design automation through silicon compilation; currently this consists of the synthesis of analog and predesigned digital blocks. The compilation is based on successive decompositions of high-level specifications and physical assembly requirements into those of lower level
... Rabindra K . Roy Naveena Nagi Abhijit Chatterjee and Manuel A. d'Abreu NEC Research ... more ... Rabindra K . Roy Naveena Nagi Abhijit Chatterjee and Manuel A. d'Abreu NEC Research Institute Computer Engineering General Electric Research and ... Iterative Arithmetic Arrays (IAAs) are an impor-tant class of circuits, used extensively in modem digi-tal systems. ...
Proceedings of the 1989 26th ACM/IEEE conference on Design automation conference - DAC '89, 1989
We discuss the design and implementation of VISAGE, an object-oriented user interface framework t... more We discuss the design and implementation of VISAGE, an object-oriented user interface framework that is part of GE's F,1CE Flexible Architecture Compiler Environnmnt [I]. Highlcvcl services include a doinaiii-iildependelit graph editor that provides standard methods for viewing and editing hierarchical graphs, including graph layout. Editors that are customized to a specific application are built by inheritance of the dolllain-illdepclldellt graph editor's functionality and overloading of the display, selection and editing methods. At a lower layer, presentation objects arc responsible for parsing user input, displaying application output, providing mouse sensitivity and command dialogue execution. These presentation objects separate the application from its user interface, and thus promote system modularity.
Proceedings of the 1989 26th ACM/IEEE conference on Design automation conference - DAC '89, 1989
... [ll] A. Goldberg and D. Robson. Smalltalk-80: The Language and its Implementation.Addison-Wes... more ... [ll] A. Goldberg and D. Robson. Smalltalk-80: The Language and its Implementation.Addison-Wesly, 1983. [12] J. Granacki, D. Knapp, and A. Parker. ... In Proc. 24th DAC, pages 321-327. IEEE, 1987. [16] M. Dragomirecky, E. Glinert. J. Jasica, D. Duff, W. Smith, and M. d'Abreu. ...
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers
Page 1. Flexible Module Generation In The FACE Design Environment William D. Smith, Jeffrey R. Ja... more Page 1. Flexible Module Generation In The FACE Design Environment William D. Smith, Jeffrey R. Jasica, Michael J. Hartman, Manuel A. d'Abreu General Electric Corporate Research and Development Building KW Room C301 PO Box 8 Schenectady, New York 12301 ...
IEEE/ACM International Conference on Computer-Aided Design, 1992
ABSTRACT Linear state variable digital systems, commonly implemented in bit-serial architecture u... more ABSTRACT Linear state variable digital systems, commonly implemented in bit-serial architecture using silicon compilers, are difficult to test for manufacturing defects due to deep sequentiality, low controllability and observability, and high latency. A novel hierarchical ...
VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design
Abstract Success of the fabless model has increased competition and has put pressure on design ho... more Abstract Success of the fabless model has increased competition and has put pressure on design houses to reduce die costs. One method of cost reduction is the application of design for manufacturability (DFM) at the layout stage. Previously DFM has been applied to standard cell libraries and ...
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers
A conditional resource-sharing algorithm for pipeline synthesis is presented. It allows sharing o... more A conditional resource-sharing algorithm for pipeline synthesis is presented. It allows sharing of hardware components among the mutually exclusive parts of any conditional branches appearing in a behavioral description. If done improperly, resource sharing in a conditional branch can increase its critical path delay excessively, causing performance degradation. Given area/time constraints for a pipelined design, finding an optimal conditional sharing
1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers
A scheduling and hardware sharing algorithm is presented. This algorithm is generic and can be us... more A scheduling and hardware sharing algorithm is presented. This algorithm is generic and can be used for synthesizing both nonpipelined and pipelined data paths. The scheduling algorithm tries to distribute operations equally among partitions to maximize hardware sharing. Multiplexer delays are explicitly considered to produce a more accurate scheduling. In hardware sharing, structural parameters such as the size of multiplexers,
2009 10th International Symposium on Quality of Electronic Design, 2009
Abstract We are at the crossroads of some fundamental changes that are taking place in the semico... more Abstract We are at the crossroads of some fundamental changes that are taking place in the semiconductor industry. Power is a primary design criterion for bulk of the semiconductor designs now and a key reason behind the shift towards multi-core designs as increase in power ...
2008 IEEE International High Level Design Validation and Test Workshop, 2008
We are at the crossroads of some fundamental changes that are taking place in the semiconductor i... more We are at the crossroads of some fundamental changes that are taking place in the semiconductor industry. Power consumption has become one of the most important differentiating factors for semiconductor products due to a major shift in the market towards handheld consumer devices. Power is a primary design criterion for bulk of the semiconductor designs now. Power is a key reason behind the shift towards multi-core designs as increase in power consumption limits increases in clock speed at the rate we have seen in the past.
1989 Proceedings of the IEEE Custom Integrated Circuits Conference, 1989
This paper describes a new approach to the silicon compilation of analog functional blocks; an al... more This paper describes a new approach to the silicon compilation of analog functional blocks; an algorithmic approach is adopted for the compiler and its structural components including the synthesis, analog physical assembly, analog module generation, and device compilation The approach is motivated by the need to aid the designer in assembling analog subsystems from a description of the design and parametrized leaf cells/operators. The results from an implementation that is being developed to compile high performance, medium speed sample data systems in BiCMOS technology are presented.
This paper describes a logic simulation system that supports both Bipolar as well as MOS IC desig... more This paper describes a logic simulation system that supports both Bipolar as well as MOS IC design. Some of the underlying concepts implemented in this system, which also supports mixed-level simulation, are described. A brief discussion of the basic Current Mode Logic (CML) primitives, simulation algorithms and basic data structures will also be presented.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143)
... HT Heineken, J. Khare and M. d'Abreu Level One Communications Sacramento. ... 1.0 In... more ... HT Heineken, J. Khare and M. d'Abreu Level One Communications Sacramento. ... 1.0 IntroductionModem IC manufacturing is characterized by steeply ris-ing costs: fabrication line costs have doubled every generation, to $1-2 billion today [1,2]. An important component of cost is ...
We propose a novel Design for Testability technique to apply two pattern tests for path delay fau... more We propose a novel Design for Testability technique to apply two pattern tests for path delay fault testing. Due to stringent timing requirements of deep-submicron VLSI chips, design-for-test schemes have to be tailored for de-tecting stuck-at as well as delay faults quickly and effi- ...
Proceedings of the Sixth Great Lakes Symposium on VLSI
This paper presents a n e w mechanism for power analysis and reduction that exploits the hierarch... more This paper presents a n e w mechanism for power analysis and reduction that exploits the hierarchical nature of circuits. A number of mechanisms have been proposed for power reduction, but they do n o t offer solutions in all cases. An activity-based reduction technique is presented where the clock is turned off for entire modules or sub-modules hierarchically when that portion of t h e circuit is n o t in use. BeLavioral constraints are used to determine when a portion of the circu,it is in use. T h e method shown is a top-down approach independent of the technology used during fabrication of the chip. Experimental results indicate that this method will result in a considerable reduction in i,wwer. System performance has been associated with circuit, speed. The cost depends upon the implementation strategy. For circuits, there is a reasonable correspondence between the axea and the cost. So, t,he designer usually explores the Area-Time space to strike a balance between the performance and the cost. Until recently, these where the only criteria for the designer, and power consumption was of lesser import,ance. Power is an important resocrce that needs to be conserved for the following reasons: e Higher power consumption leads to reduced reliability in the chip. e Higher power makes a computer less portable 0 The cost associated with packaging and cooling of high power consuming chips is prohibitive.
Proceedings of the IEEE 1988 Custom Integrated Circuits Conference
A description is given of the aspects of mixed analog and digital physical assembly relevant to a... more A description is given of the aspects of mixed analog and digital physical assembly relevant to analog silicon compilation. The approach addresses system-level analog design automation through silicon compilation; currently this consists of the synthesis of analog and predesigned digital blocks. The compilation is based on successive decompositions of high-level specifications and physical assembly requirements into those of lower level
... Rabindra K . Roy Naveena Nagi Abhijit Chatterjee and Manuel A. d'Abreu NEC Research ... more ... Rabindra K . Roy Naveena Nagi Abhijit Chatterjee and Manuel A. d'Abreu NEC Research Institute Computer Engineering General Electric Research and ... Iterative Arithmetic Arrays (IAAs) are an impor-tant class of circuits, used extensively in modem digi-tal systems. ...
Proceedings of the 1989 26th ACM/IEEE conference on Design automation conference - DAC '89, 1989
We discuss the design and implementation of VISAGE, an object-oriented user interface framework t... more We discuss the design and implementation of VISAGE, an object-oriented user interface framework that is part of GE's F,1CE Flexible Architecture Compiler Environnmnt [I]. Highlcvcl services include a doinaiii-iildependelit graph editor that provides standard methods for viewing and editing hierarchical graphs, including graph layout. Editors that are customized to a specific application are built by inheritance of the dolllain-illdepclldellt graph editor's functionality and overloading of the display, selection and editing methods. At a lower layer, presentation objects arc responsible for parsing user input, displaying application output, providing mouse sensitivity and command dialogue execution. These presentation objects separate the application from its user interface, and thus promote system modularity.
Proceedings of the 1989 26th ACM/IEEE conference on Design automation conference - DAC '89, 1989
... [ll] A. Goldberg and D. Robson. Smalltalk-80: The Language and its Implementation.Addison-Wes... more ... [ll] A. Goldberg and D. Robson. Smalltalk-80: The Language and its Implementation.Addison-Wesly, 1983. [12] J. Granacki, D. Knapp, and A. Parker. ... In Proc. 24th DAC, pages 321-327. IEEE, 1987. [16] M. Dragomirecky, E. Glinert. J. Jasica, D. Duff, W. Smith, and M. d'Abreu. ...
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers
Page 1. Flexible Module Generation In The FACE Design Environment William D. Smith, Jeffrey R. Ja... more Page 1. Flexible Module Generation In The FACE Design Environment William D. Smith, Jeffrey R. Jasica, Michael J. Hartman, Manuel A. d'Abreu General Electric Corporate Research and Development Building KW Room C301 PO Box 8 Schenectady, New York 12301 ...
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