Papers by Marleen Van Der Veen
Patterns down to 21nm metal pitch (MP) have been used in the hybrid metallization scheme of Ru vi... more Patterns down to 21nm metal pitch (MP) have been used in the hybrid metallization scheme of Ru via prefill followed by a Cu trench metallization. The via resistance for Ru in hybrid with TaNRu/Cu trench fill is benchmarked to Co and Ru dual-damascene (DD) metallization schemes. At 30nm MP, a 40% via resistance reduction is observed upon introducing the Ru prefill prior to the Cu metallization. The Ru prefill significantly improved the via yield for the Cu metallization in 21nm MP. At this dimension, a 35% lower resistance is obtained with the Ru-Cu hybrid system when benchmarked to Co and Ru full fill with a 1nm TiN barrier. The electromigration of the Ru-Cu hybrid system does not a show a performance degradation, making it a viable scaling scenario for DD metallizations in N5 technologies and beyond.
Meeting abstracts, Oct 9, 2022
The dimensional scaling of the back-end of line (BeOL)interconnects is a significant challenge fo... more The dimensional scaling of the back-end of line (BeOL)interconnects is a significant challenge for the deposition and fill of conductive metals in narrow lines and small vias that are needed to connect the semiconductor devices. Especially at the lower and the smaller interconnect levels, the scaling of the copper (Cu) dual damascene is becoming the limiting factor due to the increase in the resistance-capacitance delay. The increase in RC delay results in a degradation of the chip performance. So, while the scaling in the logic device landscape leads to a continuous improvement of the device performance and an increased transistor density, the Cu wiring in the interconnects systems tend to perform worse when scaling down the dimensions. This paper addresses methodologies to continue the scaling of the BEOL interconnects down to small CD’s like 12nm. For this, process and materials innovation are the key to reduce the interconnect area and its resistance.[1] Examples that will be discussed include Cu hybrid metallization and the use of new conductor materials or integration methodologies like metal patterning. In being the workhorse for building multilevel interconnects, the first desired direction is to push and extend the conventional Cu dual damascene metallization to small dimensions. However, extending Cu is not only challenging from a metal fill point of view, but also from the resistance as well as reliability point of view. The ideal metal that could replace the conventional Cu should have a low electrical resistance in scaled dimensions, have a good thermal conductivity, is resistant against oxidation and possesses a high melting point.[2] This melting is a good measure for the ease of electromigration due to metal diffusion where a high melting point would allow for a reliable operation without the need for a barrier material to prevent it to diffuse. This brings Ru, Mo and W in the picture as interesting material to replace Cu in the vias, and potential later in the lines as well. Figure 1 (left) shows the tabulated via and line resistance predictions for Cu and alternative metals to Cu like Co, Ru, Mo and W (method described elsewhere [3]). The red color coding is used to indicate too high resistance values, where green indicates the desired target resistance. The resistance benefit for the use of Ru, Mo or W compared to Cu is clearly visible in the table. An efficient way to introduce a new alternative metal in the Cu interconnect metallization without being too disruptive is using a selective metal deposition for the vias landing on the exposed bottom metal (Fig.1 middle). After the vias are filled using a selective metal-on-metal deposition with a barrierless metal like Ru or W [4,5], the remainder of the structures can be filled using the conventional Cu metallization scheme. This process is called a Cu hybrid metallization scheme. Filling the vias before the Cu line metallization, improves the process window and yield for the Cu gapfill. Challenges for the selective deposition of metals in vias will be discussed. The XTEM in Figure 1 (right) shows a successful example of the metal prefill in a via hole with bottom CD of 14nm. The via is nicely filled with the metal while the top lines in the dielectric that are not connected to vias do not show any non-selective deposition. Even though the vias are becoming more and more critical in the signal routing on a system-on-chip level, the resistance penalty for the Cu lines is unacceptable at small CDs as can be seen in the table in Fig.1. But eventually, the Cu electromigration will set the limit because at 10nm CD copper lines are not expected to meet electromigration requirements anymore [6]. This is then an inflection point to also replace the lines with alternative metals like Ru, Mo or more exotic conductors like binary metals. For these metals, the challenges in the line fill, processing, and integration will be discussed which may lead to the introduction of the so-called semi-damascene module [7] instead of using the dual damascene methodology. [1] J. Clarke et al, IEEE VLSI 2014, p. 176 [2] D. Gall et al, J. Appl. Phys. 2016, 119, p.085101 [3] I. Ciofi et al, IEEE transactions on Electron Devices 2017, 64 (5), p.2306 [5] M.H. van der Veen et al, Proc. of the IITC 2021, S7-2 [4] M. van der Veen et al, Proc. of the IITC 2020, p.16 [6] K. Croes et al, IEDM 2018, p 5.3.1 [7] Zs. Tőkei et al, IEDM 2020, p 32.2.2 Figure 1
Bulletin of the American Physical Society, Mar 14, 2008
The electromigration (EM) performance of Cu interconnects with different barrier/liner combinatio... more The electromigration (EM) performance of Cu interconnects with different barrier/liner combinations is studied by means of 1/f (or generally known as low-frequency) noise measurements. It is shown that Cu interconnects with a TaN barrier and Co liner have lower EM activation energies for 22nm half-pitch line-widths than Ru based liners. Indeed, interconnects with a 1nm Ru liner (both with TaN and Mn-based barriers) are found to outperform lines with a Co liner in terms of EM reliability. A possible explanation for this is a less defective Cu/Ru interface as compared to Cu/Co.
Advanced Functional Materials, Aug 1, 2004
The inspiration for the concept of omniconjugation was found in the works of Prof. Fred Wudl on c... more The inspiration for the concept of omniconjugation was found in the works of Prof. Fred Wudl on conjugated systems. We would like to thank him for a stimulating discussion during the preparation of this manuscript. This work was financially supported by the Dutch Ministries of EZ, O&W, and VROM through the EET program (EETK97 115).
Journal of Applied Physics, Apr 9, 2014
We used a cyclic reactive ion etching (RIE) process to increase the Co catalyst density on a coba... more We used a cyclic reactive ion etching (RIE) process to increase the Co catalyst density on a cobalt disilicide (CoSi2) substrate for carbon nanotube (CNT) growth. Each cycle of catalyst formation consists of a room temperature RIE step and an annealing step at 450 °C. The RIE step transfers the top-surface of CoSi2 into cobalt fluoride; while the annealing reduces the fluoride into metallic Co nanoparticles. We have optimized this cyclic RIE process and determined that the catalyst density can be doubled in three cycles, resulting in a final CNT shell density of 6.6 × 1011 walls·cm−2. This work demonstrates a very effective approach to increase the CNT density grown directly on silicides.
Aggressive downscaling of the barrier/liner thickness is the key to meet line and via resistance ... more Aggressive downscaling of the barrier/liner thickness is the key to meet line and via resistance requirements from 15nm metal half pitch and below interconnects. For this purpose, porous low-k(2.4) dielectric/Mn-based barrier/Ru-liner/Cu system was extensively studied. Mn-silicate (MnSiO3) formation, intrinsic Cu diffusion barrier property and O2 barrier efficiency of the system were demonstrated. A stack of 1nm Mn-based barrier/1nm Ru liner was successfully integrated in tight pitch dual damascene (DD) Cu wires and its extendibility to at least 15nm feature size was confirmed both morphologically and electrically. Although, it was shown that Mn/Ru-based system is intrinsically reliable from electro-migration (EM) perspective, the absence of the flux divergence at the via bottom was also established, which needs to be addressed. Overall, this work shows that the Mn/Ru-based system is a serious barrier/liner solution for future technology nodes.
We study the reliability performance in terms of electromigration and thermal storage of barrierl... more We study the reliability performance in terms of electromigration and thermal storage of barrierless Co vias. While for our reference with Cu filled vias and a TaNCo barrier/liner system we did observe voids in some vias after electromigration, these voids were not observed for the Co vias and thus the studied system is more scalable towards smaller vias. Long thermal storage measurements show more failures in barrierless Co vias. As this problem is linked to a weak Co/dielectric interface and Co/Cu-intermixing, a better adhesion between the Co and the low-k, the use of a non-porous low-k dielectric and the use of a barrier at the via bottom could help to reduce this phenomenon.
Journal of The Electrochemical Society, 2014
ABSTRACT Glyoxylic acid is seen as a promising candidate to replace formaldehyde as reducing agen... more ABSTRACT Glyoxylic acid is seen as a promising candidate to replace formaldehyde as reducing agent in electroless Cu baths. For deposition on ruthenium, the anodic reaction of glyoxylic acid has been evaluated and compared to formaldehyde using linear sweep voltammetry. Significant differences were observed for the deposition of copper on ruthenium. First of all, a faster nucleation was inferred from open-circuit potential measurements, which is beneficial as it reduces the total process time. Secondary, we found 2,2’ bipyridyl worked as stabilizer and brightener in this glyoxylic acid-based electroless bath. Thirdly, the purity of the copper films improved when 2,2’ bipyridyl was present in the solution. Using the optimized composition, we demonstrate a conformal Cu seed layer deposition (∼100 nm) inside high aspect ratio (16.7) through-Si vias. This work shows the feasibility for electroless Cu seeding in a through-Si via metallization sequence.
Self-forming barriers and advanced liner materials are studied extensively for their Cu gapfill p... more Self-forming barriers and advanced liner materials are studied extensively for their Cu gapfill performance and interconnect scaling. In this paper, 22nm1/2 pitch Cu low-k interconnects with barrier (Mn-based, TaN) /liner (Co, Ru) combinations are compared and benchmarked for their resistivity, resistance scaling, and electromigration (EM) performance. Extendibility to 16nm copper width was explored experimentally and a projection towards 12nm width is performed. It is found that the Ru-liner based systems show a higher overall Cu-resistivity. We show that this increase can be compensated by combining Ru with a thinner Mn-based barrier, which increases the effective Cu-area at a particular trench width. The EM performance reveals that the Ru-liner systems have a better EM lifetime compared to the Co-liner based systems. More interestingly, in a comparison of the maximum current density Jmax a significant improvement is found for the scaled Mn-based/Ru system, making it therefore a serious candidate to extend the Cu metallization.
We evaluate the dielectric reliability performance of 21 nm pitch interconnects integrated in a d... more We evaluate the dielectric reliability performance of 21 nm pitch interconnects integrated in a dense low-k and using a barrierless Ru fill scheme. We show our line-to-line and tip-to-tip TDDB pass 10 years of lifetime at 0.75 V for technology relevant line lengths and number of tips, respectively. Intrinsic dielectric breakdown without metal drift is demonstrated using BTS-TVS measurements. We also investigate the impact of dielectric scaling towards lower dimensions using planar capacitor structures. We observe an increasing field acceleration factor with decreasing thickness possibly suggesting different, slower, degradation mechanisms being present in the thinner dielectrics leading towards more reliability margin for scaled interconnects.
ABSTRACT We discuss the improvement in the electrical characterization and the performance of 150... more ABSTRACT We discuss the improvement in the electrical characterization and the performance of 150 nm diameter contacts filled with carbon nanotubes (CNT) and a Cu damascene top metal on 200mm wafers. The excellent agreement between the yield curves for the parallel and single contacts shows that a reliable electrical characterization is obtained. We demonstrate that integration changes improved the resistivity of the CNT contact significantly by reducing it from 11.8·103 μΩ·cm down to 5.1·103 μΩ·cm. Finally, a length scaling of the CNT contacts was used to find the individual contributors to the lowering of the single CNT contact resistance.
ECS Journal of Solid State Science and Technology, Nov 6, 2014
To enable Cu fill of through-Si vias (TSV) with a high aspect ratio (diameter 3 μm, depth 50 μm),... more To enable Cu fill of through-Si vias (TSV) with a high aspect ratio (diameter 3 μm, depth 50 μm), the electroless deposition of a Cu seed on Co liner material was investigated. The reducing agent glyoxylic acid showed anodic oxidation on Co, which did not appear for the case of formaldehyde. From electrochemical analysis, an optimized bath composition caused limited Co corrosion during the electroless Cu nucleation phase. The concentration ratio of the complexing agent (ethylenediaminetetraacetic acid) and copper was found to strongly impact the liner corrosion; in case free complexing agent is present in the bath, the Co corrosion was assisted by complexation and replacement reactions. A continuous seed layer could be deposited in the entire TSV, which enabled the filling by electrochemical deposition (ECD). The substantially thinner total copper overburden generated for this combination of a wet-chemical seed deposition and an ECD fill process contributes to a cost reduction of its chemical mechanical polishing (CMP).
A carbon nanotube (CNT) contact length scaling is used to derive the electron mean-free path (λ C... more A carbon nanotube (CNT) contact length scaling is used to derive the electron mean-free path (λ CNT) after full integration. A CNT-to-metal contact resistance of 76 Ω and lower was obtained for 150 nm diameter contacts. By estimating the number of conducting walls in the CNT bundle, a λ CNT of 74 nm is found, which is longer than for Cu. We propose a more conservative approach of calculating λ CNT solely from electrical data. The result is that our CNT interconnects have ballistic transport over 24 nm, which is 5 times longer than reported so far.
Metal drift induced failure is a serious threat to the reliability of advanced back-end-of-line (... more Metal drift induced failure is a serious threat to the reliability of advanced back-end-of-line (BEOL) systems based on ultra-thin dielectric layers and metallization schemes with, at best, a very thin barrier. We evaluate the reliability of Cobalt (Co) and low-k dielectric (LK3.0) systems, with a focus on the impact of the metal/dielectric (m/d) interface and of barrier thickness and continuity. Our study confirms that metal drift is a surface driven phenomenon; in the case of low-k dielectrics, it is therefore crucial to preserve a hydrophobic m/d interface to minimize the occurrence of metal drift. Moreover, we find that, as the dielectric thickness is reduced, a thicker barrier is needed to prevent metal drift induced failure, regardless of the interface conditions. Nonetheless, we observed a sizeable increase of the intrinsic field acceleration factor, i.e. when no metal drift occurs, as dielectric thickness decreases, suggesting that scaled dielectrics are more resilient to intrinsic dielectric breakdown.
Interconnects pose increasing challenges as technology scaling proceeds. In order to overcome the... more Interconnects pose increasing challenges as technology scaling proceeds. In order to overcome these challenges simultaneous optimization of novel metallization schemes, new materials, circuit and system level approaches are required.
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Papers by Marleen Van Der Veen