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Khairul Alam

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Papers by Khairul Alam

Uniform Benchmarking of Low-Voltage van der Waals FETs

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2016

and black phosphorous field-effect transistors (FETs) operating in the low-voltage (LV) regime (0... more and black phosphorous field-effect transistors (FETs) operating in the low-voltage (LV) regime (0.3 V) with geometries from the 2019 and 2028 nodes of the 2013 International Technology Roadmap for Semiconductors are benchmarked along with an ultrathin-body Si FET. Current can increase or decrease with scaling, and the trend is strongly correlated with the effective mass. For LV operation at the 2028 node, an effective mass of ∼0.4 m 0 , corresponding to that of WSe 2 , gives the maximum drive current. The short 6-nm gate length combined with LV operation is forgiving in its requirements for material quality and contact resistances. In this LV regime, device and circuit performances are competitive using currently measured values for mobilities and contact resistances for the monolayer 2-D materials. INDEX TERMS 2-D materials, benchmarking, black phosphorous (BP), field-effect transistor (FET), transition metal dichalcogenide (TMD), ultrathin body (UTB) Si, van der Waals (vdW) materials. I. INTRODUCTION

Electronic properties of carbon nanotubes calculated from density functional theory and the empirical π-bond model

Journal of Computational Electronics, 2007

The validity of the DFT models implemented by FIREBALL for CNT electronic device modeling is asse... more The validity of the DFT models implemented by FIREBALL for CNT electronic device modeling is assessed. The effective masses, band gaps, and transmission coefficients of semi-conducting, zigzag, (n, 0) carbon nanotubes (CNTs) resulting from the ab-initio tight-binding density functional theory (DFT) code FIREBALL and the empirical, nearest-neighbor π-bond model are compared for all semiconducting n values 5 ≤ n ≤ 35. The DFT values for the effective masses differ from the π-bond values by ±9% over the range of n values, 17 ≤ n ≤ 29, most important for electronic device applications. Over the range 13 ≤ n ≤ 35, the DFT bandgaps are less than the empirical bandgaps by 20-180 meV depending on the functional and the n value. The π-bond model gives results that differ significantly from the DFT results when the CNT diameter goes below 1 nm due to the large curvature of the CNT. The π-bond model quickly becomes inaccurate away from the bandedges for a (10, 0) CNT, and it is completely inaccurate for n ≤ 8.

Material Selection for Minimizing Direct Tunneling in Nanowire Transistors

IEEE Transactions on Electron Devices, 2012

When the physical gate length is reduced to 5 nm, direct channel tunneling dominates the leakage ... more When the physical gate length is reduced to 5 nm, direct channel tunneling dominates the leakage current for both field effect transistors (FETs) and tunnel field effect transistors (TFETs). Therefore, a survey of materials in a nanowire (NW) geometry is performed to determine their ability to suppress the direct tunnel current through a 5 nm barrier. The materials investigated are InAs, InSb, InP, GaAs, GaN, Si, Ge and carbon nanotubes (CNTs). The tunneling effective mass gives the best indication of the relative size of the tunnel currents when comparing two different materials of any type. The indirect gap materials, Si and Ge, give the largest tunneling masses in the conduction band, and they give the smallest conduction band tunnel currents within the range of diameters considered. Si gives the lowest overall tunnel current for both the conduction and valence band and, therefore, it is the optimum choice for suppressing tunnel current at the 5 nm scale. A semianalytic approach to calculating tunnel current is demonstrated which requires considerably less computation than a full-band numerical calculation.

Electronic Properties of Silicon Nanowires

IEEE Transactions on Electron Devices, 2005

The electronic structure and transmission coefficients of Si nanowires are calculated in a 3 5 mo... more The electronic structure and transmission coefficients of Si nanowires are calculated in a 3 5 model. The effect of wire thickness on the bandgap, conduction valley splitting, hole band splitting, effective masses, and transmission is demonstrated. Results from the 3 5 model are compared to those from a single-band effective mass model to assess the validity of the singleband effective mass model in narrow Si nanowires. The one-dimensional Brillouin zone of a Si nanowire is direct gap. The conduction band minimum can split into a quartet of energies although often two of the energies are degenerate. Conduction band valley splitting reduces the averaged mobility mass along the axis of the wire, but quantum confinement increases the transverse mass of the conduction band edge. Quantum confinement results in a large increase in the hole masses of the two highest valence bands. A single-band model performs reasonably well at calculating the effective band edges for wires as small as 1.54-nm square. A wiresubstrate interface can be viewed as a heterojunction with band offsets resulting in reflection in the transmission. Index Terms-Nanowires (NWs), silicon nanowires (SiNWs). I. INTRODUCTION S EMICONDUCTOR nanowires (NWs) have been widely studied as nanoscale building blocks for nanoelectronics, since they can function both as devices and wires that access the devices. NWs are synthesized from a range of different materials [1], such as CdS and ZnS [2], GaN [3], p-GaN [4], Si, Ge

Role of Phonon Scattering on the Transport and Performance of an N-Channel Monolayer Black Phosphorus Transistor

Journal of Electronics and Electrical Engineering, Jan 7, 2024

We investigate the influence of phonon scattering on the transport properties and performance met... more We investigate the influence of phonon scattering on the transport properties and performance metrics of a monolayer n-channel black phosphorus transistor within a four-band tight binding Hamiltonian, employing a recursive Green's function algorithm and Buttiker probe scattering model. Our analysis reveals that electronphonon scattering significantly degrades the on-state current, while its effects in the subthreshold region are found to be negligible. Further examination identifies optical phonons as the primary contributors to the degradation of on-state current, with acoustic phonons playing a less prominent role. The ballisticity of the device declines from 42% to 24% when transitioning from solely acoustic phonon scattering to the combined influence of acoustic and optical phonons. Expanding the placement of Buttiker probes from beneath the gate region to cover the entire path from source to drain results in a further 48% reduction in on-state current. The on-state current exhibits a parabolic relationship with the inverse Kelvin temperature. To quantify the effects of phonon scattering on device performance, we assess the key parameters, transconductance and unity current gain frequency. Phonon scattering is observed to severely impact both the parameters. The on-state transconductance declines from its ballistic value of 24.9 mS/µm to 3.99 mS/µm when both acoustic and optical phonons are concurrently active. Similarly, the unity current gain frequency decreases from 1.18 to 0.2 THz due to phonon scattering. Additionally, our analysis reveals that approximately 7-9% of the total power dissipated within the device is attributed to phonon scattering effects, while the remainder is released through thermalization in the device's contacts. Phonon scattering is shown to induce both lattice cooling and heating, depending on the presence or absence of potential barriers. When a potential barrier exists in the channel, electrons injected from the source experience lattice cooling before the barrier region and lattice heating after crossing the barrier. Including the source and drain contact resistances in our model unveils that achieving a contact resistance value of approximately 100 Ω-µm is crucial for the effective functioning of black phosphorus devices.

Orientation Engineering for Improved Performance of a Ge-Si Heterojunction Nanowire TFET

IEEE Transactions on Electron Devices

Simulation study on the effects of changing band gap on solar cell parameters

2016 9th International Conference on Electrical and Computer Engineering (ICECE), 2016

Design issue analysis for InAs nanowire tunnel FETs

Proceedings of Spie the International Society For Optical Engineering, Sep 1, 2011

InAs nanowire-tunnel eld eect transistors (NW-TFETs) are being considered for future, beyond-Si e... more InAs nanowire-tunnel eld eect transistors (NW-TFETs) are being considered for future, beyond-Si electronics. They oer the possibility of beating the ideal thermal limit to the inverse subthreshold slope of 60 mV/dec and thus promise reduced power operation. However, whether the tunneling can provide sucient on-current for high-speed operation is an open question. In this work, for a p-i-n device, we investigate the source doping level necessary to achieve a target on-current (1 A) while maintaining a high ION=IOFF ratio (1106) for a range of NW diameters (2 -8 nm). With a xed drain bias voltage and a maximum gate overdrive, we compare the performance in terms of the inverse subthreshold slope (SS) and ION=IOFF ratio as a function of NW- diameter and source doping. As expected, increasing the source doping level increases the current as a result of the reduced screening length and increased electric eld at source which narrows the tunnel barrier. However, since the degeneracy is also increasing, it moves the eective energy window for tunneling away from the barrier where it is the narrowest. This, in turn, tends to decrease the current for a given voltage which, along with the consideration of inverse SS and ION=IOFF ratio leads to an optimum choice of source doping.

Molecular Resonant Tunneling Diode

Accurate modeling of direct tunneling hole current in p-metal-oxide-semiconductor devices

Applied Physics Letters, Jul 21, 2002

We critically examine a number of important issues related to modeling hole direct tunneling in p... more We critically examine a number of important issues related to modeling hole direct tunneling in p-metal-oxide-semiconductor devices with p ϩ-polycrystalline silicon gate. By comparing our simulated direct tunneling hole current with experimental data, several observations are made. It is found that inelastic trap scattering of holes in the gate-oxide region increases the hole tunneling current significantly at lower gate voltages in devices with gate-oxide thickness greater than 2 nm. Appropriate spatial and gate bias dependence of the scattering rate needs to be considered for accurately predicting experimental current over the entire gate voltage range. Effective mass of holes in gate-oxide region is not a constant, rather, it increases with increasing gate bias voltage and we propose a relationship between the two. Bulk values for hole effective masses in silicon may be used to accurately model the hole tunneling current even in the presence of hole quantization. The contribution of split-off holes to direct tunneling current is not negligible in strong inversion.

Performance Metrics of a 5 nm, Planar, Top Gate, Carbon Nanotube on Insulator (COI) Transistor

Ieee Transactions on Nanotechnology, Mar 1, 2007

The performance of a planar, 5 nm top gate, carbon nanotube on insulator (COI) field-effect trans... more The performance of a planar, 5 nm top gate, carbon nanotube on insulator (COI) field-effect transistor (COIFET) with source/drain underlaps is analyzed. The performance metrics of switching delay time and cutoff frequency are calculated. A 2 nm thick, relatively low-K, SiO 2 gate dielectric combined with a source/drain underlap geometry and insulating substrate minimizes the parasitic gate to source CGS and gate to drain CGD capacitances and results in a 23 fs switching delay time. The simplicity of the device design is required to satisfy the constraints of a self-assembly process. The device analyzed is also a scaled version of recently demonstrated CNTFETs on sapphire

Electron transport through molecular-carbon nanotube interfaces

Aps Meeting Abstracts, Mar 1, 2007

Investigations have focused on electron transport through metal-molecule systems. Less effort has... more

Near Ideal Operation of Nanometer Gate Length Carbon Nanotube FETs

Discrete random distribution of source dopants in nanowire tunnel transistors (TFETs)

InAs and InSb nanowire (NW) tunnel field effect transistors (TFETs) require highly degenerate sou... more InAs and InSb nanowire (NW) tunnel field effect transistors (TFETs) require highly degenerate source doping to support the high electric fields in the tunnel region. For a target on-current of 1$\ mu A $, the doping requirement may be as high as $1.5\ times10^{20}~\ mathrm {cm^{-3}} $ in a NW with diameter as low as 4 nm. The small size of these devices demand that the dopants near tunneling region be treated discretely. Therefore, the effects resulting from the random distribution of dopant atoms in the source of a TFET are studied ...

$Research paper thumbnail of Monolayer $ hbox{MoS}_{2}$ Transistors Beyond the Technology Road Map$

Monolayer $ hbox{MoS}_{2}$ Transistors Beyond the Technology Road Map

Ieee Transactions on Electron Devices, Dec 1, 2012

A Ge Ultrathin-Body n-Channel Tunnel FET: Effects of Surface Orientation

IEEE Transactions on Electron Devices, 2014

The effects of doping, gate length, and gate dielectric on inverse subthreshold slope and on/off current ratio of a top gate silicon nanowire transistor

2008 International Conference on Electrical and Computer Engineering, 2008

The effects of gate length Lg, gate dielectric constant isinox, gate oxide thickness tox, and sou... more The effects of gate length Lg, gate dielectric constant isinox, gate oxide thickness tox, and sourc/drain doping concentration on inverse subthreshold slope and on/off current ratio of a top gate silicon nanowire on insulator device are studied using three dimensional quantum simulation. The variation of inverse subthreshold slope and on/off current ratio are very sensitive to gate length, gate dielectric

Effects of phonon scattering on the performance of silicon nanowire transistors

International Conference on Electrical & Computer Engineering (ICECE 2010), 2010

... York, 2006. [14] Redwan N. Sajjad, K. Alam, and Q. Khosru, Parametrization of silicon nanowi... more

<title>Design issue analysis for InAs nanowire tunnel FETs</title>

Nanoengineering: Fabrication, Properties, Optics, and Devices VIII, 2011

InAs nanowire-tunnel eld eect transistors (NW-TFETs) are being considered for future, beyond-Si e... more InAs nanowire-tunnel eld eect transistors (NW-TFETs) are being considered for future, beyond-Si electronics. They oer the possibility of beating the ideal thermal limit to the inverse subthreshold slope of 60 mV/dec and thus promise reduced power operation. However, whether the tunneling can provide sucient on-current for high-speed operation is an open question. In this work, for a p-i-n device, we investigate the source doping level necessary to achieve a target on-current (1 A) while maintaining a high ION=IOFF ratio (1106) for a range of NW diameters (2 -8 nm). With a xed drain bias voltage and a maximum gate overdrive, we compare the performance in terms of the inverse subthreshold slope (SS) and ION=IOFF ratio as a function of NW- diameter and source doping. As expected, increasing the source doping level increases the current as a result of the reduced screening length and increased electric eld at source which narrows the tunnel barrier. However, since the degeneracy is also increasing, it moves the eective energy window for tunneling away from the barrier where it is the narrowest. This, in turn, tends to decrease the current for a given voltage which, along with the consideration of inverse SS and ION=IOFF ratio leads to an optimum choice of source doping.

Effects of source-drain underlaps on the performance of silicon nanowire on insulator transistors

Nano-Micro Letters, 2010

The effects of source-drain underlaps on the performance of a top gate silicon nanowire on insula... more The effects of source-drain underlaps on the performance of a top gate silicon nanowire on insulator transistor are studied using a three dimensional (3D) self-consistent Poisson-Schrodinger quantum simulation. Voltage-controlled tunnel barrier is the device transport physics. The off current, the on/off current ratio, and the inverse subthreshold slope are improved while the on current is degraded with underlap. The physics behind this behavior is the modulation of a tunnel barrier with underlap. The underlap primarily affects the tunneling component of drain current. About 50% contribution to the gate capacitance comes from the fringing electric fields emanating from the gate metal to the source and drain. The gate capacitance reduces with underlap, which should reduce the intrinsic switching delay and increase the intrinsic cutoff frequency. However, both the on current and the transconductance reduce with underlap, and the consequence is the increase of delay and the reduction of cutoff frequency.

Uniform Benchmarking of Low-Voltage van der Waals FETs

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2016

and black phosphorous field-effect transistors (FETs) operating in the low-voltage (LV) regime (0... more and black phosphorous field-effect transistors (FETs) operating in the low-voltage (LV) regime (0.3 V) with geometries from the 2019 and 2028 nodes of the 2013 International Technology Roadmap for Semiconductors are benchmarked along with an ultrathin-body Si FET. Current can increase or decrease with scaling, and the trend is strongly correlated with the effective mass. For LV operation at the 2028 node, an effective mass of ∼0.4 m 0 , corresponding to that of WSe 2 , gives the maximum drive current. The short 6-nm gate length combined with LV operation is forgiving in its requirements for material quality and contact resistances. In this LV regime, device and circuit performances are competitive using currently measured values for mobilities and contact resistances for the monolayer 2-D materials. INDEX TERMS 2-D materials, benchmarking, black phosphorous (BP), field-effect transistor (FET), transition metal dichalcogenide (TMD), ultrathin body (UTB) Si, van der Waals (vdW) materials. I. INTRODUCTION

Electronic properties of carbon nanotubes calculated from density functional theory and the empirical π-bond model

Journal of Computational Electronics, 2007

The validity of the DFT models implemented by FIREBALL for CNT electronic device modeling is asse... more The validity of the DFT models implemented by FIREBALL for CNT electronic device modeling is assessed. The effective masses, band gaps, and transmission coefficients of semi-conducting, zigzag, (n, 0) carbon nanotubes (CNTs) resulting from the ab-initio tight-binding density functional theory (DFT) code FIREBALL and the empirical, nearest-neighbor π-bond model are compared for all semiconducting n values 5 ≤ n ≤ 35. The DFT values for the effective masses differ from the π-bond values by ±9% over the range of n values, 17 ≤ n ≤ 29, most important for electronic device applications. Over the range 13 ≤ n ≤ 35, the DFT bandgaps are less than the empirical bandgaps by 20-180 meV depending on the functional and the n value. The π-bond model gives results that differ significantly from the DFT results when the CNT diameter goes below 1 nm due to the large curvature of the CNT. The π-bond model quickly becomes inaccurate away from the bandedges for a (10, 0) CNT, and it is completely inaccurate for n ≤ 8.

Material Selection for Minimizing Direct Tunneling in Nanowire Transistors

IEEE Transactions on Electron Devices, 2012

When the physical gate length is reduced to 5 nm, direct channel tunneling dominates the leakage ... more When the physical gate length is reduced to 5 nm, direct channel tunneling dominates the leakage current for both field effect transistors (FETs) and tunnel field effect transistors (TFETs). Therefore, a survey of materials in a nanowire (NW) geometry is performed to determine their ability to suppress the direct tunnel current through a 5 nm barrier. The materials investigated are InAs, InSb, InP, GaAs, GaN, Si, Ge and carbon nanotubes (CNTs). The tunneling effective mass gives the best indication of the relative size of the tunnel currents when comparing two different materials of any type. The indirect gap materials, Si and Ge, give the largest tunneling masses in the conduction band, and they give the smallest conduction band tunnel currents within the range of diameters considered. Si gives the lowest overall tunnel current for both the conduction and valence band and, therefore, it is the optimum choice for suppressing tunnel current at the 5 nm scale. A semianalytic approach to calculating tunnel current is demonstrated which requires considerably less computation than a full-band numerical calculation.

Electronic Properties of Silicon Nanowires

IEEE Transactions on Electron Devices, 2005

The electronic structure and transmission coefficients of Si nanowires are calculated in a 3 5 mo... more The electronic structure and transmission coefficients of Si nanowires are calculated in a 3 5 model. The effect of wire thickness on the bandgap, conduction valley splitting, hole band splitting, effective masses, and transmission is demonstrated. Results from the 3 5 model are compared to those from a single-band effective mass model to assess the validity of the singleband effective mass model in narrow Si nanowires. The one-dimensional Brillouin zone of a Si nanowire is direct gap. The conduction band minimum can split into a quartet of energies although often two of the energies are degenerate. Conduction band valley splitting reduces the averaged mobility mass along the axis of the wire, but quantum confinement increases the transverse mass of the conduction band edge. Quantum confinement results in a large increase in the hole masses of the two highest valence bands. A single-band model performs reasonably well at calculating the effective band edges for wires as small as 1.54-nm square. A wiresubstrate interface can be viewed as a heterojunction with band offsets resulting in reflection in the transmission. Index Terms-Nanowires (NWs), silicon nanowires (SiNWs). I. INTRODUCTION S EMICONDUCTOR nanowires (NWs) have been widely studied as nanoscale building blocks for nanoelectronics, since they can function both as devices and wires that access the devices. NWs are synthesized from a range of different materials [1], such as CdS and ZnS [2], GaN [3], p-GaN [4], Si, Ge

Role of Phonon Scattering on the Transport and Performance of an N-Channel Monolayer Black Phosphorus Transistor

Journal of Electronics and Electrical Engineering, Jan 7, 2024

We investigate the influence of phonon scattering on the transport properties and performance met... more We investigate the influence of phonon scattering on the transport properties and performance metrics of a monolayer n-channel black phosphorus transistor within a four-band tight binding Hamiltonian, employing a recursive Green's function algorithm and Buttiker probe scattering model. Our analysis reveals that electronphonon scattering significantly degrades the on-state current, while its effects in the subthreshold region are found to be negligible. Further examination identifies optical phonons as the primary contributors to the degradation of on-state current, with acoustic phonons playing a less prominent role. The ballisticity of the device declines from 42% to 24% when transitioning from solely acoustic phonon scattering to the combined influence of acoustic and optical phonons. Expanding the placement of Buttiker probes from beneath the gate region to cover the entire path from source to drain results in a further 48% reduction in on-state current. The on-state current exhibits a parabolic relationship with the inverse Kelvin temperature. To quantify the effects of phonon scattering on device performance, we assess the key parameters, transconductance and unity current gain frequency. Phonon scattering is observed to severely impact both the parameters. The on-state transconductance declines from its ballistic value of 24.9 mS/µm to 3.99 mS/µm when both acoustic and optical phonons are concurrently active. Similarly, the unity current gain frequency decreases from 1.18 to 0.2 THz due to phonon scattering. Additionally, our analysis reveals that approximately 7-9% of the total power dissipated within the device is attributed to phonon scattering effects, while the remainder is released through thermalization in the device's contacts. Phonon scattering is shown to induce both lattice cooling and heating, depending on the presence or absence of potential barriers. When a potential barrier exists in the channel, electrons injected from the source experience lattice cooling before the barrier region and lattice heating after crossing the barrier. Including the source and drain contact resistances in our model unveils that achieving a contact resistance value of approximately 100 Ω-µm is crucial for the effective functioning of black phosphorus devices.

Orientation Engineering for Improved Performance of a Ge-Si Heterojunction Nanowire TFET

IEEE Transactions on Electron Devices

Simulation study on the effects of changing band gap on solar cell parameters

2016 9th International Conference on Electrical and Computer Engineering (ICECE), 2016

Design issue analysis for InAs nanowire tunnel FETs

Proceedings of Spie the International Society For Optical Engineering, Sep 1, 2011

InAs nanowire-tunnel eld eect transistors (NW-TFETs) are being considered for future, beyond-Si e... more InAs nanowire-tunnel eld eect transistors (NW-TFETs) are being considered for future, beyond-Si electronics. They oer the possibility of beating the ideal thermal limit to the inverse subthreshold slope of 60 mV/dec and thus promise reduced power operation. However, whether the tunneling can provide sucient on-current for high-speed operation is an open question. In this work, for a p-i-n device, we investigate the source doping level necessary to achieve a target on-current (1 A) while maintaining a high ION=IOFF ratio (1106) for a range of NW diameters (2 -8 nm). With a xed drain bias voltage and a maximum gate overdrive, we compare the performance in terms of the inverse subthreshold slope (SS) and ION=IOFF ratio as a function of NW- diameter and source doping. As expected, increasing the source doping level increases the current as a result of the reduced screening length and increased electric eld at source which narrows the tunnel barrier. However, since the degeneracy is also increasing, it moves the eective energy window for tunneling away from the barrier where it is the narrowest. This, in turn, tends to decrease the current for a given voltage which, along with the consideration of inverse SS and ION=IOFF ratio leads to an optimum choice of source doping.

Molecular Resonant Tunneling Diode

Accurate modeling of direct tunneling hole current in p-metal-oxide-semiconductor devices

Applied Physics Letters, Jul 21, 2002

We critically examine a number of important issues related to modeling hole direct tunneling in p... more We critically examine a number of important issues related to modeling hole direct tunneling in p-metal-oxide-semiconductor devices with p ϩ-polycrystalline silicon gate. By comparing our simulated direct tunneling hole current with experimental data, several observations are made. It is found that inelastic trap scattering of holes in the gate-oxide region increases the hole tunneling current significantly at lower gate voltages in devices with gate-oxide thickness greater than 2 nm. Appropriate spatial and gate bias dependence of the scattering rate needs to be considered for accurately predicting experimental current over the entire gate voltage range. Effective mass of holes in gate-oxide region is not a constant, rather, it increases with increasing gate bias voltage and we propose a relationship between the two. Bulk values for hole effective masses in silicon may be used to accurately model the hole tunneling current even in the presence of hole quantization. The contribution of split-off holes to direct tunneling current is not negligible in strong inversion.

Performance Metrics of a 5 nm, Planar, Top Gate, Carbon Nanotube on Insulator (COI) Transistor

Ieee Transactions on Nanotechnology, Mar 1, 2007

The performance of a planar, 5 nm top gate, carbon nanotube on insulator (COI) field-effect trans... more The performance of a planar, 5 nm top gate, carbon nanotube on insulator (COI) field-effect transistor (COIFET) with source/drain underlaps is analyzed. The performance metrics of switching delay time and cutoff frequency are calculated. A 2 nm thick, relatively low-K, SiO 2 gate dielectric combined with a source/drain underlap geometry and insulating substrate minimizes the parasitic gate to source CGS and gate to drain CGD capacitances and results in a 23 fs switching delay time. The simplicity of the device design is required to satisfy the constraints of a self-assembly process. The device analyzed is also a scaled version of recently demonstrated CNTFETs on sapphire

Electron transport through molecular-carbon nanotube interfaces

Aps Meeting Abstracts, Mar 1, 2007

Investigations have focused on electron transport through metal-molecule systems. Less effort has... more

Near Ideal Operation of Nanometer Gate Length Carbon Nanotube FETs

Discrete random distribution of source dopants in nanowire tunnel transistors (TFETs)

InAs and InSb nanowire (NW) tunnel field effect transistors (TFETs) require highly degenerate sou... more InAs and InSb nanowire (NW) tunnel field effect transistors (TFETs) require highly degenerate source doping to support the high electric fields in the tunnel region. For a target on-current of 1$\ mu A $, the doping requirement may be as high as $1.5\ times10^{20}~\ mathrm {cm^{-3}} $ in a NW with diameter as low as 4 nm. The small size of these devices demand that the dopants near tunneling region be treated discretely. Therefore, the effects resulting from the random distribution of dopant atoms in the source of a TFET are studied ...

$Research paper thumbnail of Monolayer $ hbox{MoS}_{2}$ Transistors Beyond the Technology Road Map$

Monolayer $ hbox{MoS}_{2}$ Transistors Beyond the Technology Road Map

Ieee Transactions on Electron Devices, Dec 1, 2012

A Ge Ultrathin-Body n-Channel Tunnel FET: Effects of Surface Orientation

IEEE Transactions on Electron Devices, 2014

The effects of doping, gate length, and gate dielectric on inverse subthreshold slope and on/off current ratio of a top gate silicon nanowire transistor

2008 International Conference on Electrical and Computer Engineering, 2008

The effects of gate length Lg, gate dielectric constant isinox, gate oxide thickness tox, and sou... more The effects of gate length Lg, gate dielectric constant isinox, gate oxide thickness tox, and sourc/drain doping concentration on inverse subthreshold slope and on/off current ratio of a top gate silicon nanowire on insulator device are studied using three dimensional quantum simulation. The variation of inverse subthreshold slope and on/off current ratio are very sensitive to gate length, gate dielectric

Effects of phonon scattering on the performance of silicon nanowire transistors

International Conference on Electrical & Computer Engineering (ICECE 2010), 2010

... York, 2006. [14] Redwan N. Sajjad, K. Alam, and Q. Khosru, Parametrization of silicon nanowi... more

<title>Design issue analysis for InAs nanowire tunnel FETs</title>

Nanoengineering: Fabrication, Properties, Optics, and Devices VIII, 2011

InAs nanowire-tunnel eld eect transistors (NW-TFETs) are being considered for future, beyond-Si e... more InAs nanowire-tunnel eld eect transistors (NW-TFETs) are being considered for future, beyond-Si electronics. They oer the possibility of beating the ideal thermal limit to the inverse subthreshold slope of 60 mV/dec and thus promise reduced power operation. However, whether the tunneling can provide sucient on-current for high-speed operation is an open question. In this work, for a p-i-n device, we investigate the source doping level necessary to achieve a target on-current (1 A) while maintaining a high ION=IOFF ratio (1106) for a range of NW diameters (2 -8 nm). With a xed drain bias voltage and a maximum gate overdrive, we compare the performance in terms of the inverse subthreshold slope (SS) and ION=IOFF ratio as a function of NW- diameter and source doping. As expected, increasing the source doping level increases the current as a result of the reduced screening length and increased electric eld at source which narrows the tunnel barrier. However, since the degeneracy is also increasing, it moves the eective energy window for tunneling away from the barrier where it is the narrowest. This, in turn, tends to decrease the current for a given voltage which, along with the consideration of inverse SS and ION=IOFF ratio leads to an optimum choice of source doping.

Effects of source-drain underlaps on the performance of silicon nanowire on insulator transistors

Nano-Micro Letters, 2010

The effects of source-drain underlaps on the performance of a top gate silicon nanowire on insula... more The effects of source-drain underlaps on the performance of a top gate silicon nanowire on insulator transistor are studied using a three dimensional (3D) self-consistent Poisson-Schrodinger quantum simulation. Voltage-controlled tunnel barrier is the device transport physics. The off current, the on/off current ratio, and the inverse subthreshold slope are improved while the on current is degraded with underlap. The physics behind this behavior is the modulation of a tunnel barrier with underlap. The underlap primarily affects the tunneling component of drain current. About 50% contribution to the gate capacitance comes from the fringing electric fields emanating from the gate metal to the source and drain. The gate capacitance reduces with underlap, which should reduce the intrinsic switching delay and increase the intrinsic cutoff frequency. However, both the on current and the transconductance reduce with underlap, and the consequence is the increase of delay and the reduction of cutoff frequency.