Analysis of Charged Device Model (CDM) current waveforms on multiple package options / styles sho... more Analysis of Charged Device Model (CDM) current waveforms on multiple package options / styles shows significant variation with package size / pin count, package physical characteristics and pin location. Die-level CDM analysis shows much higher CDM peak current compared to their packaged counterparts. Thus, package-level CDM results cannot be substituted for die-level CDM results.
Physical mechanisms that define the triggering conditions of lateral P1N1-P2N2 structures for ESD... more Physical mechanisms that define the triggering conditions of lateral P1N1-P2N2 structures for ESD (electrostatic discharge) protection are identified using 2D numerical simulations. The TCAD (technology computer aided design) allows for accurate prediction of the forward and reverse blocking voltages, necessary for custom ESD protection design. Symmetrical and asymmetrical dual-polarity S-type I-V characteristics are achieved for bipolar input/output ESD protection design. This is realized by using 1) tailored forward-and reverse- blocking junction configurations embedded in coupled (P1N1-P2N2)//(N 2P3-N3P1) structures, and 2) optimized adjustment of the structures' doping implantations and isolation regions
Gate oxide breakdown is analyzed under very fast transmission line pulsed (VFTLP) stress, using d... more Gate oxide breakdown is analyzed under very fast transmission line pulsed (VFTLP) stress, using different pulserise times and -widths. The switching of oxide behavior pre-and post-breakdown occurs in tenths of a nanosecond and it shows reproducible voltage and current characteristics. The total stress and time-dependent-dielectric-breakdown (TDDB) during pulsed stress-method are evaluated using the following two procedures: 1) by adding up the total pulsed stress time, and 2) by extrapolation of the pulsed stress time to a constant voltage stress (CVS)-type measurements. It is shown that the latter method allows for a better comparison of identical oxides TDDB under various stress conditions. A methodology to characterize gate oxide breakdown using a single pulse is finally discussed. This is important to assess the gate-oxide failure condition during a charged device model (CDM)-type electrostatic discharge (ESD).
IEEE Transactions on Circuits and Systems I-regular Papers, 2002
We report on the use of a simple design optimization criterion for obtaining maximum static trans... more We report on the use of a simple design optimization criterion for obtaining maximum static transfer function linearity. It is based on an analytic function that corresponds to the integral nonlinearity of the circuit. The criterion may be useful, either as an analytic tool to gain insight into the circuit's behavior, or as an efficient computational alternative to calculating total harmonic distortion (THD). It is utilized here to optimize the design parameters of a recently proposed bipolar transconductor capable of high linearity, which is composed of two parallel-connected nonlinear blocks: a hyperbolic tangent-type transconductor and hyperbolic sine-type transconductor. Examination of this tanh sinh-type transconductor concept, using the analytic version of the present criterion, indicates that this new circuit configuration is theoretically capable of achieving values of THD lower than possible with conventional bipolar hyperbolic tangent-type transconductors. A particular design example is presented to demonstrate, through simulations, the performance of the new transconductor, and in order to ascertain the ability of the proposed design optimization criterion for obtaining maximum static transfer function linearity. In this particular example, THD values of less than 0.3% are obtained with a 100-S transconductance up to a maximum input voltage swing of 50-mV peak.
A comprehensive methodology for synthesizing robust ESD performance in highly sensitive high volt... more A comprehensive methodology for synthesizing robust ESD performance in highly sensitive high voltage NLDMOS functional blocks is introduced. Optimizing high voltage output stage design for robust device- and system-level (IEC 61000-4-2)/HMM is assessed under 1-, 2-, 5-, 10-, 100-ns wide time frames of typical electrostatic discharge (ESD) stress models.
Robust and novel devices called High Holding, Low-Voltage-Trigger Silicon Controlled Rectifiers (... more Robust and novel devices called High Holding, Low-Voltage-Trigger Silicon Controlled Rectifiers (HH-LVTSCRs) for Electrostatic Discharge (ESD) protection of integrated circuits (ICs) are designed, fabricated and characterized. The S-type current-voltage (I-V) characteristics of the HH-LVTSCRs are adjustable to different operating conditions by changing the device dimensions and terminal interconnections. Experimental results demonstrate that HH-LVTSCRs with a multiple-finger layout render high levels of ESD protection per unit area, applicable in the design of ICs with stringent ESD protection requirements of over 15 kV IEC.
ABSTRACT Passing voltage levels measured from the human metal model tester are correlated with th... more ABSTRACT Passing voltage levels measured from the human metal model tester are correlated with the failure current levels ob- tained from the transmission line pulsing (TLP) tester for electro- static discharge protection devices fabricated in 0.18- and 0.35-μm MOS technologies. Various relevant TLP parameters, including the holding voltage and ON-state resistance, are accounted for in the improved correlation formula developed in this study. Index Terms—Electrostatic discharge (ESD), human body model (HBM), human metal model (HMM), transmission line pulsing (TLP).
Page 1. Transient Safe Operating Area (TSOA) Definition for ESD Applications Juin J. Liou1, Slavi... more Page 1. Transient Safe Operating Area (TSOA) Definition for ESD Applications Juin J. Liou1, Slavica Malobabic1, David F. Ellis1, Javier A. Salcedo2, Jean-Jacques Hajjar2, Yuanzhong Zhou2 (1) School of Electrical Engineering ...
Realization of on-chip electrostatic discharge (ESD) protection requires extensive technical expe... more Realization of on-chip electrostatic discharge (ESD) protection requires extensive technical experience and know-how. A technology computer-aided design (TCAD) methodology aimed to assist in the design and implementation of robust ESD devices is developed and presented. The methodology provides a systematic and practical means for the evaluation and optimization of ESD devices in a simulation environment. Advanced siliconcontrolled-rectifier devices are considered to illustrate the approach, and experimental data measured from these devices are also included in support of the TCAD development.
Transient safe operating area (TSOA) of n-type and p-type laterally diffused metal-oxide-semicond... more Transient safe operating area (TSOA) of n-type and p-type laterally diffused metal-oxide-semiconductor (LDMOS) subject to transient stresses is presented for electrostatic discharge applications. LDMOS devices connected in the gate-grounded and gate-biased configurations are stressed with 1-, 2-, 5-, 10-, and 100-ns duration transmission line pulses, and a methodology to develop an effective and accurate TSOA based on these measurements is discussed. Two-dimensional technology computer-aided design simulations are also used to discuss critical physical mechanisms governing the current conduction during the transients and the condition that finally leads to device failure beyond the TSOA.
Silicon-controlled rectifiers (SCRs) are frequently used to build on-chip electrostatic discharge... more Silicon-controlled rectifiers (SCRs) are frequently used to build on-chip electrostatic discharge (ESD) protection structures, but SCRs are not sufficiently robust to meet a wide range of ESD requirements in various integrated circuits. In this paper, a novel and robust SCR-based device called the HHLVTSCR is presented. It is demonstrated that HHLVTSCR can exhibit various characteristics useful for ESD solutions. An example is also included to illustrate how HHVLTSCRs can be used to provide ESD protection to a practical application.
A Transient safe operating area (TSOA) definition for ESD applications is introduced. Within this... more A Transient safe operating area (TSOA) definition for ESD applications is introduced. Within this concept framework, ESD protection device topologies developed in a mixed-signal submicron high-voltage CMOS technology are studied to identify turn-on voltage and the resulting voltage overshoot conditions during fast ESD transients. A state-of-the-art numerical simulation environment used to study and optimize the fast transient response of ESD protection devices is discussed and simulation results are benchmarked versus very fast transmission line pulsing measurements. Constraints for triggering control of clamp devices are also investigated via simulations and pulse measurements.
Robust and novel devices called high-holding low-voltage trigger silicon controlled rectifiers (H... more Robust and novel devices called high-holding low-voltage trigger silicon controlled rectifiers (HH-LVTSCRs) for electrostatic discharge (ESD) protection of integrated circuits (ICs) are designed, fabricated and characterized. The S-type current-voltage (I-V) characteristics of the HH-LVTSCRs are adjustable to different operating conditions by changing the device dimensions and terminal interconnections. Comparison between complementary n- and p-type HH-LVTSCR devices shows that n-type devices perform better than p-type devices when a low holding voltage (VH) is allowed during the on-state of the ESD protection structure, but when a relatively high holding voltage is required, p-type devices perform better. Results further demonstrate that HH-LVTSCRs with a multiple-finger layout render high levels of ESD protection per unit area, applicable in the design of ICs with stringent ESD protection requirements of over 15 kV IEC.
Realization of on-chip electrostatic discharge (ESD) protection requires extensive technical expe... more Realization of on-chip electrostatic discharge (ESD) protection requires extensive technical experience and know-how. A technology computer-aided design (TCAD) methodology aimed to assist in the design and implementation of robust ESD devices is developed and presented. The methodology provides a systematic and practical means for the evaluation and optimization of ESD devices in a simulation environment. Advanced siliconcontrolled-rectifier devices are considered to illustrate the approach, and experimental data measured from these devices are also included in support of the TCAD development.
An on-chip electrostatic discharge (ESD) protection scheme is demonstrated for an emerging techno... more An on-chip electrostatic discharge (ESD) protection scheme is demonstrated for an emerging technology of microelectromechanical systems (MEMS)-based embedded sensor (ES) system-on-a-chip (SoC). The ESD protection scheme is implemented using ground-referenced multifinger thyristor-type devices optimized for (1) the input/output (I/O) protection, (2) the power supply clamp, and (3) the internal sensors’ electrodes during the micromachining process. The ESD structure developed demonstrates a leakage current below 10−10 A, high on-state conductance, and high level of human body model (HBM) immunity.
A novel and compact device with adjustable forward and reverse conductions and symmetrical/asymme... more A novel and compact device with adjustable forward and reverse conductions and symmetrical/asymmetrical I-V characteristics for ESD (electrostatic discharge) applications is presented. The device allows for the dual-polarity conduction with the proper selection of blocking junction configurations. This design enables high-level ESD protections for various mixed-signal integrated circuits operating under a wide range of symmetrical and asymmetrical bias conditions.
A new on-chip Electrostatic Discharge (ESD) protection scheme is demonstrated for MicroElectroMec... more A new on-chip Electrostatic Discharge (ESD) protection scheme is demonstrated for MicroElectroMechanical Systems (MEMS)based Embedded Sensor (ES) System-on-a-Chip (SoC). The ESD protection scheme includes ground-referenced protection cells implemented with novel multifinger thyristor-type devices for 1) the Input/Output (I/O) protection, 2) the power supply clamp, and 3) the protection at the internal sensors' electrodes. The I-V characteristics of the thyristor-type protection cells are adjusted for providing an optimum ESD protection per unit area. Transmission Line Pulsing (TLP) measurements and ESD testing show superb high conductance on-state I-V characteristics with no latch-up problem when thyristor-type devices are subjected to an ESD event, while very low leakage current is obtained at the SoC operating voltage.
A reliable dielectric breakdown model under transient stresses via an extension of the power law ... more A reliable dielectric breakdown model under transient stresses via an extension of the power law is demonstrated. The model, which is based on the percolation model and the assumption of no significant detrapping, is successfully used in ramped voltage stress breakdown analysis. A demonstration of the model's validity consists of applying repetitive time-variant voltage waveforms-pulses, sine waves, ramps, and noise-until breakdown and, consequently, comparing prediction to reality. The breakdown distribution is initially derived from DC measurements, with the model predicting both the center and the shape of the distribution. Index Terms-Charged device model (CDM), gate oxide breakdown (GOB), power law (PL), time-dependent dielectric breakdown (TDDB), very fast transmission line pulse (VFTLP).
The snapback and postsnapback saturation characteristics in a pseudomorphic high-electron mobilit... more The snapback and postsnapback saturation characteristics in a pseudomorphic high-electron mobility transistor (PHEMT) subject to electrostatic discharge (ESD) transient overstress are studied. This is undertaken, for the first time, via transmission line pulsing (TLP)-like 2-D device simulations and benchmarked against TLP measurements. Physical mechanisms underlying the postsnapback behavior and ESD-induced failure are identified and discussed by analyzing TLP-like simulation results rather than extrapolating dc-like numerical simulation data.
Analysis of Charged Device Model (CDM) current waveforms on multiple package options / styles sho... more Analysis of Charged Device Model (CDM) current waveforms on multiple package options / styles shows significant variation with package size / pin count, package physical characteristics and pin location. Die-level CDM analysis shows much higher CDM peak current compared to their packaged counterparts. Thus, package-level CDM results cannot be substituted for die-level CDM results.
Physical mechanisms that define the triggering conditions of lateral P1N1-P2N2 structures for ESD... more Physical mechanisms that define the triggering conditions of lateral P1N1-P2N2 structures for ESD (electrostatic discharge) protection are identified using 2D numerical simulations. The TCAD (technology computer aided design) allows for accurate prediction of the forward and reverse blocking voltages, necessary for custom ESD protection design. Symmetrical and asymmetrical dual-polarity S-type I-V characteristics are achieved for bipolar input/output ESD protection design. This is realized by using 1) tailored forward-and reverse- blocking junction configurations embedded in coupled (P1N1-P2N2)//(N 2P3-N3P1) structures, and 2) optimized adjustment of the structures' doping implantations and isolation regions
Gate oxide breakdown is analyzed under very fast transmission line pulsed (VFTLP) stress, using d... more Gate oxide breakdown is analyzed under very fast transmission line pulsed (VFTLP) stress, using different pulserise times and -widths. The switching of oxide behavior pre-and post-breakdown occurs in tenths of a nanosecond and it shows reproducible voltage and current characteristics. The total stress and time-dependent-dielectric-breakdown (TDDB) during pulsed stress-method are evaluated using the following two procedures: 1) by adding up the total pulsed stress time, and 2) by extrapolation of the pulsed stress time to a constant voltage stress (CVS)-type measurements. It is shown that the latter method allows for a better comparison of identical oxides TDDB under various stress conditions. A methodology to characterize gate oxide breakdown using a single pulse is finally discussed. This is important to assess the gate-oxide failure condition during a charged device model (CDM)-type electrostatic discharge (ESD).
IEEE Transactions on Circuits and Systems I-regular Papers, 2002
We report on the use of a simple design optimization criterion for obtaining maximum static trans... more We report on the use of a simple design optimization criterion for obtaining maximum static transfer function linearity. It is based on an analytic function that corresponds to the integral nonlinearity of the circuit. The criterion may be useful, either as an analytic tool to gain insight into the circuit's behavior, or as an efficient computational alternative to calculating total harmonic distortion (THD). It is utilized here to optimize the design parameters of a recently proposed bipolar transconductor capable of high linearity, which is composed of two parallel-connected nonlinear blocks: a hyperbolic tangent-type transconductor and hyperbolic sine-type transconductor. Examination of this tanh sinh-type transconductor concept, using the analytic version of the present criterion, indicates that this new circuit configuration is theoretically capable of achieving values of THD lower than possible with conventional bipolar hyperbolic tangent-type transconductors. A particular design example is presented to demonstrate, through simulations, the performance of the new transconductor, and in order to ascertain the ability of the proposed design optimization criterion for obtaining maximum static transfer function linearity. In this particular example, THD values of less than 0.3% are obtained with a 100-S transconductance up to a maximum input voltage swing of 50-mV peak.
A comprehensive methodology for synthesizing robust ESD performance in highly sensitive high volt... more A comprehensive methodology for synthesizing robust ESD performance in highly sensitive high voltage NLDMOS functional blocks is introduced. Optimizing high voltage output stage design for robust device- and system-level (IEC 61000-4-2)/HMM is assessed under 1-, 2-, 5-, 10-, 100-ns wide time frames of typical electrostatic discharge (ESD) stress models.
Robust and novel devices called High Holding, Low-Voltage-Trigger Silicon Controlled Rectifiers (... more Robust and novel devices called High Holding, Low-Voltage-Trigger Silicon Controlled Rectifiers (HH-LVTSCRs) for Electrostatic Discharge (ESD) protection of integrated circuits (ICs) are designed, fabricated and characterized. The S-type current-voltage (I-V) characteristics of the HH-LVTSCRs are adjustable to different operating conditions by changing the device dimensions and terminal interconnections. Experimental results demonstrate that HH-LVTSCRs with a multiple-finger layout render high levels of ESD protection per unit area, applicable in the design of ICs with stringent ESD protection requirements of over 15 kV IEC.
ABSTRACT Passing voltage levels measured from the human metal model tester are correlated with th... more ABSTRACT Passing voltage levels measured from the human metal model tester are correlated with the failure current levels ob- tained from the transmission line pulsing (TLP) tester for electro- static discharge protection devices fabricated in 0.18- and 0.35-μm MOS technologies. Various relevant TLP parameters, including the holding voltage and ON-state resistance, are accounted for in the improved correlation formula developed in this study. Index Terms—Electrostatic discharge (ESD), human body model (HBM), human metal model (HMM), transmission line pulsing (TLP).
Page 1. Transient Safe Operating Area (TSOA) Definition for ESD Applications Juin J. Liou1, Slavi... more Page 1. Transient Safe Operating Area (TSOA) Definition for ESD Applications Juin J. Liou1, Slavica Malobabic1, David F. Ellis1, Javier A. Salcedo2, Jean-Jacques Hajjar2, Yuanzhong Zhou2 (1) School of Electrical Engineering ...
Realization of on-chip electrostatic discharge (ESD) protection requires extensive technical expe... more Realization of on-chip electrostatic discharge (ESD) protection requires extensive technical experience and know-how. A technology computer-aided design (TCAD) methodology aimed to assist in the design and implementation of robust ESD devices is developed and presented. The methodology provides a systematic and practical means for the evaluation and optimization of ESD devices in a simulation environment. Advanced siliconcontrolled-rectifier devices are considered to illustrate the approach, and experimental data measured from these devices are also included in support of the TCAD development.
Transient safe operating area (TSOA) of n-type and p-type laterally diffused metal-oxide-semicond... more Transient safe operating area (TSOA) of n-type and p-type laterally diffused metal-oxide-semiconductor (LDMOS) subject to transient stresses is presented for electrostatic discharge applications. LDMOS devices connected in the gate-grounded and gate-biased configurations are stressed with 1-, 2-, 5-, 10-, and 100-ns duration transmission line pulses, and a methodology to develop an effective and accurate TSOA based on these measurements is discussed. Two-dimensional technology computer-aided design simulations are also used to discuss critical physical mechanisms governing the current conduction during the transients and the condition that finally leads to device failure beyond the TSOA.
Silicon-controlled rectifiers (SCRs) are frequently used to build on-chip electrostatic discharge... more Silicon-controlled rectifiers (SCRs) are frequently used to build on-chip electrostatic discharge (ESD) protection structures, but SCRs are not sufficiently robust to meet a wide range of ESD requirements in various integrated circuits. In this paper, a novel and robust SCR-based device called the HHLVTSCR is presented. It is demonstrated that HHLVTSCR can exhibit various characteristics useful for ESD solutions. An example is also included to illustrate how HHVLTSCRs can be used to provide ESD protection to a practical application.
A Transient safe operating area (TSOA) definition for ESD applications is introduced. Within this... more A Transient safe operating area (TSOA) definition for ESD applications is introduced. Within this concept framework, ESD protection device topologies developed in a mixed-signal submicron high-voltage CMOS technology are studied to identify turn-on voltage and the resulting voltage overshoot conditions during fast ESD transients. A state-of-the-art numerical simulation environment used to study and optimize the fast transient response of ESD protection devices is discussed and simulation results are benchmarked versus very fast transmission line pulsing measurements. Constraints for triggering control of clamp devices are also investigated via simulations and pulse measurements.
Robust and novel devices called high-holding low-voltage trigger silicon controlled rectifiers (H... more Robust and novel devices called high-holding low-voltage trigger silicon controlled rectifiers (HH-LVTSCRs) for electrostatic discharge (ESD) protection of integrated circuits (ICs) are designed, fabricated and characterized. The S-type current-voltage (I-V) characteristics of the HH-LVTSCRs are adjustable to different operating conditions by changing the device dimensions and terminal interconnections. Comparison between complementary n- and p-type HH-LVTSCR devices shows that n-type devices perform better than p-type devices when a low holding voltage (VH) is allowed during the on-state of the ESD protection structure, but when a relatively high holding voltage is required, p-type devices perform better. Results further demonstrate that HH-LVTSCRs with a multiple-finger layout render high levels of ESD protection per unit area, applicable in the design of ICs with stringent ESD protection requirements of over 15 kV IEC.
Realization of on-chip electrostatic discharge (ESD) protection requires extensive technical expe... more Realization of on-chip electrostatic discharge (ESD) protection requires extensive technical experience and know-how. A technology computer-aided design (TCAD) methodology aimed to assist in the design and implementation of robust ESD devices is developed and presented. The methodology provides a systematic and practical means for the evaluation and optimization of ESD devices in a simulation environment. Advanced siliconcontrolled-rectifier devices are considered to illustrate the approach, and experimental data measured from these devices are also included in support of the TCAD development.
An on-chip electrostatic discharge (ESD) protection scheme is demonstrated for an emerging techno... more An on-chip electrostatic discharge (ESD) protection scheme is demonstrated for an emerging technology of microelectromechanical systems (MEMS)-based embedded sensor (ES) system-on-a-chip (SoC). The ESD protection scheme is implemented using ground-referenced multifinger thyristor-type devices optimized for (1) the input/output (I/O) protection, (2) the power supply clamp, and (3) the internal sensors’ electrodes during the micromachining process. The ESD structure developed demonstrates a leakage current below 10−10 A, high on-state conductance, and high level of human body model (HBM) immunity.
A novel and compact device with adjustable forward and reverse conductions and symmetrical/asymme... more A novel and compact device with adjustable forward and reverse conductions and symmetrical/asymmetrical I-V characteristics for ESD (electrostatic discharge) applications is presented. The device allows for the dual-polarity conduction with the proper selection of blocking junction configurations. This design enables high-level ESD protections for various mixed-signal integrated circuits operating under a wide range of symmetrical and asymmetrical bias conditions.
A new on-chip Electrostatic Discharge (ESD) protection scheme is demonstrated for MicroElectroMec... more A new on-chip Electrostatic Discharge (ESD) protection scheme is demonstrated for MicroElectroMechanical Systems (MEMS)based Embedded Sensor (ES) System-on-a-Chip (SoC). The ESD protection scheme includes ground-referenced protection cells implemented with novel multifinger thyristor-type devices for 1) the Input/Output (I/O) protection, 2) the power supply clamp, and 3) the protection at the internal sensors' electrodes. The I-V characteristics of the thyristor-type protection cells are adjusted for providing an optimum ESD protection per unit area. Transmission Line Pulsing (TLP) measurements and ESD testing show superb high conductance on-state I-V characteristics with no latch-up problem when thyristor-type devices are subjected to an ESD event, while very low leakage current is obtained at the SoC operating voltage.
A reliable dielectric breakdown model under transient stresses via an extension of the power law ... more A reliable dielectric breakdown model under transient stresses via an extension of the power law is demonstrated. The model, which is based on the percolation model and the assumption of no significant detrapping, is successfully used in ramped voltage stress breakdown analysis. A demonstration of the model's validity consists of applying repetitive time-variant voltage waveforms-pulses, sine waves, ramps, and noise-until breakdown and, consequently, comparing prediction to reality. The breakdown distribution is initially derived from DC measurements, with the model predicting both the center and the shape of the distribution. Index Terms-Charged device model (CDM), gate oxide breakdown (GOB), power law (PL), time-dependent dielectric breakdown (TDDB), very fast transmission line pulse (VFTLP).
The snapback and postsnapback saturation characteristics in a pseudomorphic high-electron mobilit... more The snapback and postsnapback saturation characteristics in a pseudomorphic high-electron mobility transistor (PHEMT) subject to electrostatic discharge (ESD) transient overstress are studied. This is undertaken, for the first time, via transmission line pulsing (TLP)-like 2-D device simulations and benchmarked against TLP measurements. Physical mechanisms underlying the postsnapback behavior and ESD-induced failure are identified and discussed by analyzing TLP-like simulation results rather than extrapolating dc-like numerical simulation data.
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Papers by Javier Salcedo