The delays of paths in a chip can be monitored to detect via voiding. This work relates the proba... more The delays of paths in a chip can be monitored to detect via voiding. This work relates the probability of failure of individual vias to an increase in delay for monitors of the system using data for 65 nm technology. The sensitivity of the trigger point as a function of the failure distribution parameters and the path length has been investigated. A circuit has been designed to detect the onset of chip failure due to via voiding.
The delays of paths in a chip can be monitored to detect via voiding. This work relates the proba... more The delays of paths in a chip can be monitored to detect via voiding. This work relates the probability of failure of individual vias to an increase in delay for monitors of the system using data for 65 nm technology. The sensitivity of the trigger point as a function of the failure distribution parameters and the path length has been investigated. A circuit has been designed to detect the onset of chip failure due to via voiding.
The delays of paths in a chip can be monitored to detect via voiding. This work relates the proba... more The delays of paths in a chip can be monitored to detect via voiding. This work relates the probability of failure of individual vias to an increase in delay for monitors of the system using data for 65 nm technology. The sensitivity of the trigger point as a function of the failure distribution parameters and the path length has been investigated. A circuit has been designed to detect the onset of chip failure due to via voiding.
The delays of paths in a chip can be monitored to detect via voiding. This work relates the proba... more The delays of paths in a chip can be monitored to detect via voiding. This work relates the probability of failure of individual vias to an increase in delay for monitors of the system using data for 65 nm technology. The sensitivity of the trigger point as a function of the failure distribution parameters and the path length has been investigated. A circuit has been designed to detect the onset of chip failure due to via voiding.
Scaling of device sizes has reduced gate oxide thickness to a few atomic layers, increasing the v... more Scaling of device sizes has reduced gate oxide thickness to a few atomic layers, increasing the vulnerability of the gate oxide to breakdown. During breakdown, devices go through a gradual wearout process after an initial gate leakage increase leading to device failure. It is proposed that if wearout can be monitored, cache arrays with failing cells can be reliably operated after reconfiguration given available memory redundancy. Using experimentally verified gate oxide breakdown models, a detailed analysis of the effect of progressive gate oxide breakdown on the performance of a conventional 6T SRAM cell is presented for 45 nm predictive technology. The DC margin trends (Read, Write and Retention) and access times (Read and Write) during wearout are analyzed, and a cell breakdown point due to degradation in each of these parameters is defined. A combination of these results is used to formulate a practical definition for the hard-breakdown point of a cell. Using an on-chip PVT (process, voltage, and temperature) tolerant monitoring scheme, it has been shown that gradual wearout in SRAM cells, due to gate oxide breakdown, is detectible, and cell failure can be predicted before its occurrence.
Scaling of device sizes has reduced gate oxide thickness to a few atomic layers, increasing the v... more Scaling of device sizes has reduced gate oxide thickness to a few atomic layers, increasing the vulnerability of the gate oxide to breakdown. During breakdown, devices go through a gradual wearout process after an initial gate leakage increase leading to device failure. It is proposed that if wearout can be monitored, cache arrays with failing cells can be reliably operated after reconfiguration given available memory redundancy. Using experimentally verified gate oxide breakdown models, a detailed analysis of the effect of progressive gate oxide breakdown on the performance of a conventional 6T SRAM cell is presented for 45 nm predictive technology. The DC margin trends (Read, Write and Retention) and access times (Read and Write) during wearout are analyzed, and a cell breakdown point due to degradation in each of these parameters is defined. A combination of these results is used to formulate a practical definition for the hard-breakdown point of a cell. Using an on-chip PVT (process, voltage, and temperature) tolerant monitoring scheme, it has been shown that gradual wearout in SRAM cells, due to gate oxide breakdown, is detectible, and cell failure can be predicted before its occurrence.
This project aims to detect the onset of chip failure due to via voiding through monitoring the d... more This project aims to detect the onset of chip failure due to via voiding through monitoring the delays of paths in a chip. The proposed method relates the probability of failure of individual vias to an increase in delay for monitors of the system using data for 65 nm technology. The delay increase, as a function of the failure distribution parameters, the path length, gate type, and process variation, has been investigated. An on-chip, ring oscillator-based wearout monitoring circuit is presented. The proposed scheme monitors the delay through a data path using a delay detection circuit (DDC).
This project aims to detect the onset of chip failure due to via voiding through monitoring the d... more This project aims to detect the onset of chip failure due to via voiding through monitoring the delays of paths in a chip. The proposed method relates the probability of failure of individual vias to an increase in delay for monitors of the system using data for 65 nm technology. The delay increase, as a function of the failure distribution parameters, the path length, gate type, and process variation, has been investigated. An on-chip, ring oscillator-based wearout monitoring circuit is presented. The proposed scheme monitors the delay through a data path using a delay detection circuit (DDC).
Abstract—Constant scaling in device dimensions and increasing operating temperatures and vertical... more Abstract—Constant scaling in device dimensions and increasing operating temperatures and vertical electrical fields have all contributed to faster device aging due to NBTI. The problem is further compounded in SRAM cells where the devices are among the smallest for a ...
Abstract—Constant scaling in device dimensions and increasing operating temperatures and vertical... more Abstract—Constant scaling in device dimensions and increasing operating temperatures and vertical electrical fields have all contributed to faster device aging due to NBTI. The problem is further compounded in SRAM cells where the devices are among the smallest for a ...
IEEE Transactions on Very Large Scale Integration Systems, 2012
Scaling of device sizes has reduced gate oxide thickness to a few atomic layers, increasing the v... more Scaling of device sizes has reduced gate oxide thickness to a few atomic layers, increasing the vulnerability of the gate oxide to breakdown. During breakdown, devices go through a gradual wearout process characterized by increased leakage. Using experimentally verified gate oxide breakdown models, a detailed analysis of the effect of progressive gate oxide breakdown on the performance of a conventional 6T SRAM cell is presented for 45-nm predictive technology. The DC margins (read, write, and retention) and access times (read and write) during wearout are analyzed, and a cell breakdown point due to degradation in each of these parameters is defined. A combination of these results is used to formulate a definition for the hard-breakdown point of a cell. An on-chip process, voltage, and temperature tolerant monitoring scheme is proposed to detect the gradual wearout of SRAM cells. The monitoring scheme enables the detection of impending cell failure, which in turn can trigger reconfiguration of the SRAM with redundant rows and/or columns prior to failure.
IEEE Transactions on Very Large Scale Integration Systems, 2012
Scaling of device sizes has reduced gate oxide thickness to a few atomic layers, increasing the v... more Scaling of device sizes has reduced gate oxide thickness to a few atomic layers, increasing the vulnerability of the gate oxide to breakdown. During breakdown, devices go through a gradual wearout process characterized by increased leakage. Using experimentally verified gate oxide breakdown models, a detailed analysis of the effect of progressive gate oxide breakdown on the performance of a conventional 6T SRAM cell is presented for 45-nm predictive technology. The DC margins (read, write, and retention) and access times (read and write) during wearout are analyzed, and a cell breakdown point due to degradation in each of these parameters is defined. A combination of these results is used to formulate a definition for the hard-breakdown point of a cell. An on-chip process, voltage, and temperature tolerant monitoring scheme is proposed to detect the gradual wearout of SRAM cells. The monitoring scheme enables the detection of impending cell failure, which in turn can trigger reconfiguration of the SRAM with redundant rows and/or columns prior to failure.
Until recently, negative bias temperature instability (NBTI) has been regarded as the primary rel... more Until recently, negative bias temperature instability (NBTI) has been regarded as the primary reliability concern. However, with the introduction of high-k metal gate stacks, positive bias temperature instability (PBTI) has gradually become equally important. Conventional ring oscillator based structures monitor the delay/frequency through an inverter chain to track the PMOS threshold voltage (Vt) degradation due to NBTI, with the assumption of zero degradation in the NMOS device. Therefore these structures lose their effectiveness in the presence of PBTI. In this work, we propose a ring oscillator based test structure that isolates the Vt degradation in the PMOS device and the NMOS device, hence permitting simultaneous monitoring of both. We also introduce a switching activity replication scheme for more accurate prediction of degradation in actual data paths.
Increasing operating temperatures and electrical fields, combined with the scaling of dimensions,... more Increasing operating temperatures and electrical fields, combined with the scaling of dimensions, have contributed to faster device aging due to negative bias temperature instability (NBTI). This problem is further compounded in SRAM cells because SRAMs use devices that are among the smallest for a technology node. Since device degradation is a gradual process, it is proposed that if the threshold voltage increase in PMOS devices of SRAM cells can be monitored, failing cells in SRAMs can be detected and the SRAM can be operated without failures, given available memory redundancy. Using an experimentally verified NBTI model, we study the performances of conventional 6T SRAM cells, as a function of NBTI degradation, in the presence of process variations. An on-chip monitoring scheme is presented that can be embedded within conventional SRAM designs without affecting normal device operation. It identifies cells susceptible to read and write failures in the near future, enabling the prediction of cell failure before its occurrence in order to trigger reconfiguration.
Until recently, negative bias temperature instability (NBTI) has been regarded as the primary rel... more Until recently, negative bias temperature instability (NBTI) has been regarded as the primary reliability concern. However, with the introduction of high-k metal gate stacks, positive bias temperature instability (PBTI) has gradually become equally important. Conventional ring oscillator based structures monitor the delay/frequency through an inverter chain to track the PMOS threshold voltage (Vt) degradation due to NBTI, with the assumption of zero degradation in the NMOS device. Therefore these structures lose their effectiveness in the presence of PBTI. In this work, we propose a ring oscillator based test structure that isolates the Vt degradation in the PMOS device and the NMOS device, hence permitting simultaneous monitoring of both. We also introduce a switching activity replication scheme for more accurate prediction of degradation in actual data paths.
Although constant technology scaling has resulted in considerable benefits, smaller device dimens... more Although constant technology scaling has resulted in considerable benefits, smaller device dimensions, higher operating temperatures and electric fields have also contributed to faster device aging due to wearout. Not only does this result in the shortening of processor lifetimes, it leads to faster wearout resultant performance degradation with operating time. Instead of taking a reactive approach towards reliability awareness, we propose a pre-emptive route toward wearout mitigation. Given the significant thermal and stress variation across the components of microprocessors, in this work we focus on one of the most likely candidates for overheating and hence reliability failures, the register file. We propose different wearout-aware compiler-directed register assignment techniques that distribute the stress induced wearout throughout the register file, with the aim of improving the lifetime of the register file, with negligible performance overhead. We compare our results with a state-of-the-art thermal-aware compilation scheme to show the clear advantage our proposed wearout-aware scheme has over thermal-aware schemes in terms of lifetime improvement that can reach up to 20% for Bias Temperature Instability.
Increasing operating temperatures and electrical fields, combined with the scaling of dimensions,... more Increasing operating temperatures and electrical fields, combined with the scaling of dimensions, have contributed to faster device aging due to negative bias temperature instability (NBTI). This problem is further compounded in SRAM cells because SRAMs use devices that are among the smallest for a technology node. Since device degradation is a gradual process, it is proposed that if the threshold voltage increase in PMOS devices of SRAM cells can be monitored, failing cells in SRAMs can be detected and the SRAM can be operated without failures, given available memory redundancy. Using an experimentally verified NBTI model, we study the performances of conventional 6T SRAM cells, as a function of NBTI degradation, in the presence of process variations. An on-chip monitoring scheme is presented that can be embedded within conventional SRAM designs without affecting normal device operation. It identifies cells susceptible to read and write failures in the near future, enabling the prediction of cell failure before its occurrence in order to trigger reconfiguration.
Although constant technology scaling has resulted in considerable benefits, smaller device dimens... more Although constant technology scaling has resulted in considerable benefits, smaller device dimensions, higher operating temperatures and electric fields have also contributed to faster device aging due to wearout. Not only does this result in the shortening of processor lifetimes, it leads to faster wearout resultant performance degradation with operating time. Instead of taking a reactive approach towards reliability awareness, we propose a pre-emptive route toward wearout mitigation. Given the significant thermal and stress variation across the components of microprocessors, in this work we focus on one of the most likely candidates for overheating and hence reliability failures, the register file. We propose different wearout-aware compiler-directed register assignment techniques that distribute the stress induced wearout throughout the register file, with the aim of improving the lifetime of the register file, with negligible performance overhead. We compare our results with a state-of-the-art thermal-aware compilation scheme to show the clear advantage our proposed wearout-aware scheme has over thermal-aware schemes in terms of lifetime improvement that can reach up to 20% for Bias Temperature Instability.
Motorcycle is widely used around the world and particularly in Pakistan. The gear shifting system... more Motorcycle is widely used around the world and particularly in Pakistan. The gear shifting system of the motorcycle is conventionally manual. This paper covers development of an indigenous automatic gear shifting/changing system for the standard motorcycle. By this system the manual mechanicalgear-shifting system will remain unchanged because an additional electro-mechanical system is placed on the vehicle to shift the gear and for automatic controlling the clutch. So the system has both the options manual as well as automatic. This system uses low-cost microcontrollers to make the accurate decision for shifting the gear up and down by observing the speed, and it controls the clutch transmission where necessary. The complete hardware and software has been tested and the functioning of the automatic gear shifting system is verified. This system is flexile and can be used with any motorcycle manufactured in Pakistan ranging from 50cc to 200cc.
The delays of paths in a chip can be monitored to detect via voiding. This work relates the proba... more The delays of paths in a chip can be monitored to detect via voiding. This work relates the probability of failure of individual vias to an increase in delay for monitors of the system using data for 65 nm technology. The sensitivity of the trigger point as a function of the failure distribution parameters and the path length has been investigated. A circuit has been designed to detect the onset of chip failure due to via voiding.
The delays of paths in a chip can be monitored to detect via voiding. This work relates the proba... more The delays of paths in a chip can be monitored to detect via voiding. This work relates the probability of failure of individual vias to an increase in delay for monitors of the system using data for 65 nm technology. The sensitivity of the trigger point as a function of the failure distribution parameters and the path length has been investigated. A circuit has been designed to detect the onset of chip failure due to via voiding.
The delays of paths in a chip can be monitored to detect via voiding. This work relates the proba... more The delays of paths in a chip can be monitored to detect via voiding. This work relates the probability of failure of individual vias to an increase in delay for monitors of the system using data for 65 nm technology. The sensitivity of the trigger point as a function of the failure distribution parameters and the path length has been investigated. A circuit has been designed to detect the onset of chip failure due to via voiding.
The delays of paths in a chip can be monitored to detect via voiding. This work relates the proba... more The delays of paths in a chip can be monitored to detect via voiding. This work relates the probability of failure of individual vias to an increase in delay for monitors of the system using data for 65 nm technology. The sensitivity of the trigger point as a function of the failure distribution parameters and the path length has been investigated. A circuit has been designed to detect the onset of chip failure due to via voiding.
Scaling of device sizes has reduced gate oxide thickness to a few atomic layers, increasing the v... more Scaling of device sizes has reduced gate oxide thickness to a few atomic layers, increasing the vulnerability of the gate oxide to breakdown. During breakdown, devices go through a gradual wearout process after an initial gate leakage increase leading to device failure. It is proposed that if wearout can be monitored, cache arrays with failing cells can be reliably operated after reconfiguration given available memory redundancy. Using experimentally verified gate oxide breakdown models, a detailed analysis of the effect of progressive gate oxide breakdown on the performance of a conventional 6T SRAM cell is presented for 45 nm predictive technology. The DC margin trends (Read, Write and Retention) and access times (Read and Write) during wearout are analyzed, and a cell breakdown point due to degradation in each of these parameters is defined. A combination of these results is used to formulate a practical definition for the hard-breakdown point of a cell. Using an on-chip PVT (process, voltage, and temperature) tolerant monitoring scheme, it has been shown that gradual wearout in SRAM cells, due to gate oxide breakdown, is detectible, and cell failure can be predicted before its occurrence.
Scaling of device sizes has reduced gate oxide thickness to a few atomic layers, increasing the v... more Scaling of device sizes has reduced gate oxide thickness to a few atomic layers, increasing the vulnerability of the gate oxide to breakdown. During breakdown, devices go through a gradual wearout process after an initial gate leakage increase leading to device failure. It is proposed that if wearout can be monitored, cache arrays with failing cells can be reliably operated after reconfiguration given available memory redundancy. Using experimentally verified gate oxide breakdown models, a detailed analysis of the effect of progressive gate oxide breakdown on the performance of a conventional 6T SRAM cell is presented for 45 nm predictive technology. The DC margin trends (Read, Write and Retention) and access times (Read and Write) during wearout are analyzed, and a cell breakdown point due to degradation in each of these parameters is defined. A combination of these results is used to formulate a practical definition for the hard-breakdown point of a cell. Using an on-chip PVT (process, voltage, and temperature) tolerant monitoring scheme, it has been shown that gradual wearout in SRAM cells, due to gate oxide breakdown, is detectible, and cell failure can be predicted before its occurrence.
This project aims to detect the onset of chip failure due to via voiding through monitoring the d... more This project aims to detect the onset of chip failure due to via voiding through monitoring the delays of paths in a chip. The proposed method relates the probability of failure of individual vias to an increase in delay for monitors of the system using data for 65 nm technology. The delay increase, as a function of the failure distribution parameters, the path length, gate type, and process variation, has been investigated. An on-chip, ring oscillator-based wearout monitoring circuit is presented. The proposed scheme monitors the delay through a data path using a delay detection circuit (DDC).
This project aims to detect the onset of chip failure due to via voiding through monitoring the d... more This project aims to detect the onset of chip failure due to via voiding through monitoring the delays of paths in a chip. The proposed method relates the probability of failure of individual vias to an increase in delay for monitors of the system using data for 65 nm technology. The delay increase, as a function of the failure distribution parameters, the path length, gate type, and process variation, has been investigated. An on-chip, ring oscillator-based wearout monitoring circuit is presented. The proposed scheme monitors the delay through a data path using a delay detection circuit (DDC).
Abstract—Constant scaling in device dimensions and increasing operating temperatures and vertical... more Abstract—Constant scaling in device dimensions and increasing operating temperatures and vertical electrical fields have all contributed to faster device aging due to NBTI. The problem is further compounded in SRAM cells where the devices are among the smallest for a ...
Abstract—Constant scaling in device dimensions and increasing operating temperatures and vertical... more Abstract—Constant scaling in device dimensions and increasing operating temperatures and vertical electrical fields have all contributed to faster device aging due to NBTI. The problem is further compounded in SRAM cells where the devices are among the smallest for a ...
IEEE Transactions on Very Large Scale Integration Systems, 2012
Scaling of device sizes has reduced gate oxide thickness to a few atomic layers, increasing the v... more Scaling of device sizes has reduced gate oxide thickness to a few atomic layers, increasing the vulnerability of the gate oxide to breakdown. During breakdown, devices go through a gradual wearout process characterized by increased leakage. Using experimentally verified gate oxide breakdown models, a detailed analysis of the effect of progressive gate oxide breakdown on the performance of a conventional 6T SRAM cell is presented for 45-nm predictive technology. The DC margins (read, write, and retention) and access times (read and write) during wearout are analyzed, and a cell breakdown point due to degradation in each of these parameters is defined. A combination of these results is used to formulate a definition for the hard-breakdown point of a cell. An on-chip process, voltage, and temperature tolerant monitoring scheme is proposed to detect the gradual wearout of SRAM cells. The monitoring scheme enables the detection of impending cell failure, which in turn can trigger reconfiguration of the SRAM with redundant rows and/or columns prior to failure.
IEEE Transactions on Very Large Scale Integration Systems, 2012
Scaling of device sizes has reduced gate oxide thickness to a few atomic layers, increasing the v... more Scaling of device sizes has reduced gate oxide thickness to a few atomic layers, increasing the vulnerability of the gate oxide to breakdown. During breakdown, devices go through a gradual wearout process characterized by increased leakage. Using experimentally verified gate oxide breakdown models, a detailed analysis of the effect of progressive gate oxide breakdown on the performance of a conventional 6T SRAM cell is presented for 45-nm predictive technology. The DC margins (read, write, and retention) and access times (read and write) during wearout are analyzed, and a cell breakdown point due to degradation in each of these parameters is defined. A combination of these results is used to formulate a definition for the hard-breakdown point of a cell. An on-chip process, voltage, and temperature tolerant monitoring scheme is proposed to detect the gradual wearout of SRAM cells. The monitoring scheme enables the detection of impending cell failure, which in turn can trigger reconfiguration of the SRAM with redundant rows and/or columns prior to failure.
Until recently, negative bias temperature instability (NBTI) has been regarded as the primary rel... more Until recently, negative bias temperature instability (NBTI) has been regarded as the primary reliability concern. However, with the introduction of high-k metal gate stacks, positive bias temperature instability (PBTI) has gradually become equally important. Conventional ring oscillator based structures monitor the delay/frequency through an inverter chain to track the PMOS threshold voltage (Vt) degradation due to NBTI, with the assumption of zero degradation in the NMOS device. Therefore these structures lose their effectiveness in the presence of PBTI. In this work, we propose a ring oscillator based test structure that isolates the Vt degradation in the PMOS device and the NMOS device, hence permitting simultaneous monitoring of both. We also introduce a switching activity replication scheme for more accurate prediction of degradation in actual data paths.
Increasing operating temperatures and electrical fields, combined with the scaling of dimensions,... more Increasing operating temperatures and electrical fields, combined with the scaling of dimensions, have contributed to faster device aging due to negative bias temperature instability (NBTI). This problem is further compounded in SRAM cells because SRAMs use devices that are among the smallest for a technology node. Since device degradation is a gradual process, it is proposed that if the threshold voltage increase in PMOS devices of SRAM cells can be monitored, failing cells in SRAMs can be detected and the SRAM can be operated without failures, given available memory redundancy. Using an experimentally verified NBTI model, we study the performances of conventional 6T SRAM cells, as a function of NBTI degradation, in the presence of process variations. An on-chip monitoring scheme is presented that can be embedded within conventional SRAM designs without affecting normal device operation. It identifies cells susceptible to read and write failures in the near future, enabling the prediction of cell failure before its occurrence in order to trigger reconfiguration.
Until recently, negative bias temperature instability (NBTI) has been regarded as the primary rel... more Until recently, negative bias temperature instability (NBTI) has been regarded as the primary reliability concern. However, with the introduction of high-k metal gate stacks, positive bias temperature instability (PBTI) has gradually become equally important. Conventional ring oscillator based structures monitor the delay/frequency through an inverter chain to track the PMOS threshold voltage (Vt) degradation due to NBTI, with the assumption of zero degradation in the NMOS device. Therefore these structures lose their effectiveness in the presence of PBTI. In this work, we propose a ring oscillator based test structure that isolates the Vt degradation in the PMOS device and the NMOS device, hence permitting simultaneous monitoring of both. We also introduce a switching activity replication scheme for more accurate prediction of degradation in actual data paths.
Although constant technology scaling has resulted in considerable benefits, smaller device dimens... more Although constant technology scaling has resulted in considerable benefits, smaller device dimensions, higher operating temperatures and electric fields have also contributed to faster device aging due to wearout. Not only does this result in the shortening of processor lifetimes, it leads to faster wearout resultant performance degradation with operating time. Instead of taking a reactive approach towards reliability awareness, we propose a pre-emptive route toward wearout mitigation. Given the significant thermal and stress variation across the components of microprocessors, in this work we focus on one of the most likely candidates for overheating and hence reliability failures, the register file. We propose different wearout-aware compiler-directed register assignment techniques that distribute the stress induced wearout throughout the register file, with the aim of improving the lifetime of the register file, with negligible performance overhead. We compare our results with a state-of-the-art thermal-aware compilation scheme to show the clear advantage our proposed wearout-aware scheme has over thermal-aware schemes in terms of lifetime improvement that can reach up to 20% for Bias Temperature Instability.
Increasing operating temperatures and electrical fields, combined with the scaling of dimensions,... more Increasing operating temperatures and electrical fields, combined with the scaling of dimensions, have contributed to faster device aging due to negative bias temperature instability (NBTI). This problem is further compounded in SRAM cells because SRAMs use devices that are among the smallest for a technology node. Since device degradation is a gradual process, it is proposed that if the threshold voltage increase in PMOS devices of SRAM cells can be monitored, failing cells in SRAMs can be detected and the SRAM can be operated without failures, given available memory redundancy. Using an experimentally verified NBTI model, we study the performances of conventional 6T SRAM cells, as a function of NBTI degradation, in the presence of process variations. An on-chip monitoring scheme is presented that can be embedded within conventional SRAM designs without affecting normal device operation. It identifies cells susceptible to read and write failures in the near future, enabling the prediction of cell failure before its occurrence in order to trigger reconfiguration.
Although constant technology scaling has resulted in considerable benefits, smaller device dimens... more Although constant technology scaling has resulted in considerable benefits, smaller device dimensions, higher operating temperatures and electric fields have also contributed to faster device aging due to wearout. Not only does this result in the shortening of processor lifetimes, it leads to faster wearout resultant performance degradation with operating time. Instead of taking a reactive approach towards reliability awareness, we propose a pre-emptive route toward wearout mitigation. Given the significant thermal and stress variation across the components of microprocessors, in this work we focus on one of the most likely candidates for overheating and hence reliability failures, the register file. We propose different wearout-aware compiler-directed register assignment techniques that distribute the stress induced wearout throughout the register file, with the aim of improving the lifetime of the register file, with negligible performance overhead. We compare our results with a state-of-the-art thermal-aware compilation scheme to show the clear advantage our proposed wearout-aware scheme has over thermal-aware schemes in terms of lifetime improvement that can reach up to 20% for Bias Temperature Instability.
Motorcycle is widely used around the world and particularly in Pakistan. The gear shifting system... more Motorcycle is widely used around the world and particularly in Pakistan. The gear shifting system of the motorcycle is conventionally manual. This paper covers development of an indigenous automatic gear shifting/changing system for the standard motorcycle. By this system the manual mechanicalgear-shifting system will remain unchanged because an additional electro-mechanical system is placed on the vehicle to shift the gear and for automatic controlling the clutch. So the system has both the options manual as well as automatic. This system uses low-cost microcontrollers to make the accurate decision for shifting the gear up and down by observing the speed, and it controls the clutch transmission where necessary. The complete hardware and software has been tested and the functioning of the automatic gear shifting system is verified. This system is flexile and can be used with any motorcycle manufactured in Pakistan ranging from 50cc to 200cc.
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Papers by Fahad Ahmed